xref: /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phyreg_n.h (revision 0898782247ae533d1f4e47a06bc5d4870931b284)
1 // SPDX-License-Identifier: ISC
2 /*
3  * Copyright (c) 2010 Broadcom Corporation
4  */
5 
6 #define NPHY_TBL_ID_GAIN1		0
7 #define NPHY_TBL_ID_GAIN2		1
8 #define NPHY_TBL_ID_GAINBITS1		2
9 #define NPHY_TBL_ID_GAINBITS2		3
10 #define NPHY_TBL_ID_GAINLIMIT		4
11 #define NPHY_TBL_ID_WRSSIGainLimit	5
12 #define NPHY_TBL_ID_RFSEQ		7
13 #define NPHY_TBL_ID_AFECTRL		8
14 #define NPHY_TBL_ID_ANTSWCTRLLUT	9
15 #define NPHY_TBL_ID_IQLOCAL		15
16 #define NPHY_TBL_ID_NOISEVAR		16
17 #define NPHY_TBL_ID_SAMPLEPLAY		17
18 #define NPHY_TBL_ID_CORE1TXPWRCTL	26
19 #define NPHY_TBL_ID_CORE2TXPWRCTL	27
20 #define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL	30
21 
22 #define NPHY_TBL_ID_EPSILONTBL0   31
23 #define NPHY_TBL_ID_SCALARTBL0    32
24 #define NPHY_TBL_ID_EPSILONTBL1   33
25 #define NPHY_TBL_ID_SCALARTBL1    34
26 
27 #define	NPHY_TO_BPHY_OFF	0xc00
28 
29 #define NPHY_BandControl_currentBand			0x0001
30 #define RFCC_CHIP0_PU			0x0400
31 #define RFCC_POR_FORCE			0x0040
32 #define RFCC_OE_POR_FORCE		0x0080
33 #define NPHY_RfctrlIntc_override_OFF			0
34 #define NPHY_RfctrlIntc_override_TRSW			1
35 #define NPHY_RfctrlIntc_override_PA				2
36 #define NPHY_RfctrlIntc_override_EXT_LNA_PU		3
37 #define NPHY_RfctrlIntc_override_EXT_LNA_GAIN	4
38 #define RIFS_ENABLE			0x80
39 #define BPHY_BAND_SEL_UP20		0x10
40 #define NPHY_MLenable			0x02
41 
42 #define NPHY_RfseqMode_CoreActv_override 0x0001
43 #define NPHY_RfseqMode_Trigger_override	0x0002
44 #define NPHY_RfseqCoreActv_TxRxChain0	(0x11)
45 #define NPHY_RfseqCoreActv_TxRxChain1	(0x22)
46 
47 #define NPHY_RfseqTrigger_rx2tx		0x0001
48 #define NPHY_RfseqTrigger_tx2rx		0x0002
49 #define NPHY_RfseqTrigger_updategainh	0x0004
50 #define NPHY_RfseqTrigger_updategainl	0x0008
51 #define NPHY_RfseqTrigger_updategainu	0x0010
52 #define NPHY_RfseqTrigger_reset2rx	0x0020
53 #define NPHY_RfseqStatus_rx2tx		0x0001
54 #define NPHY_RfseqStatus_tx2rx		0x0002
55 #define NPHY_RfseqStatus_updategainh	0x0004
56 #define NPHY_RfseqStatus_updategainl	0x0008
57 #define NPHY_RfseqStatus_updategainu	0x0010
58 #define NPHY_RfseqStatus_reset2rx	0x0020
59 #define NPHY_ClassifierCtrl_cck_en	0x1
60 #define NPHY_ClassifierCtrl_ofdm_en	0x2
61 #define NPHY_ClassifierCtrl_waited_en	0x4
62 #define NPHY_IQFlip_ADC1		0x0001
63 #define NPHY_IQFlip_ADC2		0x0010
64 #define NPHY_sampleCmd_STOP		0x0002
65 
66 #define RX_GF_OR_MM			0x0004
67 #define RX_GF_MM_AUTO			0x0100
68 
69 #define NPHY_iqloCalCmdGctl_IQLO_CAL_EN	0x8000
70 
71 #define NPHY_IqestCmd_iqstart		0x1
72 #define NPHY_IqestCmd_iqMode		0x2
73 
74 #define NPHY_TxPwrCtrlCmd_pwrIndex_init		0x40
75 #define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7	0x19
76 
77 #define PRIM_SEL_UP20		0x8000
78 
79 #define NPHY_RFSEQ_RX2TX		0x0
80 #define NPHY_RFSEQ_TX2RX		0x1
81 #define NPHY_RFSEQ_RESET2RX		0x2
82 #define NPHY_RFSEQ_UPDATEGAINH		0x3
83 #define NPHY_RFSEQ_UPDATEGAINL		0x4
84 #define NPHY_RFSEQ_UPDATEGAINU		0x5
85 
86 #define NPHY_RFSEQ_CMD_NOP		0x0
87 #define NPHY_RFSEQ_CMD_RXG_FBW		0x1
88 #define NPHY_RFSEQ_CMD_TR_SWITCH	0x2
89 #define NPHY_RFSEQ_CMD_EXT_PA		0x3
90 #define NPHY_RFSEQ_CMD_RXPD_TXPD	0x4
91 #define NPHY_RFSEQ_CMD_TX_GAIN		0x5
92 #define NPHY_RFSEQ_CMD_RX_GAIN		0x6
93 #define NPHY_RFSEQ_CMD_SET_HPF_BW	0x7
94 #define NPHY_RFSEQ_CMD_CLR_HIQ_DIS	0x8
95 #define NPHY_RFSEQ_CMD_END		0xf
96 
97 #define NPHY_REV3_RFSEQ_CMD_NOP		0x0
98 #define NPHY_REV3_RFSEQ_CMD_RXG_FBW	0x1
99 #define NPHY_REV3_RFSEQ_CMD_TR_SWITCH	0x2
100 #define NPHY_REV3_RFSEQ_CMD_INT_PA_PU	0x3
101 #define NPHY_REV3_RFSEQ_CMD_EXT_PA	0x4
102 #define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD	0x5
103 #define NPHY_REV3_RFSEQ_CMD_TX_GAIN	0x6
104 #define NPHY_REV3_RFSEQ_CMD_RX_GAIN	0x7
105 #define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS	0x8
106 #define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC	0x9
107 #define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC	0xa
108 #define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC	0xb
109 #define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC	0xc
110 #define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC	0xd
111 #define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC	0xe
112 #define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS	0xf
113 #define NPHY_REV3_RFSEQ_CMD_END		0x1f
114 
115 #define NPHY_RSSI_SEL_W1		0x0
116 #define NPHY_RSSI_SEL_W2		0x1
117 #define NPHY_RSSI_SEL_NB		0x2
118 #define NPHY_RSSI_SEL_IQ		0x3
119 #define NPHY_RSSI_SEL_TSSI_2G		0x4
120 #define NPHY_RSSI_SEL_TSSI_5G		0x5
121 #define NPHY_RSSI_SEL_TBD		0x6
122 
123 #define NPHY_RAIL_I			0x0
124 #define NPHY_RAIL_Q			0x1
125 
126 #define NPHY_FORCESIG_DECODEGATEDCLKS	0x8
127 
128 #define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
129 #define NPHY_REV7_RfctrlOverride_cmd_rx_pu   0x1
130 #define NPHY_REV7_RfctrlOverride_cmd_tx_pu   0x2
131 #define NPHY_REV7_RfctrlOverride_cmd_rxgain  0x3
132 #define NPHY_REV7_RfctrlOverride_cmd_txgain  0x4
133 
134 #define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
135 #define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK  0x0ff00
136 #define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
137 
138 #define NPHY_REV7_TXGAINCODE_TGAIN_MASK     0x7fff
139 #define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK   0x8000
140 #define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
141 
142 #define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
143 #define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
144 #define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
145 
146 #define NPHY_IqestIqAccLo(core)  ((core == 0) ? 0x12c : 0x134)
147 
148 #define NPHY_IqestIqAccHi(core)  ((core == 0) ? 0x12d : 0x135)
149 
150 #define NPHY_IqestipwrAccLo(core)  ((core == 0) ? 0x12e : 0x136)
151 
152 #define NPHY_IqestipwrAccHi(core)  ((core == 0) ? 0x12f : 0x137)
153 
154 #define NPHY_IqestqpwrAccLo(core)  ((core == 0) ? 0x130 : 0x138)
155 
156 #define NPHY_IqestqpwrAccHi(core)  ((core == 0) ? 0x131 : 0x139)
157