1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // ARM CMN/CI interconnect PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_CHILD_INFO 0x0080 28 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 29 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 30 31 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 32 #define CMN_CHILD_NODE_ISOLATED BIT(30) 33 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 34 35 /* Some implementations use a mesh larger than the architectural max of 12 */ 36 #define CMN_MAX_DIMENSION 14 37 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 38 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 39 40 /* Currently XPs are the node type we can have most of; others top out at 128 */ 41 #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS 42 43 /* The CFG node has various info besides the discovery tree */ 44 #define CMN_CFGM_PERIPH_ID_01 0x0008 45 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0) 46 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32) 47 #define CMN_CFGM_PERIPH_ID_23 0x0010 48 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4) 49 50 #define CMN_CFGM_INFO_GLOBAL 0x0900 51 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 52 #define CMN_S3_R2_MULTIPLE_DTM_EN BIT_ULL(59) 53 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 54 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 55 #define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44) 56 57 #define CMN_CFGM_INFO_GLOBAL_1 0x0908 58 #define CMN_S3_R2_RSP_VC_NUM GENMASK_ULL(11, 9) 59 #define CMN_S3_R2_DAT_VC_NUM GENMASK_ULL(8, 6) 60 #define CMN_S3_R2_SNP_VC_NUM GENMASK_ULL(5, 3) 61 #define CMN_S3_R2_REQ_VC_NUM GENMASK_ULL(2, 0) 62 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 63 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 64 65 /* XPs also have some local topology info which has uses too */ 66 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 67 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5, 0) 68 69 #define CMN_MAX_PORTS 6 70 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 71 72 /* PMU registers occupy the 3rd 4KB page of each node's region */ 73 #define CMN_PMU_OFFSET 0x2000 74 /* ...except when they don't :( */ 75 #define CMN_S3_R1_DTM_OFFSET 0xa000 76 #define CMN_S3_PMU_OFFSET 0xd900 77 78 /* For most nodes, this is all there is */ 79 #define CMN_PMU_EVENT_SEL 0x000 80 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 81 #define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39) 82 #define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37) 83 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 84 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 85 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 86 87 /* But then... */ 88 #define CMN__PMU_EVICT_STATE_SEL GENMASK_ULL(54, 52) 89 #define CMN__PMU_ENHANCED_HBT_LBT_SEL GENMASK_ULL(51, 48) 90 #define CMN__PMU_SNP_VC_SEL GENMASK_ULL(47, 46) 91 #define CMN__S3_R2_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(45, 42) 92 #define CMN__S3_R2_SN_HOME_SEL GENMASK_ULL(41, 40) 93 #define CMN__S3_R2_HBT_LBT_SEL GENMASK_ULL(39, 38) 94 #define CMN__S3_R2_CLASS_OCCUP_ID GENMASK_ULL(37, 36) 95 #define CMN__S3_R2_OCCUP1_ID GENMASK_ULL(35, 32) 96 97 /* Some types are designed to coexist with another device in the same node */ 98 #define CMN_CCLA_PMU_EVENT_SEL 0x008 99 #define CMN_HNP_PMU_EVENT_SEL 0x008 100 101 /* DTMs live in the PMU space of XP registers */ 102 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 103 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 104 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 105 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 106 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 107 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 108 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 109 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 110 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 111 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 112 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 113 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 114 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 115 116 #define CMN_DTM_PMU_CONFIG 0x210 117 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 118 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 119 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 120 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 121 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 122 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 123 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 124 #define CMN__PMEVCNT23_COMBINED BIT(2) 125 #define CMN__PMEVCNT01_COMBINED BIT(1) 126 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 127 128 #define CMN_DTM_PMEVCNT 0x220 129 130 #define CMN_DTM_PMEVCNTSR 0x240 131 132 #define CMN650_DTM_UNIT_INFO 0x0910 133 #define CMN_DTM_UNIT_INFO 0x0960 134 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0) 135 136 #define CMN_DTM_NUM_COUNTERS 4 137 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 138 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 139 140 /* The DTC node is where the magic happens */ 141 #define CMN_DT_DTC_CTL 0x0a00 142 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 143 #define CMN_DT_DTC_CTL_CG_DISABLE BIT(10) 144 145 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 146 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 147 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n)) 148 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40) 149 150 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n)) 151 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90) 152 153 #define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100) 154 #define CMN_DT_PMCR_PMU_EN BIT(0) 155 #define CMN_DT_PMCR_CNTR_RST BIT(5) 156 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 157 158 #define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118) 159 #define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120) 160 161 #define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128) 162 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 163 164 #define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130) 165 #define CMN_DT_PMSRR_SS_REQ BIT(0) 166 167 #define CMN_DT_NUM_COUNTERS 8 168 #define CMN_MAX_DTCS 4 169 170 /* 171 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 172 * so throwing away one bit to make overflow handling easy is no big deal. 173 */ 174 #define CMN_COUNTER_INIT 0x80000000 175 /* Similarly for the 40-bit cycle counter */ 176 #define CMN_CC_INIT 0x8000000000ULL 177 178 179 /* Event attributes */ 180 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 181 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 182 #define CMN_CONFIG_FILTER GENMASK_ULL(30, 27) 183 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 184 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 185 #define CMN_CONFIG_FILTER2 GENMASK_ULL(51, 48) 186 187 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 188 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 189 #define CMN_EVENT_FILTER(event) FIELD_GET(CMN_CONFIG_FILTER, (event)->attr.config) 190 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 191 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 192 #define CMN_EVENT_FILTER2(event) FIELD_GET(CMN_CONFIG_FILTER2, (event)->attr.config) 193 194 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 195 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 196 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 197 #define CMN_CONFIG_WP_GRP GENMASK_ULL(57, 56) 198 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58) 199 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 200 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 201 202 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 203 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 204 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 205 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 206 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 207 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 208 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 209 210 /* Made-up event IDs for watchpoint direction */ 211 #define CMN_WP_UP 0 212 #define CMN_WP_DOWN 2 213 214 215 /* Internal values for encoding event support */ 216 enum cmn_model { 217 CMN600 = 1, 218 CMN650 = 2, 219 CI700 = 4, 220 CMN700 = 8, 221 CMNS3R01 = 16, 222 CMNS3R2 = 32, 223 /* ...and then we can use bitmap tricks for commonality */ 224 CMN_ANY = -1, 225 NOT_CMN600 = -2, 226 CMN_700ON = ~(CMN700 - 1), 227 CMN_650ON = CMN_700ON | CMN650, 228 CMNS3 = CMNS3R01 | CMNS3R2, 229 }; 230 231 /* Actual part numbers and revision IDs defined by the hardware */ 232 enum cmn_part { 233 PART_CMN600 = 0x434, 234 PART_CMN650 = 0x436, 235 PART_CMN600AE = 0x438, 236 PART_CMN700 = 0x43c, 237 PART_CI700 = 0x43a, 238 PART_CMN_S3 = 0x43e, 239 /* Synthetic part number, overridden to PART_CMN_S3 during discovery */ 240 PART_GRAVITON5 = 0xa5, 241 }; 242 243 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 244 enum cmn_revision { 245 REV_CMN600_R1P0, 246 REV_CMN600_R1P1, 247 REV_CMN600_R1P2, 248 REV_CMN600_R1P3, 249 REV_CMN600_R2P0, 250 REV_CMN600_R3P0, 251 REV_CMN600_R3P1, 252 REV_CMN650_R0P0 = 0, 253 REV_CMN650_R1P0, 254 REV_CMN650_R1P1, 255 REV_CMN650_R2P0, 256 REV_CMN650_R1P2, 257 REV_CMN700_R0P0 = 0, 258 REV_CMN700_R1P0, 259 REV_CMN700_R2P0, 260 REV_CMN700_R3P0, 261 REV_CMNS3_R0P0 = 0, 262 REV_CMNS3_R0P1, 263 REV_CMNS3_R1P0, 264 REV_CMNS3_R2P0, 265 REV_CMNS3_R2P1, 266 REV_CMNS3_R2P2, 267 REV_CMNS3_R2P5, 268 REV_CI700_R0P0 = 0, 269 REV_CI700_R1P0, 270 REV_CI700_R2P0, 271 }; 272 273 enum cmn_node_type { 274 CMN_TYPE_INVALID, 275 CMN_TYPE_DVM, 276 CMN_TYPE_CFG, 277 CMN_TYPE_DTC, 278 CMN_TYPE_HNI, 279 CMN_TYPE_HNF, 280 CMN_TYPE_XP, 281 CMN_TYPE_SBSX, 282 CMN_TYPE_MPAM_S, 283 CMN_TYPE_MPAM_NS, 284 CMN_TYPE_RNI, 285 CMN_TYPE_RND = 0xd, 286 CMN_TYPE_RNSAM = 0xf, 287 CMN_TYPE_MTSX, 288 CMN_TYPE_HNP, 289 CMN_TYPE_CXRA = 0x100, 290 CMN_TYPE_CXHA, 291 CMN_TYPE_CXLA, 292 CMN_TYPE_CCRA, 293 CMN_TYPE_CCHA, 294 CMN_TYPE_CCLA, 295 CMN_TYPE_CCLA_RNI, 296 CMN_TYPE_HNS = 0x200, 297 CMN_TYPE_HNS_MPAM_S, 298 CMN_TYPE_HNS_MPAM_NS, 299 CMN_TYPE_APB = 0x1000, 300 /* Not a real node type */ 301 CMN_TYPE_WP = 0x7770 302 }; 303 304 enum cmn_filter_select { 305 SEL_NONE, 306 SEL_OCCUP1_ID, 307 SEL_CLASS_OCCUP_ID, 308 SEL_CBUSY_SNTHROTTLE_SEL, 309 SEL_HBT_LBT_SEL, 310 SEL_SN_HOME_SEL, 311 SEL_SNP_VC_SEL, 312 SEL_ENHANCED_HBT_LBT_SEL, 313 SEL_EVICT_STATE_SEL, 314 SEL_MAX 315 }; 316 317 struct arm_cmn_node { 318 void __iomem *pmu_base; 319 u16 id, logid; 320 enum cmn_node_type type; 321 322 /* XP properties really, but replicated to children for convenience */ 323 u8 dtm; 324 s8 dtc; 325 u8 portid_bits:4; 326 u8 deviceid_bits:4; 327 /* DN/HN-F/CXHA */ 328 struct { 329 u8 val : 4; 330 u8 count : 4; 331 } filter[SEL_MAX]; 332 union { 333 u8 event[4]; 334 __le32 event_sel; 335 u16 event_w[4]; 336 __le64 event_sel_w; 337 }; 338 }; 339 340 struct arm_cmn_dtm { 341 void __iomem *base; 342 u32 pmu_config_low; 343 union { 344 u8 input_sel[4]; 345 __le32 pmu_config_high; 346 }; 347 s8 wp_event[4]; 348 }; 349 350 struct arm_cmn_dtc { 351 void __iomem *base; 352 void __iomem *pmu_base; 353 int irq; 354 s8 irq_friend; 355 bool cc_active; 356 357 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 358 struct perf_event *cycles; 359 }; 360 361 #define CMN_STATE_DISABLED BIT(0) 362 #define CMN_STATE_TXN BIT(1) 363 364 struct arm_cmn { 365 struct device *dev; 366 void __iomem *base; 367 unsigned int state; 368 369 enum cmn_revision rev; 370 enum cmn_part part; 371 u8 mesh_x; 372 u8 mesh_y; 373 u16 num_xps; 374 u16 num_dns; 375 bool multi_dtm; 376 u8 ports_used; 377 struct { 378 unsigned int rsp_vc_num : 2; 379 unsigned int dat_vc_num : 2; 380 unsigned int snp_vc_num : 2; 381 unsigned int req_vc_num : 2; 382 }; 383 384 struct arm_cmn_node *xps; 385 struct arm_cmn_node *dns; 386 387 struct arm_cmn_dtm *dtms; 388 struct arm_cmn_dtc *dtc; 389 unsigned int num_dtcs; 390 391 int cpu; 392 struct hlist_node cpuhp_node; 393 394 struct pmu pmu; 395 struct dentry *debug; 396 }; 397 398 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 399 400 static int arm_cmn_hp_state; 401 402 struct arm_cmn_nodeid { 403 u8 port; 404 u8 dev; 405 }; 406 407 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 408 { 409 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1)); 410 } 411 412 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn) 413 { 414 struct arm_cmn_nodeid nid; 415 416 nid.dev = dn->id & ((1U << dn->deviceid_bits) - 1); 417 nid.port = (dn->id >> dn->deviceid_bits) & ((1U << dn->portid_bits) - 1); 418 return nid; 419 } 420 421 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 422 const struct arm_cmn_node *dn) 423 { 424 int id = dn->id >> (dn->portid_bits + dn->deviceid_bits); 425 int bits = arm_cmn_xyidbits(cmn); 426 int x = id >> bits; 427 int y = id & ((1U << bits) - 1); 428 429 return cmn->xps + cmn->mesh_x * y + x; 430 } 431 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 432 enum cmn_node_type type) 433 { 434 struct arm_cmn_node *dn; 435 436 for (dn = cmn->dns; dn->type; dn++) 437 if (dn->type == type) 438 return dn; 439 return NULL; 440 } 441 442 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) 443 { 444 switch (cmn->part) { 445 case PART_CMN600: 446 return CMN600; 447 case PART_CMN650: 448 return CMN650; 449 case PART_CMN700: 450 return CMN700; 451 case PART_CI700: 452 return CI700; 453 case PART_CMN_S3: 454 if (cmn->rev >= REV_CMNS3_R2P0) 455 return CMNS3R2; 456 return CMNS3R01; 457 default: 458 return 0; 459 }; 460 } 461 462 static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_cmn_node *dn) 463 { 464 if (cmn->part == PART_CMN_S3) { 465 if (cmn->rev >= REV_CMNS3_R1P0 && dn->type == CMN_TYPE_XP) 466 return CMN_S3_R1_DTM_OFFSET; 467 return CMN_S3_PMU_OFFSET; 468 } 469 return CMN_PMU_OFFSET; 470 } 471 472 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 473 const struct arm_cmn_node *xp, int port) 474 { 475 int offset = CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp); 476 477 if (port >= 2) { 478 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650) 479 return 0; 480 /* 481 * CI-700 may have extra ports, but still has the 482 * mesh_port_connect_info registers in the way. 483 */ 484 if (cmn->part == PART_CI700) 485 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 486 } 487 488 return readl_relaxed(xp->pmu_base + offset); 489 } 490 491 static struct dentry *arm_cmn_debugfs; 492 493 #ifdef CONFIG_DEBUG_FS 494 static const char *arm_cmn_device_type(u8 type) 495 { 496 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 497 case 0x00: return " |"; 498 case 0x01: return " RN-I |"; 499 case 0x02: return " RN-D |"; 500 case 0x04: return " RN-F_B |"; 501 case 0x05: return "RN-F_B_E|"; 502 case 0x06: return " RN-F_A |"; 503 case 0x07: return "RN-F_A_E|"; 504 case 0x08: return " HN-T |"; 505 case 0x09: return " HN-I |"; 506 case 0x0a: return " HN-D |"; 507 case 0x0b: return " HN-P |"; 508 case 0x0c: return " SN-F |"; 509 case 0x0d: return " SBSX |"; 510 case 0x0e: return " HN-F |"; 511 case 0x0f: return " SN-F_E |"; 512 case 0x10: return " SN-F_D |"; 513 case 0x11: return " CXHA |"; 514 case 0x12: return " CXRA |"; 515 case 0x13: return " CXRH |"; 516 case 0x14: return " RN-F_D |"; 517 case 0x15: return "RN-F_D_E|"; 518 case 0x16: return " RN-F_C |"; 519 case 0x17: return "RN-F_C_E|"; 520 case 0x18: return " RN-F_E |"; 521 case 0x19: return "RN-F_E_E|"; 522 case 0x1a: return " HN-S |"; 523 case 0x1b: return " LCN |"; 524 case 0x1c: return " MTSX |"; 525 case 0x1d: return " HN-V |"; 526 case 0x1e: return " CCG |"; 527 case 0x20: return " RN-F_F |"; 528 case 0x21: return "RN-F_F_E|"; 529 case 0x22: return " SN-F_F |"; 530 default: return " ???? |"; 531 } 532 } 533 534 static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d) 535 { 536 struct arm_cmn *cmn = s->private; 537 struct arm_cmn_node *dn; 538 u16 id = xp->id | d | (p << xp->deviceid_bits); 539 540 for (dn = cmn->dns; dn->type; dn++) { 541 int pad = dn->logid < 10; 542 543 if (dn->type == CMN_TYPE_XP) 544 continue; 545 /* Ignore the extra components that will overlap on some ports */ 546 if (dn->type < CMN_TYPE_HNI) 547 continue; 548 549 if (dn->id != id) 550 continue; 551 552 seq_printf(s, " %*c#%-*d |", pad + 1, ' ', 3 - pad, dn->logid); 553 return; 554 } 555 seq_puts(s, " |"); 556 } 557 558 static int arm_cmn_map_show(struct seq_file *s, void *data) 559 { 560 struct arm_cmn *cmn = s->private; 561 int x, y, p, pmax = fls(cmn->ports_used); 562 563 seq_puts(s, " X"); 564 for (x = 0; x < cmn->mesh_x; x++) 565 seq_printf(s, " %-2d ", x); 566 seq_puts(s, "\nY P D+"); 567 y = cmn->mesh_y; 568 while (y--) { 569 int xp_base = cmn->mesh_x * y; 570 struct arm_cmn_node *xp = cmn->xps + xp_base; 571 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 572 573 for (x = 0; x < cmn->mesh_x; x++) 574 seq_puts(s, "--------+"); 575 576 seq_printf(s, "\n%-2d |", y); 577 for (x = 0; x < cmn->mesh_x; x++) { 578 for (p = 0; p < CMN_MAX_PORTS; p++) 579 port[p][x] = arm_cmn_device_connect_info(cmn, xp + x, p); 580 seq_printf(s, " XP #%-3d|", xp_base + x); 581 } 582 583 seq_puts(s, "\n |"); 584 for (x = 0; x < cmn->mesh_x; x++) { 585 s8 dtc = xp[x].dtc; 586 587 if (dtc < 0) 588 seq_puts(s, " DTC ?? |"); 589 else 590 seq_printf(s, " DTC %d |", dtc); 591 } 592 seq_puts(s, "\n |"); 593 for (x = 0; x < cmn->mesh_x; x++) 594 seq_puts(s, "........|"); 595 596 for (p = 0; p < pmax; p++) { 597 seq_printf(s, "\n %d |", p); 598 for (x = 0; x < cmn->mesh_x; x++) 599 seq_puts(s, arm_cmn_device_type(port[p][x])); 600 seq_puts(s, "\n 0|"); 601 for (x = 0; x < cmn->mesh_x; x++) 602 arm_cmn_show_logid(s, xp + x, p, 0); 603 seq_puts(s, "\n 1|"); 604 for (x = 0; x < cmn->mesh_x; x++) 605 arm_cmn_show_logid(s, xp + x, p, 1); 606 } 607 seq_puts(s, "\n-----+"); 608 } 609 for (x = 0; x < cmn->mesh_x; x++) 610 seq_puts(s, "--------+"); 611 seq_puts(s, "\n"); 612 return 0; 613 } 614 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 615 616 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 617 { 618 const char *name = "map"; 619 620 if (id > 0) 621 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 622 if (!name) 623 return; 624 625 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 626 } 627 #else 628 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 629 #endif 630 631 enum cmn_filter_type { 632 FILT_NONE, 633 FILT_OCCUP1_ID, 634 FILT_HNF_700, 635 FILT_HNS, 636 FILT_HNS_S3R2, 637 }; 638 #define CMN_FILTER(_sel) [SEL_##_sel] = CMN__PMU_##_sel 639 #define CMN_FILTER_V2(_sel) [SEL_##_sel] = CMN__S3_R2_##_sel 640 641 static const u64 arm_cmn_filters[][SEL_MAX] = { 642 [FILT_NONE] = {}, 643 /* DVM etc. */ 644 [FILT_OCCUP1_ID] = { 645 CMN_FILTER(OCCUP1_ID) 646 }, 647 /* Newer HN-F */ 648 [FILT_HNF_700] = { 649 CMN_FILTER(OCCUP1_ID), 650 CMN_FILTER(CLASS_OCCUP_ID), 651 CMN_FILTER(CBUSY_SNTHROTTLE_SEL) 652 }, 653 /* HN-S */ 654 [FILT_HNS] = { 655 CMN_FILTER(OCCUP1_ID), 656 CMN_FILTER(CLASS_OCCUP_ID), 657 CMN_FILTER(CBUSY_SNTHROTTLE_SEL), 658 CMN_FILTER(HBT_LBT_SEL), 659 CMN_FILTER(SN_HOME_SEL) 660 }, 661 /* Newer HN-S */ 662 [FILT_HNS_S3R2] = { 663 CMN_FILTER_V2(OCCUP1_ID), 664 CMN_FILTER_V2(CLASS_OCCUP_ID), 665 CMN_FILTER_V2(CBUSY_SNTHROTTLE_SEL), 666 CMN_FILTER_V2(HBT_LBT_SEL), 667 CMN_FILTER_V2(SN_HOME_SEL), 668 CMN_FILTER(SNP_VC_SEL), 669 CMN_FILTER(ENHANCED_HBT_LBT_SEL), 670 CMN_FILTER(EVICT_STATE_SEL) 671 } 672 }; 673 674 static enum cmn_filter_type arm_cmn_filter(enum cmn_node_type node, 675 enum cmn_model model) 676 { 677 switch (node) { 678 default: 679 return FILT_NONE; 680 case CMN_TYPE_DVM: 681 case CMN_TYPE_CXRA: 682 case CMN_TYPE_CXHA: 683 case CMN_TYPE_CCRA: 684 case CMN_TYPE_CCHA: 685 return FILT_OCCUP1_ID; 686 case CMN_TYPE_HNF: 687 if (model < CMN700) 688 return FILT_OCCUP1_ID; 689 return FILT_HNF_700; 690 case CMN_TYPE_HNS: 691 if (model < CMNS3R2) 692 return FILT_HNS; 693 return FILT_HNS_S3R2; 694 }; 695 } 696 697 struct arm_cmn_hw_event { 698 struct arm_cmn_node *dn; 699 union { 700 unsigned long *dtm_idx; 701 int cc_idx; 702 }; 703 unsigned long *wp_idx; 704 s8 dtc_idx[CMN_MAX_DTCS]; 705 u8 num_dns; 706 u8 dtm_offset; 707 bool wide_sel; 708 enum cmn_filter_select filter_sel; 709 }; 710 static_assert(sizeof(struct arm_cmn_hw_event) <= offsetof(struct hw_perf_event, target)); 711 712 #define for_each_hw_dn(hw, dn, i) \ 713 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 714 715 /* @i is the DTC number, @idx is the counter index on that DTC */ 716 #define for_each_hw_dtc_idx(hw, i, idx) \ 717 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0) 718 719 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 720 { 721 return (struct arm_cmn_hw_event *)&event->hw; 722 } 723 724 #define BPL2 (BITS_PER_LONG / 2) 725 726 static void arm_cmn_set_dtm_idx(struct arm_cmn_hw_event *hw, unsigned int pos, unsigned int val) 727 { 728 hw->dtm_idx[pos / BPL2] |= (unsigned long)val << ((pos % BPL2) * 2); 729 } 730 731 static unsigned int arm_cmn_get_dtm_idx(struct arm_cmn_hw_event *hw, unsigned int pos) 732 { 733 return (hw->dtm_idx[pos / BPL2] >> ((pos % BPL2) * 2)) & 3; 734 } 735 736 static unsigned long *arm_cmn_alloc_dtm_idx(void) 737 { 738 return bitmap_zalloc(CMN_MAX_NODES_PER_EVENT * 2, GFP_KERNEL); 739 } 740 741 static void arm_cmn_set_wp_idx(struct arm_cmn_hw_event *hw, unsigned int pos, bool val) 742 { 743 if (val) 744 set_bit(pos, hw->wp_idx); 745 } 746 747 static unsigned int arm_cmn_get_wp_idx(struct arm_cmn_hw_event *hw, unsigned int pos) 748 { 749 return test_bit(pos, hw->wp_idx); 750 } 751 752 static unsigned long *arm_cmn_alloc_wp_idx(void) 753 { 754 return bitmap_zalloc(CMN_MAX_XPS, GFP_KERNEL); 755 } 756 757 static void arm_cmn_clear_idx(struct arm_cmn_hw_event *hw) 758 { 759 bitmap_zero(hw->dtm_idx, CMN_MAX_NODES_PER_EVENT * 2); 760 if (hw->wp_idx) 761 bitmap_zero(hw->wp_idx, CMN_MAX_XPS); 762 } 763 764 struct arm_cmn_filter_attr { 765 enum cmn_filter_select sel; 766 u8 val; 767 }; 768 769 struct arm_cmn_event_attr { 770 struct device_attribute attr; 771 enum cmn_model model; 772 enum cmn_node_type type; 773 u16 eventid; 774 struct arm_cmn_filter_attr filter[2]; 775 }; 776 777 struct arm_cmn_format_attr { 778 struct device_attribute attr; 779 u64 field; 780 int config; 781 }; 782 783 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _fa, _fb, _fc, _fd, ...) \ 784 (&((struct arm_cmn_event_attr[]) {{ \ 785 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 786 .model = _model, \ 787 .type = _type, \ 788 .eventid = _eventid, \ 789 .filter = {{_fa, _fb}, {_fc, _fd}}, \ 790 }})[0].attr.attr) 791 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid, _filter...) \ 792 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, ##_filter, 0, 0, 0, 0) 793 794 static ssize_t arm_cmn_event_show(struct device *dev, 795 struct device_attribute *attr, char *buf) 796 { 797 struct arm_cmn_event_attr *eattr; 798 struct arm_cmn_filter_attr *filter; 799 800 eattr = container_of(attr, typeof(*eattr), attr); 801 filter = eattr->filter; 802 803 if (eattr->type == CMN_TYPE_DTC) 804 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 805 806 if (eattr->type == CMN_TYPE_WP) 807 return sysfs_emit(buf, 808 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 809 eattr->type, eattr->eventid); 810 811 if (filter[1].sel) 812 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,filter=0x%x,filter2=0x%x\n", 813 eattr->type, eattr->eventid, filter[0].val, filter[1].val); 814 815 if (filter[0].sel) 816 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,filter=0x%x\n", 817 eattr->type, eattr->eventid, filter[0].val); 818 819 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 820 eattr->eventid); 821 } 822 823 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 824 struct attribute *attr, 825 int unused) 826 { 827 struct device *dev = kobj_to_dev(kobj); 828 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 829 struct arm_cmn_event_attr *eattr; 830 enum cmn_node_type type; 831 u16 eventid; 832 833 eattr = container_of(attr, typeof(*eattr), attr.attr); 834 835 if (!(eattr->model & arm_cmn_model(cmn))) 836 return 0; 837 838 type = eattr->type; 839 eventid = eattr->eventid; 840 841 /* Watchpoints aren't nodes, so avoid confusion */ 842 if (type == CMN_TYPE_WP) 843 return attr->mode; 844 845 /* Hide XP events for unused interfaces/channels */ 846 if (type == CMN_TYPE_XP) { 847 unsigned int intf = (eventid >> 2) & 7; 848 unsigned int chan = eventid >> 5; 849 850 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 851 return 0; 852 853 if (chan == 4 && cmn->part == PART_CMN600) 854 return 0; 855 856 if ((chan == 5 && cmn->rsp_vc_num < 2) || 857 (chan == 6 && cmn->dat_vc_num < 2) || 858 (chan == 7 && cmn->req_vc_num < 2) || 859 (chan == 8 && cmn->snp_vc_num < 2)) 860 return 0; 861 } 862 863 /* Revision-specific differences */ 864 if (cmn->part == PART_CMN600) { 865 if (cmn->rev < REV_CMN600_R1P3) { 866 if (type == CMN_TYPE_CXRA && eventid > 0x10) 867 return 0; 868 } 869 if (cmn->rev < REV_CMN600_R1P2) { 870 if (type == CMN_TYPE_HNF && eventid == 0x1b) 871 return 0; 872 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 873 return 0; 874 } 875 } else if (cmn->part == PART_CMN650) { 876 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) { 877 if (type == CMN_TYPE_HNF && eventid > 0x22) 878 return 0; 879 if (type == CMN_TYPE_SBSX && eventid == 0x17) 880 return 0; 881 if (type == CMN_TYPE_RNI && eventid > 0x10) 882 return 0; 883 } 884 } else if (cmn->part == PART_CMN700) { 885 if (cmn->rev < REV_CMN700_R2P0) { 886 if (type == CMN_TYPE_HNF && eventid > 0x2c) 887 return 0; 888 if (type == CMN_TYPE_CCHA && eventid > 0x74) 889 return 0; 890 if (type == CMN_TYPE_CCLA && eventid > 0x27) 891 return 0; 892 } 893 if (cmn->rev < REV_CMN700_R1P0) { 894 if (type == CMN_TYPE_HNF && eventid > 0x2b) 895 return 0; 896 } 897 } 898 899 if (!arm_cmn_node(cmn, type)) 900 return 0; 901 902 return attr->mode; 903 } 904 905 #define CMN_EVENT_DVM(_model, _name, _event, _filter...) \ 906 CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, ##_filter) 907 #define CMN_EVENT_DTC(_name) \ 908 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 909 #define CMN_EVENT_HNF(_model, _name, _event) \ 910 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event) 911 #define CMN_EVENT_HNI(_name, _event) \ 912 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 913 #define CMN_EVENT_HNP(_name, _event) \ 914 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 915 #define __CMN_EVENT_XP(_name, _event) \ 916 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 917 #define CMN_EVENT_SBSX(_model, _name, _event) \ 918 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 919 #define CMN_EVENT_RNID(_model, _name, _event) \ 920 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 921 #define CMN_EVENT_MTSX(_name, _event) \ 922 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 923 #define CMN_EVENT_CXRA(_model, _name, _event) \ 924 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 925 #define CMN_EVENT_CXHA(_name, _event) \ 926 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 927 #define CMN_EVENT_CCRA(_name, _event) \ 928 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 929 #define CMN_EVENT_CCHA(_model, _name, _event) \ 930 CMN_EVENT_ATTR(_model, ccha_##_name, CMN_TYPE_CCHA, _event) 931 #define CMN_EVENT_CCLA(_name, _event) \ 932 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 933 #define _CMN_EVENT_HNS(_model, _name, _event, _filter...) \ 934 CMN_EVENT_ATTR(_model, hns_##_name, CMN_TYPE_HNS, _event, ##_filter) 935 936 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 937 CMN_EVENT_DVM(_model, _name##_all, _event, SEL_OCCUP1_ID, 0), \ 938 CMN_EVENT_DVM(_model, _name##_dvmop, _event, SEL_OCCUP1_ID, 1), \ 939 CMN_EVENT_DVM(_model, _name##_dvmsync, _event, SEL_OCCUP1_ID, 2) 940 941 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \ 942 CMN_EVENT_ATTR(_model, _name##_all, _type, _event, SEL_OCCUP1_ID, 0), \ 943 CMN_EVENT_ATTR(_model, _name##_read, _type, _event, SEL_OCCUP1_ID, 1), \ 944 CMN_EVENT_ATTR(_model, _name##_write, _type, _event, SEL_OCCUP1_ID, 2), \ 945 CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, SEL_OCCUP1_ID, 3), \ 946 CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, SEL_OCCUP1_ID, 4) 947 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \ 948 CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, SEL_CLASS_OCCUP_ID, 0), \ 949 CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, SEL_CLASS_OCCUP_ID, 1), \ 950 CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, SEL_CLASS_OCCUP_ID, 2), \ 951 CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, SEL_CLASS_OCCUP_ID, 3) 952 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \ 953 CMN_EVENT_ATTR(_model, _name##_all, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 0), \ 954 CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 1), \ 955 CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 2), \ 956 CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 3), \ 957 CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 4), \ 958 CMN_EVENT_ATTR(_model, _name##_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 5), \ 959 CMN_EVENT_ATTR(_model, _name##_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 6), \ 960 CMN_EVENT_ATTR(CMNS3R2, _name##_ccg_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 9), \ 961 CMN_EVENT_ATTR(CMNS3R2, _name##_ccg_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 10), \ 962 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 11), \ 963 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 12), \ 964 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 13) 965 966 #define CMN_EVENT_HNF_OCC(_model, _name, _event) \ 967 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event) 968 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 969 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event) 970 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 971 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event) 972 973 #define CMN_EVENT_HNS(_name, _event) \ 974 _CMN_EVENT_HNS(CMN_ANY, _name, _event) 975 #define CMN_EVENT_HNSR0(_name, _event) \ 976 _CMN_EVENT_HNS(CMN700 | CMNS3R01, _name, _event) 977 #define _CMN_EVENT_HNS_HBT(_model, _name, _event, _sel) \ 978 _CMN_EVENT_HNS(_model, _name##_all, _event, _sel, 0), \ 979 _CMN_EVENT_HNS(_model, _name##_hbt, _event, _sel, 1), \ 980 _CMN_EVENT_HNS(_model, _name##_lbt, _event, _sel, 2) 981 #define _CMN_EVENT_HNS_HBT2(_model, _name, _event, _fsel1, f1) \ 982 _CMN_EVENT_HNS(_model, _name##_all, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 0), \ 983 _CMN_EVENT_HNS(_model, _name##_hbt, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 1), \ 984 _CMN_EVENT_HNS(_model, _name##_lbt, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 2) 985 986 #define CMN_EVENT_HNS_OCC(_model, _name, _event) \ 987 CMN_EVENT_HN_OCC(_model, hns_##_name, CMN_TYPE_HNS, _event), \ 988 _CMN_EVENT_HNS(_model, _name##_rxsnp, _event, SEL_OCCUP1_ID, 5), \ 989 _CMN_EVENT_HNS(_model, _name##_lbt, _event, SEL_OCCUP1_ID, 6), \ 990 _CMN_EVENT_HNS(_model, _name##_hbt, _event, SEL_OCCUP1_ID, 7), \ 991 _CMN_EVENT_HNS(CMNS3R2, _name##_rnf, _event, SEL_OCCUP1_ID, 8), \ 992 _CMN_EVENT_HNS(CMNS3R2, _name##_rni, _event, SEL_OCCUP1_ID, 9), \ 993 _CMN_EVENT_HNS(CMNS3R2, _name##_ccglcn, _event, SEL_OCCUP1_ID, 10), \ 994 _CMN_EVENT_HNS(CMNS3R2, _name##_ccgrn, _event, SEL_OCCUP1_ID, 11) 995 #define CMN_EVENT_HNS_CLS( _name, _event) \ 996 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 997 #define CMN_EVENT_HNSR0_CLS( _name, _event) \ 998 CMN_EVENT_HN_CLS(CMN700 | CMNS3R01, hns_##_name, CMN_TYPE_HNS, _event) 999 #define CMN_EVENT_HNS_SNT(_model, _name, _event) \ 1000 CMN_EVENT_HN_SNT(_model, hns_##_name, CMN_TYPE_HNS, _event) 1001 #define CMN_EVENT_HNS_SNH(_model, _name, _event) \ 1002 _CMN_EVENT_HNS(_model, _name##_all, _event, SEL_SN_HOME_SEL, 0), \ 1003 _CMN_EVENT_HNS(_model, _name##_sn, _event, SEL_SN_HOME_SEL, 1), \ 1004 _CMN_EVENT_HNS(_model, _name##_home, _event, SEL_SN_HOME_SEL, 2) 1005 #define CMN_EVENT_HNS_VC(_name, _event) \ 1006 CMN_EVENT_HNSR0(_name, _event), \ 1007 _CMN_EVENT_HNS(CMNS3R2, _name##_vc0, _event, SEL_SNP_VC_SEL, 0), \ 1008 _CMN_EVENT_HNS(CMNS3R2, _name##_vc1, _event, SEL_SNP_VC_SEL, 1), \ 1009 _CMN_EVENT_HNS(CMNS3R2, _name##_vc2, _event, SEL_SNP_VC_SEL, 2) 1010 #define CMN_EVENT_HNS_ENHBT(_name, _event) \ 1011 _CMN_EVENT_HNS_HBT(CMNS3R2, _name, _event, SEL_ENHANCED_HBT_LBT_SEL), \ 1012 _CMN_EVENT_HNS(CMNS3R2, _name##_rnf, _event, SEL_ENHANCED_HBT_LBT_SEL, 3), \ 1013 _CMN_EVENT_HNS(CMNS3R2, _name##_rni, _event, SEL_ENHANCED_HBT_LBT_SEL, 4), \ 1014 _CMN_EVENT_HNS(CMNS3R2, _name##_ccglcn, _event, SEL_ENHANCED_HBT_LBT_SEL, 5), \ 1015 _CMN_EVENT_HNS(CMNS3R2, _name##_ccgrn, _event, SEL_ENHANCED_HBT_LBT_SEL, 6) 1016 #define CMN_EVENT_HNS_EVICT(_model, _name, _event) \ 1017 _CMN_EVENT_HNS_HBT2(_model, _name##_all, _event, SEL_EVICT_STATE_SEL, 0), \ 1018 _CMN_EVENT_HNS_HBT2(_model, _name##_eu, _event, SEL_EVICT_STATE_SEL, 1), \ 1019 _CMN_EVENT_HNS_HBT2(_model, _name##_en, _event, SEL_EVICT_STATE_SEL, 2), \ 1020 _CMN_EVENT_HNS_HBT2(_model, _name##_su, _event, SEL_EVICT_STATE_SEL, 3), \ 1021 _CMN_EVENT_HNS_HBT2(_model, _name##_sn, _event, SEL_EVICT_STATE_SEL, 4), \ 1022 _CMN_EVENT_HNS_HBT2(_model, _name##_mu, _event, SEL_EVICT_STATE_SEL, 5), \ 1023 _CMN_EVENT_HNS_HBT2(_model, _name##_mn, _event, SEL_EVICT_STATE_SEL, 6) 1024 1025 #define CMN_EVENT_HNSR0_HBT(_name, _event) \ 1026 _CMN_EVENT_HNS_HBT(CMN700 | CMNS3R01, _name, _event, SEL_HBT_LBT_SEL) 1027 #define CMN_EVENT_HNS_R2SNH(_name, _event) \ 1028 CMN_EVENT_HNSR0(_name, _event), \ 1029 CMN_EVENT_HNS_SNH(CMNS3R2, _name, _event) 1030 #define CMN_EVENT_HNS_R2HBT(_name, _event) \ 1031 CMN_EVENT_HNSR0(_name, _event), \ 1032 _CMN_EVENT_HNS_HBT(CMNS3R2, _name, _event, SEL_HBT_LBT_SEL) 1033 #define CMN_EVENT_HNS_HBT_ENHBT(_name, _event) \ 1034 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1035 CMN_EVENT_HNS_ENHBT(_name, _event) 1036 #define CMN_EVENT_HNS_HBT_OCC(_name, _event) \ 1037 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1038 CMN_EVENT_HNS_OCC(CMNS3R2, _name, _event) 1039 #define CMN_EVENT_HNS_HBT_EVICT(_name, _event) \ 1040 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1041 CMN_EVENT_HNS_EVICT(CMNS3R2, _name, _event) 1042 1043 #define _CMN_EVENT_XP_MESH(_name, _event) \ 1044 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 1045 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 1046 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 1047 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)) 1048 1049 #define _CMN_EVENT_XP_PORT(_name, _event) \ 1050 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 1051 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 1052 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 1053 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 1054 1055 #define _CMN_EVENT_XP(_name, _event) \ 1056 _CMN_EVENT_XP_MESH(_name, _event), \ 1057 _CMN_EVENT_XP_PORT(_name, _event) 1058 1059 /* Good thing there are only 3 fundamental XP events... */ 1060 #define CMN_EVENT_XP(_name, _event) \ 1061 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 1062 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 1063 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 1064 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 1065 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 1066 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 1067 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 1068 _CMN_EVENT_XP(req2_##_name, (_event) | (7 << 5)), \ 1069 _CMN_EVENT_XP(snp2_##_name, (_event) | (8 << 5)) 1070 1071 #define CMN_EVENT_XP_DAT(_name, _event) \ 1072 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \ 1073 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5)) 1074 1075 1076 static struct attribute *arm_cmn_event_attrs[] = { 1077 CMN_EVENT_DTC(cycles), 1078 1079 /* 1080 * DVM node events conflict with HN-I events in the equivalent PMU 1081 * slot, but our lazy short-cut of using the DTM counter index for 1082 * the PMU index as well happens to avoid that by construction. 1083 */ 1084 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 1085 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 1086 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 1087 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 1088 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 1089 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 1090 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 1091 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 1092 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 1093 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 1094 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 1095 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 1096 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 1097 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 1098 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 1099 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 1100 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 1101 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_cxha, 0x0d), 1102 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_pdn, 0x0e), 1103 CMN_EVENT_DVM(CMN_700ON, trk_alloc, 0x0f), 1104 CMN_EVENT_DVM(CMN_700ON, trk_cxha_alloc, 0x10), 1105 CMN_EVENT_DVM(CMN_700ON, trk_pdn_alloc, 0x11), 1106 CMN_EVENT_DVM(CMN_700ON, txsnp_stall_limit, 0x12), 1107 CMN_EVENT_DVM(CMN_700ON, rxsnp_stall_starv, 0x13), 1108 CMN_EVENT_DVM(CMN_700ON, txsnp_sync_stall_op, 0x14), 1109 1110 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 1111 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 1112 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 1113 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 1114 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 1115 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 1116 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 1117 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 1118 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 1119 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 1120 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 1121 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 1122 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 1123 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 1124 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 1125 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 1126 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 1127 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 1128 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 1129 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 1130 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 1131 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 1132 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 1133 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 1134 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 1135 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 1136 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 1137 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 1138 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 1139 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 1140 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 1141 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 1142 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 1143 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 1144 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 1145 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 1146 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 1147 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 1148 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 1149 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 1150 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 1151 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 1152 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 1153 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 1154 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 1155 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 1156 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 1157 1158 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 1159 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 1160 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 1161 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 1162 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 1163 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 1164 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 1165 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 1166 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 1167 CMN_EVENT_HNI(wdb_alloc, 0x29), 1168 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 1169 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 1170 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 1171 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 1172 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 1173 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 1174 CMN_EVENT_HNI(txdat_stall, 0x30), 1175 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 1176 CMN_EVENT_HNI(pcie_serialization, 0x32), 1177 1178 /* 1179 * HN-P events squat on top of the HN-I similarly to DVM events, except 1180 * for being crammed into the same physical node as well. And of course 1181 * where would the fun be if the same events were in the same order... 1182 */ 1183 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 1184 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 1185 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 1186 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 1187 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 1188 CMN_EVENT_HNP(wdb_alloc, 0x06), 1189 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 1190 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 1191 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 1192 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 1193 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 1194 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 1195 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 1196 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 1197 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 1198 1199 CMN_EVENT_XP(txflit_valid, 0x01), 1200 CMN_EVENT_XP(txflit_stall, 0x02), 1201 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03), 1202 /* We treat watchpoints as a special made-up class of XP events */ 1203 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 1204 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 1205 1206 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 1207 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 1208 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 1209 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 1210 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 1211 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 1212 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 1213 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 1214 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 1215 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 1216 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 1217 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 1218 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 1219 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 1220 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 1221 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 1222 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 1223 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 1224 1225 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 1226 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 1227 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 1228 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 1229 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 1230 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 1231 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 1232 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 1233 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 1234 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 1235 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 1236 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 1237 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 1238 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 1239 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 1240 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 1241 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 1242 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 1243 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 1244 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 1245 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 1246 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 1247 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 1248 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 1249 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 1250 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 1251 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 1252 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 1253 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 1254 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 1255 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 1256 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 1257 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 1258 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 1259 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 1260 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 1261 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 1262 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 1263 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 1264 1265 CMN_EVENT_MTSX(tc_lookup, 0x01), 1266 CMN_EVENT_MTSX(tc_fill, 0x02), 1267 CMN_EVENT_MTSX(tc_miss, 0x03), 1268 CMN_EVENT_MTSX(tdb_forward, 0x04), 1269 CMN_EVENT_MTSX(tcq_hazard, 0x05), 1270 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 1271 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 1272 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 1273 CMN_EVENT_MTSX(axi_rd_req, 0x09), 1274 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 1275 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 1276 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 1277 1278 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 1279 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 1280 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 1281 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 1282 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1283 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1284 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1285 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1286 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1287 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1288 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1289 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1290 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1291 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1292 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1293 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1294 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1295 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1296 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1297 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1298 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1299 1300 CMN_EVENT_CXHA(rddatbyp, 0x21), 1301 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1302 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1303 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1304 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1305 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1306 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1307 CMN_EVENT_CXHA(rdb_occ, 0x28), 1308 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1309 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1310 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1311 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1312 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1313 1314 CMN_EVENT_CCRA(rht_occ, 0x41), 1315 CMN_EVENT_CCRA(sht_occ, 0x42), 1316 CMN_EVENT_CCRA(rdb_occ, 0x43), 1317 CMN_EVENT_CCRA(wdb_occ, 0x44), 1318 CMN_EVENT_CCRA(ssb_occ, 0x45), 1319 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1320 CMN_EVENT_CCRA(req_chains, 0x47), 1321 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1322 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1323 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1324 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1325 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1326 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1327 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1328 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1329 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1330 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1331 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1332 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1333 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1334 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1335 CMN_EVENT_CCRA(rht_alloc, 0x56), 1336 CMN_EVENT_CCRA(sht_alloc, 0x57), 1337 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1338 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1339 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1340 1341 CMN_EVENT_CCHA(CMN_ANY, rddatbyp, 0x61), 1342 CMN_EVENT_CCHA(CMN_ANY, chirsp_up_stall, 0x62), 1343 CMN_EVENT_CCHA(CMN_ANY, chidat_up_stall, 0x63), 1344 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link0_stall, 0x64), 1345 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link1_stall, 0x65), 1346 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link2_stall, 0x66), 1347 CMN_EVENT_CCHA(CMN_ANY, reqtrk_occ, 0x67), 1348 CMN_EVENT_CCHA(CMN_ANY, rdb_occ, 0x68), 1349 CMN_EVENT_CCHA(CMN_ANY, rdbyp_occ, 0x69), 1350 CMN_EVENT_CCHA(CMN_ANY, wdb_occ, 0x6a), 1351 CMN_EVENT_CCHA(CMN_ANY, snptrk_occ, 0x6b), 1352 CMN_EVENT_CCHA(CMN_ANY, sdb_occ, 0x6c), 1353 CMN_EVENT_CCHA(CMN_ANY, snphaz_occ, 0x6d), 1354 CMN_EVENT_CCHA(CMN_ANY, reqtrk_alloc, 0x6e), 1355 CMN_EVENT_CCHA(CMN_ANY, rdb_alloc, 0x6f), 1356 CMN_EVENT_CCHA(CMN_ANY, rdbyp_alloc, 0x70), 1357 CMN_EVENT_CCHA(CMN_ANY, wdb_alloc, 0x71), 1358 CMN_EVENT_CCHA(CMN_ANY, snptrk_alloc, 0x72), 1359 CMN_EVENT_CCHA(CMN_ANY, db_alloc, 0x73), 1360 CMN_EVENT_CCHA(CMN_ANY, snphaz_alloc, 0x74), 1361 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_occ, 0x75), 1362 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_alloc, 0x76), 1363 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_occ, 0x77), 1364 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_alloc, 0x78), 1365 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_occ, 0x79), 1366 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_alloc, 0x7a), 1367 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_occ, 0x7b), 1368 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_alloc, 0x7c), 1369 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_occ, 0x7d), 1370 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_alloc, 0x7e), 1371 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_occ, 0x7f), 1372 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_alloc, 0x80), 1373 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_occ, 0x81), 1374 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_alloc, 0x82), 1375 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_occ, 0x83), 1376 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_alloc, 0x84), 1377 CMN_EVENT_CCHA(CMNS3, chirsp1_up_stall, 0x85), 1378 1379 CMN_EVENT_CCLA(rx_cxs, 0x21), 1380 CMN_EVENT_CCLA(tx_cxs, 0x22), 1381 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1382 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1383 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1384 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1385 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1386 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1387 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1388 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1389 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1390 1391 CMN_EVENT_HNS_HBT_ENHBT(cache_miss, 0x01), 1392 CMN_EVENT_HNS_HBT_ENHBT(slc_sf_cache_access, 0x02), 1393 CMN_EVENT_HNS_HBT_ENHBT(cache_fill, 0x03), 1394 CMN_EVENT_HNS_HBT_OCC(pocq_retry, 0x04), 1395 CMN_EVENT_HNS_HBT_OCC(pocq_reqs_recvd, 0x05), 1396 CMN_EVENT_HNS_HBT_ENHBT(sf_hit, 0x06), 1397 CMN_EVENT_HNS_HBT_EVICT(sf_evictions, 0x07), 1398 CMN_EVENT_HNS_VC(dir_snoops_sent, 0x08), 1399 CMN_EVENT_HNS_VC(brd_snoops_sent, 0x09), 1400 CMN_EVENT_HNS_HBT_EVICT(slc_eviction, 0x0a), 1401 CMN_EVENT_HNS_HBT_ENHBT(slc_fill_invalid_way, 0x0b), 1402 CMN_EVENT_HNS_R2SNH(mc_retries_local, 0x0c), 1403 CMN_EVENT_HNS_SNH(CMN_ANY, mc_reqs_local, 0x0d), 1404 CMN_EVENT_HNS(qos_hh_retry, 0x0e), 1405 CMN_EVENT_HNS_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 1406 CMN_EVENT_HNS_HBT_ENHBT(pocq_addrhaz, 0x10), 1407 CMN_EVENT_HNS_HBT_ENHBT(pocq_atomic_addrhaz, 0x11), 1408 CMN_EVENT_HNSR0(ld_st_swp_adq_full, 0x12), 1409 CMN_EVENT_HNSR0(cmp_adq_full, 0x13), 1410 CMN_EVENT_HNS(txdat_stall, 0x14), 1411 CMN_EVENT_HNS(txrsp_stall, 0x15), 1412 CMN_EVENT_HNSR0(seq_full, 0x16), 1413 CMN_EVENT_HNS(seq_hit, 0x17), 1414 CMN_EVENT_HNS_VC(snp_sent, 0x18), 1415 CMN_EVENT_HNS_VC(sfbi_dir_snp_sent, 0x19), 1416 CMN_EVENT_HNS_VC(sfbi_brd_snp_sent, 0x1a), 1417 CMN_EVENT_HNS(intv_dirty, 0x1c), 1418 CMN_EVENT_HNSR0(stash_snp_sent, 0x1d), 1419 CMN_EVENT_HNSR0(stash_data_pull, 0x1e), 1420 CMN_EVENT_HNS_VC(snp_fwded, 0x1f), 1421 CMN_EVENT_HNSR0(atomic_fwd, 0x20), 1422 CMN_EVENT_HNS(mpam_hardlim, 0x21), 1423 CMN_EVENT_HNS(mpam_softlim, 0x22), 1424 CMN_EVENT_HNS_VC(snp_sent_cluster, 0x23), 1425 CMN_EVENT_HNS_R2HBT(sf_imprecise_evict, 0x24), 1426 CMN_EVENT_HNS(sf_evict_shared_line, 0x25), 1427 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26), 1428 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27), 1429 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28), 1430 CMN_EVENT_HNSR0_CLS(class_cgnt_cmin, 0x29), 1431 CMN_EVENT_HNS_SNT(CMN_ANY, sn_throttle, 0x2a), 1432 CMN_EVENT_HNS_SNT(CMN_ANY, sn_throttle_min, 0x2b), 1433 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c), 1434 CMN_EVENT_HNS(snp_intv_cln, 0x2d), 1435 CMN_EVENT_HNS(nc_excl, 0x2e), 1436 CMN_EVENT_HNSR0(excl_mon_ovfl, 0x2f), 1437 CMN_EVENT_HNS(snp_req_recvd, 0x30), 1438 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31), 1439 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32), 1440 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33), 1441 CMN_EVENT_HNSR0(ccgha_snp_stall, 0x34), 1442 CMN_EVENT_HNS(lbt_req_hardlim, 0x35), 1443 CMN_EVENT_HNS(hbt_req_hardlim, 0x36), 1444 CMN_EVENT_HNS(sf_reupdate, 0x37), 1445 CMN_EVENT_HNS_R2HBT(excl_sf_imprecise, 0x38), 1446 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39), 1447 CMN_EVENT_HNS_R2SNH(mc_retries_remote, 0x3a), 1448 CMN_EVENT_HNS_SNH(CMN_ANY, mc_reqs_remote, 0x3b), 1449 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c), 1450 CMN_EVENT_HNS_ENHBT(readonce_hazard_detected, 0x3d), 1451 CMN_EVENT_HNS_ENHBT(readonce_fwd_data_completed, 0x3e), 1452 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy00, 0x40), 1453 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy01, 0x41), 1454 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy10, 0x42), 1455 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy11, 0x43), 1456 CMN_EVENT_HNS_ENHBT(ro_rnsd_new_alloc_hint, 0x44), 1457 1458 NULL 1459 }; 1460 1461 static const struct attribute_group arm_cmn_event_attrs_group = { 1462 .name = "events", 1463 .attrs = arm_cmn_event_attrs, 1464 .is_visible = arm_cmn_event_attr_is_visible, 1465 }; 1466 1467 static ssize_t arm_cmn_format_show(struct device *dev, 1468 struct device_attribute *attr, char *buf) 1469 { 1470 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1471 1472 if (!fmt->config) 1473 return sysfs_emit(buf, "config:%*pbl\n", 64, &fmt->field); 1474 1475 return sysfs_emit(buf, "config%d:%*pbl\n", fmt->config, 64, &fmt->field); 1476 } 1477 1478 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1479 (&((struct arm_cmn_format_attr[]) {{ \ 1480 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1481 .config = _cfg, \ 1482 .field = _fld, \ 1483 }})[0].attr.attr) 1484 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1485 1486 static struct attribute *arm_cmn_format_attrs[] = { 1487 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1488 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1489 CMN_FORMAT_ATTR(filter, CMN_CONFIG_FILTER), 1490 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1491 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1492 CMN_FORMAT_ATTR(filter2, CMN_CONFIG_FILTER2), 1493 1494 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1495 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1496 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1497 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1498 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1499 1500 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1501 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1502 1503 /* Old name for UAPI compatibility */ 1504 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_FILTER), 1505 1506 NULL 1507 }; 1508 1509 static const struct attribute_group arm_cmn_format_attrs_group = { 1510 .name = "format", 1511 .attrs = arm_cmn_format_attrs, 1512 }; 1513 1514 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1515 struct device_attribute *attr, char *buf) 1516 { 1517 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1518 1519 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpumask_of(cmn->cpu))); 1520 } 1521 1522 static struct device_attribute arm_cmn_cpumask_attr = 1523 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1524 1525 static ssize_t arm_cmn_identifier_show(struct device *dev, 1526 struct device_attribute *attr, char *buf) 1527 { 1528 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1529 1530 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev); 1531 } 1532 1533 static struct device_attribute arm_cmn_identifier_attr = 1534 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL); 1535 1536 static struct attribute *arm_cmn_other_attrs[] = { 1537 &arm_cmn_cpumask_attr.attr, 1538 &arm_cmn_identifier_attr.attr, 1539 NULL, 1540 }; 1541 1542 static const struct attribute_group arm_cmn_other_attrs_group = { 1543 .attrs = arm_cmn_other_attrs, 1544 }; 1545 1546 static const struct attribute_group *arm_cmn_attr_groups[] = { 1547 &arm_cmn_event_attrs_group, 1548 &arm_cmn_format_attrs_group, 1549 &arm_cmn_other_attrs_group, 1550 NULL 1551 }; 1552 1553 static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm, 1554 struct perf_event *event) 1555 { 1556 int wp_idx = CMN_EVENT_EVENTID(event); 1557 1558 if (dtm->wp_event[wp_idx] >= 0) 1559 if (dtm->wp_event[++wp_idx] >= 0) 1560 return -ENOSPC; 1561 1562 return wp_idx; 1563 } 1564 1565 static int arm_cmn_get_assigned_wp_idx(struct perf_event *event, 1566 struct arm_cmn_hw_event *hw, 1567 unsigned int pos) 1568 { 1569 return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw, pos); 1570 } 1571 1572 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm, 1573 struct perf_event *event, 1574 unsigned int dtc, int wp_idx, 1575 unsigned int pos) 1576 { 1577 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1578 1579 dtm->wp_event[wp_idx] = hw->dtc_idx[dtc]; 1580 arm_cmn_set_wp_idx(hw, pos, wp_idx - CMN_EVENT_EVENTID(event)); 1581 } 1582 1583 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx) 1584 { 1585 struct arm_cmn *cmn = to_cmn(event->pmu); 1586 u32 config; 1587 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1588 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1589 u32 grp = CMN_EVENT_WP_GRP(event); 1590 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1591 u32 combine = CMN_EVENT_WP_COMBINE(event); 1592 bool is_cmn600 = cmn->part == PART_CMN600; 1593 1594 /* CMN-600 supports only primary and secondary matching groups */ 1595 if (is_cmn600) 1596 grp &= 1; 1597 1598 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1599 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1600 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp); 1601 1602 if (!cmn->multi_dtm) 1603 config |= FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1604 1605 if (exc) 1606 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1607 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1608 1609 /* wp_combine is available only on WP0 and WP2 */ 1610 if (combine && !(wp_idx & 0x1)) 1611 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1612 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1613 return config; 1614 } 1615 1616 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1617 { 1618 if (!cmn->state) 1619 writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0])); 1620 cmn->state |= state; 1621 } 1622 1623 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1624 { 1625 cmn->state &= ~state; 1626 if (!cmn->state) 1627 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1628 CMN_DT_PMCR(&cmn->dtc[0])); 1629 } 1630 1631 static void arm_cmn_pmu_enable(struct pmu *pmu) 1632 { 1633 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1634 } 1635 1636 static void arm_cmn_pmu_disable(struct pmu *pmu) 1637 { 1638 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1639 } 1640 1641 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1642 bool snapshot) 1643 { 1644 struct arm_cmn_dtm *dtm = NULL; 1645 struct arm_cmn_node *dn; 1646 unsigned int i, offset, dtm_idx; 1647 u64 reg, count = 0; 1648 1649 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1650 for_each_hw_dn(hw, dn, i) { 1651 if (dtm != &cmn->dtms[dn->dtm]) { 1652 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1653 reg = readq_relaxed(dtm->base + offset); 1654 } 1655 dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1656 count += (u16)(reg >> (dtm_idx * 16)); 1657 } 1658 return count; 1659 } 1660 1661 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1662 { 1663 void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc); 1664 u64 val = readq_relaxed(pmccntr); 1665 1666 writeq_relaxed(CMN_CC_INIT, pmccntr); 1667 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1668 } 1669 1670 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1671 { 1672 void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx); 1673 u32 val = readl_relaxed(pmevcnt); 1674 1675 writel_relaxed(CMN_COUNTER_INIT, pmevcnt); 1676 return val - CMN_COUNTER_INIT; 1677 } 1678 1679 static void arm_cmn_init_counter(struct perf_event *event) 1680 { 1681 struct arm_cmn *cmn = to_cmn(event->pmu); 1682 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1683 u64 count; 1684 1685 for_each_hw_dtc_idx(hw, i, idx) { 1686 writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx)); 1687 cmn->dtc[i].counters[idx] = event; 1688 } 1689 1690 count = arm_cmn_read_dtm(cmn, hw, false); 1691 local64_set(&event->hw.prev_count, count); 1692 } 1693 1694 static void arm_cmn_event_read(struct perf_event *event) 1695 { 1696 struct arm_cmn *cmn = to_cmn(event->pmu); 1697 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1698 u64 delta, new, prev; 1699 unsigned long flags; 1700 1701 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) { 1702 delta = arm_cmn_read_cc(cmn->dtc + hw->cc_idx); 1703 local64_add(delta, &event->count); 1704 return; 1705 } 1706 new = arm_cmn_read_dtm(cmn, hw, false); 1707 prev = local64_xchg(&event->hw.prev_count, new); 1708 1709 delta = new - prev; 1710 1711 local_irq_save(flags); 1712 for_each_hw_dtc_idx(hw, i, idx) { 1713 new = arm_cmn_read_counter(cmn->dtc + i, idx); 1714 delta += new << 16; 1715 } 1716 local_irq_restore(flags); 1717 local64_add(delta, &event->count); 1718 } 1719 1720 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1721 enum cmn_filter_select fsel, u8 val) 1722 { 1723 if (!dn->filter[fsel].count) { 1724 const u64 *filter = arm_cmn_filters[dn->filter[SEL_NONE].val]; 1725 u64 reg = 0; 1726 1727 dn->filter[fsel].val = val; 1728 for (int i = SEL_OCCUP1_ID; i < SEL_MAX; i++) { 1729 if (filter[i]) 1730 reg |= field_prep(filter[i], dn->filter[i].val); 1731 } 1732 1733 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1734 } else if (dn->filter[fsel].val != val) { 1735 return -EBUSY; 1736 } 1737 dn->filter[fsel].count++; 1738 return 0; 1739 } 1740 1741 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1742 int eventid, bool wide_sel) 1743 { 1744 if (wide_sel) { 1745 dn->event_w[dtm_idx] = eventid; 1746 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1747 } else { 1748 dn->event[dtm_idx] = eventid; 1749 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1750 } 1751 } 1752 1753 static void arm_cmn_event_start(struct perf_event *event, int flags) 1754 { 1755 struct arm_cmn *cmn = to_cmn(event->pmu); 1756 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1757 struct arm_cmn_node *dn; 1758 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1759 int i; 1760 1761 if (type == CMN_TYPE_DTC) { 1762 struct arm_cmn_dtc *dtc = cmn->dtc + hw->cc_idx; 1763 1764 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE, 1765 dtc->base + CMN_DT_DTC_CTL); 1766 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); 1767 dtc->cc_active = true; 1768 } else if (type == CMN_TYPE_WP) { 1769 u64 val = CMN_EVENT_WP_VAL(event); 1770 u64 mask = CMN_EVENT_WP_MASK(event); 1771 1772 for_each_hw_dn(hw, dn, i) { 1773 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1774 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1775 1776 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1777 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1778 } 1779 } else for_each_hw_dn(hw, dn, i) { 1780 int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1781 1782 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1783 hw->wide_sel); 1784 } 1785 } 1786 1787 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1788 { 1789 struct arm_cmn *cmn = to_cmn(event->pmu); 1790 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1791 struct arm_cmn_node *dn; 1792 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1793 int i; 1794 1795 if (type == CMN_TYPE_DTC) { 1796 struct arm_cmn_dtc *dtc = cmn->dtc + hw->cc_idx; 1797 1798 dtc->cc_active = false; 1799 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 1800 } else if (type == CMN_TYPE_WP) { 1801 for_each_hw_dn(hw, dn, i) { 1802 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1803 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1804 1805 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1806 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1807 } 1808 } else for_each_hw_dn(hw, dn, i) { 1809 int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1810 1811 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1812 } 1813 1814 arm_cmn_event_read(event); 1815 } 1816 1817 struct arm_cmn_val { 1818 u8 dtm_count[CMN_MAX_DTMS]; 1819 u8 filter[CMN_MAX_DTMS][SEL_MAX]; 1820 u8 wp[CMN_MAX_DTMS][4]; 1821 u8 wp_combine[CMN_MAX_DTMS][2]; 1822 int dtc_count[CMN_MAX_DTCS]; 1823 bool cycles; 1824 }; 1825 1826 static int arm_cmn_val_find_free_wp_config(struct perf_event *event, 1827 struct arm_cmn_val *val, int dtm) 1828 { 1829 int wp_idx = CMN_EVENT_EVENTID(event); 1830 1831 if (val->wp[dtm][wp_idx]) 1832 if (val->wp[dtm][++wp_idx]) 1833 return -ENOSPC; 1834 1835 return wp_idx; 1836 } 1837 1838 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1839 struct perf_event *event) 1840 { 1841 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1842 struct arm_cmn_node *dn; 1843 enum cmn_node_type type; 1844 int i; 1845 1846 if (is_software_event(event)) 1847 return; 1848 1849 type = CMN_EVENT_TYPE(event); 1850 if (type == CMN_TYPE_DTC) { 1851 val->cycles = true; 1852 return; 1853 } 1854 1855 for_each_hw_dtc_idx(hw, dtc, idx) 1856 val->dtc_count[dtc]++; 1857 1858 for_each_hw_dn(hw, dn, i) { 1859 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1860 1861 val->dtm_count[dtm]++; 1862 1863 if (sel) 1864 val->filter[dtm][sel] = CMN_EVENT_FILTER(event) + 1; 1865 if (sel == SEL_EVICT_STATE_SEL) 1866 val->filter[dtm][SEL_HBT_LBT_SEL] = CMN_EVENT_FILTER2(event) + 1; 1867 1868 if (type != CMN_TYPE_WP) 1869 continue; 1870 1871 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1872 val->wp[dtm][wp_idx] = 1; 1873 val->wp_combine[dtm][wp_idx >> 1] += !!CMN_EVENT_WP_COMBINE(event); 1874 } 1875 } 1876 1877 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1878 { 1879 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1880 struct arm_cmn_node *dn; 1881 struct perf_event *sibling, *leader = event->group_leader; 1882 enum cmn_node_type type; 1883 struct arm_cmn_val *val; 1884 int i, ret = -EINVAL; 1885 1886 if (leader == event) 1887 return 0; 1888 1889 if (event->pmu != leader->pmu && !is_software_event(leader)) 1890 return -EINVAL; 1891 1892 val = kzalloc_obj(*val); 1893 if (!val) 1894 return -ENOMEM; 1895 1896 arm_cmn_val_add_event(cmn, val, leader); 1897 1898 for_each_sibling_event(sibling, leader) 1899 arm_cmn_val_add_event(cmn, val, sibling); 1900 1901 type = CMN_EVENT_TYPE(event); 1902 if (type == CMN_TYPE_DTC) { 1903 ret = val->cycles ? -EINVAL : 0; 1904 goto done; 1905 } 1906 1907 for_each_hw_dtc_idx(hw, dtc, idx) 1908 if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS) 1909 goto done; 1910 1911 for_each_hw_dn(hw, dn, i) { 1912 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1913 1914 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1915 goto done; 1916 1917 if (sel && val->filter[dtm][sel] && 1918 val->filter[dtm][sel] != CMN_EVENT_FILTER(event) + 1) 1919 goto done; 1920 1921 if (sel == SEL_EVICT_STATE_SEL && val->filter[dtm][SEL_HBT_LBT_SEL] && 1922 val->filter[dtm][SEL_HBT_LBT_SEL] != CMN_EVENT_FILTER2(event) + 1) 1923 goto done; 1924 1925 if (type != CMN_TYPE_WP) 1926 continue; 1927 1928 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1929 if (wp_idx < 0) 1930 goto done; 1931 1932 if (wp_idx & 1 && 1933 val->wp_combine[dtm][wp_idx >> 1] != !!CMN_EVENT_WP_COMBINE(event)) 1934 goto done; 1935 } 1936 1937 ret = 0; 1938 done: 1939 kfree(val); 1940 return ret; 1941 } 1942 1943 static enum cmn_filter_select arm_cmn_event_filter(const struct arm_cmn *cmn, 1944 enum cmn_node_type type, 1945 unsigned int eventid) 1946 { 1947 struct arm_cmn_event_attr *e; 1948 enum cmn_model model = arm_cmn_model(cmn); 1949 1950 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1951 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1952 if (e->model & model && e->type == type && e->eventid == eventid) 1953 return e->filter[0].sel; 1954 } 1955 return SEL_NONE; 1956 } 1957 1958 1959 static void arm_cmn_event_destroy(struct perf_event *event) 1960 { 1961 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1962 1963 bitmap_free(hw->dtm_idx); 1964 bitmap_free(hw->wp_idx); 1965 } 1966 1967 static int arm_cmn_event_init(struct perf_event *event) 1968 { 1969 struct arm_cmn *cmn = to_cmn(event->pmu); 1970 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1971 struct arm_cmn_node *dn; 1972 enum cmn_node_type type; 1973 bool bynodeid; 1974 u16 nodeid, eventid; 1975 1976 if (event->attr.type != event->pmu->type) 1977 return -ENOENT; 1978 1979 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1980 return -EINVAL; 1981 1982 event->cpu = cmn->cpu; 1983 if (event->cpu < 0) 1984 return -EINVAL; 1985 1986 type = CMN_EVENT_TYPE(event); 1987 /* DTC events (i.e. cycles) already have everything they need */ 1988 if (type == CMN_TYPE_DTC) 1989 return arm_cmn_validate_group(cmn, event); 1990 1991 event->destroy = arm_cmn_event_destroy; 1992 hw->dtm_idx = arm_cmn_alloc_dtm_idx(); 1993 if (!hw->dtm_idx) 1994 return -ENOMEM; 1995 1996 eventid = CMN_EVENT_EVENTID(event); 1997 /* For watchpoints we need the actual XP node here */ 1998 if (type == CMN_TYPE_WP) { 1999 type = CMN_TYPE_XP; 2000 /* ...and we need a "real" direction */ 2001 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 2002 return -EINVAL; 2003 /* ...but the DTM may depend on which port we're watching */ 2004 if (cmn->multi_dtm) 2005 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 2006 hw->wp_idx = arm_cmn_alloc_wp_idx(); 2007 if (!hw->wp_idx) 2008 return -ENOMEM; 2009 } else if (type == CMN_TYPE_XP && 2010 (cmn->part == PART_CMN700 || cmn->part == PART_CMN_S3)) { 2011 hw->wide_sel = true; 2012 } else if (type == CMN_TYPE_RND) { 2013 /* Secretly permit this as an alias for "rnid" events */ 2014 type = CMN_TYPE_RNI; 2015 } 2016 2017 /* This is sufficiently annoying to recalculate, so cache it */ 2018 hw->filter_sel = arm_cmn_event_filter(cmn, type, eventid); 2019 2020 bynodeid = CMN_EVENT_BYNODEID(event); 2021 nodeid = CMN_EVENT_NODEID(event); 2022 2023 hw->dn = arm_cmn_node(cmn, type); 2024 if (!hw->dn) 2025 return -EINVAL; 2026 2027 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx)); 2028 for (dn = hw->dn; dn->type == type; dn++) { 2029 if (bynodeid && dn->id != nodeid) { 2030 hw->dn++; 2031 continue; 2032 } 2033 hw->num_dns++; 2034 if (dn->dtc < 0) 2035 memset(hw->dtc_idx, 0, cmn->num_dtcs); 2036 else 2037 hw->dtc_idx[dn->dtc] = 0; 2038 2039 if (bynodeid) 2040 break; 2041 } 2042 2043 if (!hw->num_dns) { 2044 dev_dbg(cmn->dev, "invalid node 0x%x type 0x%x\n", nodeid, type); 2045 return -EINVAL; 2046 } 2047 2048 return arm_cmn_validate_group(cmn, event); 2049 } 2050 2051 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 2052 int i) 2053 { 2054 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2055 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2056 2057 while (i--) { 2058 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 2059 unsigned int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 2060 2061 if (type == CMN_TYPE_WP) { 2062 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 2063 2064 dtm->wp_event[wp_idx] = -1; 2065 } 2066 2067 if (hw->filter_sel) 2068 hw->dn[i].filter[hw->filter_sel].count--; 2069 if (hw->filter_sel == SEL_EVICT_STATE_SEL) 2070 hw->dn[i].filter[SEL_HBT_LBT_SEL].count--; 2071 2072 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 2073 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2074 } 2075 arm_cmn_clear_idx(hw); 2076 2077 for_each_hw_dtc_idx(hw, j, idx) 2078 cmn->dtc[j].counters[idx] = NULL; 2079 } 2080 2081 static int arm_cmn_set_event_filter(struct arm_cmn_node *dn, struct perf_event *event) 2082 { 2083 enum cmn_filter_select fsel = to_cmn_hw(event)->filter_sel; 2084 int ret = 0; 2085 2086 if (fsel) 2087 ret = arm_cmn_set_event_sel_hi(dn, fsel, CMN_EVENT_FILTER(event)); 2088 2089 if (fsel == SEL_EVICT_STATE_SEL && !ret) { 2090 ret = arm_cmn_set_event_sel_hi(dn, SEL_HBT_LBT_SEL, CMN_EVENT_FILTER2(event)); 2091 if (ret) 2092 dn->filter[fsel].count--; 2093 } 2094 return ret; 2095 } 2096 2097 static int arm_cmn_event_add(struct perf_event *event, int flags) 2098 { 2099 struct arm_cmn *cmn = to_cmn(event->pmu); 2100 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2101 struct arm_cmn_node *dn; 2102 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2103 unsigned int input_sel, i = 0; 2104 2105 if (type == CMN_TYPE_DTC) { 2106 while (cmn->dtc[i].cycles) 2107 if (++i == cmn->num_dtcs) 2108 return -ENOSPC; 2109 2110 cmn->dtc[i].cycles = event; 2111 hw->cc_idx = i; 2112 2113 if (flags & PERF_EF_START) 2114 arm_cmn_event_start(event, 0); 2115 return 0; 2116 } 2117 2118 /* Grab the global counters first... */ 2119 for_each_hw_dtc_idx(hw, j, idx) { 2120 if (cmn->part == PART_CMN600 && j > 0) { 2121 idx = hw->dtc_idx[0]; 2122 } else { 2123 idx = 0; 2124 while (cmn->dtc[j].counters[idx]) 2125 if (++idx == CMN_DT_NUM_COUNTERS) 2126 return -ENOSPC; 2127 } 2128 hw->dtc_idx[j] = idx; 2129 } 2130 2131 /* ...then the local counters to feed them */ 2132 for_each_hw_dn(hw, dn, i) { 2133 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 2134 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0); 2135 u64 reg; 2136 2137 dtm_idx = 0; 2138 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 2139 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 2140 goto free_dtms; 2141 2142 if (type == CMN_TYPE_XP) { 2143 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 2144 } else if (type == CMN_TYPE_WP) { 2145 int tmp, wp_idx; 2146 u32 cfg; 2147 2148 wp_idx = arm_cmn_find_free_wp_idx(dtm, event); 2149 if (wp_idx < 0) 2150 goto free_dtms; 2151 2152 cfg = arm_cmn_wp_config(event, wp_idx); 2153 2154 tmp = dtm->wp_event[wp_idx ^ 1]; 2155 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 2156 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp])) 2157 goto free_dtms; 2158 2159 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 2160 2161 arm_cmn_claim_wp_idx(dtm, event, d, wp_idx, i); 2162 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 2163 } else { 2164 struct arm_cmn_nodeid nid = arm_cmn_nid(dn); 2165 2166 if (cmn->multi_dtm) 2167 nid.port %= 2; 2168 2169 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 2170 (nid.port << 4) + (nid.dev << 2); 2171 2172 if (arm_cmn_set_event_filter(dn, event)) 2173 goto free_dtms; 2174 } 2175 2176 arm_cmn_set_dtm_idx(hw, i, dtm_idx); 2177 2178 dtm->input_sel[dtm_idx] = input_sel; 2179 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 2180 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 2181 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift; 2182 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 2183 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 2184 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 2185 } 2186 2187 /* Go go go! */ 2188 arm_cmn_init_counter(event); 2189 2190 if (flags & PERF_EF_START) 2191 arm_cmn_event_start(event, 0); 2192 2193 return 0; 2194 2195 free_dtms: 2196 arm_cmn_event_clear(cmn, event, i); 2197 return -ENOSPC; 2198 } 2199 2200 static void arm_cmn_event_del(struct perf_event *event, int flags) 2201 { 2202 struct arm_cmn *cmn = to_cmn(event->pmu); 2203 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2204 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2205 2206 arm_cmn_event_stop(event, PERF_EF_UPDATE); 2207 2208 if (type == CMN_TYPE_DTC) 2209 cmn->dtc[hw->cc_idx].cycles = NULL; 2210 else 2211 arm_cmn_event_clear(cmn, event, hw->num_dns); 2212 } 2213 2214 /* 2215 * We stop the PMU for both add and read, to avoid skew across DTM counters. 2216 * In theory we could use snapshots to read without stopping, but then it 2217 * becomes a lot trickier to deal with overlow and racing against interrupts, 2218 * plus it seems they don't work properly on some hardware anyway :( 2219 */ 2220 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 2221 { 2222 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 2223 } 2224 2225 static void arm_cmn_end_txn(struct pmu *pmu) 2226 { 2227 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 2228 } 2229 2230 static int arm_cmn_commit_txn(struct pmu *pmu) 2231 { 2232 arm_cmn_end_txn(pmu); 2233 return 0; 2234 } 2235 2236 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 2237 { 2238 unsigned int i; 2239 2240 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 2241 for (i = 0; i < cmn->num_dtcs; i++) 2242 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 2243 cmn->cpu = cpu; 2244 } 2245 2246 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2247 { 2248 struct arm_cmn *cmn; 2249 int node; 2250 2251 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2252 node = dev_to_node(cmn->dev); 2253 if (cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 2254 arm_cmn_migrate(cmn, cpu); 2255 return 0; 2256 } 2257 2258 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2259 { 2260 struct arm_cmn *cmn; 2261 unsigned int target; 2262 int node; 2263 2264 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2265 if (cpu != cmn->cpu) 2266 return 0; 2267 2268 node = dev_to_node(cmn->dev); 2269 2270 target = cpumask_any_and_but(cpumask_of_node(node), cpu_online_mask, cpu); 2271 if (target >= nr_cpu_ids) 2272 target = cpumask_any_but(cpu_online_mask, cpu); 2273 2274 if (target < nr_cpu_ids) 2275 arm_cmn_migrate(cmn, target); 2276 2277 return 0; 2278 } 2279 2280 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 2281 { 2282 struct arm_cmn_dtc *dtc = dev_id; 2283 irqreturn_t ret = IRQ_NONE; 2284 2285 for (;;) { 2286 u32 status = readl_relaxed(CMN_DT_PMOVSR(dtc)); 2287 u64 delta; 2288 int i; 2289 2290 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) { 2291 if (status & (1U << i)) { 2292 ret = IRQ_HANDLED; 2293 if (WARN_ON(!dtc->counters[i])) 2294 continue; 2295 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 2296 local64_add(delta, &dtc->counters[i]->count); 2297 } 2298 } 2299 2300 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 2301 ret = IRQ_HANDLED; 2302 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 2303 delta = arm_cmn_read_cc(dtc); 2304 local64_add(delta, &dtc->cycles->count); 2305 } 2306 } 2307 2308 writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc)); 2309 2310 if (!dtc->irq_friend) 2311 return ret; 2312 dtc += dtc->irq_friend; 2313 } 2314 } 2315 2316 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 2317 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 2318 { 2319 int i, j, irq, err; 2320 2321 for (i = 0; i < cmn->num_dtcs; i++) { 2322 irq = cmn->dtc[i].irq; 2323 for (j = i; j--; ) { 2324 if (cmn->dtc[j].irq == irq) { 2325 cmn->dtc[j].irq_friend = i - j; 2326 goto next; 2327 } 2328 } 2329 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 2330 IRQF_NOBALANCING | IRQF_NO_THREAD, 2331 dev_name(cmn->dev), &cmn->dtc[i]); 2332 if (err) 2333 return err; 2334 2335 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 2336 if (err) 2337 return err; 2338 next: 2339 ; /* isn't C great? */ 2340 } 2341 return 0; 2342 } 2343 2344 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 2345 { 2346 int i; 2347 2348 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 2349 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 2350 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2351 for (i = 0; i < 4; i++) { 2352 dtm->wp_event[i] = -1; 2353 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 2354 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 2355 } 2356 } 2357 2358 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 2359 { 2360 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 2361 const struct resource *cfg; 2362 resource_size_t base, size; 2363 2364 dtc->pmu_base = dn->pmu_base; 2365 dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn); 2366 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 2367 if (dtc->irq < 0) 2368 return dtc->irq; 2369 2370 cfg = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 0); 2371 base = dtc->base - cmn->base + cfg->start; 2372 size = cmn->part == PART_CMN600 ? SZ_16K : SZ_64K; 2373 if (!devm_request_mem_region(cmn->dev, base, size, dev_name(cmn->dev))) 2374 return dev_err_probe(cmn->dev, -EBUSY, 2375 "Failed to request DTC region 0x%pa\n", &base); 2376 2377 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 2378 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc)); 2379 writeq_relaxed(0, CMN_DT_PMCCNTR(dtc)); 2380 writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc)); 2381 2382 return 0; 2383 } 2384 2385 static int arm_cmn_node_cmp(const void *a, const void *b) 2386 { 2387 const struct arm_cmn_node *dna = a, *dnb = b; 2388 int cmp; 2389 2390 cmp = dna->type - dnb->type; 2391 if (!cmp) 2392 cmp = dna->logid - dnb->logid; 2393 return cmp; 2394 } 2395 2396 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 2397 { 2398 struct arm_cmn_node *dn, *xp; 2399 int dtc_idx = 0; 2400 2401 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 2402 if (!cmn->dtc) 2403 return -ENOMEM; 2404 2405 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 2406 2407 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 2408 2409 for (dn = cmn->dns; dn->type; dn++) { 2410 if (dn->type == CMN_TYPE_XP) 2411 continue; 2412 2413 xp = arm_cmn_node_to_xp(cmn, dn); 2414 dn->dtc = xp->dtc; 2415 dn->dtm = xp->dtm; 2416 if (cmn->multi_dtm) 2417 dn->dtm += arm_cmn_nid(dn).port / 2; 2418 2419 if (dn->type == CMN_TYPE_DTC) { 2420 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 2421 2422 if (err) 2423 return err; 2424 } 2425 2426 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 2427 if (dn->type == CMN_TYPE_RND) 2428 dn->type = CMN_TYPE_RNI; 2429 2430 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 2431 if (dn->type == CMN_TYPE_CCLA_RNI) 2432 dn->type = CMN_TYPE_CCLA; 2433 } 2434 2435 arm_cmn_set_state(cmn, CMN_STATE_DISABLED); 2436 2437 return 0; 2438 } 2439 2440 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region) 2441 { 2442 int offset = CMN_DTM_UNIT_INFO; 2443 2444 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700) 2445 offset = CMN650_DTM_UNIT_INFO; 2446 2447 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset)); 2448 } 2449 2450 static unsigned int arm_cmn_graviton5_dtc_domain(u16 xp_id) 2451 { 2452 unsigned int x = (xp_id >> 7) & 0xf; 2453 unsigned int y = (xp_id >> 3) & 0xf; 2454 2455 /* 2456 * The unit info register reads as zero; derive the DTC domain from 2457 * the XP's mesh coordinates over the 10x14 mesh. 2458 */ 2459 return (x / 5) + (y / 7) * 2; 2460 } 2461 2462 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 2463 { 2464 int level; 2465 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 2466 2467 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 2468 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 2469 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 2470 2471 node->pmu_base = cmn->base + offset + arm_cmn_pmu_offset(cmn, node); 2472 2473 if (node->type == CMN_TYPE_CFG) 2474 level = 0; 2475 else if (node->type == CMN_TYPE_XP) 2476 level = 1; 2477 else 2478 level = 2; 2479 2480 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 2481 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 2482 node->type, node->logid, offset); 2483 } 2484 2485 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 2486 { 2487 switch (type) { 2488 case CMN_TYPE_HNP: 2489 return CMN_TYPE_HNI; 2490 case CMN_TYPE_CCLA_RNI: 2491 return CMN_TYPE_RNI; 2492 default: 2493 return CMN_TYPE_INVALID; 2494 } 2495 } 2496 2497 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2498 { 2499 void __iomem *cfg_region, __iomem *xp_region; 2500 struct arm_cmn_node cfg, *dn; 2501 struct arm_cmn_dtm *dtm; 2502 enum cmn_model model; 2503 enum cmn_part part; 2504 u16 child_count, child_poff; 2505 u64 reg; 2506 int i, j; 2507 size_t sz; 2508 bool graviton5_workaround = false; 2509 2510 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2511 if (cfg.type != CMN_TYPE_CFG) 2512 return -ENODEV; 2513 2514 cfg_region = cmn->base + rgn_offset; 2515 2516 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2517 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2518 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2519 2520 /* Graviton5 has a customised CMN-S3 which needs some fixups */ 2521 if (cmn->part == PART_GRAVITON5) { 2522 cmn->part = PART_CMN_S3; 2523 graviton5_workaround = true; 2524 } 2525 2526 /* 600AE is close enough that it's not really worth more complexity */ 2527 if (part == PART_CMN600AE) 2528 part = PART_CMN600; 2529 if (cmn->part && cmn->part != part) 2530 dev_warn(cmn->dev, 2531 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", 2532 cmn->part, part); 2533 cmn->part = part; 2534 2535 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23); 2536 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2537 2538 model = arm_cmn_model(cmn); 2539 if (!model) 2540 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part); 2541 2542 /* 2543 * With the device isolation feature, if firmware has neglected to enable 2544 * an XP port then we risk locking up if we try to access anything behind 2545 * it; however prior to CMN S3 r2p0 we also have no way to tell from 2546 * Non-Secure whether any given port is disabled or not, so in that case 2547 * the only way to win is not to play... 2548 */ 2549 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2550 if (reg & CMN_INFO_DEVICE_ISO_ENABLE && model == CMNS3R01) { 2551 dev_err(cmn->dev, "Device isolation enabled, not continuing due to risk of lockup\n"); 2552 return -ENODEV; 2553 } 2554 if (model < CMNS3R2) { 2555 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2556 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2557 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2558 } else { 2559 cmn->multi_dtm = reg & CMN_S3_R2_MULTIPLE_DTM_EN; 2560 } 2561 2562 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2563 if (model < CMNS3R2) { 2564 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2565 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2566 } else { 2567 cmn->rsp_vc_num = FIELD_GET(CMN_S3_R2_RSP_VC_NUM, reg); 2568 cmn->dat_vc_num = FIELD_GET(CMN_S3_R2_DAT_VC_NUM, reg); 2569 cmn->snp_vc_num = FIELD_GET(CMN_S3_R2_SNP_VC_NUM, reg); 2570 cmn->req_vc_num = FIELD_GET(CMN_S3_R2_REQ_VC_NUM, reg); 2571 } 2572 2573 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2574 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2575 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2576 2577 cmn->num_xps = child_count; 2578 cmn->num_dns = cmn->num_xps; 2579 2580 /* Pass 1: visit the XPs, enumerate their children */ 2581 cfg_region += child_poff; 2582 for (i = 0; i < cmn->num_xps; i++) { 2583 reg = readq_relaxed(cfg_region + i * 8); 2584 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2585 2586 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2587 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2588 } 2589 2590 /* 2591 * Some nodes effectively have two separate types, which we'll handle 2592 * by creating one of each internally. For a (very) safe initial upper 2593 * bound, account for double the number of non-XP nodes. 2594 */ 2595 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2596 sizeof(*dn), GFP_KERNEL); 2597 if (!dn) 2598 return -ENOMEM; 2599 2600 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2601 i = cmn->num_xps; 2602 if (cmn->multi_dtm) 2603 i += cmn->num_xps + 1; 2604 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2605 if (!dtm) 2606 return -ENOMEM; 2607 2608 /* Pass 2: now we can actually populate the nodes */ 2609 cmn->dns = dn; 2610 cmn->dtms = dtm; 2611 for (i = 0; i < cmn->num_xps; i++) { 2612 struct arm_cmn_node *xp = dn++; 2613 unsigned int xp_ports = 0; 2614 2615 reg = readq_relaxed(cfg_region + i * 8); 2616 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2617 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, xp); 2618 /* 2619 * Thanks to the order in which XP logical IDs seem to be 2620 * assigned, we can handily infer the mesh X dimension by 2621 * looking out for the XP at (0,1) without needing to know 2622 * the exact node ID format, which we can later derive. 2623 */ 2624 if (xp->id == (1 << 3)) 2625 cmn->mesh_x = xp->logid; 2626 2627 if (cmn->part == PART_CMN600) 2628 xp->dtc = -1; 2629 else if (graviton5_workaround) 2630 xp->dtc = arm_cmn_graviton5_dtc_domain(xp->id); 2631 else 2632 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region); 2633 2634 xp->dtm = dtm - cmn->dtms; 2635 arm_cmn_init_dtm(dtm++, xp, 0); 2636 /* 2637 * Keeping track of connected ports will let us filter out 2638 * unnecessary XP events easily, and also infer the per-XP 2639 * part of the node ID format. 2640 */ 2641 for (int p = 0; p < CMN_MAX_PORTS; p++) 2642 if (arm_cmn_device_connect_info(cmn, xp, p)) 2643 xp_ports |= BIT(p); 2644 2645 if (cmn->num_xps == 1) { 2646 xp->portid_bits = 3; 2647 xp->deviceid_bits = 2; 2648 } else if (xp_ports > 0x3) { 2649 xp->portid_bits = 2; 2650 xp->deviceid_bits = 1; 2651 } else { 2652 xp->portid_bits = 1; 2653 xp->deviceid_bits = 2; 2654 } 2655 2656 if (cmn->multi_dtm && (xp_ports > 0x3)) 2657 arm_cmn_init_dtm(dtm++, xp, 1); 2658 if (cmn->multi_dtm && (xp_ports > 0xf)) 2659 arm_cmn_init_dtm(dtm++, xp, 2); 2660 2661 cmn->ports_used |= xp_ports; 2662 2663 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2664 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2665 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2666 2667 for (j = 0; j < child_count; j++) { 2668 reg = readq_relaxed(xp_region + child_poff + j * 8); 2669 /* 2670 * Don't even try to touch anything external, since in general 2671 * we haven't a clue how to power up arbitrary CHI requesters, 2672 * and none of them have standard PMU events anyway. Isolated 2673 * nodes effectively just do not exist at all from our PoV. 2674 */ 2675 if (reg & (CMN_CHILD_NODE_EXTERNAL | CMN_CHILD_NODE_ISOLATED)) { 2676 dev_dbg(cmn->dev, "ignoring external/isolated node %llx\n", reg); 2677 continue; 2678 } 2679 /* 2680 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus 2681 * child count larger than the number of valid child pointers. 2682 * A child offset of 0 can only occur on CMN-600; otherwise it 2683 * would imply the root node being its own grandchild, which 2684 * we can safely dismiss in general. 2685 */ 2686 if (reg == 0 && cmn->part != PART_CMN600) { 2687 dev_dbg(cmn->dev, "bogus child pointer?\n"); 2688 continue; 2689 } 2690 2691 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2692 dn->portid_bits = xp->portid_bits; 2693 dn->deviceid_bits = xp->deviceid_bits; 2694 /* 2695 * Logical IDs are assigned from 0 per node type, so as 2696 * soon as we see one bigger than expected, we can assume 2697 * there are more than we can cope with. 2698 */ 2699 if (dn->logid > CMN_MAX_NODES_PER_EVENT) { 2700 dev_err(cmn->dev, "Node ID invalid for supported CMN versions: %d\n", dn->logid); 2701 return -ENODEV; 2702 } 2703 /* 2704 * We can utilise the "wasted" filter array slot to store 2705 * the index for referencing the filter encodings later. 2706 */ 2707 dn->filter[SEL_NONE].val = arm_cmn_filter(dn->type, model); 2708 2709 switch (dn->type) { 2710 case CMN_TYPE_DTC: 2711 if (graviton5_workaround) { 2712 /* Node info logical ID is zeroed; use the XP's */ 2713 dn->logid = xp->logid; 2714 } 2715 cmn->num_dtcs++; 2716 dn++; 2717 break; 2718 /* These guys have PMU events */ 2719 case CMN_TYPE_DVM: 2720 case CMN_TYPE_HNI: 2721 case CMN_TYPE_HNF: 2722 case CMN_TYPE_SBSX: 2723 case CMN_TYPE_RNI: 2724 case CMN_TYPE_RND: 2725 case CMN_TYPE_MTSX: 2726 case CMN_TYPE_CXRA: 2727 case CMN_TYPE_CXHA: 2728 case CMN_TYPE_CCRA: 2729 case CMN_TYPE_CCHA: 2730 case CMN_TYPE_HNS: 2731 dn++; 2732 break; 2733 case CMN_TYPE_CCLA: 2734 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2735 dn++; 2736 break; 2737 /* Nothing to see here */ 2738 case CMN_TYPE_MPAM_S: 2739 case CMN_TYPE_MPAM_NS: 2740 case CMN_TYPE_RNSAM: 2741 case CMN_TYPE_CXLA: 2742 case CMN_TYPE_HNS_MPAM_S: 2743 case CMN_TYPE_HNS_MPAM_NS: 2744 case CMN_TYPE_APB: 2745 break; 2746 /* 2747 * Split "optimised" combination nodes into separate 2748 * types for the different event sets. Offsetting the 2749 * base address lets us handle the second pmu_event_sel 2750 * register via the normal mechanism later. 2751 */ 2752 case CMN_TYPE_HNP: 2753 case CMN_TYPE_CCLA_RNI: 2754 dn[1] = dn[0]; 2755 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2756 dn[1].type = arm_cmn_subtype(dn->type); 2757 dn += 2; 2758 break; 2759 /* Something has gone horribly wrong */ 2760 default: 2761 dev_err(cmn->dev, "Device node type invalid for supported CMN versions: 0x%x\n", dn->type); 2762 return -ENODEV; 2763 } 2764 } 2765 } 2766 2767 /* Correct for any nodes we added or skipped */ 2768 cmn->num_dns = dn - cmn->dns; 2769 2770 /* Cheeky +1 to help terminate pointer-based iteration later */ 2771 sz = (void *)(dn + 1) - (void *)cmn->dns; 2772 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2773 if (dn) 2774 cmn->dns = dn; 2775 2776 sz = (void *)dtm - (void *)cmn->dtms; 2777 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2778 if (dtm) 2779 cmn->dtms = dtm; 2780 2781 /* 2782 * If mesh_x wasn't set during discovery then we never saw 2783 * an XP at (0,1), thus we must have an Nx1 configuration. 2784 */ 2785 if (!cmn->mesh_x) 2786 cmn->mesh_x = cmn->num_xps; 2787 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2788 2789 if (max(cmn->mesh_x, cmn->mesh_y) > CMN_MAX_DIMENSION) { 2790 dev_err(cmn->dev, "Mesh size invalid for supported CMN versions: %dx%d\n", cmn->mesh_x, cmn->mesh_y); 2791 return -ENODEV; 2792 } 2793 /* 1x1 config plays havoc with XP event encodings */ 2794 if (cmn->num_xps == 1) 2795 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2796 2797 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev); 2798 reg = cmn->ports_used; 2799 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2800 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2801 cmn->multi_dtm ? ", multi-DTM" : ""); 2802 2803 return 0; 2804 } 2805 2806 static int arm_cmn_get_root(struct arm_cmn *cmn, const struct resource *cfg) 2807 { 2808 const struct device_node *np = cmn->dev->of_node; 2809 const struct resource *root; 2810 u32 rootnode; 2811 2812 if (cmn->part != PART_CMN600) 2813 return 0; 2814 2815 if (np) 2816 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2817 2818 root = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 1); 2819 return root ? root->start - cfg->start : -EINVAL; 2820 } 2821 2822 static int arm_cmn_probe(struct platform_device *pdev) 2823 { 2824 struct arm_cmn *cmn; 2825 const struct resource *cfg; 2826 const char *name; 2827 static atomic_t id; 2828 int err, rootnode, this_id; 2829 2830 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2831 if (!cmn) 2832 return -ENOMEM; 2833 2834 cmn->dev = &pdev->dev; 2835 cmn->part = (unsigned long)device_get_match_data(cmn->dev); 2836 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2837 platform_set_drvdata(pdev, cmn); 2838 2839 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2840 if (!cfg) 2841 return -EINVAL; 2842 2843 /* Map the whole region now, claim the DTCs once we've found them */ 2844 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2845 if (!cmn->base) 2846 return -ENOMEM; 2847 2848 rootnode = arm_cmn_get_root(cmn, cfg); 2849 if (rootnode < 0) 2850 return rootnode; 2851 2852 err = arm_cmn_discover(cmn, rootnode); 2853 if (err) 2854 return err; 2855 2856 err = arm_cmn_init_dtcs(cmn); 2857 if (err) 2858 return err; 2859 2860 err = arm_cmn_init_irqs(cmn); 2861 if (err) 2862 return err; 2863 2864 cmn->pmu = (struct pmu) { 2865 .module = THIS_MODULE, 2866 .parent = cmn->dev, 2867 .attr_groups = arm_cmn_attr_groups, 2868 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2869 .task_ctx_nr = perf_invalid_context, 2870 .pmu_enable = arm_cmn_pmu_enable, 2871 .pmu_disable = arm_cmn_pmu_disable, 2872 .event_init = arm_cmn_event_init, 2873 .add = arm_cmn_event_add, 2874 .del = arm_cmn_event_del, 2875 .start = arm_cmn_event_start, 2876 .stop = arm_cmn_event_stop, 2877 .read = arm_cmn_event_read, 2878 .start_txn = arm_cmn_start_txn, 2879 .commit_txn = arm_cmn_commit_txn, 2880 .cancel_txn = arm_cmn_end_txn, 2881 }; 2882 2883 this_id = atomic_fetch_inc(&id); 2884 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2885 if (!name) 2886 return -ENOMEM; 2887 2888 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2889 if (err) 2890 return err; 2891 2892 err = perf_pmu_register(&cmn->pmu, name, -1); 2893 if (err) 2894 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2895 else 2896 arm_cmn_debugfs_init(cmn, this_id); 2897 2898 return err; 2899 } 2900 2901 static void arm_cmn_remove(struct platform_device *pdev) 2902 { 2903 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2904 2905 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2906 2907 perf_pmu_unregister(&cmn->pmu); 2908 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2909 debugfs_remove(cmn->debug); 2910 } 2911 2912 #ifdef CONFIG_OF 2913 static const struct of_device_id arm_cmn_of_match[] = { 2914 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 }, 2915 { .compatible = "arm,cmn-650" }, 2916 { .compatible = "arm,cmn-700" }, 2917 { .compatible = "arm,cmn-s3" }, 2918 { .compatible = "arm,ci-700" }, 2919 {} 2920 }; 2921 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2922 #endif 2923 2924 #ifdef CONFIG_ACPI 2925 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2926 { "ARMHC600", PART_CMN600 }, 2927 { "ARMHC650" }, 2928 { "ARMHC700" }, 2929 { "ARMHC003" }, 2930 { "AMZN0070", PART_GRAVITON5 }, 2931 {} 2932 }; 2933 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2934 #endif 2935 2936 static struct platform_driver arm_cmn_driver = { 2937 .driver = { 2938 .name = "arm-cmn", 2939 .of_match_table = of_match_ptr(arm_cmn_of_match), 2940 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2941 .suppress_bind_attrs = true, 2942 }, 2943 .probe = arm_cmn_probe, 2944 .remove = arm_cmn_remove, 2945 }; 2946 2947 static int __init arm_cmn_init(void) 2948 { 2949 int ret; 2950 2951 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2952 "perf/arm/cmn:online", 2953 arm_cmn_pmu_online_cpu, 2954 arm_cmn_pmu_offline_cpu); 2955 if (ret < 0) 2956 return ret; 2957 2958 arm_cmn_hp_state = ret; 2959 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2960 2961 ret = platform_driver_register(&arm_cmn_driver); 2962 if (ret) { 2963 cpuhp_remove_multi_state(arm_cmn_hp_state); 2964 debugfs_remove(arm_cmn_debugfs); 2965 } 2966 return ret; 2967 } 2968 2969 static void __exit arm_cmn_exit(void) 2970 { 2971 platform_driver_unregister(&arm_cmn_driver); 2972 cpuhp_remove_multi_state(arm_cmn_hp_state); 2973 debugfs_remove(arm_cmn_debugfs); 2974 } 2975 2976 module_init(arm_cmn_init); 2977 module_exit(arm_cmn_exit); 2978 2979 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2980 MODULE_DESCRIPTION("Arm CMN/CI interconnect PMU driver"); 2981 MODULE_LICENSE("GPL v2"); 2982