1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef CGX_H 9 #define CGX_H 10 11 #include "mbox.h" 12 #include "cgx_fw_if.h" 13 #include "rpm.h" 14 15 /* PCI device IDs */ 16 #define PCI_DEVID_OCTEONTX2_CGX 0xA059 17 18 /* PCI BAR nos */ 19 #define PCI_CFG_REG_BAR_NUM 0 20 21 #define CGX_ID_MASK 0xF 22 23 /* Registers */ 24 #define CGXX_CMRX_CFG 0x00 25 #define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59) 26 #define CMR_P2X_SEL_SHIFT 59ULL 27 #define CMR_P2X_SEL_NIX0 1ULL 28 #define CMR_P2X_SEL_NIX1 2ULL 29 #define DATA_PKT_TX_EN BIT_ULL(53) 30 #define DATA_PKT_RX_EN BIT_ULL(54) 31 #define CGX_LMAC_TYPE_SHIFT 40 32 #define CGX_LMAC_TYPE_MASK 0xF 33 #define CGXX_CMRX_INT 0x040 34 #define FW_CGX_INT BIT_ULL(1) 35 #define CGXX_CMR_GLOBAL_CONFIG 0x08 36 #define CGX_NIX0_RESET BIT_ULL(2) 37 #define CGX_NIX1_RESET BIT_ULL(3) 38 #define CGX_NSCI_DROP BIT_ULL(9) 39 #define CGXX_CMRX_INT_ENA_W1S 0x058 40 #define CGXX_CMRX_RX_ID_MAP 0x060 41 #define CGXX_CMRX_RX_STAT0 0x070 42 #define CGXX_CMRX_RX_STAT4 0x090 43 #define CGXX_CMRX_RX_LOGL_XON 0x100 44 #define CGXX_CMRX_RX_LMACS 0x128 45 #define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset) 46 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) 47 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3) 48 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2) 49 #define CGX_DMAC_MCAST_MODE BIT_ULL(1) 50 #define CGX_DMAC_BCAST_MODE BIT_ULL(0) 51 #define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset) 52 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48) 53 #define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49) 54 #define CGXX_CMRX_RX_DMAC_CAM1 0x400 55 #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) 56 #define CGXX_CMRX_TX_STAT0 0x700 57 #define CGXX_SCRATCH0_REG 0x1050 58 #define CGXX_SCRATCH1_REG 0x1058 59 #define CGX_CONST 0x2000 60 #define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32) 61 #define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24) 62 #define CGXX_SPUX_CONTROL1 0x10000 63 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700 64 #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800 65 #define CGXX_SPUX_RSFEC_CORR 0x10088 66 #define CGXX_SPUX_RSFEC_UNCORR 0x10090 67 68 #define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14) 69 #define CGXX_GMP_PCS_MRX_CTL 0x30000 70 #define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14) 71 72 #define CGXX_SMUX_RX_FRM_CTL 0x20020 73 #define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3) 74 #define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12) 75 #define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028 76 #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3) 77 #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12) 78 #define CGXX_SMUX_TX_CTL 0x20178 79 #define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110 80 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120 81 #define CGXX_SMUX_SMAC 0x20108 82 #define CGXX_SMUX_CBFC_CTL 0x20218 83 #define CGXX_SMUX_CBFC_CTL_RX_EN BIT_ULL(0) 84 #define CGXX_SMUX_CBFC_CTL_TX_EN BIT_ULL(1) 85 #define CGXX_SMUX_CBFC_CTL_DRP_EN BIT_ULL(2) 86 #define CGXX_SMUX_CBFC_CTL_BCK_EN BIT_ULL(3) 87 #define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32) 88 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230 89 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248 90 #define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7) 91 #define CGXX_CMR_RX_OVR_BP 0x130 92 #define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8)) 93 #define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4)) 94 95 #define CGX_COMMAND_REG CGXX_SCRATCH1_REG 96 #define CGX_EVENT_REG CGXX_SCRATCH0_REG 97 #define CGX_CMD_TIMEOUT 5000 /* msecs */ 98 #define DEFAULT_PAUSE_TIME 0x7FF 99 100 #define CGX_LMAC_FWI 0 101 102 enum cgx_nix_stat_type { 103 NIX_STATS_RX, 104 NIX_STATS_TX, 105 }; 106 107 enum LMAC_TYPE { 108 LMAC_MODE_SGMII = 0, 109 LMAC_MODE_XAUI = 1, 110 LMAC_MODE_RXAUI = 2, 111 LMAC_MODE_10G_R = 3, 112 LMAC_MODE_40G_R = 4, 113 LMAC_MODE_QSGMII = 6, 114 LMAC_MODE_25G_R = 7, 115 LMAC_MODE_50G_R = 8, 116 LMAC_MODE_100G_R = 9, 117 LMAC_MODE_USXGMII = 10, 118 LMAC_MODE_USGMII = 11, 119 LMAC_MODE_MAX, 120 }; 121 122 struct cgx_link_event { 123 struct cgx_link_user_info link_uinfo; 124 u8 cgx_id; 125 u8 lmac_id; 126 }; 127 128 /** 129 * struct cgx_event_cb 130 * @notify_link_chg: callback for link change notification 131 * @data: data passed to callback function 132 */ 133 struct cgx_event_cb { 134 int (*notify_link_chg)(struct cgx_link_event *event, void *data); 135 void *data; 136 }; 137 138 extern struct pci_driver cgx_driver; 139 140 int cgx_get_cgxcnt_max(void); 141 int cgx_get_cgxid(void *cgxd); 142 int cgx_get_lmac_cnt(void *cgxd); 143 void *cgx_get_pdata(int cgx_id); 144 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind); 145 int cgx_get_pkind(void *cgxd, u8 lmac_id, int *pkind); 146 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); 147 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); 148 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); 149 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); 150 int cgx_stats_reset(void *cgxd, int lmac_id); 151 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); 152 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable); 153 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 154 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id); 155 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); 156 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 157 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index); 158 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id); 159 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); 160 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable); 161 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); 162 int cgx_get_link_info(void *cgxd, int lmac_id, 163 struct cgx_link_user_info *linfo); 164 int cgx_lmac_linkup_start(void *cgxd); 165 int cgx_get_fwdata_base(u64 *base); 166 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable); 167 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id); 168 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id); 169 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); 170 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id); 171 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 172 struct cgx_lmac_fwdata_s *linkmodes, 173 int cgx_id, int lmac_id); 174 u64 cgx_features_get(void *cgxd); 175 struct mac_ops *get_mac_ops(void *cgxd); 176 int cgx_get_nr_lmacs(void *cgxd); 177 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index); 178 unsigned long cgx_get_lmac_bmap(void *cgxd); 179 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val); 180 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset); 181 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index); 182 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id); 183 u64 cgx_read_dmac_entry(void *cgxd, int index); 184 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 185 u16 pfc_en); 186 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, 187 u8 *rx_pause); 188 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 189 int pfvf_idx); 190 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr); 191 u64 cgx_get_dmacflt_dropped_pktcnt(void *cgx, int lmac_id); 192 u32 cgx_get_fifo_len(void *cgxd); 193 #endif /* CGX_H */ 194