1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13 #include <linux/ethtool.h>
14
15 #include "rvu_struct.h"
16 #include "common.h"
17 #include "cn20k/struct.h"
18
19 #define MBOX_SIZE SZ_64K
20
21 #define MBOX_DOWN_MSG 1
22 #define MBOX_UP_MSG 2
23
24 /* AF/PF: PF initiated, PF/VF VF initiated */
25 #define MBOX_DOWN_RX_START 0
26 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
27 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
28 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
29 /* AF/PF: AF initiated, PF/VF PF initiated */
30 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
31 #define MBOX_UP_RX_SIZE SZ_1K
32 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
33 #define MBOX_UP_TX_SIZE SZ_1K
34
35 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
36 # error "incorrect mailbox area sizes"
37 #endif
38
39 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
40
41 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
42
43 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
44
45 /* Mailbox directions */
46 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
47 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
48 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
49 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
50 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
51 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
52 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
53 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
54
55 enum {
56 TYPE_AFVF,
57 TYPE_AFPF,
58 };
59
60 struct otx2_mbox_dev {
61 void *mbase; /* This dev's mbox region */
62 void *hwbase;
63 spinlock_t mbox_lock;
64 u16 msg_size; /* Total msg size to be sent */
65 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
66 u16 num_msgs; /* No of msgs sent or waiting for response */
67 u16 msgs_acked; /* No of msgs for which response is received */
68 };
69
70 struct otx2_mbox {
71 struct pci_dev *pdev;
72 void *hwbase; /* Mbox region advertised by HW */
73 void *reg_base;/* CSR base for this dev */
74 u64 trigger; /* Trigger mbox notification */
75 u16 tr_shift; /* Mbox trigger shift */
76 u64 rx_start; /* Offset of Rx region in mbox memory */
77 u64 tx_start; /* Offset of Tx region in mbox memory */
78 u16 rx_size; /* Size of Rx region */
79 u16 tx_size; /* Size of Tx region */
80 u16 ndevs; /* The number of peers */
81 struct otx2_mbox_dev *dev;
82 };
83
84 /* Header which precedes all mbox messages */
85 struct mbox_hdr {
86 u64 msg_size; /* Total msgs size embedded */
87 u16 num_msgs; /* No of msgs embedded */
88 u16 opt_msg;
89 u8 sig;
90 };
91
92 /* Header which precedes every msg and is also part of it */
93 struct mbox_msghdr {
94 u16 pcifunc; /* Who's sending this msg */
95 u16 id; /* Mbox message ID */
96 #define OTX2_MBOX_REQ_SIG (0xdead)
97 #define OTX2_MBOX_RSP_SIG (0xbeef)
98 u16 sig; /* Signature, for validating corrupted msgs */
99 #define OTX2_MBOX_VERSION (0x000a)
100 u16 ver; /* Version of msg's structure for this ID */
101 u16 next_msgoff; /* Offset of next msg within mailbox region */
102 int rc; /* Msg process'ed response code */
103 };
104
105 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
106 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
107 void otx2_mbox_destroy(struct otx2_mbox *mbox);
108 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
109 struct pci_dev *pdev, void __force *reg_base,
110 int direction, int ndevs);
111
112 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
113 struct pci_dev *pdev, void __force *reg_base,
114 int direction, int ndevs, unsigned long *bmap);
115 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
116 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
117 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
118 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
119 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
120 int size, int size_rsp);
121 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
122 struct mbox_msghdr *msg);
123 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
124 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
125 u16 pcifunc, u16 id);
126 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
127 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)128 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
129 int devid, int size)
130 {
131 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
132 }
133
134 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
135
136 /* Mailbox message types */
137 #define MBOX_MSG_MASK 0xFFFF
138 #define MBOX_MSG_INVALID 0xFFFE
139 #define MBOX_MSG_MAX 0xFFFF
140
141 #define MBOX_MESSAGES \
142 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
143 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
144 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
145 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
146 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
147 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
148 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
149 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
150 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
151 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
152 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
153 msg_rsp) \
154 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
155 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
156 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
157 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
158 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
159 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
160 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
161 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
162 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
163 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
164 cgx_mac_addr_set_or_get) \
165 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
166 cgx_mac_addr_set_or_get) \
167 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
168 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
169 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
170 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
171 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
172 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
173 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
174 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
175 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
176 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
177 cgx_pause_frm_cfg) \
178 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
179 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
180 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
181 cgx_mac_addr_add_rsp) \
182 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
183 msg_rsp) \
184 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
185 cgx_max_dmac_entries_get_rsp) \
186 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
187 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
188 cgx_set_link_mode_rsp) \
189 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
190 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
191 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
192 cgx_features_info_msg) \
193 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
194 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
195 msg_rsp) \
196 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
197 cgx_mac_addr_update_rsp) \
198 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
199 cgx_pfc_rsp) \
200 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
201 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
202 npa_lf_alloc_req, npa_lf_alloc_rsp) \
203 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
204 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
205 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
206 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
207 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
208 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
209 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
210 msg_rsp) \
211 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
212 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
213 cpt_rd_wr_reg_msg) \
214 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
215 cpt_inline_ipsec_cfg_msg, msg_rsp) \
216 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
217 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
218 msg_rsp) \
219 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
220 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
221 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
222 cpt_flt_eng_info_rsp) \
223 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
224 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
225 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
226 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
227 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
228 npc_mcam_alloc_entry_rsp) \
229 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
230 npc_mcam_free_entry_req, msg_rsp) \
231 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
232 npc_mcam_write_entry_req, msg_rsp) \
233 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
234 npc_mcam_ena_dis_entry_req, msg_rsp) \
235 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
236 npc_mcam_ena_dis_entry_req, msg_rsp) \
237 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
238 npc_mcam_shift_entry_rsp) \
239 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
240 npc_mcam_alloc_counter_req, \
241 npc_mcam_alloc_counter_rsp) \
242 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
243 npc_mcam_oper_counter_req, msg_rsp) \
244 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
245 npc_mcam_unmap_counter_req, msg_rsp) \
246 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
247 npc_mcam_oper_counter_req, msg_rsp) \
248 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
249 npc_mcam_oper_counter_req, \
250 npc_mcam_oper_counter_rsp) \
251 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
252 npc_mcam_alloc_and_write_entry_req, \
253 npc_mcam_alloc_and_write_entry_rsp) \
254 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
255 msg_req, npc_get_kex_cfg_rsp) \
256 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
257 npc_install_flow_req, npc_install_flow_rsp) \
258 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
259 npc_delete_flow_req, npc_delete_flow_rsp) \
260 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
261 npc_mcam_read_entry_req, \
262 npc_mcam_read_entry_rsp) \
263 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
264 npc_set_pkind, msg_rsp) \
265 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
266 msg_req, npc_mcam_read_base_rule_rsp) \
267 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
268 npc_mcam_get_stats_req, \
269 npc_mcam_get_stats_rsp) \
270 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
271 npc_get_field_hash_info_req, \
272 npc_get_field_hash_info_rsp) \
273 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
274 npc_get_field_status_req, \
275 npc_get_field_status_rsp) \
276 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
277 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
278 nix_lf_alloc_req, nix_lf_alloc_rsp) \
279 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
280 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
281 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
282 hwctx_disable_req, msg_rsp) \
283 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
284 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
285 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
286 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
287 nix_txschq_config) \
288 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
289 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
290 nix_vtag_config_rsp) \
291 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
292 nix_rss_flowkey_cfg, \
293 nix_rss_flowkey_cfg_rsp) \
294 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
295 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
296 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
297 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
298 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
299 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
300 nix_mark_format_cfg, \
301 nix_mark_format_cfg_rsp) \
302 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
303 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
304 nix_lso_format_cfg, \
305 nix_lso_format_cfg_rsp) \
306 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
307 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
308 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
309 nix_bp_cfg_rsp) \
310 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
311 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
312 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
313 nix_inline_ipsec_cfg, msg_rsp) \
314 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
315 nix_inline_ipsec_lf_cfg, msg_rsp) \
316 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
317 nix_cn10k_aq_enq_rsp) \
318 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
319 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
320 nix_bandprof_alloc_rsp) \
321 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
322 msg_rsp) \
323 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
324 nix_bandprof_get_hwinfo_rsp) \
325 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
326 nix_bp_cfg_rsp) \
327 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
328 msg_rsp) \
329 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
330 msg_req, nix_inline_ipsec_cfg) \
331 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
332 nix_mcast_grp_create_rsp) \
333 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
334 msg_rsp) \
335 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
336 nix_mcast_grp_update_req, \
337 nix_mcast_grp_update_rsp) \
338 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \
339 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
340 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
341 mcs_alloc_rsrc_rsp) \
342 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
343 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
344 msg_rsp) \
345 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
346 msg_rsp) \
347 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
348 msg_rsp) \
349 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
350 msg_rsp) \
351 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
352 msg_rsp) \
353 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
354 msg_rsp) \
355 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
356 msg_rsp) \
357 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
358 msg_rsp) \
359 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
360 msg_rsp) \
361 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
362 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
363 mcs_flowid_stats) \
364 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
365 mcs_secy_stats) \
366 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
367 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
368 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
369 mcs_port_stats) \
370 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
371 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
372 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
373 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
374 msg_rsp) \
375 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
376 mcs_alloc_ctrl_pkt_rule_req, \
377 mcs_alloc_ctrl_pkt_rule_rsp) \
378 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
379 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
380 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
381 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
382 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
383 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
384 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
385 mcs_port_cfg_get_rsp) \
386 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
387 mcs_custom_tag_cfg_get_req, \
388 mcs_custom_tag_cfg_get_rsp)
389
390 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
391 #define MBOX_UP_CGX_MESSAGES \
392 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
393
394 #define MBOX_UP_CPT_MESSAGES \
395 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
396
397 #define MBOX_UP_MCS_MESSAGES \
398 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
399
400 #define MBOX_UP_REP_MESSAGES \
401 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
402
403 enum {
404 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
405 MBOX_MESSAGES
406 MBOX_UP_CGX_MESSAGES
407 MBOX_UP_CPT_MESSAGES
408 MBOX_UP_MCS_MESSAGES
409 MBOX_UP_REP_MESSAGES
410 #undef M
411 };
412
413 /* Mailbox message formats */
414
415 #define RVU_DEFAULT_PF_FUNC 0xFFFF
416
417 /* Generic request msg used for those mbox messages which
418 * don't send any data in the request.
419 */
420 struct msg_req {
421 struct mbox_msghdr hdr;
422 };
423
424 /* Generic response msg used an ack or response for those mbox
425 * messages which don't have a specific rsp msg format.
426 */
427 struct msg_rsp {
428 struct mbox_msghdr hdr;
429 };
430
431 /* RVU mailbox error codes
432 * Range 256 - 300.
433 */
434 enum rvu_af_status {
435 RVU_INVALID_VF_ID = -256,
436 };
437
438 struct ready_msg_rsp {
439 struct mbox_msghdr hdr;
440 u16 sclk_freq; /* SCLK frequency (in MHz) */
441 u16 rclk_freq; /* RCLK frequency (in MHz) */
442 };
443
444 /* Structure for requesting resource provisioning.
445 * 'modify' flag to be used when either requesting more
446 * or to detach partial of a certain resource type.
447 * Rest of the fields specify how many of what type to
448 * be attached.
449 * To request LFs from two blocks of same type this mailbox
450 * can be sent twice as below:
451 * struct rsrc_attach *attach;
452 * .. Allocate memory for message ..
453 * attach->cptlfs = 3; <3 LFs from CPT0>
454 * .. Send message ..
455 * .. Allocate memory for message ..
456 * attach->modify = 1;
457 * attach->cpt_blkaddr = BLKADDR_CPT1;
458 * attach->cptlfs = 2; <2 LFs from CPT1>
459 * .. Send message ..
460 */
461 struct rsrc_attach {
462 struct mbox_msghdr hdr;
463 u8 modify:1;
464 u8 npalf:1;
465 u8 nixlf:1;
466 u16 sso;
467 u16 ssow;
468 u16 timlfs;
469 u16 cptlfs;
470 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
471 };
472
473 /* Structure for relinquishing resources.
474 * 'partial' flag to be used when relinquishing all resources
475 * but only of a certain type. If not set, all resources of all
476 * types provisioned to the RVU function will be detached.
477 */
478 struct rsrc_detach {
479 struct mbox_msghdr hdr;
480 u8 partial:1;
481 u8 npalf:1;
482 u8 nixlf:1;
483 u8 sso:1;
484 u8 ssow:1;
485 u8 timlfs:1;
486 u8 cptlfs:1;
487 };
488
489 /* Number of resources available to the caller.
490 * In reply to MBOX_MSG_FREE_RSRC_CNT.
491 */
492 struct free_rsrcs_rsp {
493 struct mbox_msghdr hdr;
494 u16 schq[NIX_TXSCH_LVL_CNT];
495 u16 sso;
496 u16 tim;
497 u16 ssow;
498 u16 cpt;
499 u8 npa;
500 u8 nix;
501 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
502 u8 nix1;
503 u8 cpt1;
504 u8 ree0;
505 u8 ree1;
506 };
507
508 #define MSIX_VECTOR_INVALID 0xFFFF
509 #define MAX_RVU_BLKLF_CNT 256
510
511 struct msix_offset_rsp {
512 struct mbox_msghdr hdr;
513 u16 npa_msixoff;
514 u16 nix_msixoff;
515 u16 sso;
516 u16 ssow;
517 u16 timlfs;
518 u16 cptlfs;
519 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
520 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
521 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
522 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
523 u16 cpt1_lfs;
524 u16 ree0_lfs;
525 u16 ree1_lfs;
526 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
527 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
528 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
529 };
530
531 struct get_hw_cap_rsp {
532 struct mbox_msghdr hdr;
533 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
534 u8 nix_shaping; /* Is shaping and coloring supported */
535 u8 npc_hash_extract; /* Is hash extract supported */
536 #define HW_CAP_MACSEC BIT_ULL(1)
537 u64 hw_caps;
538 };
539
540 /* CGX mbox message formats */
541
542 struct cgx_stats_rsp {
543 struct mbox_msghdr hdr;
544 #define CGX_RX_STATS_COUNT 9
545 #define CGX_TX_STATS_COUNT 18
546 u64 rx_stats[CGX_RX_STATS_COUNT];
547 u64 tx_stats[CGX_TX_STATS_COUNT];
548 };
549
550 struct cgx_fec_stats_rsp {
551 struct mbox_msghdr hdr;
552 u64 fec_corr_blks;
553 u64 fec_uncorr_blks;
554 };
555 /* Structure for requesting the operation for
556 * setting/getting mac address in the CGX interface
557 */
558 struct cgx_mac_addr_set_or_get {
559 struct mbox_msghdr hdr;
560 u8 mac_addr[ETH_ALEN];
561 u32 index;
562 };
563
564 /* Structure for requesting the operation to
565 * add DMAC filter entry into CGX interface
566 */
567 struct cgx_mac_addr_add_req {
568 struct mbox_msghdr hdr;
569 u8 mac_addr[ETH_ALEN];
570 };
571
572 /* Structure for response against the operation to
573 * add DMAC filter entry into CGX interface
574 */
575 struct cgx_mac_addr_add_rsp {
576 struct mbox_msghdr hdr;
577 u32 index;
578 };
579
580 /* Structure for requesting the operation to
581 * delete DMAC filter entry from CGX interface
582 */
583 struct cgx_mac_addr_del_req {
584 struct mbox_msghdr hdr;
585 u32 index;
586 };
587
588 /* Structure for response against the operation to
589 * get maximum supported DMAC filter entries
590 */
591 struct cgx_max_dmac_entries_get_rsp {
592 struct mbox_msghdr hdr;
593 u32 max_dmac_filters;
594 };
595
596 struct cgx_link_user_info {
597 uint64_t link_up:1;
598 uint64_t full_duplex:1;
599 uint64_t lmac_type_id:4;
600 uint64_t speed:20; /* speed in Mbps */
601 uint64_t an:1; /* AN supported or not */
602 uint64_t fec:2; /* FEC type if enabled else 0 */
603 #define LMACTYPE_STR_LEN 16
604 char lmac_type[LMACTYPE_STR_LEN];
605 };
606
607 struct cgx_link_info_msg {
608 struct mbox_msghdr hdr;
609 struct cgx_link_user_info link_info;
610 };
611
612 struct cgx_pause_frm_cfg {
613 struct mbox_msghdr hdr;
614 u8 set;
615 /* set = 1 if the request is to config pause frames */
616 /* set = 0 if the request is to fetch pause frames config */
617 u8 rx_pause;
618 u8 tx_pause;
619 };
620
621 enum fec_type {
622 OTX2_FEC_NONE,
623 OTX2_FEC_BASER,
624 OTX2_FEC_RS,
625 OTX2_FEC_STATS_CNT = 2,
626 OTX2_FEC_OFF,
627 };
628
629 struct fec_mode {
630 struct mbox_msghdr hdr;
631 int fec;
632 };
633
634 struct sfp_eeprom_s {
635 #define SFP_EEPROM_SIZE 256
636 u16 sff_id;
637 u8 buf[SFP_EEPROM_SIZE];
638 u64 reserved;
639 };
640
641 struct phy_s {
642 struct {
643 u64 can_change_mod_type:1;
644 u64 mod_type:1;
645 u64 has_fec_stats:1;
646 } misc;
647 struct fec_stats_s {
648 u32 rsfec_corr_cws;
649 u32 rsfec_uncorr_cws;
650 u32 brfec_corr_blks;
651 u32 brfec_uncorr_blks;
652 } fec_stats;
653 };
654
655 struct cgx_lmac_fwdata_s {
656 u16 rw_valid;
657 u64 supported_fec;
658 u64 supported_an;
659 u64 supported_link_modes;
660 /* only applicable if AN is supported */
661 u64 advertised_fec;
662 u64 advertised_link_modes_own:1; /* CGX_CMD_OWN */
663 u64 advertised_link_modes:63;
664 /* Only applicable if SFP/QSFP slot is present */
665 struct sfp_eeprom_s sfp_eeprom;
666 struct phy_s phy;
667 u32 lmac_type;
668 u32 portm_idx;
669 u64 mgmt_port:1;
670 u64 advertised_an:1;
671 u64 port;
672 #define LMAC_FWDATA_RESERVED_MEM 1018
673 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
674 };
675
676 struct cgx_fw_data {
677 struct mbox_msghdr hdr;
678 struct cgx_lmac_fwdata_s fwdata;
679 };
680
681 struct cgx_set_link_mode_args {
682 u32 speed;
683 u8 duplex;
684 u8 an;
685 u8 mode_baseidx;
686 u8 multimode;
687 u64 mode;
688 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
689 };
690
691 struct cgx_set_link_mode_req {
692 struct mbox_msghdr hdr;
693 struct cgx_set_link_mode_args args;
694 };
695
696 struct cgx_set_link_mode_rsp {
697 struct mbox_msghdr hdr;
698 int status;
699 };
700
701 struct cgx_mac_addr_reset_req {
702 struct mbox_msghdr hdr;
703 u32 index;
704 };
705
706 struct cgx_mac_addr_update_req {
707 struct mbox_msghdr hdr;
708 u8 mac_addr[ETH_ALEN];
709 u32 index;
710 };
711
712 struct cgx_mac_addr_update_rsp {
713 struct mbox_msghdr hdr;
714 u32 index;
715 };
716
717 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
718 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
719 /* flow control from physical link higig2 messages */
720 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
721 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
722 #define RVU_MAC_VERSION BIT_ULL(4)
723 #define RVU_MAC_CGX BIT_ULL(5)
724 #define RVU_MAC_RPM BIT_ULL(6)
725
726 struct cgx_features_info_msg {
727 struct mbox_msghdr hdr;
728 u64 lmac_features;
729 };
730
731 struct rpm_stats_rsp {
732 struct mbox_msghdr hdr;
733 #define RPM_RX_STATS_COUNT 43
734 #define RPM_TX_STATS_COUNT 34
735 u64 rx_stats[RPM_RX_STATS_COUNT];
736 u64 tx_stats[RPM_TX_STATS_COUNT];
737 };
738
739 struct cgx_pfc_cfg {
740 struct mbox_msghdr hdr;
741 u8 rx_pause;
742 u8 tx_pause;
743 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
744 };
745
746 struct cgx_pfc_rsp {
747 struct mbox_msghdr hdr;
748 u8 rx_pause;
749 u8 tx_pause;
750 };
751
752 /* NPA mbox message formats */
753
754 struct npc_set_pkind {
755 struct mbox_msghdr hdr;
756 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
757 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
758 u64 mode;
759 #define PKIND_TX BIT_ULL(0)
760 #define PKIND_RX BIT_ULL(1)
761 u8 dir;
762 u8 pkind; /* valid only in case custom flag */
763 u8 var_len_off; /* Offset of custom header length field.
764 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
765 */
766 u8 var_len_off_mask; /* Mask for length with in offset */
767 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
768 };
769
770 /* NPA mbox message formats */
771
772 /* NPA mailbox error codes
773 * Range 301 - 400.
774 */
775 enum npa_af_status {
776 NPA_AF_ERR_PARAM = -301,
777 NPA_AF_ERR_AQ_FULL = -302,
778 NPA_AF_ERR_AQ_ENQUEUE = -303,
779 NPA_AF_ERR_AF_LF_INVALID = -304,
780 NPA_AF_ERR_AF_LF_ALLOC = -305,
781 NPA_AF_ERR_LF_RESET = -306,
782 };
783
784 /* For NPA LF context alloc and init */
785 struct npa_lf_alloc_req {
786 struct mbox_msghdr hdr;
787 int node;
788 int aura_sz; /* No of auras */
789 u32 nr_pools; /* No of pools */
790 u64 way_mask;
791 };
792
793 struct npa_lf_alloc_rsp {
794 struct mbox_msghdr hdr;
795 u32 stack_pg_ptrs; /* No of ptrs per stack page */
796 u32 stack_pg_bytes; /* Size of stack page */
797 u16 qints; /* NPA_AF_CONST::QINTS */
798 u8 cache_lines; /*BATCH ALLOC DMA */
799 };
800
801 /* NPA AQ enqueue msg */
802 struct npa_aq_enq_req {
803 struct mbox_msghdr hdr;
804 u32 aura_id;
805 u8 ctype;
806 u8 op;
807 union {
808 /* Valid when op == WRITE/INIT and ctype == AURA.
809 * LF fills the pool_id in aura.pool_addr. AF will translate
810 * the pool_id to pool context pointer.
811 */
812 struct npa_aura_s aura;
813 /* Valid when op == WRITE/INIT and ctype == POOL */
814 struct npa_pool_s pool;
815 };
816 /* Mask data when op == WRITE (1=write, 0=don't write) */
817 union {
818 /* Valid when op == WRITE and ctype == AURA */
819 struct npa_aura_s aura_mask;
820 /* Valid when op == WRITE and ctype == POOL */
821 struct npa_pool_s pool_mask;
822 };
823 };
824
825 struct npa_aq_enq_rsp {
826 struct mbox_msghdr hdr;
827 union {
828 /* Valid when op == READ and ctype == AURA */
829 struct npa_aura_s aura;
830 /* Valid when op == READ and ctype == POOL */
831 struct npa_pool_s pool;
832 };
833 };
834
835 /* Disable all contexts of type 'ctype' */
836 struct hwctx_disable_req {
837 struct mbox_msghdr hdr;
838 u8 ctype;
839 };
840
841 /* NIX mbox message formats */
842
843 /* NIX mailbox error codes
844 * Range 401 - 500.
845 */
846 enum nix_af_status {
847 NIX_AF_ERR_PARAM = -401,
848 NIX_AF_ERR_AQ_FULL = -402,
849 NIX_AF_ERR_AQ_ENQUEUE = -403,
850 NIX_AF_ERR_AF_LF_INVALID = -404,
851 NIX_AF_ERR_AF_LF_ALLOC = -405,
852 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
853 NIX_AF_ERR_TLX_INVALID = -407,
854 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
855 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
856 NIX_AF_ERR_FRS_INVALID = -410,
857 NIX_AF_ERR_RX_LINK_INVALID = -411,
858 NIX_AF_INVAL_TXSCHQ_CFG = -412,
859 NIX_AF_SMQ_FLUSH_FAILED = -413,
860 NIX_AF_ERR_LF_RESET = -414,
861 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
862 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
863 NIX_AF_ERR_MARK_CFG_FAIL = -417,
864 NIX_AF_ERR_LSO_CFG_FAIL = -418,
865 NIX_AF_INVAL_NPA_PF_FUNC = -419,
866 NIX_AF_INVAL_SSO_PF_FUNC = -420,
867 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
868 NIX_AF_ERR_RX_VTAG_INUSE = -422,
869 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
870 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
871 NIX_AF_ERR_INVALID_NIXBLK = -425,
872 NIX_AF_ERR_INVALID_BANDPROF = -426,
873 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
874 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
875 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
876 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
877 NIX_AF_ERR_LINK_CREDITS = -431,
878 NIX_AF_ERR_INVALID_BPID = -434,
879 NIX_AF_ERR_INVALID_BPID_REQ = -435,
880 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
881 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
882 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
883 };
884
885 /* For NIX RX vtag action */
886 enum nix_rx_vtag0_type {
887 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
888 NIX_AF_LFX_RX_VTAG_TYPE1,
889 NIX_AF_LFX_RX_VTAG_TYPE2,
890 NIX_AF_LFX_RX_VTAG_TYPE3,
891 NIX_AF_LFX_RX_VTAG_TYPE4,
892 NIX_AF_LFX_RX_VTAG_TYPE5,
893 NIX_AF_LFX_RX_VTAG_TYPE6,
894 NIX_AF_LFX_RX_VTAG_TYPE7,
895 };
896
897 /* For NIX LF context alloc and init */
898 struct nix_lf_alloc_req {
899 struct mbox_msghdr hdr;
900 int node;
901 u32 rq_cnt; /* No of receive queues */
902 u32 sq_cnt; /* No of send queues */
903 u32 cq_cnt; /* No of completion queues */
904 u8 xqe_sz;
905 u16 rss_sz;
906 u8 rss_grps;
907 u16 npa_func;
908 u16 sso_func;
909 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
910 u64 way_mask;
911 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
912 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
913 u64 flags;
914 };
915
916 struct nix_lf_alloc_rsp {
917 struct mbox_msghdr hdr;
918 u16 sqb_size;
919 u16 rx_chan_base;
920 u16 tx_chan_base;
921 u8 rx_chan_cnt; /* total number of RX channels */
922 u8 tx_chan_cnt; /* total number of TX channels */
923 u8 lso_tsov4_idx;
924 u8 lso_tsov6_idx;
925 u8 mac_addr[ETH_ALEN];
926 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
927 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
928 u16 cints; /* NIX_AF_CONST2::CINTS */
929 u16 qints; /* NIX_AF_CONST2::QINTS */
930 u8 cgx_links; /* No. of CGX links present in HW */
931 u8 lbk_links; /* No. of LBK links present in HW */
932 u8 sdp_links; /* No. of SDP links present in HW */
933 u8 tx_link; /* Transmit channel link number */
934 };
935
936 struct nix_lf_free_req {
937 struct mbox_msghdr hdr;
938 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
939 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
940 u64 flags;
941 };
942
943 /* CN10K NIX AQ enqueue msg */
944 struct nix_cn10k_aq_enq_req {
945 struct mbox_msghdr hdr;
946 u32 qidx;
947 u8 ctype;
948 u8 op;
949 union {
950 struct nix_cn10k_rq_ctx_s rq;
951 struct nix_cn10k_sq_ctx_s sq;
952 struct nix_cq_ctx_s cq;
953 struct nix_rsse_s rss;
954 struct nix_rx_mce_s mce;
955 struct nix_bandprof_s prof;
956 };
957 union {
958 struct nix_cn10k_rq_ctx_s rq_mask;
959 struct nix_cn10k_sq_ctx_s sq_mask;
960 struct nix_cq_ctx_s cq_mask;
961 struct nix_rsse_s rss_mask;
962 struct nix_rx_mce_s mce_mask;
963 struct nix_bandprof_s prof_mask;
964 };
965 };
966
967 struct nix_cn10k_aq_enq_rsp {
968 struct mbox_msghdr hdr;
969 union {
970 struct nix_cn10k_rq_ctx_s rq;
971 struct nix_cn10k_sq_ctx_s sq;
972 struct nix_cq_ctx_s cq;
973 struct nix_rsse_s rss;
974 struct nix_rx_mce_s mce;
975 struct nix_bandprof_s prof;
976 };
977 };
978
979 /* NIX AQ enqueue msg */
980 struct nix_aq_enq_req {
981 struct mbox_msghdr hdr;
982 u32 qidx;
983 u8 ctype;
984 u8 op;
985 union {
986 struct nix_rq_ctx_s rq;
987 struct nix_sq_ctx_s sq;
988 struct nix_cq_ctx_s cq;
989 struct nix_rsse_s rss;
990 struct nix_rx_mce_s mce;
991 struct nix_bandprof_s prof;
992 };
993 union {
994 struct nix_rq_ctx_s rq_mask;
995 struct nix_sq_ctx_s sq_mask;
996 struct nix_cq_ctx_s cq_mask;
997 struct nix_rsse_s rss_mask;
998 struct nix_rx_mce_s mce_mask;
999 struct nix_bandprof_s prof_mask;
1000 };
1001 };
1002
1003 struct nix_aq_enq_rsp {
1004 struct mbox_msghdr hdr;
1005 union {
1006 struct nix_rq_ctx_s rq;
1007 struct nix_sq_ctx_s sq;
1008 struct nix_cq_ctx_s cq;
1009 struct nix_rsse_s rss;
1010 struct nix_rx_mce_s mce;
1011 struct nix_bandprof_s prof;
1012 };
1013 };
1014
1015 /* Tx scheduler/shaper mailbox messages */
1016
1017 #define MAX_TXSCHQ_PER_FUNC 128
1018
1019 struct nix_txsch_alloc_req {
1020 struct mbox_msghdr hdr;
1021 /* Scheduler queue count request at each level */
1022 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
1023 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
1024 };
1025
1026 struct nix_txsch_alloc_rsp {
1027 struct mbox_msghdr hdr;
1028 /* Scheduler queue count allocated at each level */
1029 u16 schq_contig[NIX_TXSCH_LVL_CNT];
1030 u16 schq[NIX_TXSCH_LVL_CNT];
1031 /* Scheduler queue list allocated at each level */
1032 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1033 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1034 u8 aggr_level; /* Traffic aggregation scheduler level */
1035 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
1036 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1037 };
1038
1039 struct nix_txsch_free_req {
1040 struct mbox_msghdr hdr;
1041 #define TXSCHQ_FREE_ALL BIT_ULL(0)
1042 u16 flags;
1043 /* Scheduler queue level to be freed */
1044 u16 schq_lvl;
1045 /* List of scheduler queues to be freed */
1046 u16 schq;
1047 };
1048
1049 struct nix_txschq_config {
1050 struct mbox_msghdr hdr;
1051 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1052 u8 read;
1053 #define TXSCHQ_IDX_SHIFT 16
1054 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1055 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1056 u8 num_regs;
1057 #define MAX_REGS_PER_MBOX_MSG 20
1058 u64 reg[MAX_REGS_PER_MBOX_MSG];
1059 u64 regval[MAX_REGS_PER_MBOX_MSG];
1060 /* All 0's => overwrite with new value */
1061 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1062 };
1063
1064 struct nix_vtag_config {
1065 struct mbox_msghdr hdr;
1066 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1067 u8 vtag_size;
1068 /* cfg_type is '0' for tx vlan cfg
1069 * cfg_type is '1' for rx vlan cfg
1070 */
1071 u8 cfg_type;
1072 union {
1073 /* valid when cfg_type is '0' */
1074 struct {
1075 u64 vtag0;
1076 u64 vtag1;
1077
1078 /* cfg_vtag0 & cfg_vtag1 fields are valid
1079 * when free_vtag0 & free_vtag1 are '0's.
1080 */
1081 /* cfg_vtag0 = 1 to configure vtag0 */
1082 u8 cfg_vtag0 :1;
1083 /* cfg_vtag1 = 1 to configure vtag1 */
1084 u8 cfg_vtag1 :1;
1085
1086 /* vtag0_idx & vtag1_idx are only valid when
1087 * both cfg_vtag0 & cfg_vtag1 are '0's,
1088 * these fields are used along with free_vtag0
1089 * & free_vtag1 to free the nix lf's tx_vlan
1090 * configuration.
1091 *
1092 * Denotes the indices of tx_vtag def registers
1093 * that needs to be cleared and freed.
1094 */
1095 int vtag0_idx;
1096 int vtag1_idx;
1097
1098 /* free_vtag0 & free_vtag1 fields are valid
1099 * when cfg_vtag0 & cfg_vtag1 are '0's.
1100 */
1101 /* free_vtag0 = 1 clears vtag0 configuration
1102 * vtag0_idx denotes the index to be cleared.
1103 */
1104 u8 free_vtag0 :1;
1105 /* free_vtag1 = 1 clears vtag1 configuration
1106 * vtag1_idx denotes the index to be cleared.
1107 */
1108 u8 free_vtag1 :1;
1109 } tx;
1110
1111 /* valid when cfg_type is '1' */
1112 struct {
1113 /* rx vtag type index, valid values are in 0..7 range */
1114 u8 vtag_type;
1115 /* rx vtag strip */
1116 u8 strip_vtag :1;
1117 /* rx vtag capture */
1118 u8 capture_vtag :1;
1119 } rx;
1120 };
1121 };
1122
1123 struct nix_vtag_config_rsp {
1124 struct mbox_msghdr hdr;
1125 int vtag0_idx;
1126 int vtag1_idx;
1127 /* Indices of tx_vtag def registers used to configure
1128 * tx vtag0 & vtag1 headers, these indices are valid
1129 * when nix_vtag_config mbox requested for vtag0 and/
1130 * or vtag1 configuration.
1131 */
1132 };
1133
1134 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1135
1136 struct nix_rss_flowkey_cfg {
1137 struct mbox_msghdr hdr;
1138 int mcam_index; /* MCAM entry index to modify */
1139 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1140 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1141 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1142 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1143 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1144 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1145 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1146 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1147 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1148 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1149 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1150 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1151 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1152 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1153 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1154 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1155 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1156 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1157 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1158 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1159 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1160 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1161 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1162 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1163 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1164 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1165 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1166 u32 flowkey_cfg; /* Flowkey types selected */
1167 u8 group; /* RSS context or group */
1168 };
1169
1170 struct nix_rss_flowkey_cfg_rsp {
1171 struct mbox_msghdr hdr;
1172 u8 alg_idx; /* Selected algo index */
1173 };
1174
1175 struct nix_set_mac_addr {
1176 struct mbox_msghdr hdr;
1177 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1178 };
1179
1180 struct nix_get_mac_addr_rsp {
1181 struct mbox_msghdr hdr;
1182 u8 mac_addr[ETH_ALEN];
1183 };
1184
1185 struct nix_mark_format_cfg {
1186 struct mbox_msghdr hdr;
1187 u8 offset;
1188 u8 y_mask;
1189 u8 y_val;
1190 u8 r_mask;
1191 u8 r_val;
1192 };
1193
1194 struct nix_mark_format_cfg_rsp {
1195 struct mbox_msghdr hdr;
1196 u8 mark_format_idx;
1197 };
1198
1199 struct nix_rx_mode {
1200 struct mbox_msghdr hdr;
1201 #define NIX_RX_MODE_UCAST BIT(0)
1202 #define NIX_RX_MODE_PROMISC BIT(1)
1203 #define NIX_RX_MODE_ALLMULTI BIT(2)
1204 #define NIX_RX_MODE_USE_MCE BIT(3)
1205 u16 mode;
1206 };
1207
1208 struct nix_rx_cfg {
1209 struct mbox_msghdr hdr;
1210 #define NIX_RX_OL3_VERIFY BIT(0)
1211 #define NIX_RX_OL4_VERIFY BIT(1)
1212 #define NIX_RX_DROP_RE BIT(2)
1213 u8 len_verify; /* Outer L3/L4 len check */
1214 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1215 u8 csum_verify; /* Outer L4 checksum verification */
1216 };
1217
1218 struct nix_frs_cfg {
1219 struct mbox_msghdr hdr;
1220 u8 update_smq; /* Update SMQ's min/max lens */
1221 u8 update_minlen; /* Set minlen also */
1222 u8 sdp_link; /* Set SDP RX link */
1223 u16 maxlen;
1224 u16 minlen;
1225 };
1226
1227 struct nix_lso_format_cfg {
1228 struct mbox_msghdr hdr;
1229 u64 field_mask;
1230 #define NIX_LSO_FIELD_MAX 8
1231 u64 fields[NIX_LSO_FIELD_MAX];
1232 };
1233
1234 struct nix_lso_format_cfg_rsp {
1235 struct mbox_msghdr hdr;
1236 u8 lso_format_idx;
1237 };
1238
1239 struct nix_bp_cfg_req {
1240 struct mbox_msghdr hdr;
1241 u16 chan_base; /* Starting channel number */
1242 u8 chan_cnt; /* Number of channels */
1243 u8 bpid_per_chan;
1244 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1245 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1246 };
1247
1248 /* Maximum channels any single NIX interface can have */
1249 #define NIX_MAX_BPID_CHAN 256
1250 struct nix_bp_cfg_rsp {
1251 struct mbox_msghdr hdr;
1252 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1253 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1254 };
1255
1256 struct nix_mcast_grp_create_req {
1257 struct mbox_msghdr hdr;
1258 #define NIX_MCAST_INGRESS 0
1259 #define NIX_MCAST_EGRESS 1
1260 u8 dir;
1261 u8 reserved[11];
1262 /* Reserving few bytes for future requirement */
1263 };
1264
1265 struct nix_mcast_grp_create_rsp {
1266 struct mbox_msghdr hdr;
1267 /* This mcast_grp_idx should be passed during MCAM
1268 * write entry for multicast. AF will identify the
1269 * corresponding multicast table index associated
1270 * with the group id and program the same to MCAM entry.
1271 * This group id is also needed during group delete
1272 * and update request.
1273 */
1274 u32 mcast_grp_idx;
1275 };
1276
1277 struct nix_mcast_grp_destroy_req {
1278 struct mbox_msghdr hdr;
1279 /* Group id returned by nix_mcast_grp_create_rsp */
1280 u32 mcast_grp_idx;
1281 /* If AF is requesting for destroy, then set
1282 * it to '1'. Otherwise keep it to '0'
1283 */
1284 u8 is_af;
1285 };
1286
1287 struct nix_mcast_grp_update_req {
1288 struct mbox_msghdr hdr;
1289 /* Group id returned by nix_mcast_grp_create_rsp */
1290 u32 mcast_grp_idx;
1291 /* Number of multicast/mirror entries requested */
1292 u32 num_mce_entry;
1293 #define NIX_MCE_ENTRY_MAX 64
1294 #define NIX_RX_RQ 0
1295 #define NIX_RX_RSS 1
1296 /* Receive queue or RSS index within pf_func */
1297 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1298 /* pcifunc is required for both ingress and egress multicast */
1299 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1300 /* channel is required for egress multicast */
1301 u16 channel[NIX_MCE_ENTRY_MAX];
1302 #define NIX_MCAST_OP_ADD_ENTRY 0
1303 #define NIX_MCAST_OP_DEL_ENTRY 1
1304 /* Destination type. 0:Receive queue, 1:RSS*/
1305 u8 dest_type[NIX_MCE_ENTRY_MAX];
1306 u8 op;
1307 /* If AF is requesting for update, then set
1308 * it to '1'. Otherwise keep it to '0'
1309 */
1310 u8 is_af;
1311 };
1312
1313 struct nix_mcast_grp_update_rsp {
1314 struct mbox_msghdr hdr;
1315 u32 mce_start_index;
1316 };
1317
1318 /* Global NIX inline IPSec configuration */
1319 struct nix_inline_ipsec_cfg {
1320 struct mbox_msghdr hdr;
1321 u32 cpt_credit;
1322 struct {
1323 u8 egrp;
1324 u16 opcode;
1325 u16 param1;
1326 u16 param2;
1327 } gen_cfg;
1328 struct {
1329 u16 cpt_pf_func;
1330 u8 cpt_slot;
1331 } inst_qsel;
1332 u8 enable;
1333 u16 bpid;
1334 u32 credit_th;
1335 };
1336
1337 /* Per NIX LF inline IPSec configuration */
1338 struct nix_inline_ipsec_lf_cfg {
1339 struct mbox_msghdr hdr;
1340 u64 sa_base_addr;
1341 struct {
1342 u32 tag_const;
1343 u16 lenm1_max;
1344 u8 sa_pow2_size;
1345 u8 tt;
1346 } ipsec_cfg0;
1347 struct {
1348 u32 sa_idx_max;
1349 u8 sa_idx_w;
1350 } ipsec_cfg1;
1351 u8 enable;
1352 };
1353
1354 struct nix_hw_info {
1355 struct mbox_msghdr hdr;
1356 u16 rsvs16;
1357 u16 max_mtu;
1358 u16 min_mtu;
1359 u32 rpm_dwrr_mtu;
1360 u32 sdp_dwrr_mtu;
1361 u32 lbk_dwrr_mtu;
1362 u32 rsvd32[1];
1363 u64 rsvd[15]; /* Add reserved fields for future expansion */
1364 };
1365
1366 struct nix_bandprof_alloc_req {
1367 struct mbox_msghdr hdr;
1368 /* Count of profiles needed per layer */
1369 u16 prof_count[BAND_PROF_NUM_LAYERS];
1370 };
1371
1372 struct nix_bandprof_alloc_rsp {
1373 struct mbox_msghdr hdr;
1374 u16 prof_count[BAND_PROF_NUM_LAYERS];
1375
1376 /* There is no need to allocate morethan 1 bandwidth profile
1377 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1378 * profiles to 64 per PF_FUNC.
1379 */
1380 #define MAX_BANDPROF_PER_PFFUNC 64
1381 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1382 };
1383
1384 struct nix_bandprof_free_req {
1385 struct mbox_msghdr hdr;
1386 u8 free_all;
1387 u16 prof_count[BAND_PROF_NUM_LAYERS];
1388 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1389 };
1390
1391 struct nix_bandprof_get_hwinfo_rsp {
1392 struct mbox_msghdr hdr;
1393 u16 prof_count[BAND_PROF_NUM_LAYERS];
1394 u32 policer_timeunit;
1395 };
1396
1397 struct nix_stats_req {
1398 struct mbox_msghdr hdr;
1399 u8 reset;
1400 u16 pcifunc;
1401 u64 rsvd;
1402 };
1403
1404 struct nix_stats_rsp {
1405 struct mbox_msghdr hdr;
1406 u16 pcifunc;
1407 struct {
1408 u64 octs;
1409 u64 ucast;
1410 u64 bcast;
1411 u64 mcast;
1412 u64 drop;
1413 u64 drop_octs;
1414 u64 drop_mcast;
1415 u64 drop_bcast;
1416 u64 err;
1417 u64 rsvd[5];
1418 } rx;
1419 struct {
1420 u64 ucast;
1421 u64 bcast;
1422 u64 mcast;
1423 u64 drop;
1424 u64 octs;
1425 } tx;
1426 };
1427
1428 /* NPC mbox message structs */
1429
1430 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1431 #define NPC_MCAM_INVALID_MAP 0xFFFF
1432
1433 /* NPC mailbox error codes
1434 * Range 701 - 800.
1435 */
1436 enum npc_af_status {
1437 NPC_MCAM_INVALID_REQ = -701,
1438 NPC_MCAM_ALLOC_DENIED = -702,
1439 NPC_MCAM_ALLOC_FAILED = -703,
1440 NPC_MCAM_PERM_DENIED = -704,
1441 NPC_FLOW_INTF_INVALID = -707,
1442 NPC_FLOW_CHAN_INVALID = -708,
1443 NPC_FLOW_NO_NIXLF = -709,
1444 NPC_FLOW_NOT_SUPPORTED = -710,
1445 NPC_FLOW_VF_PERM_DENIED = -711,
1446 NPC_FLOW_VF_NOT_INIT = -712,
1447 NPC_FLOW_VF_OVERLAP = -713,
1448 };
1449
1450 struct npc_mcam_alloc_entry_req {
1451 struct mbox_msghdr hdr;
1452 #define NPC_MAX_NONCONTIG_ENTRIES 256
1453 u8 contig; /* Contiguous entries ? */
1454 #define NPC_MCAM_ANY_PRIO 0
1455 #define NPC_MCAM_LOWER_PRIO 1
1456 #define NPC_MCAM_HIGHER_PRIO 2
1457 u8 priority; /* Lower or higher w.r.t ref_entry */
1458 u16 ref_entry;
1459 u16 count; /* Number of entries requested */
1460 };
1461
1462 struct npc_mcam_alloc_entry_rsp {
1463 struct mbox_msghdr hdr;
1464 u16 entry; /* Entry allocated or start index if contiguous.
1465 * Invalid incase of non-contiguous.
1466 */
1467 u16 count; /* Number of entries allocated */
1468 u16 free_count; /* Number of entries available */
1469 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1470 };
1471
1472 struct npc_mcam_free_entry_req {
1473 struct mbox_msghdr hdr;
1474 u16 entry; /* Entry index to be freed */
1475 u8 all; /* If all entries allocated to this PFVF to be freed */
1476 };
1477
1478 struct mcam_entry {
1479 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1480 u64 kw[NPC_MAX_KWS_IN_KEY];
1481 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1482 u64 action;
1483 u64 vtag_action;
1484 };
1485
1486 struct npc_mcam_write_entry_req {
1487 struct mbox_msghdr hdr;
1488 struct mcam_entry entry_data;
1489 u16 entry; /* MCAM entry to write this match key */
1490 u16 cntr; /* Counter for this MCAM entry */
1491 u8 intf; /* Rx or Tx interface */
1492 u8 enable_entry;/* Enable this MCAM entry ? */
1493 u8 set_cntr; /* Set counter for this entry ? */
1494 };
1495
1496 /* Enable/Disable a given entry */
1497 struct npc_mcam_ena_dis_entry_req {
1498 struct mbox_msghdr hdr;
1499 u16 entry;
1500 };
1501
1502 struct npc_mcam_shift_entry_req {
1503 struct mbox_msghdr hdr;
1504 #define NPC_MCAM_MAX_SHIFTS 64
1505 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1506 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1507 u16 shift_count; /* Number of entries to shift */
1508 };
1509
1510 struct npc_mcam_shift_entry_rsp {
1511 struct mbox_msghdr hdr;
1512 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1513 };
1514
1515 struct npc_mcam_alloc_counter_req {
1516 struct mbox_msghdr hdr;
1517 u8 contig; /* Contiguous counters ? */
1518 #define NPC_MAX_NONCONTIG_COUNTERS 64
1519 u16 count; /* Number of counters requested */
1520 };
1521
1522 struct npc_mcam_alloc_counter_rsp {
1523 struct mbox_msghdr hdr;
1524 u16 cntr; /* Counter allocated or start index if contiguous.
1525 * Invalid incase of non-contiguous.
1526 */
1527 u16 count; /* Number of counters allocated */
1528 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1529 };
1530
1531 struct npc_mcam_oper_counter_req {
1532 struct mbox_msghdr hdr;
1533 u16 cntr; /* Free a counter or clear/fetch it's stats */
1534 };
1535
1536 struct npc_mcam_oper_counter_rsp {
1537 struct mbox_msghdr hdr;
1538 u64 stat; /* valid only while fetching counter's stats */
1539 };
1540
1541 struct npc_mcam_unmap_counter_req {
1542 struct mbox_msghdr hdr;
1543 u16 cntr;
1544 u16 entry; /* Entry and counter to be unmapped */
1545 u8 all; /* Unmap all entries using this counter ? */
1546 };
1547
1548 struct npc_mcam_alloc_and_write_entry_req {
1549 struct mbox_msghdr hdr;
1550 struct mcam_entry entry_data;
1551 u16 ref_entry;
1552 u8 priority; /* Lower or higher w.r.t ref_entry */
1553 u8 intf; /* Rx or Tx interface */
1554 u8 enable_entry;/* Enable this MCAM entry ? */
1555 u8 alloc_cntr; /* Allocate counter and map ? */
1556 };
1557
1558 struct npc_mcam_alloc_and_write_entry_rsp {
1559 struct mbox_msghdr hdr;
1560 u16 entry;
1561 u16 cntr;
1562 };
1563
1564 struct npc_get_kex_cfg_rsp {
1565 struct mbox_msghdr hdr;
1566 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1567 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1568 #define NPC_MAX_INTF 2
1569 #define NPC_MAX_LID 8
1570 #define NPC_MAX_LT 16
1571 #define NPC_MAX_LD 2
1572 #define NPC_MAX_LFL 16
1573 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1574 u64 kex_ld_flags[NPC_MAX_LD];
1575 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1576 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1577 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1578 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1579 #define MKEX_NAME_LEN 128
1580 u8 mkex_pfl_name[MKEX_NAME_LEN];
1581 };
1582
1583 struct ptp_get_cap_rsp {
1584 struct mbox_msghdr hdr;
1585 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1586 u64 cap;
1587 };
1588
1589 struct get_rep_cnt_rsp {
1590 struct mbox_msghdr hdr;
1591 u16 rep_cnt;
1592 u16 rep_pf_map[64];
1593 u64 rsvd;
1594 };
1595
1596 struct esw_cfg_req {
1597 struct mbox_msghdr hdr;
1598 u8 ena;
1599 u64 rsvd;
1600 };
1601
1602 struct rep_evt_data {
1603 u8 port_state;
1604 u8 vf_state;
1605 u16 rx_mode;
1606 u16 rx_flags;
1607 u16 mtu;
1608 u8 mac[ETH_ALEN];
1609 u64 rsvd[5];
1610 };
1611
1612 struct rep_event {
1613 struct mbox_msghdr hdr;
1614 u16 pcifunc;
1615 #define RVU_EVENT_PORT_STATE BIT_ULL(0)
1616 #define RVU_EVENT_PFVF_STATE BIT_ULL(1)
1617 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2)
1618 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3)
1619 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4)
1620 u16 event;
1621 struct rep_evt_data evt_data;
1622 };
1623
1624 struct flow_msg {
1625 unsigned char dmac[6];
1626 unsigned char smac[6];
1627 __be16 etype;
1628 __be16 vlan_etype;
1629 __be16 vlan_tci;
1630 union {
1631 __be32 ip4src;
1632 __be32 ip6src[4];
1633 };
1634 union {
1635 __be32 ip4dst;
1636 __be32 ip6dst[4];
1637 };
1638 union {
1639 __be32 spi;
1640 };
1641
1642 u8 tos;
1643 u8 ip_ver;
1644 u8 ip_proto;
1645 u8 tc;
1646 __be16 sport;
1647 __be16 dport;
1648 union {
1649 u8 ip_flag;
1650 u8 next_header;
1651 };
1652 __be16 vlan_itci;
1653 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1654 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1655 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1656 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1657 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1658 u32 mpls_lse[4];
1659 u8 icmp_type;
1660 u8 icmp_code;
1661 __be16 tcp_flags;
1662 u16 sq_id;
1663 };
1664
1665 struct npc_install_flow_req {
1666 struct mbox_msghdr hdr;
1667 struct flow_msg packet;
1668 struct flow_msg mask;
1669 u64 features;
1670 u16 entry;
1671 u16 channel;
1672 u16 chan_mask;
1673 u8 intf;
1674 u8 set_cntr; /* If counter is available set counter for this entry ? */
1675 u8 default_rule;
1676 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1677 u16 vf;
1678 /* action */
1679 u32 index;
1680 u16 match_id;
1681 u8 flow_key_alg;
1682 u8 op;
1683 /* vtag rx action */
1684 u8 vtag0_type;
1685 u8 vtag0_valid;
1686 u8 vtag1_type;
1687 u8 vtag1_valid;
1688 /* vtag tx action */
1689 u16 vtag0_def;
1690 u8 vtag0_op;
1691 u16 vtag1_def;
1692 u8 vtag1_op;
1693 /* old counter value */
1694 u16 cntr_val;
1695 };
1696
1697 struct npc_install_flow_rsp {
1698 struct mbox_msghdr hdr;
1699 int counter; /* negative if no counter else counter number */
1700 };
1701
1702 struct npc_delete_flow_req {
1703 struct mbox_msghdr hdr;
1704 u16 entry;
1705 u16 start;/*Disable range of entries */
1706 u16 end;
1707 u8 all; /* PF + VFs */
1708 };
1709
1710 struct npc_delete_flow_rsp {
1711 struct mbox_msghdr hdr;
1712 u16 cntr_val;
1713 };
1714
1715 struct npc_mcam_read_entry_req {
1716 struct mbox_msghdr hdr;
1717 u16 entry; /* MCAM entry to read */
1718 };
1719
1720 struct npc_mcam_read_entry_rsp {
1721 struct mbox_msghdr hdr;
1722 struct mcam_entry entry_data;
1723 u8 intf;
1724 u8 enable;
1725 };
1726
1727 struct npc_mcam_read_base_rule_rsp {
1728 struct mbox_msghdr hdr;
1729 struct mcam_entry entry;
1730 };
1731
1732 struct npc_mcam_get_stats_req {
1733 struct mbox_msghdr hdr;
1734 u16 entry; /* mcam entry */
1735 };
1736
1737 struct npc_mcam_get_stats_rsp {
1738 struct mbox_msghdr hdr;
1739 u64 stat; /* counter stats */
1740 u8 stat_ena; /* enabled */
1741 };
1742
1743 struct npc_get_field_hash_info_req {
1744 struct mbox_msghdr hdr;
1745 u8 intf;
1746 };
1747
1748 struct npc_get_field_hash_info_rsp {
1749 struct mbox_msghdr hdr;
1750 u64 secret_key[3];
1751 #define NPC_MAX_HASH 2
1752 #define NPC_MAX_HASH_MASK 2
1753 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1754 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1755 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1756 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1757 };
1758
1759 enum ptp_op {
1760 PTP_OP_ADJFINE = 0,
1761 PTP_OP_GET_CLOCK = 1,
1762 PTP_OP_GET_TSTMP = 2,
1763 PTP_OP_SET_THRESH = 3,
1764 PTP_OP_PPS_ON = 4,
1765 PTP_OP_ADJTIME = 5,
1766 PTP_OP_SET_CLOCK = 6,
1767 };
1768
1769 struct ptp_req {
1770 struct mbox_msghdr hdr;
1771 u8 op;
1772 s64 scaled_ppm;
1773 u64 thresh;
1774 u64 period;
1775 int pps_on;
1776 s64 delta;
1777 u64 clk;
1778 };
1779
1780 struct ptp_rsp {
1781 struct mbox_msghdr hdr;
1782 u64 clk;
1783 u64 tsc;
1784 };
1785
1786 struct npc_get_field_status_req {
1787 struct mbox_msghdr hdr;
1788 u8 intf;
1789 u8 field;
1790 };
1791
1792 struct npc_get_field_status_rsp {
1793 struct mbox_msghdr hdr;
1794 u8 enable;
1795 };
1796
1797 struct set_vf_perm {
1798 struct mbox_msghdr hdr;
1799 u16 vf;
1800 #define RESET_VF_PERM BIT_ULL(0)
1801 #define VF_TRUSTED BIT_ULL(1)
1802 u64 flags;
1803 };
1804
1805 struct lmtst_tbl_setup_req {
1806 struct mbox_msghdr hdr;
1807 u64 dis_sched_early_comp :1;
1808 u64 sch_ena :1;
1809 u64 dis_line_pref :1;
1810 u64 ssow_pf_func :13;
1811 u16 base_pcifunc;
1812 u8 use_local_lmt_region;
1813 u64 lmt_iova;
1814 u64 rsvd[4];
1815 };
1816
1817 struct ndc_sync_op {
1818 struct mbox_msghdr hdr;
1819 u8 nix_lf_tx_sync;
1820 u8 nix_lf_rx_sync;
1821 u8 npa_lf_sync;
1822 };
1823
1824 /* CPT mailbox error codes
1825 * Range 901 - 1000.
1826 */
1827 enum cpt_af_status {
1828 CPT_AF_ERR_PARAM = -901,
1829 CPT_AF_ERR_GRP_INVALID = -902,
1830 CPT_AF_ERR_LF_INVALID = -903,
1831 CPT_AF_ERR_ACCESS_DENIED = -904,
1832 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1833 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1834 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1835 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1836 };
1837
1838 /* CPT mbox message formats */
1839 struct cpt_rd_wr_reg_msg {
1840 struct mbox_msghdr hdr;
1841 u64 reg_offset;
1842 u64 *ret_val;
1843 u64 val;
1844 u8 is_write;
1845 int blkaddr;
1846 };
1847
1848 struct cpt_lf_alloc_req_msg {
1849 struct mbox_msghdr hdr;
1850 u16 nix_pf_func;
1851 u16 sso_pf_func;
1852 u16 eng_grpmsk;
1853 u8 blkaddr;
1854 u8 ctx_ilen_valid : 1;
1855 u8 ctx_ilen : 7;
1856 };
1857
1858 #define CPT_INLINE_INBOUND 0
1859 #define CPT_INLINE_OUTBOUND 1
1860
1861 /* Mailbox message request format for CPT IPsec
1862 * inline inbound and outbound configuration.
1863 */
1864 struct cpt_inline_ipsec_cfg_msg {
1865 struct mbox_msghdr hdr;
1866 u8 enable;
1867 u8 slot;
1868 u8 dir;
1869 u8 sso_pf_func_ovrd;
1870 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1871 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1872 };
1873
1874 /* Mailbox message request and response format for CPT stats. */
1875 struct cpt_sts_req {
1876 struct mbox_msghdr hdr;
1877 u8 blkaddr;
1878 };
1879
1880 struct cpt_sts_rsp {
1881 struct mbox_msghdr hdr;
1882 u64 inst_req_pc;
1883 u64 inst_lat_pc;
1884 u64 rd_req_pc;
1885 u64 rd_lat_pc;
1886 u64 rd_uc_pc;
1887 u64 active_cycles_pc;
1888 u64 ctx_mis_pc;
1889 u64 ctx_hit_pc;
1890 u64 ctx_aop_pc;
1891 u64 ctx_aop_lat_pc;
1892 u64 ctx_ifetch_pc;
1893 u64 ctx_ifetch_lat_pc;
1894 u64 ctx_ffetch_pc;
1895 u64 ctx_ffetch_lat_pc;
1896 u64 ctx_wback_pc;
1897 u64 ctx_wback_lat_pc;
1898 u64 ctx_psh_pc;
1899 u64 ctx_psh_lat_pc;
1900 u64 ctx_err;
1901 u64 ctx_enc_id;
1902 u64 ctx_flush_timer;
1903 u64 rxc_time;
1904 u64 rxc_time_cfg;
1905 u64 rxc_active_sts;
1906 u64 rxc_zombie_sts;
1907 u64 busy_sts_ae;
1908 u64 free_sts_ae;
1909 u64 busy_sts_se;
1910 u64 free_sts_se;
1911 u64 busy_sts_ie;
1912 u64 free_sts_ie;
1913 u64 exe_err_info;
1914 u64 cptclk_cnt;
1915 u64 diag;
1916 u64 rxc_dfrg;
1917 u64 x2p_link_cfg0;
1918 u64 x2p_link_cfg1;
1919 };
1920
1921 /* Mailbox message request format to configure reassembly timeout. */
1922 struct cpt_rxc_time_cfg_req {
1923 struct mbox_msghdr hdr;
1924 int blkaddr;
1925 u32 step;
1926 u16 zombie_thres;
1927 u16 zombie_limit;
1928 u16 active_thres;
1929 u16 active_limit;
1930 };
1931
1932 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1933 struct cpt_inst_lmtst_req {
1934 struct mbox_msghdr hdr;
1935 u64 inst[8];
1936 u64 rsvd;
1937 };
1938
1939 /* Mailbox message format to request for CPT LF reset */
1940 struct cpt_lf_rst_req {
1941 struct mbox_msghdr hdr;
1942 u32 slot;
1943 u32 rsvd;
1944 };
1945
1946 /* Mailbox message format to request for CPT faulted engines */
1947 struct cpt_flt_eng_info_req {
1948 struct mbox_msghdr hdr;
1949 int blkaddr;
1950 bool reset;
1951 u32 rsvd;
1952 };
1953
1954 struct cpt_flt_eng_info_rsp {
1955 struct mbox_msghdr hdr;
1956 #define CPT_AF_MAX_FLT_INT_VECS 3
1957 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1958 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1959 u64 rsvd;
1960 };
1961
1962 struct sdp_node_info {
1963 /* Node to which this PF belons to */
1964 u8 node_id;
1965 u8 max_vfs;
1966 u8 num_pf_rings;
1967 u8 pf_srn;
1968 #define SDP_MAX_VFS 128
1969 u8 vf_rings[SDP_MAX_VFS];
1970 };
1971
1972 struct sdp_chan_info_msg {
1973 struct mbox_msghdr hdr;
1974 struct sdp_node_info info;
1975 };
1976
1977 struct sdp_get_chan_info_msg {
1978 struct mbox_msghdr hdr;
1979 u16 chan_base;
1980 u16 num_chan;
1981 };
1982
1983 /* CGX mailbox error codes
1984 * Range 1101 - 1200.
1985 */
1986 enum cgx_af_status {
1987 LMAC_AF_ERR_INVALID_PARAM = -1101,
1988 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1989 LMAC_AF_ERR_PERM_DENIED = -1103,
1990 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1991 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1992 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1993 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1994 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1995 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1996 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1997 };
1998
1999 enum mcs_direction {
2000 MCS_RX,
2001 MCS_TX,
2002 };
2003
2004 enum mcs_rsrc_type {
2005 MCS_RSRC_TYPE_FLOWID,
2006 MCS_RSRC_TYPE_SECY,
2007 MCS_RSRC_TYPE_SC,
2008 MCS_RSRC_TYPE_SA,
2009 };
2010
2011 struct mcs_alloc_rsrc_req {
2012 struct mbox_msghdr hdr;
2013 u8 rsrc_type;
2014 u8 rsrc_cnt; /* Resources count */
2015 u8 mcs_id; /* MCS block ID */
2016 u8 dir; /* Macsec ingress or egress side */
2017 u8 all; /* Allocate all resource type one each */
2018 u64 rsvd;
2019 };
2020
2021 struct mcs_alloc_rsrc_rsp {
2022 struct mbox_msghdr hdr;
2023 u8 flow_ids[128]; /* Index of reserved entries */
2024 u8 secy_ids[128];
2025 u8 sc_ids[128];
2026 u8 sa_ids[256];
2027 u8 rsrc_type;
2028 u8 rsrc_cnt; /* No of entries reserved */
2029 u8 mcs_id;
2030 u8 dir;
2031 u8 all;
2032 u8 rsvd[256]; /* reserved fields for future expansion */
2033 };
2034
2035 struct mcs_free_rsrc_req {
2036 struct mbox_msghdr hdr;
2037 u8 rsrc_id; /* Index of the entry to be freed */
2038 u8 rsrc_type;
2039 u8 mcs_id;
2040 u8 dir;
2041 u8 all; /* Free all the cam resources */
2042 u64 rsvd;
2043 };
2044
2045 struct mcs_flowid_entry_write_req {
2046 struct mbox_msghdr hdr;
2047 u64 data[4];
2048 u64 mask[4];
2049 u64 sci; /* CNF10K-B for tx_secy_mem_map */
2050 u8 flow_id;
2051 u8 secy_id; /* secyid for which flowid is mapped */
2052 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
2053 u8 ena; /* Enable tcam entry */
2054 u8 ctrl_pkt;
2055 u8 mcs_id;
2056 u8 dir;
2057 u64 rsvd;
2058 };
2059
2060 struct mcs_secy_plcy_write_req {
2061 struct mbox_msghdr hdr;
2062 u64 plcy;
2063 u8 secy_id;
2064 u8 mcs_id;
2065 u8 dir;
2066 u64 rsvd;
2067 };
2068
2069 /* RX SC_CAM mapping */
2070 struct mcs_rx_sc_cam_write_req {
2071 struct mbox_msghdr hdr;
2072 u64 sci; /* SCI */
2073 u64 secy_id; /* secy index mapped to SC */
2074 u8 sc_id; /* SC CAM entry index */
2075 u8 mcs_id;
2076 u64 rsvd;
2077 };
2078
2079 struct mcs_sa_plcy_write_req {
2080 struct mbox_msghdr hdr;
2081 u64 plcy[2][9]; /* Support 2 SA policy */
2082 u8 sa_index[2];
2083 u8 sa_cnt;
2084 u8 mcs_id;
2085 u8 dir;
2086 u64 rsvd;
2087 };
2088
2089 struct mcs_tx_sc_sa_map {
2090 struct mbox_msghdr hdr;
2091 u8 sa_index0;
2092 u8 sa_index1;
2093 u8 rekey_ena;
2094 u8 sa_index0_vld;
2095 u8 sa_index1_vld;
2096 u8 tx_sa_active;
2097 u64 sectag_sci;
2098 u8 sc_id; /* used as index for SA_MEM_MAP */
2099 u8 mcs_id;
2100 u64 rsvd;
2101 };
2102
2103 struct mcs_rx_sc_sa_map {
2104 struct mbox_msghdr hdr;
2105 u8 sa_index;
2106 u8 sa_in_use;
2107 u8 sc_id;
2108 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
2109 u8 mcs_id;
2110 u64 rsvd;
2111 };
2112
2113 struct mcs_flowid_ena_dis_entry {
2114 struct mbox_msghdr hdr;
2115 u8 flow_id;
2116 u8 ena;
2117 u8 mcs_id;
2118 u8 dir;
2119 u64 rsvd;
2120 };
2121
2122 struct mcs_pn_table_write_req {
2123 struct mbox_msghdr hdr;
2124 u64 next_pn;
2125 u8 pn_id;
2126 u8 mcs_id;
2127 u8 dir;
2128 u64 rsvd;
2129 };
2130
2131 struct mcs_hw_info {
2132 struct mbox_msghdr hdr;
2133 u8 num_mcs_blks; /* Number of MCS blocks */
2134 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2135 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2136 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2137 u16 sa_entries; /* PN table entries = SA entries */
2138 u64 rsvd[16];
2139 };
2140
2141 struct mcs_set_active_lmac {
2142 struct mbox_msghdr hdr;
2143 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2144 u8 mcs_id;
2145 u16 chan_base; /* MCS channel base */
2146 u64 rsvd;
2147 };
2148
2149 struct mcs_set_lmac_mode {
2150 struct mbox_msghdr hdr;
2151 u8 mode; /* 1:Bypass 0:Operational */
2152 u8 lmac_id;
2153 u8 mcs_id;
2154 u64 rsvd;
2155 };
2156
2157 struct mcs_port_reset_req {
2158 struct mbox_msghdr hdr;
2159 u8 reset;
2160 u8 mcs_id;
2161 u8 port_id;
2162 u64 rsvd;
2163 };
2164
2165 struct mcs_port_cfg_set_req {
2166 struct mbox_msghdr hdr;
2167 u8 cstm_tag_rel_mode_sel;
2168 u8 custom_hdr_enb;
2169 u8 fifo_skid;
2170 u8 port_mode;
2171 u8 port_id;
2172 u8 mcs_id;
2173 u64 rsvd;
2174 };
2175
2176 struct mcs_port_cfg_get_req {
2177 struct mbox_msghdr hdr;
2178 u8 port_id;
2179 u8 mcs_id;
2180 u64 rsvd;
2181 };
2182
2183 struct mcs_port_cfg_get_rsp {
2184 struct mbox_msghdr hdr;
2185 u8 cstm_tag_rel_mode_sel;
2186 u8 custom_hdr_enb;
2187 u8 fifo_skid;
2188 u8 port_mode;
2189 u8 port_id;
2190 u8 mcs_id;
2191 u64 rsvd;
2192 };
2193
2194 struct mcs_custom_tag_cfg_get_req {
2195 struct mbox_msghdr hdr;
2196 u8 mcs_id;
2197 u8 dir;
2198 u64 rsvd;
2199 };
2200
2201 struct mcs_custom_tag_cfg_get_rsp {
2202 struct mbox_msghdr hdr;
2203 u16 cstm_etype[8];
2204 u8 cstm_indx[8];
2205 u8 cstm_etype_en;
2206 u8 mcs_id;
2207 u8 dir;
2208 u64 rsvd;
2209 };
2210
2211 /* MCS mailbox error codes
2212 * Range 1201 - 1300.
2213 */
2214 enum mcs_af_status {
2215 MCS_AF_ERR_INVALID_MCSID = -1201,
2216 MCS_AF_ERR_NOT_MAPPED = -1202,
2217 };
2218
2219 struct mcs_set_pn_threshold {
2220 struct mbox_msghdr hdr;
2221 u64 threshold;
2222 u8 xpn; /* '1' for setting xpn threshold */
2223 u8 mcs_id;
2224 u8 dir;
2225 u64 rsvd;
2226 };
2227
2228 enum mcs_ctrl_pkt_rulew_type {
2229 MCS_CTRL_PKT_RULE_TYPE_ETH,
2230 MCS_CTRL_PKT_RULE_TYPE_DA,
2231 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2232 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2233 MCS_CTRL_PKT_RULE_TYPE_MAC,
2234 };
2235
2236 struct mcs_alloc_ctrl_pkt_rule_req {
2237 struct mbox_msghdr hdr;
2238 u8 rule_type;
2239 u8 mcs_id; /* MCS block ID */
2240 u8 dir; /* Macsec ingress or egress side */
2241 u64 rsvd;
2242 };
2243
2244 struct mcs_alloc_ctrl_pkt_rule_rsp {
2245 struct mbox_msghdr hdr;
2246 u8 rule_idx;
2247 u8 rule_type;
2248 u8 mcs_id;
2249 u8 dir;
2250 u64 rsvd;
2251 };
2252
2253 struct mcs_free_ctrl_pkt_rule_req {
2254 struct mbox_msghdr hdr;
2255 u8 rule_idx;
2256 u8 rule_type;
2257 u8 mcs_id;
2258 u8 dir;
2259 u8 all;
2260 u64 rsvd;
2261 };
2262
2263 struct mcs_ctrl_pkt_rule_write_req {
2264 struct mbox_msghdr hdr;
2265 u64 data0;
2266 u64 data1;
2267 u64 data2;
2268 u8 rule_idx;
2269 u8 rule_type;
2270 u8 mcs_id;
2271 u8 dir;
2272 u64 rsvd;
2273 };
2274
2275 struct mcs_stats_req {
2276 struct mbox_msghdr hdr;
2277 u8 id;
2278 u8 mcs_id;
2279 u8 dir;
2280 u64 rsvd;
2281 };
2282
2283 struct mcs_flowid_stats {
2284 struct mbox_msghdr hdr;
2285 u64 tcam_hit_cnt;
2286 u64 rsvd;
2287 };
2288
2289 struct mcs_secy_stats {
2290 struct mbox_msghdr hdr;
2291 u64 ctl_pkt_bcast_cnt;
2292 u64 ctl_pkt_mcast_cnt;
2293 u64 ctl_pkt_ucast_cnt;
2294 u64 ctl_octet_cnt;
2295 u64 unctl_pkt_bcast_cnt;
2296 u64 unctl_pkt_mcast_cnt;
2297 u64 unctl_pkt_ucast_cnt;
2298 u64 unctl_octet_cnt;
2299 /* Valid only for RX */
2300 u64 octet_decrypted_cnt;
2301 u64 octet_validated_cnt;
2302 u64 pkt_port_disabled_cnt;
2303 u64 pkt_badtag_cnt;
2304 u64 pkt_nosa_cnt;
2305 u64 pkt_nosaerror_cnt;
2306 u64 pkt_tagged_ctl_cnt;
2307 u64 pkt_untaged_cnt;
2308 u64 pkt_ctl_cnt; /* CN10K-B */
2309 u64 pkt_notag_cnt; /* CNF10K-B */
2310 /* Valid only for TX */
2311 u64 octet_encrypted_cnt;
2312 u64 octet_protected_cnt;
2313 u64 pkt_noactivesa_cnt;
2314 u64 pkt_toolong_cnt;
2315 u64 pkt_untagged_cnt;
2316 u64 rsvd[4];
2317 };
2318
2319 struct mcs_port_stats {
2320 struct mbox_msghdr hdr;
2321 u64 tcam_miss_cnt;
2322 u64 parser_err_cnt;
2323 u64 preempt_err_cnt; /* CNF10K-B */
2324 u64 sectag_insert_err_cnt;
2325 u64 rsvd[4];
2326 };
2327
2328 /* Only for CN10K-B */
2329 struct mcs_sa_stats {
2330 struct mbox_msghdr hdr;
2331 /* RX */
2332 u64 pkt_invalid_cnt;
2333 u64 pkt_nosaerror_cnt;
2334 u64 pkt_notvalid_cnt;
2335 u64 pkt_ok_cnt;
2336 u64 pkt_nosa_cnt;
2337 /* TX */
2338 u64 pkt_encrypt_cnt;
2339 u64 pkt_protected_cnt;
2340 u64 rsvd[4];
2341 };
2342
2343 struct mcs_sc_stats {
2344 struct mbox_msghdr hdr;
2345 /* RX */
2346 u64 hit_cnt;
2347 u64 pkt_invalid_cnt;
2348 u64 pkt_late_cnt;
2349 u64 pkt_notvalid_cnt;
2350 u64 pkt_unchecked_cnt;
2351 u64 pkt_delay_cnt; /* CNF10K-B */
2352 u64 pkt_ok_cnt; /* CNF10K-B */
2353 u64 octet_decrypt_cnt; /* CN10K-B */
2354 u64 octet_validate_cnt; /* CN10K-B */
2355 /* TX */
2356 u64 pkt_encrypt_cnt;
2357 u64 pkt_protected_cnt;
2358 u64 octet_encrypt_cnt; /* CN10K-B */
2359 u64 octet_protected_cnt; /* CN10K-B */
2360 u64 rsvd[4];
2361 };
2362
2363 struct mcs_clear_stats {
2364 struct mbox_msghdr hdr;
2365 #define MCS_FLOWID_STATS 0
2366 #define MCS_SECY_STATS 1
2367 #define MCS_SC_STATS 2
2368 #define MCS_SA_STATS 3
2369 #define MCS_PORT_STATS 4
2370 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2371 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2372 u8 mcs_id;
2373 u8 dir;
2374 u8 all; /* All resources stats mapped to PF are cleared */
2375 };
2376
2377 struct mcs_intr_cfg {
2378 struct mbox_msghdr hdr;
2379 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2380 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2381 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2382 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2383 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2384 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2385 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2386 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2387 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2388 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2389 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2390 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2391 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2392 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2393 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2394 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2395 u64 intr_mask; /* Interrupt enable mask */
2396 u8 mcs_id;
2397 u8 lmac_id;
2398 u64 rsvd;
2399 };
2400
2401 struct mcs_intr_info {
2402 struct mbox_msghdr hdr;
2403 u64 intr_mask;
2404 int sa_id;
2405 u8 mcs_id;
2406 u8 lmac_id;
2407 u64 rsvd;
2408 };
2409
2410 #endif /* MBOX_H */
2411