xref: /linux/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
3 
4 /* nfp_net_ctrl.h
5  * Netronome network device driver: Control BAR layout
6  * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
7  *          Jason McMullan <jason.mcmullan@netronome.com>
8  *          Rolf Neugebauer <rolf.neugebauer@netronome.com>
9  *          Brad Petrus <brad.petrus@netronome.com>
10  */
11 
12 #ifndef _NFP_NET_CTRL_H_
13 #define _NFP_NET_CTRL_H_
14 
15 #include <linux/types.h>
16 
17 /* 64-bit per app capabilities */
18 #define NFP_NET_APP_CAP_SP_INDIFF	BIT_ULL(0) /* indifferent to port speed */
19 
20 /* Configuration BAR size.
21  *
22  * The configuration BAR is 8K in size, but due to
23  * THB-350, 32k needs to be reserved.
24  */
25 #define NFP_NET_CFG_BAR_SZ		(32 * 1024)
26 
27 /* Offset in Freelist buffer where packet starts on RX */
28 #define NFP_NET_RX_OFFSET		32
29 
30 /* LSO parameters
31  * %NFP_NET_LSO_MAX_HDR_SZ:	Maximum header size supported for LSO frames
32  * %NFP_NET_LSO_MAX_SEGS:	Maximum number of segments LSO frame can produce
33  */
34 #define NFP_NET_LSO_MAX_HDR_SZ		255
35 #define NFP_NET_LSO_MAX_SEGS		64
36 
37 /* working with metadata vlan api (NFD version >= 2.0) */
38 #define NFP_NET_META_VLAN_STRIP			BIT(31)
39 #define NFP_NET_META_VLAN_TPID_MASK		GENMASK(19, 16)
40 #define NFP_NET_META_VLAN_TCI_MASK		GENMASK(15, 0)
41 
42 /* Prepend field types */
43 #define NFP_NET_META_FIELD_SIZE		4
44 #define NFP_NET_META_HASH		1 /* next field carries hash type */
45 #define NFP_NET_META_MARK		2
46 #define NFP_NET_META_VLAN		4 /* ctag or stag type */
47 #define NFP_NET_META_PORTID		5
48 #define NFP_NET_META_CSUM		6 /* checksum complete type */
49 #define NFP_NET_META_CONN_HANDLE	7
50 #define NFP_NET_META_RESYNC_INFO	8 /* RX resync info request */
51 #define NFP_NET_META_IPSEC		9 /* IPsec SA index for tx and rx */
52 
53 #define NFP_META_PORT_ID_CTRL		~0U
54 
55 /* Prepend field sizes */
56 #define NFP_NET_META_VLAN_SIZE			4
57 #define NFP_NET_META_PORTID_SIZE		4
58 #define NFP_NET_META_CONN_HANDLE_SIZE		8
59 #define NFP_NET_META_IPSEC_SIZE			4
60 #define NFP_NET_META_IPSEC_FIELD_SIZE		12
61 /* Hash type pre-pended when a RSS hash was computed */
62 #define NFP_NET_RSS_NONE		0
63 #define NFP_NET_RSS_IPV4		1
64 #define NFP_NET_RSS_IPV6		2
65 #define NFP_NET_RSS_IPV6_EX		3
66 #define NFP_NET_RSS_IPV4_TCP		4
67 #define NFP_NET_RSS_IPV6_TCP		5
68 #define NFP_NET_RSS_IPV6_EX_TCP		6
69 #define NFP_NET_RSS_IPV4_UDP		7
70 #define NFP_NET_RSS_IPV6_UDP		8
71 #define NFP_NET_RSS_IPV6_EX_UDP		9
72 
73 /* Ring counts
74  * %NFP_NET_TXR_MAX:	     Maximum number of TX rings
75  * %NFP_NET_RXR_MAX:	     Maximum number of RX rings
76  */
77 #define NFP_NET_TXR_MAX			64
78 #define NFP_NET_RXR_MAX			64
79 
80 /* Read/Write config words (0x0000 - 0x002c)
81  * %NFP_NET_CFG_CTRL:	     Global control
82  * %NFP_NET_CFG_UPDATE:      Indicate which fields are updated
83  * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
84  * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
85  * %NFP_NET_CFG_MTU:	     Set MTU size
86  * %NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)
87  * %NFP_NET_CFG_EXN:	     MSI-X table entry for exceptions
88  * %NFP_NET_CFG_LSC:	     MSI-X table entry for link state changes
89  * %NFP_NET_CFG_MACADDR:     MAC address
90  *
91  * TODO:
92  * - define Error details in UPDATE
93  */
94 #define NFP_NET_CFG_CTRL		0x0000
95 #define   NFP_NET_CFG_CTRL_ENABLE	  (0x1 <<  0) /* Global enable */
96 #define   NFP_NET_CFG_CTRL_PROMISC	  (0x1 <<  1) /* Enable Promisc mode */
97 #define   NFP_NET_CFG_CTRL_L2BC		  (0x1 <<  2) /* Allow L2 Broadcast */
98 #define   NFP_NET_CFG_CTRL_L2MC		  (0x1 <<  3) /* Allow L2 Multicast */
99 #define   NFP_NET_CFG_CTRL_RXCSUM	  (0x1 <<  4) /* Enable RX Checksum */
100 #define   NFP_NET_CFG_CTRL_TXCSUM	  (0x1 <<  5) /* Enable TX Checksum */
101 #define   NFP_NET_CFG_CTRL_RXVLAN	  (0x1 <<  6) /* Enable VLAN strip */
102 #define   NFP_NET_CFG_CTRL_TXVLAN	  (0x1 <<  7) /* Enable VLAN insert */
103 #define   NFP_NET_CFG_CTRL_SCATTER	  (0x1 <<  8) /* Scatter DMA */
104 #define   NFP_NET_CFG_CTRL_GATHER	  (0x1 <<  9) /* Gather DMA */
105 #define   NFP_NET_CFG_CTRL_LSO		  (0x1 << 10) /* LSO/TSO (version 1) */
106 #define   NFP_NET_CFG_CTRL_CTAG_FILTER	  (0x1 << 11) /* VLAN CTAG filtering */
107 #define   NFP_NET_CFG_CTRL_CMSG_DATA	  (0x1 << 12) /* RX cmsgs on data Qs */
108 #define   NFP_NET_CFG_CTRL_RXQINQ	  (0x1 << 13) /* Enable S-tag strip */
109 #define   NFP_NET_CFG_CTRL_RXVLAN_V2	  (0x1 << 15) /* Enable C-tag strip */
110 #define   NFP_NET_CFG_CTRL_RINGCFG	  (0x1 << 16) /* Ring runtime changes */
111 #define   NFP_NET_CFG_CTRL_RSS		  (0x1 << 17) /* RSS (version 1) */
112 #define   NFP_NET_CFG_CTRL_IRQMOD	  (0x1 << 18) /* Interrupt moderation */
113 #define   NFP_NET_CFG_CTRL_MSIXAUTO	  (0x1 << 20) /* MSI-X auto-masking */
114 #define   NFP_NET_CFG_CTRL_TXRWB	  (0x1 << 21) /* Write-back of TX ring*/
115 #define   NFP_NET_CFG_CTRL_VEPA		  (0x1 << 22) /* Enable VEPA mode */
116 #define   NFP_NET_CFG_CTRL_TXVLAN_V2	  (0x1 << 23) /* Enable VLAN C-tag insert*/
117 #define   NFP_NET_CFG_CTRL_VXLAN	  (0x1 << 24) /* VXLAN tunnel support */
118 #define   NFP_NET_CFG_CTRL_NVGRE	  (0x1 << 25) /* NVGRE tunnel support */
119 #define   NFP_NET_CFG_CTRL_BPF		  (0x1 << 27) /* BPF offload capable */
120 #define   NFP_NET_CFG_CTRL_LSO2		  (0x1 << 28) /* LSO/TSO (version 2) */
121 #define   NFP_NET_CFG_CTRL_RSS2		  (0x1 << 29) /* RSS (version 2) */
122 #define   NFP_NET_CFG_CTRL_CSUM_COMPLETE  (0x1 << 30) /* Checksum complete */
123 #define   NFP_NET_CFG_CTRL_LIVE_ADDR	  (0x1 << 31) /* live MAC addr change */
124 
125 #define NFP_NET_CFG_CTRL_LSO_ANY	(NFP_NET_CFG_CTRL_LSO | \
126 					 NFP_NET_CFG_CTRL_LSO2)
127 #define NFP_NET_CFG_CTRL_RSS_ANY	(NFP_NET_CFG_CTRL_RSS | \
128 					 NFP_NET_CFG_CTRL_RSS2)
129 #define NFP_NET_CFG_CTRL_RXCSUM_ANY	(NFP_NET_CFG_CTRL_RXCSUM | \
130 					 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
131 #define NFP_NET_CFG_CTRL_CHAIN_META	(NFP_NET_CFG_CTRL_RSS2 | \
132 					 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
133 #define NFP_NET_CFG_CTRL_RXVLAN_ANY	(NFP_NET_CFG_CTRL_RXVLAN | \
134 					 NFP_NET_CFG_CTRL_RXVLAN_V2)
135 #define NFP_NET_CFG_CTRL_TXVLAN_ANY	(NFP_NET_CFG_CTRL_TXVLAN | \
136 					 NFP_NET_CFG_CTRL_TXVLAN_V2)
137 
138 #define NFP_NET_CFG_UPDATE		0x0004
139 #define   NFP_NET_CFG_UPDATE_GEN	  (0x1 <<  0) /* General update */
140 #define   NFP_NET_CFG_UPDATE_RING	  (0x1 <<  1) /* Ring config change */
141 #define   NFP_NET_CFG_UPDATE_RSS	  (0x1 <<  2) /* RSS config change */
142 #define   NFP_NET_CFG_UPDATE_TXRPRIO	  (0x1 <<  3) /* TX Ring prio change */
143 #define   NFP_NET_CFG_UPDATE_RXRPRIO	  (0x1 <<  4) /* RX Ring prio change */
144 #define   NFP_NET_CFG_UPDATE_MSIX	  (0x1 <<  5) /* MSI-X change */
145 #define   NFP_NET_CFG_UPDATE_RESET	  (0x1 <<  7) /* Update due to FLR */
146 #define   NFP_NET_CFG_UPDATE_IRQMOD	  (0x1 <<  8) /* IRQ mod change */
147 #define   NFP_NET_CFG_UPDATE_VXLAN	  (0x1 <<  9) /* VXLAN port change */
148 #define   NFP_NET_CFG_UPDATE_BPF	  (0x1 << 10) /* BPF program load */
149 #define   NFP_NET_CFG_UPDATE_MACADDR	  (0x1 << 11) /* MAC address change */
150 #define   NFP_NET_CFG_UPDATE_MBOX	  (0x1 << 12) /* Mailbox update */
151 #define   NFP_NET_CFG_UPDATE_VF		  (0x1 << 13) /* VF settings change */
152 #define   NFP_NET_CFG_UPDATE_CRYPTO	  (0x1 << 14) /* Crypto on/off */
153 #define   NFP_NET_CFG_UPDATE_ERR	  (0x1 << 31) /* A error occurred */
154 #define NFP_NET_CFG_TXRS_ENABLE		0x0008
155 #define NFP_NET_CFG_RXRS_ENABLE		0x0010
156 #define NFP_NET_CFG_MTU			0x0018
157 #define NFP_NET_CFG_FLBUFSZ		0x001c
158 #define NFP_NET_CFG_EXN			0x001f
159 #define NFP_NET_CFG_LSC			0x0020
160 #define NFP_NET_CFG_MACADDR		0x0024
161 
162 /* Read-only words (0x0030 - 0x0050):
163  * %NFP_NET_CFG_VERSION:     Firmware version number
164  * %NFP_NET_CFG_STS:	     Status
165  * %NFP_NET_CFG_CAP:	     Capabilities (same bits as %NFP_NET_CFG_CTRL)
166  * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
167  * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
168  * %NFP_NET_CFG_MAX_MTU:     Maximum support MTU
169  * %NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)
170  * %NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)
171  *
172  * TODO:
173  * - define more STS bits
174  */
175 #define NFP_NET_CFG_VERSION		0x0030
176 #define   NFP_NET_CFG_VERSION_RESERVED_MASK	(0xfe << 24)
177 #define   NFP_NET_CFG_VERSION_DP_NFD3		0
178 #define   NFP_NET_CFG_VERSION_DP_NFDK		1
179 #define   NFP_NET_CFG_VERSION_DP_MASK		1
180 #define   NFP_NET_CFG_VERSION_CLASS_MASK  (0xff << 16)
181 #define   NFP_NET_CFG_VERSION_CLASS(x)	  (((x) & 0xff) << 16)
182 #define   NFP_NET_CFG_VERSION_CLASS_GENERIC	0
183 #define   NFP_NET_CFG_VERSION_MAJOR_MASK  (0xff <<  8)
184 #define   NFP_NET_CFG_VERSION_MAJOR(x)	  (((x) & 0xff) <<  8)
185 #define   NFP_NET_CFG_VERSION_MINOR_MASK  (0xff <<  0)
186 #define   NFP_NET_CFG_VERSION_MINOR(x)	  (((x) & 0xff) <<  0)
187 #define NFP_NET_CFG_STS			0x0034
188 #define   NFP_NET_CFG_STS_LINK		  (0x1 << 0) /* Link up or down */
189 /* Link rate */
190 #define   NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
191 #define   NFP_NET_CFG_STS_LINK_RATE_MASK  0xF
192 #define   NFP_NET_CFG_STS_LINK_RATE	  \
193 	(NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
194 #define   NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED   0
195 #define   NFP_NET_CFG_STS_LINK_RATE_UNKNOWN	  1
196 #define   NFP_NET_CFG_STS_LINK_RATE_1G		  2
197 #define   NFP_NET_CFG_STS_LINK_RATE_10G		  3
198 #define   NFP_NET_CFG_STS_LINK_RATE_25G		  4
199 #define   NFP_NET_CFG_STS_LINK_RATE_40G		  5
200 #define   NFP_NET_CFG_STS_LINK_RATE_50G		  6
201 #define   NFP_NET_CFG_STS_LINK_RATE_100G	  7
202 /* NSP Link rate is a 16-bit word. It's determined by NSP and
203  * written to CFG BAR by NFP driver.
204  */
205 #define NFP_NET_CFG_STS_NSP_LINK_RATE	0x0036
206 #define NFP_NET_CFG_CAP			0x0038
207 #define NFP_NET_CFG_MAX_TXRINGS		0x003c
208 #define NFP_NET_CFG_MAX_RXRINGS		0x0040
209 #define NFP_NET_CFG_MAX_MTU		0x0044
210 /* Next two words are being used by VFs for solving THB350 issue */
211 #define NFP_NET_CFG_START_TXQ		0x0048
212 #define NFP_NET_CFG_START_RXQ		0x004c
213 
214 /* Prepend configuration
215  */
216 #define NFP_NET_CFG_RX_OFFSET		0x0050
217 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC		0	/* Prepend mode */
218 
219 /* RSS capabilities
220  * %NFP_NET_CFG_RSS_CAP_HFUNC:	supported hash functions (same bits as
221  *				%NFP_NET_CFG_RSS_HFUNC)
222  */
223 #define NFP_NET_CFG_RSS_CAP		0x0054
224 #define   NFP_NET_CFG_RSS_CAP_HFUNC	  0xff000000
225 
226 /* TLV area start
227  * %NFP_NET_CFG_TLV_BASE:	start anchor of the TLV area
228  */
229 #define NFP_NET_CFG_TLV_BASE		0x0058
230 
231 /* VXLAN/UDP encap configuration
232  * %NFP_NET_CFG_VXLAN_PORT:	Base address of table of tunnels' UDP dst ports
233  * %NFP_NET_CFG_VXLAN_SZ:	Size of the UDP port table in bytes
234  */
235 #define NFP_NET_CFG_VXLAN_PORT		0x0060
236 #define NFP_NET_CFG_VXLAN_SZ		  0x0008
237 
238 /* BPF section
239  * %NFP_NET_CFG_BPF_ABI:	BPF ABI version
240  * %NFP_NET_CFG_BPF_CAP:	BPF capabilities
241  * %NFP_NET_CFG_BPF_MAX_LEN:	Maximum size of JITed BPF code in bytes
242  * %NFP_NET_CFG_BPF_START:	Offset at which BPF will be loaded
243  * %NFP_NET_CFG_BPF_DONE:	Offset to jump to on exit
244  * %NFP_NET_CFG_BPF_STACK_SZ:	Total size of stack area in 64B chunks
245  * %NFP_NET_CFG_BPF_INL_MTU:	Packet data split offset in 64B chunks
246  * %NFP_NET_CFG_BPF_SIZE:	Size of the JITed BPF code in instructions
247  * %NFP_NET_CFG_BPF_ADDR:	DMA address of the buffer with JITed BPF code
248  */
249 #define NFP_NET_CFG_BPF_ABI		0x0080
250 #define NFP_NET_CFG_BPF_CAP		0x0081
251 #define   NFP_NET_BPF_CAP_RELO		(1 << 0) /* seamless reload */
252 #define NFP_NET_CFG_BPF_MAX_LEN		0x0082
253 #define NFP_NET_CFG_BPF_START		0x0084
254 #define NFP_NET_CFG_BPF_DONE		0x0086
255 #define NFP_NET_CFG_BPF_STACK_SZ	0x0088
256 #define NFP_NET_CFG_BPF_INL_MTU		0x0089
257 #define NFP_NET_CFG_BPF_SIZE		0x008e
258 #define NFP_NET_CFG_BPF_ADDR		0x0090
259 #define   NFP_NET_CFG_BPF_CFG_8CTX	(1 << 0) /* 8ctx mode */
260 #define   NFP_NET_CFG_BPF_CFG_MASK	7ULL
261 #define   NFP_NET_CFG_BPF_ADDR_MASK	(~NFP_NET_CFG_BPF_CFG_MASK)
262 
263 /* 3 words reserved for extended ctrl words (0x0098 - 0x00a4)
264  * 3 words reserved for extended cap words (0x00a4 - 0x00b0)
265  * Currently only one word is used, can be extended in future.
266  */
267 #define NFP_NET_CFG_CTRL_WORD1		0x0098
268 #define   NFP_NET_CFG_CTRL_PKT_TYPE	  (0x1 << 0) /* Pkttype offload */
269 #define   NFP_NET_CFG_CTRL_IPSEC	  (0x1 << 1) /* IPsec offload */
270 #define   NFP_NET_CFG_CTRL_MCAST_FILTER	  (0x1 << 2) /* Multicast Filter */
271 #define   NFP_NET_CFG_CTRL_FREELIST_EN	  (0x1 << 6) /* Freelist enable flag bit */
272 #define   NFP_NET_CFG_CTRL_FLOW_STEER	  (0x1 << 8) /* Flow steering */
273 #define   NFP_NET_CFG_CTRL_USO		  (0x1 << 16) /* UDP segmentation offload */
274 
275 #define NFP_NET_CFG_CAP_WORD1		0x00a4
276 
277 /* 16B reserved for future use (0x00b0 - 0x00c0) */
278 #define NFP_NET_CFG_RESERVED		0x00b0
279 #define NFP_NET_CFG_RESERVED_SZ		0x0010
280 
281 /* RSS configuration (0x0100 - 0x01ac):
282  * Used only when NFP_NET_CFG_CTRL_RSS is enabled
283  * %NFP_NET_CFG_RSS_CFG:     RSS configuration word
284  * %NFP_NET_CFG_RSS_KEY:     RSS "secret" key
285  * %NFP_NET_CFG_RSS_ITBL:    RSS indirection table
286  */
287 #define NFP_NET_CFG_RSS_BASE		0x0100
288 #define NFP_NET_CFG_RSS_CTRL		NFP_NET_CFG_RSS_BASE
289 #define   NFP_NET_CFG_RSS_MASK		  (0x7f)
290 #define   NFP_NET_CFG_RSS_MASK_of(_x)	  ((_x) & 0x7f)
291 #define   NFP_NET_CFG_RSS_IPV4		  (1 <<  8) /* RSS for IPv4 */
292 #define   NFP_NET_CFG_RSS_IPV6		  (1 <<  9) /* RSS for IPv6 */
293 #define   NFP_NET_CFG_RSS_IPV4_TCP	  (1 << 10) /* RSS for IPv4/TCP */
294 #define   NFP_NET_CFG_RSS_IPV4_UDP	  (1 << 11) /* RSS for IPv4/UDP */
295 #define   NFP_NET_CFG_RSS_IPV6_TCP	  (1 << 12) /* RSS for IPv6/TCP */
296 #define   NFP_NET_CFG_RSS_IPV6_UDP	  (1 << 13) /* RSS for IPv6/UDP */
297 #define   NFP_NET_CFG_RSS_HFUNC		  0xff000000
298 #define   NFP_NET_CFG_RSS_TOEPLITZ	  (1 << 24) /* Use Toeplitz hash */
299 #define   NFP_NET_CFG_RSS_XOR		  (1 << 25) /* Use XOR as hash */
300 #define   NFP_NET_CFG_RSS_CRC32		  (1 << 26) /* Use CRC32 as hash */
301 #define   NFP_NET_CFG_RSS_HFUNCS	  3
302 #define NFP_NET_CFG_RSS_KEY		(NFP_NET_CFG_RSS_BASE + 0x4)
303 #define NFP_NET_CFG_RSS_KEY_SZ		0x28
304 #define NFP_NET_CFG_RSS_ITBL		(NFP_NET_CFG_RSS_BASE + 0x4 + \
305 					 NFP_NET_CFG_RSS_KEY_SZ)
306 #define NFP_NET_CFG_RSS_ITBL_SZ		0x80
307 
308 /* TX ring configuration (0x200 - 0x800)
309  * %NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration
310  * %NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)
311  * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
312  * %NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)
313  * %NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)
314  * %NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)
315  * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
316  */
317 #define NFP_NET_CFG_TXR_BASE		0x0200
318 #define NFP_NET_CFG_TXR_ADDR(_x)	(NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
319 #define NFP_NET_CFG_TXR_WB_ADDR(_x)	(NFP_NET_CFG_TXR_BASE + 0x200 + \
320 					 ((_x) * 0x8))
321 #define NFP_NET_CFG_TXR_SZ(_x)		(NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
322 #define NFP_NET_CFG_TXR_VEC(_x)		(NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
323 #define NFP_NET_CFG_TXR_PRIO(_x)	(NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
324 #define NFP_NET_CFG_TXR_IRQ_MOD(_x)	(NFP_NET_CFG_TXR_BASE + 0x500 + \
325 					 ((_x) * 0x4))
326 
327 /* RX ring configuration (0x0800 - 0x0c00)
328  * %NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration
329  * %NFP_NET_CFG_RXR_ADDR:    Per RX ring DMA address (8B entries)
330  * %NFP_NET_CFG_RXR_SZ:      Per RX ring ring size (1B entries)
331  * %NFP_NET_CFG_RXR_VEC:     Per RX ring MSI-X table entry (1B entries)
332  * %NFP_NET_CFG_RXR_PRIO:    Per RX ring priority (1B entries)
333  * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
334  */
335 #define NFP_NET_CFG_RXR_BASE		0x0800
336 #define NFP_NET_CFG_RXR_ADDR(_x)	(NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
337 #define NFP_NET_CFG_RXR_SZ(_x)		(NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
338 #define NFP_NET_CFG_RXR_VEC(_x)		(NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
339 #define NFP_NET_CFG_RXR_PRIO(_x)	(NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
340 #define NFP_NET_CFG_RXR_IRQ_MOD(_x)	(NFP_NET_CFG_RXR_BASE + 0x300 + \
341 					 ((_x) * 0x4))
342 
343 /* Interrupt Control/Cause registers (0x0c00 - 0x0d00)
344  * These registers are only used when MSI-X auto-masking is not
345  * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index
346  * by MSI-X entry and are 1B in size.  If an entry is zero, the
347  * corresponding entry is enabled.  If the FW generates an interrupt,
348  * it writes a cause into the corresponding field.  This also masks
349  * the MSI-X entry and the host driver must clear the register to
350  * re-enable the interrupt.
351  */
352 #define NFP_NET_CFG_ICR_BASE		0x0c00
353 #define NFP_NET_CFG_ICR(_x)		(NFP_NET_CFG_ICR_BASE + (_x))
354 #define   NFP_NET_CFG_ICR_UNMASKED	0x0
355 #define   NFP_NET_CFG_ICR_RXTX		0x1
356 #define   NFP_NET_CFG_ICR_LSC		0x2
357 
358 /* General device stats (0x0d00 - 0x0d90)
359  * all counters are 64bit.
360  */
361 #define NFP_NET_CFG_STATS_BASE		0x0d00
362 #define NFP_NET_CFG_STATS_RX_DISCARDS	(NFP_NET_CFG_STATS_BASE + 0x00)
363 #define NFP_NET_CFG_STATS_RX_ERRORS	(NFP_NET_CFG_STATS_BASE + 0x08)
364 #define NFP_NET_CFG_STATS_RX_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x10)
365 #define NFP_NET_CFG_STATS_RX_UC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x18)
366 #define NFP_NET_CFG_STATS_RX_MC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x20)
367 #define NFP_NET_CFG_STATS_RX_BC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x28)
368 #define NFP_NET_CFG_STATS_RX_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x30)
369 #define NFP_NET_CFG_STATS_RX_MC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x38)
370 #define NFP_NET_CFG_STATS_RX_BC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x40)
371 
372 #define NFP_NET_CFG_STATS_TX_DISCARDS	(NFP_NET_CFG_STATS_BASE + 0x48)
373 #define NFP_NET_CFG_STATS_TX_ERRORS	(NFP_NET_CFG_STATS_BASE + 0x50)
374 #define NFP_NET_CFG_STATS_TX_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x58)
375 #define NFP_NET_CFG_STATS_TX_UC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x60)
376 #define NFP_NET_CFG_STATS_TX_MC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x68)
377 #define NFP_NET_CFG_STATS_TX_BC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x70)
378 #define NFP_NET_CFG_STATS_TX_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x78)
379 #define NFP_NET_CFG_STATS_TX_MC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x80)
380 #define NFP_NET_CFG_STATS_TX_BC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x88)
381 
382 #define NFP_NET_CFG_STATS_APP0_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x90)
383 #define NFP_NET_CFG_STATS_APP0_BYTES	(NFP_NET_CFG_STATS_BASE + 0x98)
384 #define NFP_NET_CFG_STATS_APP1_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xa0)
385 #define NFP_NET_CFG_STATS_APP1_BYTES	(NFP_NET_CFG_STATS_BASE + 0xa8)
386 #define NFP_NET_CFG_STATS_APP2_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xb0)
387 #define NFP_NET_CFG_STATS_APP2_BYTES	(NFP_NET_CFG_STATS_BASE + 0xb8)
388 #define NFP_NET_CFG_STATS_APP3_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xc0)
389 #define NFP_NET_CFG_STATS_APP3_BYTES	(NFP_NET_CFG_STATS_BASE + 0xc8)
390 
391 /* Per ring stats (0x1000 - 0x1800)
392  * options, 64bit per entry
393  * %NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)
394  * %NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)
395  */
396 #define NFP_NET_CFG_TXR_STATS_BASE	0x1000
397 #define NFP_NET_CFG_TXR_STATS(_x)	(NFP_NET_CFG_TXR_STATS_BASE + \
398 					 ((_x) * 0x10))
399 #define NFP_NET_CFG_RXR_STATS_BASE	0x1400
400 #define NFP_NET_CFG_RXR_STATS(_x)	(NFP_NET_CFG_RXR_STATS_BASE + \
401 					 ((_x) * 0x10))
402 
403 /* General use mailbox area (0x1800 - 0x19ff)
404  * 4B used for update command and 4B return code
405  * followed by a max of 504B of variable length value
406  */
407 #define NFP_NET_CFG_MBOX_BASE		0x1800
408 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ	0x1F8
409 #define NFP_NET_CFG_MBOX_SIMPLE_CMD	0x0
410 #define NFP_NET_CFG_MBOX_SIMPLE_RET	0x4
411 #define NFP_NET_CFG_MBOX_SIMPLE_VAL	0x8
412 
413 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1
414 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2
415 #define NFP_NET_CFG_MBOX_CMD_IPSEC 3
416 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET	5
417 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG			6
418 #define NFP_NET_CFG_MBOX_CMD_DCB_UPDATE			7
419 
420 #define NFP_NET_CFG_MBOX_CMD_MULTICAST_ADD		8
421 #define NFP_NET_CFG_MBOX_CMD_MULTICAST_DEL		9
422 
423 #define NFP_NET_CFG_MBOX_CMD_FLOW_STEER			10
424 
425 /* VLAN filtering using general use mailbox
426  * %NFP_NET_CFG_VLAN_FILTER:		Base address of VLAN filter mailbox
427  * %NFP_NET_CFG_VLAN_FILTER_VID:	VLAN ID to filter
428  * %NFP_NET_CFG_VLAN_FILTER_PROTO:	VLAN proto to filter
429  * %NFP_NET_CFG_VXLAN_SZ:		Size of the VLAN filter mailbox in bytes
430  */
431 #define NFP_NET_CFG_VLAN_FILTER		NFP_NET_CFG_MBOX_SIMPLE_VAL
432 #define  NFP_NET_CFG_VLAN_FILTER_VID	NFP_NET_CFG_VLAN_FILTER
433 #define  NFP_NET_CFG_VLAN_FILTER_PROTO	 (NFP_NET_CFG_VLAN_FILTER + 2)
434 #define NFP_NET_CFG_VLAN_FILTER_SZ	 0x0004
435 
436 /* Multicast filtering using general use mailbox
437  * %NFP_NET_CFG_MULTICAST:		Base address of Multicast filter mailbox
438  * %NFP_NET_CFG_MULTICAST_MAC_HI:	High 32-bits of Multicast MAC address
439  * %NFP_NET_CFG_MULTICAST_MAC_LO:	Low 16-bits of Multicast MAC address
440  * %NFP_NET_CFG_MULTICAST_SZ:		Size of the Multicast filter mailbox in bytes
441  */
442 #define NFP_NET_CFG_MULTICAST		NFP_NET_CFG_MBOX_SIMPLE_VAL
443 #define NFP_NET_CFG_MULTICAST_MAC_HI	NFP_NET_CFG_MULTICAST
444 #define NFP_NET_CFG_MULTICAST_MAC_LO	(NFP_NET_CFG_MULTICAST + 6)
445 #define NFP_NET_CFG_MULTICAST_SZ	0x0006
446 
447 /* Max size of FS rules in bytes */
448 #define NFP_NET_CFG_FS_SZ		0x0054
449 /* Sub commands for FS */
450 enum {
451 	NFP_NET_CFG_MBOX_CMD_FS_ADD_V4,
452 	NFP_NET_CFG_MBOX_CMD_FS_DEL_V4,
453 	NFP_NET_CFG_MBOX_CMD_FS_ADD_V6,
454 	NFP_NET_CFG_MBOX_CMD_FS_DEL_V6,
455 	NFP_NET_CFG_MBOX_CMD_FS_ADD_ETHTYPE,
456 	NFP_NET_CFG_MBOX_CMD_FS_DEL_ETHTYPE,
457 };
458 
459 /* TLV capabilities
460  * %NFP_NET_CFG_TLV_TYPE:	Offset of type within the TLV
461  * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV
462  * %NFP_NET_CFG_TLV_LENGTH:	Offset of length within the TLV
463  * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
464  * %NFP_NET_CFG_TLV_VALUE:	Offset of value with the TLV
465  *
466  * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE.
467  * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END.  Presence of TLVs
468  * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero.  TLV structures may
469  * fill the entire remainder of the BAR or be shorter.  FW must make sure TLVs
470  * don't conflict with other features which allocate space beyond
471  * %NFP_NET_CFG_TLV_BASE.  %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap
472  * space used by such features.
473  * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH.
474  */
475 #define NFP_NET_CFG_TLV_TYPE		0x00
476 #define   NFP_NET_CFG_TLV_TYPE_REQUIRED   0x8000
477 #define NFP_NET_CFG_TLV_LENGTH		0x02
478 #define   NFP_NET_CFG_TLV_LENGTH_INC	  4
479 #define NFP_NET_CFG_TLV_VALUE		0x04
480 
481 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
482 #define NFP_NET_CFG_TLV_HEADER_TYPE	0x7fff0000
483 #define NFP_NET_CFG_TLV_HEADER_LENGTH	0x0000ffff
484 
485 /* Capability TLV types
486  *
487  * %NFP_NET_CFG_TLV_TYPE_UNKNOWN:
488  * Special TLV type to catch bugs, should never be encountered.  Drivers should
489  * treat encountering this type as error and refuse to probe.
490  *
491  * %NFP_NET_CFG_TLV_TYPE_RESERVED:
492  * Reserved space, may contain legacy fixed-offset fields, or be used for
493  * padding.  The use of this type should be otherwise avoided.
494  *
495  * %NFP_NET_CFG_TLV_TYPE_END:
496  * Empty, end of TLV list.  Must be the last TLV.  Drivers will stop processing
497  * further TLVs when encountered.
498  *
499  * %NFP_NET_CFG_TLV_TYPE_ME_FREQ:
500  * Single word, ME frequency in MHz as used in calculation for
501  * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD.
502  *
503  * %NFP_NET_CFG_TLV_TYPE_MBOX:
504  * Variable, mailbox area.  Overwrites the default location which is
505  * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ.
506  *
507  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0:
508  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1:
509  * Variable, experimental IDs.  IDs designated for internal development and
510  * experiments before a stable TLV ID has been allocated to a feature.  Should
511  * never be present in production firmware.
512  *
513  * %NFP_NET_CFG_TLV_TYPE_REPR_CAP:
514  * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which
515  * can be used on representors.
516  *
517  * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES:
518  * Variable, bitmap of control message types supported by the mailbox handler.
519  * Bit 0 corresponds to message type 0, bit 1 to 1, etc.  Control messages are
520  * encapsulated into simple TLVs, with an end TLV and written to the Mailbox.
521  *
522  * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS:
523  * 8 words, bitmaps of supported and enabled crypto operations.
524  * First 16B (4 words) contains a bitmap of supported crypto operations,
525  * and next 16B contain the enabled operations.
526  * This capability is made obsolete by ones with better sync methods.
527  *
528  * %NFP_NET_CFG_TLV_TYPE_VNIC_STATS:
529  * Variable, per-vNIC statistics, data should be 8B aligned (FW should insert
530  * zero-length RESERVED TLV to pad).
531  * TLV data has two sections.  First is an array of statistics' IDs (2B each).
532  * Second 8B statistics themselves.  Statistics are 8B aligned, meaning there
533  * may be a padding between sections.
534  * Number of statistics can be determined as floor(tlv.length / (2 + 8)).
535  * This TLV overwrites %NFP_NET_CFG_STATS_* values (statistics in this TLV
536  * duplicate the old ones, so driver should be careful not to unnecessarily
537  * render both).
538  *
539  * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN:
540  * Same as %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS, but crypto TLS does stream scan
541  * RX sync, rather than kernel-assisted sync.
542  */
543 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN		0
544 #define NFP_NET_CFG_TLV_TYPE_RESERVED		1
545 #define NFP_NET_CFG_TLV_TYPE_END		2
546 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ		3
547 #define NFP_NET_CFG_TLV_TYPE_MBOX		4
548 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0	5
549 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1	6
550 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP		7
551 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES	10
552 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS		11 /* see crypto/fw.h */
553 #define NFP_NET_CFG_TLV_TYPE_VNIC_STATS		12
554 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN	13
555 
556 struct device;
557 
558 /* struct nfp_net_tlv_caps - parsed control BAR TLV capabilities
559  * @me_freq_mhz:	ME clock_freq (MHz)
560  * @mbox_off:		vNIC mailbox area offset
561  * @mbox_len:		vNIC mailbox area length
562  * @repr_cap:		capabilities for representors
563  * @mbox_cmsg_types:	cmsgs which can be passed through the mailbox
564  * @crypto_ops:		supported crypto operations
565  * @crypto_enable_off:	offset of crypto ops enable region
566  * @vnic_stats_off:	offset of vNIC stats area
567  * @vnic_stats_cnt:	number of vNIC stats
568  * @tls_resync_ss:	TLS resync will be performed via stream scan
569  */
570 struct nfp_net_tlv_caps {
571 	u32 me_freq_mhz;
572 	unsigned int mbox_off;
573 	unsigned int mbox_len;
574 	u32 repr_cap;
575 	u32 mbox_cmsg_types;
576 	u32 crypto_ops;
577 	unsigned int crypto_enable_off;
578 	unsigned int vnic_stats_off;
579 	unsigned int vnic_stats_cnt;
580 	unsigned int tls_resync_ss:1;
581 };
582 
583 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem,
584 			   struct nfp_net_tlv_caps *caps);
585 #endif /* _NFP_NET_CTRL_H_ */
586