1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * NXP NETC Blocks Control Driver
4 *
5 * Copyright 2024 NXP
6 *
7 * This driver is used for pre-initialization of NETC, such as PCS and MII
8 * protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can
9 * only be probed after the netc-blk-crtl driver has completed initialization.
10 * In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX
11 * will be powered off, except for WOL. Therefore, when the system resumes,
12 * these blocks need to be reinitialized.
13 */
14
15 #include <linux/bits.h>
16 #include <linux/clk.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/fsl/netc_global.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/seq_file.h>
28
29 /* NETCMIX registers */
30 #define IMX95_CFG_LINK_IO_VAR 0x0
31 #define IO_VAR_16FF_16G_SERDES 0x1
32 #define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2))
33
34 #define IMX95_CFG_LINK_MII_PROT 0x4
35 #define CFG_LINK_MII_PORT_0 GENMASK(3, 0)
36 #define CFG_LINK_MII_PORT_1 GENMASK(7, 4)
37 #define MII_PROT_MII 0x0
38 #define MII_PROT_RMII 0x1
39 #define MII_PROT_RGMII 0x2
40 #define MII_PROT_SERIAL 0x3
41 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2))
42
43 #define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4)
44 #define PCS_PROT_1G_SGMII BIT(0)
45 #define PCS_PROT_2500M_SGMII BIT(1)
46 #define PCS_PROT_XFI BIT(3)
47 #define PCS_PROT_SFI BIT(4)
48 #define PCS_PROT_10G_SXGMII BIT(6)
49
50 #define IMX94_EXT_PIN_CONTROL 0x10
51 #define MAC2_MAC3_SEL BIT(1)
52
53 #define IMX94_NETC_LINK_CFG(a) (0x4c + (a) * 4)
54 #define NETC_LINK_CFG_MII_PROT GENMASK(3, 0)
55 #define NETC_LINK_CFG_IO_VAR GENMASK(19, 16)
56
57 /* NETC privileged register block register */
58 #define PRB_NETCRR 0x100
59 #define NETCRR_SR BIT(0)
60 #define NETCRR_LOCK BIT(1)
61
62 #define PRB_NETCSR 0x104
63 #define NETCSR_ERROR BIT(0)
64 #define NETCSR_STATE BIT(1)
65
66 /* NETC integrated endpoint register block register */
67 #define IERB_EMDIOFAUXR 0x344
68 #define IERB_T0FAUXR 0x444
69 #define IERB_ETBCR(a) (0x300c + 0x100 * (a))
70 #define IERB_LBCR(a) (0x1010 + 0x40 * (a))
71 #define LBCR_MDIO_PHYAD_PRTAD(addr) (((addr) & 0x1f) << 8)
72
73 #define IERB_EFAUXR(a) (0x3044 + 0x100 * (a))
74 #define IERB_VFAUXR(a) (0x4004 + 0x40 * (a))
75 #define FAUXR_LDID GENMASK(3, 0)
76
77 /* Platform information */
78 #define IMX95_ENETC0_BUS_DEVFN 0x0
79 #define IMX95_ENETC1_BUS_DEVFN 0x40
80 #define IMX95_ENETC2_BUS_DEVFN 0x80
81
82 #define IMX94_ENETC0_BUS_DEVFN 0x100
83 #define IMX94_ENETC1_BUS_DEVFN 0x140
84 #define IMX94_ENETC2_BUS_DEVFN 0x180
85 #define IMX94_TIMER0_BUS_DEVFN 0x1
86 #define IMX94_TIMER1_BUS_DEVFN 0x101
87 #define IMX94_TIMER2_BUS_DEVFN 0x181
88 #define IMX94_ENETC0_LINK 3
89 #define IMX94_ENETC1_LINK 4
90 #define IMX94_ENETC2_LINK 5
91
92 #define NETC_ENETC_ID(a) (a)
93 #define NETC_TIMER_ID(a) (a)
94
95 /* Flags for different platforms */
96 #define NETC_HAS_NETCMIX BIT(0)
97
98 struct netc_devinfo {
99 u32 flags;
100 int (*netcmix_init)(struct platform_device *pdev);
101 int (*ierb_init)(struct platform_device *pdev);
102 };
103
104 struct netc_blk_ctrl {
105 void __iomem *prb;
106 void __iomem *ierb;
107 void __iomem *netcmix;
108
109 const struct netc_devinfo *devinfo;
110 struct platform_device *pdev;
111 struct dentry *debugfs_root;
112 };
113
netc_reg_write(void __iomem * base,u32 offset,u32 val)114 static void netc_reg_write(void __iomem *base, u32 offset, u32 val)
115 {
116 netc_write(base + offset, val);
117 }
118
netc_reg_read(void __iomem * base,u32 offset)119 static u32 netc_reg_read(void __iomem *base, u32 offset)
120 {
121 return netc_read(base + offset);
122 }
123
netc_of_pci_get_bus_devfn(struct device_node * np)124 static int netc_of_pci_get_bus_devfn(struct device_node *np)
125 {
126 u32 reg[5];
127 int error;
128
129 error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
130 if (error)
131 return error;
132
133 return (reg[0] >> 8) & 0xffff;
134 }
135
netc_get_link_mii_protocol(phy_interface_t interface)136 static int netc_get_link_mii_protocol(phy_interface_t interface)
137 {
138 switch (interface) {
139 case PHY_INTERFACE_MODE_MII:
140 return MII_PROT_MII;
141 case PHY_INTERFACE_MODE_RMII:
142 return MII_PROT_RMII;
143 case PHY_INTERFACE_MODE_RGMII:
144 case PHY_INTERFACE_MODE_RGMII_ID:
145 case PHY_INTERFACE_MODE_RGMII_RXID:
146 case PHY_INTERFACE_MODE_RGMII_TXID:
147 return MII_PROT_RGMII;
148 case PHY_INTERFACE_MODE_SGMII:
149 case PHY_INTERFACE_MODE_2500BASEX:
150 case PHY_INTERFACE_MODE_10GBASER:
151 case PHY_INTERFACE_MODE_XGMII:
152 case PHY_INTERFACE_MODE_USXGMII:
153 return MII_PROT_SERIAL;
154 default:
155 return -EINVAL;
156 }
157 }
158
imx95_netcmix_init(struct platform_device * pdev)159 static int imx95_netcmix_init(struct platform_device *pdev)
160 {
161 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
162 struct device_node *np = pdev->dev.of_node;
163 phy_interface_t interface;
164 int bus_devfn, mii_proto;
165 u32 val;
166 int err;
167
168 /* Default setting of MII protocol */
169 val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) |
170 MII_PROT(2, MII_PROT_SERIAL);
171
172 /* Update the link MII protocol through parsing phy-mode */
173 for_each_available_child_of_node_scoped(np, child) {
174 for_each_available_child_of_node_scoped(child, gchild) {
175 if (!of_device_is_compatible(gchild, "pci1131,e101"))
176 continue;
177
178 bus_devfn = netc_of_pci_get_bus_devfn(gchild);
179 if (bus_devfn < 0)
180 return -EINVAL;
181
182 if (bus_devfn == IMX95_ENETC2_BUS_DEVFN)
183 continue;
184
185 err = of_get_phy_mode(gchild, &interface);
186 if (err)
187 continue;
188
189 mii_proto = netc_get_link_mii_protocol(interface);
190 if (mii_proto < 0)
191 return -EINVAL;
192
193 switch (bus_devfn) {
194 case IMX95_ENETC0_BUS_DEVFN:
195 val = u32_replace_bits(val, mii_proto,
196 CFG_LINK_MII_PORT_0);
197 break;
198 case IMX95_ENETC1_BUS_DEVFN:
199 val = u32_replace_bits(val, mii_proto,
200 CFG_LINK_MII_PORT_1);
201 break;
202 default:
203 return -EINVAL;
204 }
205 }
206 }
207
208 /* Configure Link I/O variant */
209 netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
210 IO_VAR(2, IO_VAR_16FF_16G_SERDES));
211 /* Configure Link 2 PCS protocol */
212 netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2),
213 PCS_PROT_10G_SXGMII);
214 netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
215
216 return 0;
217 }
218
imx94_enetc_get_link_id(struct device_node * np)219 static int imx94_enetc_get_link_id(struct device_node *np)
220 {
221 int bus_devfn = netc_of_pci_get_bus_devfn(np);
222
223 /* Parse ENETC link number */
224 switch (bus_devfn) {
225 case IMX94_ENETC0_BUS_DEVFN:
226 return IMX94_ENETC0_LINK;
227 case IMX94_ENETC1_BUS_DEVFN:
228 return IMX94_ENETC1_LINK;
229 case IMX94_ENETC2_BUS_DEVFN:
230 return IMX94_ENETC2_LINK;
231 default:
232 return -EINVAL;
233 }
234 }
235
imx94_link_config(struct netc_blk_ctrl * priv,struct device_node * np,int link_id)236 static int imx94_link_config(struct netc_blk_ctrl *priv,
237 struct device_node *np, int link_id)
238 {
239 phy_interface_t interface;
240 int mii_proto;
241 u32 val;
242
243 /* The node may be disabled and does not have a 'phy-mode'
244 * or 'phy-connection-type' property.
245 */
246 if (of_get_phy_mode(np, &interface))
247 return 0;
248
249 mii_proto = netc_get_link_mii_protocol(interface);
250 if (mii_proto < 0)
251 return mii_proto;
252
253 val = mii_proto & NETC_LINK_CFG_MII_PROT;
254 if (val == MII_PROT_SERIAL)
255 val = u32_replace_bits(val, IO_VAR_16FF_16G_SERDES,
256 NETC_LINK_CFG_IO_VAR);
257
258 netc_reg_write(priv->netcmix, IMX94_NETC_LINK_CFG(link_id), val);
259
260 return 0;
261 }
262
imx94_enetc_link_config(struct netc_blk_ctrl * priv,struct device_node * np)263 static int imx94_enetc_link_config(struct netc_blk_ctrl *priv,
264 struct device_node *np)
265 {
266 int link_id = imx94_enetc_get_link_id(np);
267
268 if (link_id < 0)
269 return link_id;
270
271 return imx94_link_config(priv, np, link_id);
272 }
273
imx94_netcmix_init(struct platform_device * pdev)274 static int imx94_netcmix_init(struct platform_device *pdev)
275 {
276 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
277 struct device_node *np = pdev->dev.of_node;
278 u32 val;
279 int err;
280
281 for_each_child_of_node_scoped(np, child) {
282 for_each_child_of_node_scoped(child, gchild) {
283 if (!of_device_is_compatible(gchild, "pci1131,e101"))
284 continue;
285
286 err = imx94_enetc_link_config(priv, gchild);
287 if (err)
288 return err;
289 }
290 }
291
292 /* ENETC 0 and switch port 2 share the same parallel interface.
293 * Currently, the switch is not supported, so this interface is
294 * used by ENETC 0 by default.
295 */
296 val = netc_reg_read(priv->netcmix, IMX94_EXT_PIN_CONTROL);
297 val |= MAC2_MAC3_SEL;
298 netc_reg_write(priv->netcmix, IMX94_EXT_PIN_CONTROL, val);
299
300 return 0;
301 }
302
netc_ierb_is_locked(struct netc_blk_ctrl * priv)303 static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv)
304 {
305 return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK);
306 }
307
netc_lock_ierb(struct netc_blk_ctrl * priv)308 static int netc_lock_ierb(struct netc_blk_ctrl *priv)
309 {
310 u32 val;
311
312 netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK);
313
314 return read_poll_timeout(netc_reg_read, val, !(val & NETCSR_STATE),
315 100, 2000, false, priv->prb, PRB_NETCSR);
316 }
317
netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl * priv)318 static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv)
319 {
320 u32 val;
321
322 netc_reg_write(priv->prb, PRB_NETCRR, 0);
323
324 return read_poll_timeout(netc_reg_read, val, !(val & NETCRR_LOCK),
325 1000, 100000, true, priv->prb, PRB_NETCRR);
326 }
327
netc_get_phy_addr(struct device_node * np)328 static int netc_get_phy_addr(struct device_node *np)
329 {
330 struct device_node *mdio_node, *phy_node;
331 u32 addr = 0;
332 int err = 0;
333
334 mdio_node = of_get_child_by_name(np, "mdio");
335 if (!mdio_node)
336 return 0;
337
338 phy_node = of_get_next_child(mdio_node, NULL);
339 if (!phy_node)
340 goto of_put_mdio_node;
341
342 err = of_property_read_u32(phy_node, "reg", &addr);
343 if (err)
344 goto of_put_phy_node;
345
346 if (addr >= PHY_MAX_ADDR)
347 err = -EINVAL;
348
349 of_put_phy_node:
350 of_node_put(phy_node);
351
352 of_put_mdio_node:
353 of_node_put(mdio_node);
354
355 return err ? err : addr;
356 }
357
netc_parse_emdio_phy_mask(struct device_node * np,u32 * phy_mask)358 static int netc_parse_emdio_phy_mask(struct device_node *np, u32 *phy_mask)
359 {
360 u32 mask = 0;
361
362 for_each_child_of_node_scoped(np, child) {
363 u32 addr;
364 int err;
365
366 err = of_property_read_u32(child, "reg", &addr);
367 if (err)
368 return err;
369
370 if (addr >= PHY_MAX_ADDR)
371 return -EINVAL;
372
373 mask |= BIT(addr);
374 }
375
376 *phy_mask = mask;
377
378 return 0;
379 }
380
netc_get_emdio_phy_mask(struct device_node * np,u32 * phy_mask)381 static int netc_get_emdio_phy_mask(struct device_node *np, u32 *phy_mask)
382 {
383 for_each_child_of_node_scoped(np, child) {
384 for_each_child_of_node_scoped(child, gchild) {
385 if (!of_device_is_compatible(gchild, "pci1131,ee00"))
386 continue;
387
388 return netc_parse_emdio_phy_mask(gchild, phy_mask);
389 }
390 }
391
392 return 0;
393 }
394
imx95_enetc_mdio_phyaddr_config(struct platform_device * pdev)395 static int imx95_enetc_mdio_phyaddr_config(struct platform_device *pdev)
396 {
397 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
398 struct device_node *np = pdev->dev.of_node;
399 struct device *dev = &pdev->dev;
400 int bus_devfn, addr, err;
401 u32 phy_mask = 0;
402
403 err = netc_get_emdio_phy_mask(np, &phy_mask);
404 if (err) {
405 dev_err(dev, "Failed to get PHY address mask\n");
406 return err;
407 }
408
409 /* Update the port EMDIO PHY address through parsing phy properties.
410 * This is needed when using the port EMDIO but it's harmless when
411 * using the central EMDIO. So apply it on all cases.
412 */
413 for_each_child_of_node_scoped(np, child) {
414 for_each_child_of_node_scoped(child, gchild) {
415 if (!of_device_is_compatible(gchild, "pci1131,e101"))
416 continue;
417
418 bus_devfn = netc_of_pci_get_bus_devfn(gchild);
419 if (bus_devfn < 0) {
420 dev_err(dev, "Failed to get BDF number\n");
421 return bus_devfn;
422 }
423
424 addr = netc_get_phy_addr(gchild);
425 if (addr < 0) {
426 dev_err(dev, "Failed to get PHY address\n");
427 return addr;
428 }
429
430 if (phy_mask & BIT(addr)) {
431 dev_err(dev,
432 "Find same PHY address in EMDIO and ENETC node\n");
433 return -EINVAL;
434 }
435
436 /* The default value of LaBCR[MDIO_PHYAD_PRTAD ] is
437 * 0, so no need to set the register.
438 */
439 if (!addr)
440 continue;
441
442 switch (bus_devfn) {
443 case IMX95_ENETC0_BUS_DEVFN:
444 netc_reg_write(priv->ierb, IERB_LBCR(0),
445 LBCR_MDIO_PHYAD_PRTAD(addr));
446 break;
447 case IMX95_ENETC1_BUS_DEVFN:
448 netc_reg_write(priv->ierb, IERB_LBCR(1),
449 LBCR_MDIO_PHYAD_PRTAD(addr));
450 break;
451 case IMX95_ENETC2_BUS_DEVFN:
452 netc_reg_write(priv->ierb, IERB_LBCR(2),
453 LBCR_MDIO_PHYAD_PRTAD(addr));
454 break;
455 default:
456 break;
457 }
458 }
459 }
460
461 return 0;
462 }
463
imx95_ierb_init(struct platform_device * pdev)464 static int imx95_ierb_init(struct platform_device *pdev)
465 {
466 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
467
468 /* EMDIO : No MSI-X intterupt */
469 netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0);
470 /* ENETC0 PF */
471 netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0);
472 /* ENETC0 VF0 */
473 netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1);
474 /* ENETC0 VF1 */
475 netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2);
476 /* ENETC1 PF */
477 netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3);
478 /* ENETC1 VF0 */
479 netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5);
480 /* ENETC1 VF1 */
481 netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6);
482 /* ENETC2 PF */
483 netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4);
484 /* ENETC2 VF0 */
485 netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5);
486 /* ENETC2 VF1 */
487 netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6);
488 /* NETC TIMER */
489 netc_reg_write(priv->ierb, IERB_T0FAUXR, 7);
490
491 return imx95_enetc_mdio_phyaddr_config(pdev);
492 }
493
imx94_get_enetc_id(struct device_node * np)494 static int imx94_get_enetc_id(struct device_node *np)
495 {
496 int bus_devfn = netc_of_pci_get_bus_devfn(np);
497
498 /* Parse ENETC offset */
499 switch (bus_devfn) {
500 case IMX94_ENETC0_BUS_DEVFN:
501 return NETC_ENETC_ID(0);
502 case IMX94_ENETC1_BUS_DEVFN:
503 return NETC_ENETC_ID(1);
504 case IMX94_ENETC2_BUS_DEVFN:
505 return NETC_ENETC_ID(2);
506 default:
507 return -EINVAL;
508 }
509 }
510
imx94_get_timer_id(struct device_node * np)511 static int imx94_get_timer_id(struct device_node *np)
512 {
513 int bus_devfn = netc_of_pci_get_bus_devfn(np);
514
515 /* Parse NETC PTP timer ID, the timer0 is on bus 0,
516 * the timer 1 and timer2 is on bus 1.
517 */
518 switch (bus_devfn) {
519 case IMX94_TIMER0_BUS_DEVFN:
520 return NETC_TIMER_ID(0);
521 case IMX94_TIMER1_BUS_DEVFN:
522 return NETC_TIMER_ID(1);
523 case IMX94_TIMER2_BUS_DEVFN:
524 return NETC_TIMER_ID(2);
525 default:
526 return -EINVAL;
527 }
528 }
529
imx94_enetc_update_tid(struct netc_blk_ctrl * priv,struct device_node * np)530 static int imx94_enetc_update_tid(struct netc_blk_ctrl *priv,
531 struct device_node *np)
532 {
533 struct device *dev = &priv->pdev->dev;
534 struct device_node *timer_np;
535 int eid, tid;
536
537 eid = imx94_get_enetc_id(np);
538 if (eid < 0) {
539 dev_err(dev, "Failed to get ENETC ID\n");
540 return eid;
541 }
542
543 timer_np = of_parse_phandle(np, "ptp-timer", 0);
544 if (!timer_np) {
545 /* If 'ptp-timer' is not present, the timer1 is the default
546 * timer of all standalone ENETCs, which is on the same PCIe
547 * bus as these ENETCs.
548 */
549 tid = NETC_TIMER_ID(1);
550 goto end;
551 }
552
553 tid = imx94_get_timer_id(timer_np);
554 of_node_put(timer_np);
555 if (tid < 0) {
556 dev_err(dev, "Failed to get NETC Timer ID\n");
557 return tid;
558 }
559
560 end:
561 netc_reg_write(priv->ierb, IERB_ETBCR(eid), tid);
562
563 return 0;
564 }
565
imx94_enetc_mdio_phyaddr_config(struct netc_blk_ctrl * priv,struct device_node * np,u32 phy_mask)566 static int imx94_enetc_mdio_phyaddr_config(struct netc_blk_ctrl *priv,
567 struct device_node *np,
568 u32 phy_mask)
569 {
570 struct device *dev = &priv->pdev->dev;
571 int bus_devfn, addr;
572
573 bus_devfn = netc_of_pci_get_bus_devfn(np);
574 if (bus_devfn < 0) {
575 dev_err(dev, "Failed to get BDF number\n");
576 return bus_devfn;
577 }
578
579 addr = netc_get_phy_addr(np);
580 if (addr < 0) {
581 dev_err(dev, "Failed to get PHY address\n");
582 return addr;
583 }
584
585 /* The default value of LaBCR[MDIO_PHYAD_PRTAD] is 0,
586 * so no need to set the register.
587 */
588 if (!addr)
589 return 0;
590
591 if (phy_mask & BIT(addr)) {
592 dev_err(dev,
593 "Find same PHY address in EMDIO and ENETC node\n");
594 return -EINVAL;
595 }
596
597 switch (bus_devfn) {
598 case IMX94_ENETC0_BUS_DEVFN:
599 netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC0_LINK),
600 LBCR_MDIO_PHYAD_PRTAD(addr));
601 break;
602 case IMX94_ENETC1_BUS_DEVFN:
603 netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC1_LINK),
604 LBCR_MDIO_PHYAD_PRTAD(addr));
605 break;
606 case IMX94_ENETC2_BUS_DEVFN:
607 netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC2_LINK),
608 LBCR_MDIO_PHYAD_PRTAD(addr));
609 break;
610 default:
611 break;
612 }
613
614 return 0;
615 }
616
imx94_ierb_init(struct platform_device * pdev)617 static int imx94_ierb_init(struct platform_device *pdev)
618 {
619 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
620 struct device_node *np = pdev->dev.of_node;
621 u32 phy_mask = 0;
622 int err;
623
624 err = netc_get_emdio_phy_mask(np, &phy_mask);
625 if (err) {
626 dev_err(&pdev->dev, "Failed to get PHY address mask\n");
627 return err;
628 }
629
630 for_each_child_of_node_scoped(np, child) {
631 for_each_child_of_node_scoped(child, gchild) {
632 if (!of_device_is_compatible(gchild, "pci1131,e101"))
633 continue;
634
635 err = imx94_enetc_update_tid(priv, gchild);
636 if (err)
637 return err;
638
639 err = imx94_enetc_mdio_phyaddr_config(priv, gchild,
640 phy_mask);
641 if (err)
642 return err;
643 }
644 }
645
646 return 0;
647 }
648
netc_ierb_init(struct platform_device * pdev)649 static int netc_ierb_init(struct platform_device *pdev)
650 {
651 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
652 const struct netc_devinfo *devinfo = priv->devinfo;
653 int err;
654
655 if (netc_ierb_is_locked(priv)) {
656 err = netc_unlock_ierb_with_warm_reset(priv);
657 if (err) {
658 dev_err(&pdev->dev, "Unlock IERB failed.\n");
659 return err;
660 }
661 }
662
663 if (devinfo->ierb_init) {
664 err = devinfo->ierb_init(pdev);
665 if (err)
666 return err;
667 }
668
669 err = netc_lock_ierb(priv);
670 if (err) {
671 dev_err(&pdev->dev, "Lock IERB failed.\n");
672 return err;
673 }
674
675 return 0;
676 }
677
678 #if IS_ENABLED(CONFIG_DEBUG_FS)
netc_prb_show(struct seq_file * s,void * data)679 static int netc_prb_show(struct seq_file *s, void *data)
680 {
681 struct netc_blk_ctrl *priv = s->private;
682 u32 val;
683
684 val = netc_reg_read(priv->prb, PRB_NETCRR);
685 seq_printf(s, "[PRB NETCRR] Lock:%d SR:%d\n",
686 (val & NETCRR_LOCK) ? 1 : 0,
687 (val & NETCRR_SR) ? 1 : 0);
688
689 val = netc_reg_read(priv->prb, PRB_NETCSR);
690 seq_printf(s, "[PRB NETCSR] State:%d Error:%d\n",
691 (val & NETCSR_STATE) ? 1 : 0,
692 (val & NETCSR_ERROR) ? 1 : 0);
693
694 return 0;
695 }
696 DEFINE_SHOW_ATTRIBUTE(netc_prb);
697
netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl * priv)698 static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
699 {
700 struct dentry *root;
701
702 root = debugfs_create_dir("netc_blk_ctrl", NULL);
703 if (IS_ERR(root))
704 return;
705
706 priv->debugfs_root = root;
707
708 debugfs_create_file("prb", 0444, root, priv, &netc_prb_fops);
709 }
710
netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl * priv)711 static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
712 {
713 debugfs_remove_recursive(priv->debugfs_root);
714 priv->debugfs_root = NULL;
715 }
716
717 #else
718
netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl * priv)719 static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
720 {
721 }
722
netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl * priv)723 static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
724 {
725 }
726 #endif
727
netc_prb_check_error(struct netc_blk_ctrl * priv)728 static int netc_prb_check_error(struct netc_blk_ctrl *priv)
729 {
730 if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR)
731 return -1;
732
733 return 0;
734 }
735
736 static const struct netc_devinfo imx95_devinfo = {
737 .flags = NETC_HAS_NETCMIX,
738 .netcmix_init = imx95_netcmix_init,
739 .ierb_init = imx95_ierb_init,
740 };
741
742 static const struct netc_devinfo imx94_devinfo = {
743 .flags = NETC_HAS_NETCMIX,
744 .netcmix_init = imx94_netcmix_init,
745 .ierb_init = imx94_ierb_init,
746 };
747
748 static const struct of_device_id netc_blk_ctrl_match[] = {
749 { .compatible = "nxp,imx95-netc-blk-ctrl", .data = &imx95_devinfo },
750 { .compatible = "nxp,imx94-netc-blk-ctrl", .data = &imx94_devinfo },
751 {},
752 };
753 MODULE_DEVICE_TABLE(of, netc_blk_ctrl_match);
754
netc_blk_ctrl_probe(struct platform_device * pdev)755 static int netc_blk_ctrl_probe(struct platform_device *pdev)
756 {
757 struct device_node *node = pdev->dev.of_node;
758 const struct netc_devinfo *devinfo;
759 struct device *dev = &pdev->dev;
760 const struct of_device_id *id;
761 struct netc_blk_ctrl *priv;
762 struct clk *ipg_clk;
763 void __iomem *regs;
764 int err;
765
766 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
767 if (!priv)
768 return -ENOMEM;
769
770 priv->pdev = pdev;
771 ipg_clk = devm_clk_get_optional_enabled(dev, "ipg");
772 if (IS_ERR(ipg_clk))
773 return dev_err_probe(dev, PTR_ERR(ipg_clk),
774 "Set ipg clock failed\n");
775
776 id = of_match_device(netc_blk_ctrl_match, dev);
777 if (!id)
778 return dev_err_probe(dev, -EINVAL, "Cannot match device\n");
779
780 devinfo = (struct netc_devinfo *)id->data;
781 if (!devinfo)
782 return dev_err_probe(dev, -EINVAL, "No device information\n");
783
784 priv->devinfo = devinfo;
785 regs = devm_platform_ioremap_resource_byname(pdev, "ierb");
786 if (IS_ERR(regs))
787 return dev_err_probe(dev, PTR_ERR(regs),
788 "Missing IERB resource\n");
789
790 priv->ierb = regs;
791 regs = devm_platform_ioremap_resource_byname(pdev, "prb");
792 if (IS_ERR(regs))
793 return dev_err_probe(dev, PTR_ERR(regs),
794 "Missing PRB resource\n");
795
796 priv->prb = regs;
797 if (devinfo->flags & NETC_HAS_NETCMIX) {
798 regs = devm_platform_ioremap_resource_byname(pdev, "netcmix");
799 if (IS_ERR(regs))
800 return dev_err_probe(dev, PTR_ERR(regs),
801 "Missing NETCMIX resource\n");
802 priv->netcmix = regs;
803 }
804
805 platform_set_drvdata(pdev, priv);
806 if (devinfo->netcmix_init) {
807 err = devinfo->netcmix_init(pdev);
808 if (err)
809 return dev_err_probe(dev, err,
810 "Initializing NETCMIX failed\n");
811 }
812
813 err = netc_ierb_init(pdev);
814 if (err)
815 return dev_err_probe(dev, err, "Initializing IERB failed\n");
816
817 if (netc_prb_check_error(priv) < 0)
818 dev_warn(dev, "The current IERB configuration is invalid\n");
819
820 netc_blk_ctrl_create_debugfs(priv);
821
822 err = of_platform_populate(node, NULL, NULL, dev);
823 if (err) {
824 netc_blk_ctrl_remove_debugfs(priv);
825 return dev_err_probe(dev, err, "of_platform_populate failed\n");
826 }
827
828 return 0;
829 }
830
netc_blk_ctrl_remove(struct platform_device * pdev)831 static void netc_blk_ctrl_remove(struct platform_device *pdev)
832 {
833 struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
834
835 of_platform_depopulate(&pdev->dev);
836 netc_blk_ctrl_remove_debugfs(priv);
837 }
838
839 static struct platform_driver netc_blk_ctrl_driver = {
840 .driver = {
841 .name = "nxp-netc-blk-ctrl",
842 .of_match_table = netc_blk_ctrl_match,
843 },
844 .probe = netc_blk_ctrl_probe,
845 .remove = netc_blk_ctrl_remove,
846 };
847
848 module_platform_driver(netc_blk_ctrl_driver);
849
850 MODULE_DESCRIPTION("NXP NETC Blocks Control Driver");
851 MODULE_LICENSE("Dual BSD/GPL");
852