1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * NXP NETC V4 Timer driver
4 * Copyright 2025 NXP
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/fsl/netc_global.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/pci.h>
14 #include <linux/ptp_clock_kernel.h>
15
16 #define NETC_TMR_PCI_VENDOR_NXP 0x1131
17
18 #define NETC_TMR_CTRL 0x0080
19 #define TMR_CTRL_CK_SEL GENMASK(1, 0)
20 #define TMR_CTRL_TE BIT(2)
21 #define TMR_ETEP(i) BIT(8 + (i))
22 #define TMR_COMP_MODE BIT(15)
23 #define TMR_CTRL_TCLK_PERIOD GENMASK(25, 16)
24 #define TMR_CTRL_PPL(i) BIT(27 - (i))
25 #define TMR_CTRL_FS BIT(28)
26
27 #define NETC_TMR_TEVENT 0x0084
28 #define TMR_TEVNET_PPEN(i) BIT(7 - (i))
29 #define TMR_TEVENT_PPEN_ALL GENMASK(7, 5)
30 #define TMR_TEVENT_ALMEN(i) BIT(16 + (i))
31 #define TMR_TEVENT_ETS_THREN(i) BIT(20 + (i))
32 #define TMR_TEVENT_ETSEN(i) BIT(24 + (i))
33 #define TMR_TEVENT_ETS_OVEN(i) BIT(28 + (i))
34 #define TMR_TEVENT_ETS(i) (TMR_TEVENT_ETS_THREN(i) | \
35 TMR_TEVENT_ETSEN(i) | \
36 TMR_TEVENT_ETS_OVEN(i))
37
38 #define NETC_TMR_TEMASK 0x0088
39 #define NETC_TMR_STAT 0x0094
40 #define TMR_STAT_ETS_VLD(i) BIT(24 + (i))
41
42 #define NETC_TMR_CNT_L 0x0098
43 #define NETC_TMR_CNT_H 0x009c
44 #define NETC_TMR_ADD 0x00a0
45 #define NETC_TMR_PRSC 0x00a8
46 #define NETC_TMR_ECTRL 0x00ac
47 #define NETC_TMR_OFF_L 0x00b0
48 #define NETC_TMR_OFF_H 0x00b4
49
50 /* i = 0, 1, i indicates the index of TMR_ALARM */
51 #define NETC_TMR_ALARM_L(i) (0x00b8 + (i) * 8)
52 #define NETC_TMR_ALARM_H(i) (0x00bc + (i) * 8)
53
54 /* i = 0, 1, 2. i indicates the index of TMR_FIPER. */
55 #define NETC_TMR_FIPER(i) (0x00d0 + (i) * 4)
56
57 #define NETC_TMR_FIPER_CTRL 0x00dc
58 #define FIPER_CTRL_DIS(i) (BIT(7) << (i) * 8)
59 #define FIPER_CTRL_PG(i) (BIT(6) << (i) * 8)
60 #define FIPER_CTRL_FS_ALARM(i) (BIT(5) << (i) * 8)
61 #define FIPER_CTRL_PW(i) (GENMASK(4, 0) << (i) * 8)
62 #define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i))
63
64 /* i = 0, 1, i indicates the index of TMR_ETTS */
65 #define NETC_TMR_ETTS_L(i) (0x00e0 + (i) * 8)
66 #define NETC_TMR_ETTS_H(i) (0x00e4 + (i) * 8)
67 #define NETC_TMR_CUR_TIME_L 0x00f0
68 #define NETC_TMR_CUR_TIME_H 0x00f4
69
70 #define NETC_TMR_REGS_BAR 0
71 #define NETC_GLOBAL_OFFSET 0x10000
72 #define NETC_GLOBAL_IPBRR0 0xbf8
73 #define IPBRR0_IP_REV GENMASK(15, 0)
74 #define NETC_REV_4_1 0x0401
75
76 #define NETC_TMR_FIPER_NUM 3
77 #define NETC_TMR_INVALID_CHANNEL NETC_TMR_FIPER_NUM
78 #define NETC_TMR_DEFAULT_PRSC 2
79 #define NETC_TMR_DEFAULT_ALARM GENMASK_ULL(63, 0)
80 #define NETC_TMR_DEFAULT_FIPER GENMASK(31, 0)
81 #define NETC_TMR_FIPER_MAX_PW GENMASK(4, 0)
82 #define NETC_TMR_ALARM_NUM 2
83 #define NETC_TMR_DEFAULT_ETTF_THR 7
84
85 /* 1588 timer reference clock source select */
86 #define NETC_TMR_CCM_TIMER1 0 /* enet_timer1_clk_root, from CCM */
87 #define NETC_TMR_SYSTEM_CLK 1 /* enet_clk_root/2, from CCM */
88 #define NETC_TMR_EXT_OSC 2 /* tmr_1588_clk, from IO pins */
89
90 #define NETC_TMR_SYSCLK_333M 333333333U
91
92 enum netc_pp_type {
93 NETC_PP_PPS = 1,
94 NETC_PP_PEROUT,
95 };
96
97 struct netc_pp {
98 enum netc_pp_type type;
99 bool enabled;
100 int alarm_id;
101 u32 period; /* pulse period, ns */
102 u64 stime; /* start time, ns */
103 };
104
105 struct netc_timer {
106 void __iomem *base;
107 struct pci_dev *pdev;
108 spinlock_t lock; /* Prevent concurrent access to registers */
109
110 struct ptp_clock *clock;
111 struct ptp_clock_info caps;
112 u32 clk_select;
113 u32 clk_freq;
114 u32 oclk_prsc;
115 /* High 32-bit is integer part, low 32-bit is fractional part */
116 u64 period;
117
118 int irq;
119 char irq_name[24];
120 int revision;
121 u32 tmr_emask;
122 u8 pps_channel;
123 u8 fs_alarm_num;
124 u8 fs_alarm_bitmap;
125 struct netc_pp pp[NETC_TMR_FIPER_NUM]; /* periodic pulse */
126 };
127
128 #define netc_timer_rd(p, o) netc_read((p)->base + (o))
129 #define netc_timer_wr(p, o, v) netc_write((p)->base + (o), v)
130 #define ptp_to_netc_timer(ptp) container_of((ptp), struct netc_timer, caps)
131
132 static const char *const timer_clk_src[] = {
133 "ccm",
134 "ext"
135 };
136
netc_timer_cnt_write(struct netc_timer * priv,u64 ns)137 static void netc_timer_cnt_write(struct netc_timer *priv, u64 ns)
138 {
139 u32 tmr_cnt_h = upper_32_bits(ns);
140 u32 tmr_cnt_l = lower_32_bits(ns);
141
142 /* Writes to the TMR_CNT_L register copies the written value
143 * into the shadow TMR_CNT_L register. Writes to the TMR_CNT_H
144 * register copies the values written into the shadow TMR_CNT_H
145 * register. Contents of the shadow registers are copied into
146 * the TMR_CNT_L and TMR_CNT_H registers following a write into
147 * the TMR_CNT_H register. So the user must writes to TMR_CNT_L
148 * register first. Other H/L registers should have the same
149 * behavior.
150 */
151 netc_timer_wr(priv, NETC_TMR_CNT_L, tmr_cnt_l);
152 netc_timer_wr(priv, NETC_TMR_CNT_H, tmr_cnt_h);
153 }
154
netc_timer_offset_read(struct netc_timer * priv)155 static u64 netc_timer_offset_read(struct netc_timer *priv)
156 {
157 u32 tmr_off_l, tmr_off_h;
158 u64 offset;
159
160 tmr_off_l = netc_timer_rd(priv, NETC_TMR_OFF_L);
161 tmr_off_h = netc_timer_rd(priv, NETC_TMR_OFF_H);
162 offset = (((u64)tmr_off_h) << 32) | tmr_off_l;
163
164 return offset;
165 }
166
netc_timer_offset_write(struct netc_timer * priv,u64 offset)167 static void netc_timer_offset_write(struct netc_timer *priv, u64 offset)
168 {
169 u32 tmr_off_h = upper_32_bits(offset);
170 u32 tmr_off_l = lower_32_bits(offset);
171
172 netc_timer_wr(priv, NETC_TMR_OFF_L, tmr_off_l);
173 netc_timer_wr(priv, NETC_TMR_OFF_H, tmr_off_h);
174 }
175
netc_timer_cur_time_read(struct netc_timer * priv)176 static u64 netc_timer_cur_time_read(struct netc_timer *priv)
177 {
178 u32 time_h, time_l;
179 u64 ns;
180
181 /* The user should read NETC_TMR_CUR_TIME_L first to
182 * get correct current time.
183 */
184 time_l = netc_timer_rd(priv, NETC_TMR_CUR_TIME_L);
185 time_h = netc_timer_rd(priv, NETC_TMR_CUR_TIME_H);
186 ns = (u64)time_h << 32 | time_l;
187
188 return ns;
189 }
190
netc_timer_alarm_write(struct netc_timer * priv,u64 alarm,int index)191 static void netc_timer_alarm_write(struct netc_timer *priv,
192 u64 alarm, int index)
193 {
194 u32 alarm_h = upper_32_bits(alarm);
195 u32 alarm_l = lower_32_bits(alarm);
196
197 netc_timer_wr(priv, NETC_TMR_ALARM_L(index), alarm_l);
198 netc_timer_wr(priv, NETC_TMR_ALARM_H(index), alarm_h);
199 }
200
netc_timer_get_integral_period(struct netc_timer * priv)201 static u32 netc_timer_get_integral_period(struct netc_timer *priv)
202 {
203 u32 tmr_ctrl, integral_period;
204
205 tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
206 integral_period = FIELD_GET(TMR_CTRL_TCLK_PERIOD, tmr_ctrl);
207
208 return integral_period;
209 }
210
netc_timer_calculate_fiper_pw(struct netc_timer * priv,u32 fiper)211 static u32 netc_timer_calculate_fiper_pw(struct netc_timer *priv,
212 u32 fiper)
213 {
214 u64 divisor, pulse_width;
215
216 /* Set the FIPER pulse width to half FIPER interval by default.
217 * pulse_width = (fiper / 2) / TMR_GCLK_period,
218 * TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq,
219 * TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz,
220 * so pulse_width = fiper * clk_freq / (2 * NSEC_PER_SEC * oclk_prsc).
221 */
222 divisor = mul_u32_u32(2 * NSEC_PER_SEC, priv->oclk_prsc);
223 pulse_width = div64_u64(mul_u32_u32(fiper, priv->clk_freq), divisor);
224
225 /* The FIPER_PW field only has 5 bits, need to update oclk_prsc */
226 if (pulse_width > NETC_TMR_FIPER_MAX_PW)
227 pulse_width = NETC_TMR_FIPER_MAX_PW;
228
229 return pulse_width;
230 }
231
netc_timer_set_pps_alarm(struct netc_timer * priv,int channel,u32 integral_period)232 static void netc_timer_set_pps_alarm(struct netc_timer *priv, int channel,
233 u32 integral_period)
234 {
235 struct netc_pp *pp = &priv->pp[channel];
236 u64 alarm;
237
238 /* Get the alarm value */
239 alarm = netc_timer_cur_time_read(priv) + NSEC_PER_MSEC;
240 alarm = roundup_u64(alarm, NSEC_PER_SEC);
241 alarm = roundup_u64(alarm, integral_period);
242
243 netc_timer_alarm_write(priv, alarm, pp->alarm_id);
244 }
245
netc_timer_set_perout_alarm(struct netc_timer * priv,int channel,u32 integral_period)246 static void netc_timer_set_perout_alarm(struct netc_timer *priv, int channel,
247 u32 integral_period)
248 {
249 u64 cur_time = netc_timer_cur_time_read(priv);
250 struct netc_pp *pp = &priv->pp[channel];
251 u64 alarm, delta, min_time;
252 u32 period = pp->period;
253 u64 stime = pp->stime;
254
255 min_time = cur_time + NSEC_PER_MSEC + period;
256 if (stime < min_time) {
257 delta = min_time - stime;
258 stime += roundup_u64(delta, period);
259 }
260
261 alarm = roundup_u64(stime - period, integral_period);
262 netc_timer_alarm_write(priv, alarm, pp->alarm_id);
263 }
264
netc_timer_get_alarm_id(struct netc_timer * priv)265 static int netc_timer_get_alarm_id(struct netc_timer *priv)
266 {
267 int i;
268
269 for (i = 0; i < priv->fs_alarm_num; i++) {
270 if (!(priv->fs_alarm_bitmap & BIT(i))) {
271 priv->fs_alarm_bitmap |= BIT(i);
272 break;
273 }
274 }
275
276 return i;
277 }
278
netc_timer_get_gclk_period(struct netc_timer * priv)279 static u64 netc_timer_get_gclk_period(struct netc_timer *priv)
280 {
281 /* TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz.
282 * TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq.
283 * TMR_GCLK_period = (NSEC_PER_SEC * oclk_prsc) / clk_freq
284 */
285
286 return div_u64(mul_u32_u32(NSEC_PER_SEC, priv->oclk_prsc),
287 priv->clk_freq);
288 }
289
netc_timer_enable_periodic_pulse(struct netc_timer * priv,u8 channel)290 static void netc_timer_enable_periodic_pulse(struct netc_timer *priv,
291 u8 channel)
292 {
293 u32 fiper_pw, fiper, fiper_ctrl, integral_period;
294 struct netc_pp *pp = &priv->pp[channel];
295 int alarm_id = pp->alarm_id;
296
297 integral_period = netc_timer_get_integral_period(priv);
298 /* Set to desired FIPER interval in ns - TCLK_PERIOD */
299 fiper = pp->period - integral_period;
300 fiper_pw = netc_timer_calculate_fiper_pw(priv, fiper);
301
302 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
303 fiper_ctrl &= ~(FIPER_CTRL_DIS(channel) | FIPER_CTRL_PW(channel) |
304 FIPER_CTRL_FS_ALARM(channel));
305 fiper_ctrl |= FIPER_CTRL_SET_PW(channel, fiper_pw);
306 fiper_ctrl |= alarm_id ? FIPER_CTRL_FS_ALARM(channel) : 0;
307
308 priv->tmr_emask |= TMR_TEVENT_ALMEN(alarm_id);
309
310 if (pp->type == NETC_PP_PPS) {
311 priv->tmr_emask |= TMR_TEVNET_PPEN(channel);
312 netc_timer_set_pps_alarm(priv, channel, integral_period);
313 } else {
314 netc_timer_set_perout_alarm(priv, channel, integral_period);
315 }
316
317 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
318 netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper);
319 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
320 }
321
netc_timer_disable_periodic_pulse(struct netc_timer * priv,u8 channel)322 static void netc_timer_disable_periodic_pulse(struct netc_timer *priv,
323 u8 channel)
324 {
325 struct netc_pp *pp = &priv->pp[channel];
326 int alarm_id = pp->alarm_id;
327 u32 fiper_ctrl;
328
329 if (!pp->enabled)
330 return;
331
332 priv->tmr_emask &= ~(TMR_TEVNET_PPEN(channel) |
333 TMR_TEVENT_ALMEN(alarm_id));
334
335 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
336 fiper_ctrl |= FIPER_CTRL_DIS(channel);
337
338 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, alarm_id);
339 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
340 netc_timer_wr(priv, NETC_TMR_FIPER(channel), NETC_TMR_DEFAULT_FIPER);
341 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
342 }
343
netc_timer_select_pps_channel(struct netc_timer * priv)344 static u8 netc_timer_select_pps_channel(struct netc_timer *priv)
345 {
346 int i;
347
348 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
349 if (!priv->pp[i].enabled)
350 return i;
351 }
352
353 return NETC_TMR_INVALID_CHANNEL;
354 }
355
356 /* Note that users should not use this API to output PPS signal on
357 * external pins, because PTP_CLK_REQ_PPS trigger internal PPS event
358 * for input into kernel PPS subsystem. See:
359 * https://lore.kernel.org/r/20201117213826.18235-1-a.fatoum@pengutronix.de
360 */
netc_timer_enable_pps(struct netc_timer * priv,struct ptp_clock_request * rq,int on)361 static int netc_timer_enable_pps(struct netc_timer *priv,
362 struct ptp_clock_request *rq, int on)
363 {
364 struct device *dev = &priv->pdev->dev;
365 unsigned long flags;
366 struct netc_pp *pp;
367 int err = 0;
368
369 spin_lock_irqsave(&priv->lock, flags);
370
371 if (on) {
372 int alarm_id;
373 u8 channel;
374
375 if (priv->pps_channel < NETC_TMR_FIPER_NUM) {
376 channel = priv->pps_channel;
377 } else {
378 channel = netc_timer_select_pps_channel(priv);
379 if (channel == NETC_TMR_INVALID_CHANNEL) {
380 dev_err(dev, "No available FIPERs\n");
381 err = -EBUSY;
382 goto unlock_spinlock;
383 }
384 }
385
386 pp = &priv->pp[channel];
387 if (pp->enabled)
388 goto unlock_spinlock;
389
390 alarm_id = netc_timer_get_alarm_id(priv);
391 if (alarm_id == priv->fs_alarm_num) {
392 dev_err(dev, "No available ALARMs\n");
393 err = -EBUSY;
394 goto unlock_spinlock;
395 }
396
397 pp->enabled = true;
398 pp->type = NETC_PP_PPS;
399 pp->alarm_id = alarm_id;
400 pp->period = NSEC_PER_SEC;
401 priv->pps_channel = channel;
402
403 netc_timer_enable_periodic_pulse(priv, channel);
404 } else {
405 /* pps_channel is invalid if PPS is not enabled, so no
406 * processing is needed.
407 */
408 if (priv->pps_channel >= NETC_TMR_FIPER_NUM)
409 goto unlock_spinlock;
410
411 netc_timer_disable_periodic_pulse(priv, priv->pps_channel);
412 pp = &priv->pp[priv->pps_channel];
413 priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id);
414 memset(pp, 0, sizeof(*pp));
415 priv->pps_channel = NETC_TMR_INVALID_CHANNEL;
416 }
417
418 unlock_spinlock:
419 spin_unlock_irqrestore(&priv->lock, flags);
420
421 return err;
422 }
423
net_timer_enable_perout(struct netc_timer * priv,struct ptp_clock_request * rq,int on)424 static int net_timer_enable_perout(struct netc_timer *priv,
425 struct ptp_clock_request *rq, int on)
426 {
427 struct device *dev = &priv->pdev->dev;
428 u32 channel = rq->perout.index;
429 unsigned long flags;
430 struct netc_pp *pp;
431 int err = 0;
432
433 spin_lock_irqsave(&priv->lock, flags);
434
435 pp = &priv->pp[channel];
436 if (pp->type == NETC_PP_PPS) {
437 dev_err(dev, "FIPER%u is being used for PPS\n", channel);
438 err = -EBUSY;
439 goto unlock_spinlock;
440 }
441
442 if (on) {
443 u64 period_ns, gclk_period, max_period, min_period;
444 struct timespec64 period, stime;
445 u32 integral_period;
446 int alarm_id;
447
448 period.tv_sec = rq->perout.period.sec;
449 period.tv_nsec = rq->perout.period.nsec;
450 period_ns = timespec64_to_ns(&period);
451
452 integral_period = netc_timer_get_integral_period(priv);
453 max_period = (u64)NETC_TMR_DEFAULT_FIPER + integral_period;
454 gclk_period = netc_timer_get_gclk_period(priv);
455 min_period = gclk_period * 4 + integral_period;
456 if (period_ns > max_period || period_ns < min_period) {
457 dev_err(dev, "The period range is %llu ~ %llu\n",
458 min_period, max_period);
459 err = -EINVAL;
460 goto unlock_spinlock;
461 }
462
463 if (pp->enabled) {
464 alarm_id = pp->alarm_id;
465 } else {
466 alarm_id = netc_timer_get_alarm_id(priv);
467 if (alarm_id == priv->fs_alarm_num) {
468 dev_err(dev, "No available ALARMs\n");
469 err = -EBUSY;
470 goto unlock_spinlock;
471 }
472
473 pp->type = NETC_PP_PEROUT;
474 pp->enabled = true;
475 pp->alarm_id = alarm_id;
476 }
477
478 stime.tv_sec = rq->perout.start.sec;
479 stime.tv_nsec = rq->perout.start.nsec;
480 pp->stime = timespec64_to_ns(&stime);
481 pp->period = period_ns;
482
483 netc_timer_enable_periodic_pulse(priv, channel);
484 } else {
485 if (!pp->enabled)
486 goto unlock_spinlock;
487
488 netc_timer_disable_periodic_pulse(priv, channel);
489 priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id);
490 memset(pp, 0, sizeof(*pp));
491 }
492
493 unlock_spinlock:
494 spin_unlock_irqrestore(&priv->lock, flags);
495
496 return err;
497 }
498
netc_timer_handle_etts_event(struct netc_timer * priv,int index,bool update_event)499 static void netc_timer_handle_etts_event(struct netc_timer *priv, int index,
500 bool update_event)
501 {
502 struct ptp_clock_event event;
503 u32 etts_l = 0, etts_h = 0;
504
505 while (netc_timer_rd(priv, NETC_TMR_STAT) & TMR_STAT_ETS_VLD(index)) {
506 etts_l = netc_timer_rd(priv, NETC_TMR_ETTS_L(index));
507 etts_h = netc_timer_rd(priv, NETC_TMR_ETTS_H(index));
508 }
509
510 /* Invalid time stamp */
511 if (!etts_l && !etts_h)
512 return;
513
514 if (update_event) {
515 event.type = PTP_CLOCK_EXTTS;
516 event.index = index;
517 event.timestamp = (u64)etts_h << 32;
518 event.timestamp |= etts_l;
519 ptp_clock_event(priv->clock, &event);
520 }
521 }
522
netc_timer_enable_extts(struct netc_timer * priv,struct ptp_clock_request * rq,int on)523 static int netc_timer_enable_extts(struct netc_timer *priv,
524 struct ptp_clock_request *rq, int on)
525 {
526 int index = rq->extts.index;
527 unsigned long flags;
528 u32 tmr_ctrl;
529
530 /* Reject requests to enable time stamping on both edges */
531 if ((rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
532 return -EOPNOTSUPP;
533
534 spin_lock_irqsave(&priv->lock, flags);
535
536 netc_timer_handle_etts_event(priv, rq->extts.index, false);
537 if (on) {
538 tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
539 if (rq->extts.flags & PTP_FALLING_EDGE)
540 tmr_ctrl |= TMR_ETEP(index);
541 else
542 tmr_ctrl &= ~TMR_ETEP(index);
543
544 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
545 priv->tmr_emask |= TMR_TEVENT_ETS(index);
546 } else {
547 priv->tmr_emask &= ~TMR_TEVENT_ETS(index);
548 }
549
550 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
551
552 spin_unlock_irqrestore(&priv->lock, flags);
553
554 return 0;
555 }
556
netc_timer_disable_fiper(struct netc_timer * priv)557 static void netc_timer_disable_fiper(struct netc_timer *priv)
558 {
559 u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
560 int i;
561
562 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
563 if (!priv->pp[i].enabled)
564 continue;
565
566 fiper_ctrl |= FIPER_CTRL_DIS(i);
567 netc_timer_wr(priv, NETC_TMR_FIPER(i), NETC_TMR_DEFAULT_FIPER);
568 }
569
570 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
571 }
572
netc_timer_enable_fiper(struct netc_timer * priv)573 static void netc_timer_enable_fiper(struct netc_timer *priv)
574 {
575 u32 integral_period = netc_timer_get_integral_period(priv);
576 u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
577 int i;
578
579 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
580 struct netc_pp *pp = &priv->pp[i];
581 u32 fiper;
582
583 if (!pp->enabled)
584 continue;
585
586 fiper_ctrl &= ~FIPER_CTRL_DIS(i);
587
588 if (pp->type == NETC_PP_PPS)
589 netc_timer_set_pps_alarm(priv, i, integral_period);
590 else if (pp->type == NETC_PP_PEROUT)
591 netc_timer_set_perout_alarm(priv, i, integral_period);
592
593 fiper = pp->period - integral_period;
594 netc_timer_wr(priv, NETC_TMR_FIPER(i), fiper);
595 }
596
597 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
598 }
599
netc_timer_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)600 static int netc_timer_enable(struct ptp_clock_info *ptp,
601 struct ptp_clock_request *rq, int on)
602 {
603 struct netc_timer *priv = ptp_to_netc_timer(ptp);
604
605 switch (rq->type) {
606 case PTP_CLK_REQ_PPS:
607 return netc_timer_enable_pps(priv, rq, on);
608 case PTP_CLK_REQ_PEROUT:
609 return net_timer_enable_perout(priv, rq, on);
610 case PTP_CLK_REQ_EXTTS:
611 return netc_timer_enable_extts(priv, rq, on);
612 default:
613 return -EOPNOTSUPP;
614 }
615 }
616
netc_timer_perout_loopback(struct ptp_clock_info * ptp,unsigned int index,int on)617 static int netc_timer_perout_loopback(struct ptp_clock_info *ptp,
618 unsigned int index, int on)
619 {
620 struct netc_timer *priv = ptp_to_netc_timer(ptp);
621 unsigned long flags;
622 u32 tmr_ctrl;
623
624 spin_lock_irqsave(&priv->lock, flags);
625
626 tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
627 if (on)
628 tmr_ctrl |= TMR_CTRL_PPL(index);
629 else
630 tmr_ctrl &= ~TMR_CTRL_PPL(index);
631
632 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
633
634 spin_unlock_irqrestore(&priv->lock, flags);
635
636 return 0;
637 }
638
netc_timer_adjust_period(struct netc_timer * priv,u64 period)639 static void netc_timer_adjust_period(struct netc_timer *priv, u64 period)
640 {
641 u32 fractional_period = lower_32_bits(period);
642 u32 integral_period = upper_32_bits(period);
643 u32 tmr_ctrl, old_tmr_ctrl;
644 unsigned long flags;
645
646 spin_lock_irqsave(&priv->lock, flags);
647
648 old_tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
649 tmr_ctrl = u32_replace_bits(old_tmr_ctrl, integral_period,
650 TMR_CTRL_TCLK_PERIOD);
651 if (tmr_ctrl != old_tmr_ctrl) {
652 netc_timer_disable_fiper(priv);
653 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
654 netc_timer_enable_fiper(priv);
655 }
656
657 netc_timer_wr(priv, NETC_TMR_ADD, fractional_period);
658
659 spin_unlock_irqrestore(&priv->lock, flags);
660 }
661
netc_timer_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)662 static int netc_timer_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
663 {
664 struct netc_timer *priv = ptp_to_netc_timer(ptp);
665 u64 new_period;
666
667 new_period = adjust_by_scaled_ppm(priv->period, scaled_ppm);
668 netc_timer_adjust_period(priv, new_period);
669
670 return 0;
671 }
672
netc_timer_adjtime(struct ptp_clock_info * ptp,s64 delta)673 static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta)
674 {
675 struct netc_timer *priv = ptp_to_netc_timer(ptp);
676 unsigned long flags;
677 s64 tmr_off;
678
679 spin_lock_irqsave(&priv->lock, flags);
680
681 netc_timer_disable_fiper(priv);
682
683 /* Adjusting TMROFF instead of TMR_CNT is that the timer
684 * counter keeps increasing during reading and writing
685 * TMR_CNT, which will cause latency.
686 */
687 tmr_off = netc_timer_offset_read(priv);
688 tmr_off += delta;
689 netc_timer_offset_write(priv, tmr_off);
690
691 netc_timer_enable_fiper(priv);
692
693 spin_unlock_irqrestore(&priv->lock, flags);
694
695 return 0;
696 }
697
netc_timer_gettimex64(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)698 static int netc_timer_gettimex64(struct ptp_clock_info *ptp,
699 struct timespec64 *ts,
700 struct ptp_system_timestamp *sts)
701 {
702 struct netc_timer *priv = ptp_to_netc_timer(ptp);
703 unsigned long flags;
704 u64 ns;
705
706 spin_lock_irqsave(&priv->lock, flags);
707
708 ptp_read_system_prets(sts);
709 ns = netc_timer_cur_time_read(priv);
710 ptp_read_system_postts(sts);
711
712 spin_unlock_irqrestore(&priv->lock, flags);
713
714 *ts = ns_to_timespec64(ns);
715
716 return 0;
717 }
718
netc_timer_settime64(struct ptp_clock_info * ptp,const struct timespec64 * ts)719 static int netc_timer_settime64(struct ptp_clock_info *ptp,
720 const struct timespec64 *ts)
721 {
722 struct netc_timer *priv = ptp_to_netc_timer(ptp);
723 u64 ns = timespec64_to_ns(ts);
724 unsigned long flags;
725
726 spin_lock_irqsave(&priv->lock, flags);
727
728 netc_timer_disable_fiper(priv);
729 netc_timer_offset_write(priv, 0);
730 netc_timer_cnt_write(priv, ns);
731 netc_timer_enable_fiper(priv);
732
733 spin_unlock_irqrestore(&priv->lock, flags);
734
735 return 0;
736 }
737
738 static const struct ptp_clock_info netc_timer_ptp_caps = {
739 .owner = THIS_MODULE,
740 .name = "NETC Timer PTP clock",
741 .max_adj = 500000000,
742 .n_pins = 0,
743 .n_alarm = 2,
744 .pps = 1,
745 .n_per_out = 3,
746 .n_ext_ts = 2,
747 .n_per_lp = 2,
748 .supported_extts_flags = PTP_RISING_EDGE | PTP_FALLING_EDGE |
749 PTP_STRICT_FLAGS,
750 .adjfine = netc_timer_adjfine,
751 .adjtime = netc_timer_adjtime,
752 .gettimex64 = netc_timer_gettimex64,
753 .settime64 = netc_timer_settime64,
754 .enable = netc_timer_enable,
755 .perout_loopback = netc_timer_perout_loopback,
756 };
757
netc_timer_init(struct netc_timer * priv)758 static void netc_timer_init(struct netc_timer *priv)
759 {
760 u32 fractional_period = lower_32_bits(priv->period);
761 u32 integral_period = upper_32_bits(priv->period);
762 u32 tmr_ctrl, fiper_ctrl;
763 struct timespec64 now;
764 u64 ns;
765 int i;
766
767 /* Software must enable timer first and the clock selected must be
768 * active, otherwise, the registers which are in the timer clock
769 * domain are not accessible.
770 */
771 tmr_ctrl = FIELD_PREP(TMR_CTRL_CK_SEL, priv->clk_select) |
772 TMR_CTRL_TE | TMR_CTRL_FS;
773 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
774 netc_timer_wr(priv, NETC_TMR_PRSC, priv->oclk_prsc);
775 netc_timer_wr(priv, NETC_TMR_TEMASK, 0);
776
777 /* Disable FIPER by default */
778 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
779 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
780 fiper_ctrl |= FIPER_CTRL_DIS(i);
781 fiper_ctrl &= ~FIPER_CTRL_PG(i);
782 }
783 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
784 netc_timer_wr(priv, NETC_TMR_ECTRL, NETC_TMR_DEFAULT_ETTF_THR);
785
786 netc_timer_offset_write(priv, 0);
787 ktime_get_real_ts64(&now);
788 ns = timespec64_to_ns(&now);
789 netc_timer_cnt_write(priv, ns);
790
791 /* Allow atomic writes to TCLK_PERIOD and TMR_ADD, An update to
792 * TCLK_PERIOD does not take effect until TMR_ADD is written.
793 */
794 tmr_ctrl |= FIELD_PREP(TMR_CTRL_TCLK_PERIOD, integral_period) |
795 TMR_COMP_MODE;
796 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
797 netc_timer_wr(priv, NETC_TMR_ADD, fractional_period);
798 }
799
netc_timer_pci_probe(struct pci_dev * pdev)800 static int netc_timer_pci_probe(struct pci_dev *pdev)
801 {
802 struct device *dev = &pdev->dev;
803 struct netc_timer *priv;
804 int err;
805
806 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
807 if (!priv)
808 return -ENOMEM;
809
810 pcie_flr(pdev);
811 err = pci_enable_device_mem(pdev);
812 if (err)
813 return dev_err_probe(dev, err, "Failed to enable device\n");
814
815 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
816 err = pci_request_mem_regions(pdev, KBUILD_MODNAME);
817 if (err) {
818 dev_err(dev, "pci_request_regions() failed, err:%pe\n",
819 ERR_PTR(err));
820 goto disable_dev;
821 }
822
823 pci_set_master(pdev);
824
825 priv->pdev = pdev;
826 priv->base = pci_ioremap_bar(pdev, NETC_TMR_REGS_BAR);
827 if (!priv->base) {
828 err = -ENOMEM;
829 goto release_mem_regions;
830 }
831
832 pci_set_drvdata(pdev, priv);
833
834 return 0;
835
836 release_mem_regions:
837 pci_release_mem_regions(pdev);
838 disable_dev:
839 pci_disable_device(pdev);
840
841 return err;
842 }
843
netc_timer_pci_remove(struct pci_dev * pdev)844 static void netc_timer_pci_remove(struct pci_dev *pdev)
845 {
846 struct netc_timer *priv = pci_get_drvdata(pdev);
847
848 iounmap(priv->base);
849 pci_release_mem_regions(pdev);
850 pci_disable_device(pdev);
851 }
852
netc_timer_get_reference_clk_source(struct netc_timer * priv)853 static int netc_timer_get_reference_clk_source(struct netc_timer *priv)
854 {
855 struct device *dev = &priv->pdev->dev;
856 struct clk *clk;
857 int i;
858
859 /* Select NETC system clock as the reference clock by default */
860 priv->clk_select = NETC_TMR_SYSTEM_CLK;
861 priv->clk_freq = NETC_TMR_SYSCLK_333M;
862
863 /* Update the clock source of the reference clock if the clock
864 * is specified in DT node.
865 */
866 for (i = 0; i < ARRAY_SIZE(timer_clk_src); i++) {
867 clk = devm_clk_get_optional_enabled(dev, timer_clk_src[i]);
868 if (IS_ERR(clk))
869 return dev_err_probe(dev, PTR_ERR(clk),
870 "Failed to enable clock\n");
871
872 if (clk) {
873 priv->clk_freq = clk_get_rate(clk);
874 priv->clk_select = i ? NETC_TMR_EXT_OSC :
875 NETC_TMR_CCM_TIMER1;
876 break;
877 }
878 }
879
880 /* The period is a 64-bit number, the high 32-bit is the integer
881 * part of the period, the low 32-bit is the fractional part of
882 * the period. In order to get the desired 32-bit fixed-point
883 * format, multiply the numerator of the fraction by 2^32.
884 */
885 priv->period = div_u64((u64)NSEC_PER_SEC << 32, priv->clk_freq);
886
887 return 0;
888 }
889
netc_timer_parse_dt(struct netc_timer * priv)890 static int netc_timer_parse_dt(struct netc_timer *priv)
891 {
892 return netc_timer_get_reference_clk_source(priv);
893 }
894
netc_timer_isr(int irq,void * data)895 static irqreturn_t netc_timer_isr(int irq, void *data)
896 {
897 struct netc_timer *priv = data;
898 struct ptp_clock_event event;
899 u32 tmr_event;
900
901 spin_lock(&priv->lock);
902
903 tmr_event = netc_timer_rd(priv, NETC_TMR_TEVENT);
904 tmr_event &= priv->tmr_emask;
905 /* Clear interrupts status */
906 netc_timer_wr(priv, NETC_TMR_TEVENT, tmr_event);
907
908 if (!tmr_event) {
909 spin_unlock(&priv->lock);
910 return IRQ_NONE;
911 }
912
913 if (tmr_event & TMR_TEVENT_ALMEN(0))
914 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 0);
915
916 if (tmr_event & TMR_TEVENT_ALMEN(1))
917 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 1);
918
919 if (tmr_event & TMR_TEVENT_PPEN_ALL) {
920 event.type = PTP_CLOCK_PPS;
921 ptp_clock_event(priv->clock, &event);
922 }
923
924 if (tmr_event & TMR_TEVENT_ETS(0))
925 netc_timer_handle_etts_event(priv, 0, true);
926
927 if (tmr_event & TMR_TEVENT_ETS(1))
928 netc_timer_handle_etts_event(priv, 1, true);
929
930 spin_unlock(&priv->lock);
931
932 return IRQ_HANDLED;
933 }
934
netc_timer_init_msix_irq(struct netc_timer * priv)935 static int netc_timer_init_msix_irq(struct netc_timer *priv)
936 {
937 struct pci_dev *pdev = priv->pdev;
938 int err, n;
939
940 n = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
941 if (n != 1) {
942 err = (n < 0) ? n : -EPERM;
943 dev_err(&pdev->dev, "pci_alloc_irq_vectors() failed\n");
944 return err;
945 }
946
947 priv->irq = pci_irq_vector(pdev, 0);
948 err = request_irq(priv->irq, netc_timer_isr, IRQF_NO_AUTOEN,
949 priv->irq_name, priv);
950 if (err) {
951 dev_err(&pdev->dev, "request_irq() failed\n");
952 pci_free_irq_vectors(pdev);
953
954 return err;
955 }
956
957 return 0;
958 }
959
netc_timer_free_msix_irq(struct netc_timer * priv)960 static void netc_timer_free_msix_irq(struct netc_timer *priv)
961 {
962 struct pci_dev *pdev = priv->pdev;
963
964 free_irq(priv->irq, priv);
965 pci_free_irq_vectors(pdev);
966 }
967
netc_timer_get_global_ip_rev(struct netc_timer * priv)968 static int netc_timer_get_global_ip_rev(struct netc_timer *priv)
969 {
970 u32 val;
971
972 val = netc_timer_rd(priv, NETC_GLOBAL_OFFSET + NETC_GLOBAL_IPBRR0);
973
974 return val & IPBRR0_IP_REV;
975 }
976
netc_timer_probe(struct pci_dev * pdev,const struct pci_device_id * id)977 static int netc_timer_probe(struct pci_dev *pdev,
978 const struct pci_device_id *id)
979 {
980 struct device *dev = &pdev->dev;
981 struct netc_timer *priv;
982 int err;
983
984 err = netc_timer_pci_probe(pdev);
985 if (err)
986 return err;
987
988 priv = pci_get_drvdata(pdev);
989 priv->revision = netc_timer_get_global_ip_rev(priv);
990 if (priv->revision == NETC_REV_4_1)
991 priv->fs_alarm_num = 1;
992 else
993 priv->fs_alarm_num = NETC_TMR_ALARM_NUM;
994
995 err = netc_timer_parse_dt(priv);
996 if (err)
997 goto timer_pci_remove;
998
999 priv->caps = netc_timer_ptp_caps;
1000 priv->oclk_prsc = NETC_TMR_DEFAULT_PRSC;
1001 priv->pps_channel = NETC_TMR_INVALID_CHANNEL;
1002 spin_lock_init(&priv->lock);
1003 snprintf(priv->irq_name, sizeof(priv->irq_name), "ptp-netc %s",
1004 pci_name(pdev));
1005
1006 err = netc_timer_init_msix_irq(priv);
1007 if (err)
1008 goto timer_pci_remove;
1009
1010 netc_timer_init(priv);
1011 priv->clock = ptp_clock_register(&priv->caps, dev);
1012 if (IS_ERR(priv->clock)) {
1013 err = PTR_ERR(priv->clock);
1014 goto free_msix_irq;
1015 }
1016
1017 enable_irq(priv->irq);
1018
1019 return 0;
1020
1021 free_msix_irq:
1022 netc_timer_free_msix_irq(priv);
1023 timer_pci_remove:
1024 netc_timer_pci_remove(pdev);
1025
1026 return err;
1027 }
1028
netc_timer_remove(struct pci_dev * pdev)1029 static void netc_timer_remove(struct pci_dev *pdev)
1030 {
1031 struct netc_timer *priv = pci_get_drvdata(pdev);
1032
1033 disable_irq(priv->irq);
1034 ptp_clock_unregister(priv->clock);
1035 netc_timer_wr(priv, NETC_TMR_TEMASK, 0);
1036 netc_timer_wr(priv, NETC_TMR_CTRL, 0);
1037 netc_timer_free_msix_irq(priv);
1038 netc_timer_pci_remove(pdev);
1039 }
1040
1041 static const struct pci_device_id netc_timer_id_table[] = {
1042 { PCI_DEVICE(NETC_TMR_PCI_VENDOR_NXP, 0xee02) },
1043 { }
1044 };
1045 MODULE_DEVICE_TABLE(pci, netc_timer_id_table);
1046
1047 static struct pci_driver netc_timer_driver = {
1048 .name = KBUILD_MODNAME,
1049 .id_table = netc_timer_id_table,
1050 .probe = netc_timer_probe,
1051 .remove = netc_timer_remove,
1052 };
1053 module_pci_driver(netc_timer_driver);
1054
1055 MODULE_DESCRIPTION("NXP NETC Timer PTP Driver");
1056 MODULE_LICENSE("Dual BSD/GPL");
1057