1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> 4 * 5 * Info: 6 * Contains defines, datastructures for ndfc nand controller 7 */ 8 #ifndef __LINUX_MTD_NDFC_H 9 #define __LINUX_MTD_NDFC_H 10 11 /* NDFC Register definitions */ 12 #define NDFC_CMD 0x00 13 #define NDFC_ALE 0x04 14 #define NDFC_DATA 0x08 15 #define NDFC_ECC 0x10 16 #define NDFC_BCFG0 0x30 17 #define NDFC_BCFG1 0x34 18 #define NDFC_BCFG2 0x38 19 #define NDFC_BCFG3 0x3c 20 #define NDFC_CCR 0x40 21 #define NDFC_STAT 0x44 22 #define NDFC_HWCTL 0x48 23 #define NDFC_REVID 0x50 24 25 #define NDFC_STAT_IS_READY 0x01000000 26 27 #define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ 28 #define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ 29 #define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ 30 #define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ 31 #define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ 32 #define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ 33 #define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ 34 #define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ 35 #define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ 36 #define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ 37 #define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ 38 #define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ 39 #define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ 40 #define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ 41 #define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ 42 #define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ 43 44 #define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ 45 #define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ 46 #define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ 47 #define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ 48 #define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ 49 50 #define NDFC_MAX_BANKS 4 51 52 struct ndfc_controller_settings { 53 uint32_t ccr_settings; 54 uint64_t ndfc_erpn; 55 }; 56 57 struct ndfc_chip_settings { 58 uint32_t bank_settings; 59 }; 60 61 #endif 62