1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2023 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/init.h>
6 #include <linux/interrupt.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/perf_event.h>
12
13 /* Performance monitor configuration */
14 #define PMCFG1 0x00
15 #define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
16 #define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
17 #define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
18 #define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
19
20 #define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
21 #define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
22
23 #define PMCFG2 0x04
24 #define MX93_PMCFG2_ID GENMASK(17, 0)
25
26 #define PMCFG3 0x08
27 #define PMCFG4 0x0C
28 #define PMCFG5 0x10
29 #define PMCFG6 0x14
30 #define MX95_PMCFG_ID_MASK GENMASK(9, 0)
31 #define MX95_PMCFG_ID GENMASK(25, 16)
32
33 /* Global control register affects all counters and takes priority over local control registers */
34 #define PMGC0 0x40
35 /* Global control register bits */
36 #define PMGC0_FAC BIT(31)
37 #define PMGC0_PMIE BIT(30)
38 #define PMGC0_FCECE BIT(29)
39
40 /*
41 * 64bit counter0 exclusively dedicated to counting cycles
42 * 32bit counters monitor counter-specific events in addition to counting reference events
43 */
44 #define PMLCA(n) (0x40 + 0x10 + (0x10 * n))
45 #define PMLCB(n) (0x40 + 0x14 + (0x10 * n))
46 #define PMC(n) (0x40 + 0x18 + (0x10 * n))
47 /* Local control register bits */
48 #define PMLCA_FC BIT(31)
49 #define PMLCA_CE BIT(26)
50 #define PMLCA_EVENT GENMASK(22, 16)
51
52 #define NUM_COUNTERS 11
53 #define CYCLES_COUNTER 0
54 #define CYCLES_EVENT_ID 0
55
56 #define CONFIG_EVENT_MASK GENMASK(7, 0)
57 #define CONFIG_COUNTER_MASK GENMASK(23, 16)
58
59 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
60
61 #define DDR_PERF_DEV_NAME "imx9_ddr"
62 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
63
64 static DEFINE_IDA(ddr_ida);
65
66 /*
67 * V1 support 1 read transaction, 1 write transaction and 1 read beats
68 * event which corresponding respecitively to counter 2, 3 and 4.
69 */
70 #define DDR_PERF_AXI_FILTER_V1 0x1
71
72 /*
73 * V2 support 1 read beats and 3 write beats events which corresponding
74 * respecitively to counter 2-5.
75 */
76 #define DDR_PERF_AXI_FILTER_V2 0x2
77
78 struct imx_ddr_devtype_data {
79 const char *identifier; /* system PMU identifier for userspace */
80 unsigned int filter_ver; /* AXI filter version */
81 };
82
83 struct ddr_pmu {
84 struct pmu pmu;
85 void __iomem *base;
86 unsigned int cpu;
87 struct hlist_node node;
88 struct device *dev;
89 struct perf_event *events[NUM_COUNTERS];
90 int active_events;
91 enum cpuhp_state cpuhp_state;
92 const struct imx_ddr_devtype_data *devtype_data;
93 int irq;
94 int id;
95 };
96
97 static const struct imx_ddr_devtype_data imx91_devtype_data = {
98 .identifier = "imx91",
99 .filter_ver = DDR_PERF_AXI_FILTER_V1
100 };
101
102 static const struct imx_ddr_devtype_data imx93_devtype_data = {
103 .identifier = "imx93",
104 .filter_ver = DDR_PERF_AXI_FILTER_V1
105 };
106
107 static const struct imx_ddr_devtype_data imx95_devtype_data = {
108 .identifier = "imx95",
109 .filter_ver = DDR_PERF_AXI_FILTER_V2
110 };
111
axi_filter_v1(struct ddr_pmu * pmu)112 static inline bool axi_filter_v1(struct ddr_pmu *pmu)
113 {
114 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1;
115 }
116
axi_filter_v2(struct ddr_pmu * pmu)117 static inline bool axi_filter_v2(struct ddr_pmu *pmu)
118 {
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2;
120 }
121
122 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
123 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
124 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
125 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
126 { /* sentinel */ }
127 };
128 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
129
ddr_perf_identifier_show(struct device * dev,struct device_attribute * attr,char * page)130 static ssize_t ddr_perf_identifier_show(struct device *dev,
131 struct device_attribute *attr,
132 char *page)
133 {
134 struct ddr_pmu *pmu = dev_get_drvdata(dev);
135
136 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
137 }
138
139 static struct device_attribute ddr_perf_identifier_attr =
140 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
141
142 static struct attribute *ddr_perf_identifier_attrs[] = {
143 &ddr_perf_identifier_attr.attr,
144 NULL,
145 };
146
147 static struct attribute_group ddr_perf_identifier_attr_group = {
148 .attrs = ddr_perf_identifier_attrs,
149 };
150
ddr_perf_cpumask_show(struct device * dev,struct device_attribute * attr,char * buf)151 static ssize_t ddr_perf_cpumask_show(struct device *dev,
152 struct device_attribute *attr, char *buf)
153 {
154 struct ddr_pmu *pmu = dev_get_drvdata(dev);
155
156 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
157 }
158
159 static struct device_attribute ddr_perf_cpumask_attr =
160 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
161
162 static struct attribute *ddr_perf_cpumask_attrs[] = {
163 &ddr_perf_cpumask_attr.attr,
164 NULL,
165 };
166
167 static const struct attribute_group ddr_perf_cpumask_attr_group = {
168 .attrs = ddr_perf_cpumask_attrs,
169 };
170
171 struct imx9_pmu_events_attr {
172 struct device_attribute attr;
173 u64 id;
174 const struct imx_ddr_devtype_data *devtype_data;
175 };
176
ddr_pmu_event_show(struct device * dev,struct device_attribute * attr,char * page)177 static ssize_t ddr_pmu_event_show(struct device *dev,
178 struct device_attribute *attr, char *page)
179 {
180 struct imx9_pmu_events_attr *pmu_attr;
181
182 pmu_attr = container_of(attr, struct imx9_pmu_events_attr, attr);
183 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
184 }
185
186 #define COUNTER_OFFSET_IN_EVENT 8
187 #define ID(counter, id) ((counter << COUNTER_OFFSET_IN_EVENT) | id)
188
189 #define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \
190 (&((struct imx9_pmu_events_attr[]) { \
191 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
192 .id = _id, \
193 .devtype_data = _data, } \
194 })[0].attr.attr)
195
196 #define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
197 DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL)
198
199 #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
200 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
201
202 #define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \
203 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data)
204
205 static struct attribute *ddr_perf_events_attrs[] = {
206 /* counter0 cycles event */
207 IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
208
209 /* reference events for all normal counters, need assert DEBUG19[21] bit */
210 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ddrc1_rmw_for_ecc, 12),
211 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_rreorder, 13),
212 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_wreorder, 14),
213 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_0, 15),
214 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_1, 16),
215 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_2, 17),
216 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_3, 18),
217 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_4, 19),
218 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_5, 22),
219 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_6, 23),
220 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_7, 24),
221 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_8, 25),
222 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_9, 26),
223 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_10, 27),
224 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_11, 28),
225 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_12, 31),
226 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_13, 59),
227 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_15, 61),
228 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63),
229
230 /* counter1 specific events */
231 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)),
232 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)),
233 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)),
234 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)),
235 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)),
236 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)),
237 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)),
238 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)),
239
240 /* counter2 specific events */
241 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)),
242 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)),
243 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)),
244 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)),
245 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)),
246 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)),
247 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
248 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
249 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
250 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
251 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/
252
253 /* counter3 specific events */
254 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
255 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)),
256 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)),
257 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)),
258 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)),
259 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)),
260 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
261 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
262 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
263 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
264 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/
265
266 /* counter4 specific events */
267 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
268 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)),
269 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)),
270 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)),
271 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)),
272 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)),
273 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
274 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
275 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
276 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
277 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/
278
279 /* counter5 specific events */
280 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
281 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)),
282 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)),
283 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)),
284 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)),
285 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)),
286 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)),
287 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)),
288 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)),
289 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/
290
291 /* counter6 specific events */
292 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)),
293 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)),
294
295 /* counter7 specific events */
296 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)),
297 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)),
298
299 /* counter8 specific events */
300 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)),
301 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)),
302
303 /* counter9 specific events */
304 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)),
305 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)),
306
307 /* counter10 specific events */
308 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)),
309 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)),
310 NULL,
311 };
312
313 static umode_t
ddr_perf_events_attrs_is_visible(struct kobject * kobj,struct attribute * attr,int unused)314 ddr_perf_events_attrs_is_visible(struct kobject *kobj,
315 struct attribute *attr, int unused)
316 {
317 struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
318 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
319 struct imx9_pmu_events_attr *eattr;
320
321 eattr = container_of(attr, typeof(*eattr), attr.attr);
322
323 if (!eattr->devtype_data)
324 return attr->mode;
325
326 if (eattr->devtype_data != ddr_pmu->devtype_data &&
327 eattr->devtype_data->filter_ver != ddr_pmu->devtype_data->filter_ver)
328 return 0;
329
330 return attr->mode;
331 }
332
333 static const struct attribute_group ddr_perf_events_attr_group = {
334 .name = "events",
335 .attrs = ddr_perf_events_attrs,
336 .is_visible = ddr_perf_events_attrs_is_visible,
337 };
338
339 PMU_FORMAT_ATTR(event, "config:0-7,16-23");
340 PMU_FORMAT_ATTR(counter, "config:8-15");
341 PMU_FORMAT_ATTR(axi_id, "config1:0-17");
342 PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
343
344 static struct attribute *ddr_perf_format_attrs[] = {
345 &format_attr_event.attr,
346 &format_attr_counter.attr,
347 &format_attr_axi_id.attr,
348 &format_attr_axi_mask.attr,
349 NULL,
350 };
351
352 static const struct attribute_group ddr_perf_format_attr_group = {
353 .name = "format",
354 .attrs = ddr_perf_format_attrs,
355 };
356
357 static const struct attribute_group *attr_groups[] = {
358 &ddr_perf_identifier_attr_group,
359 &ddr_perf_cpumask_attr_group,
360 &ddr_perf_events_attr_group,
361 &ddr_perf_format_attr_group,
362 NULL,
363 };
364
ddr_perf_clear_counter(struct ddr_pmu * pmu,int counter)365 static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
366 {
367 if (counter == CYCLES_COUNTER) {
368 writel(0, pmu->base + PMC(counter) + 0x4);
369 writel(0, pmu->base + PMC(counter));
370 } else {
371 writel(0, pmu->base + PMC(counter));
372 }
373 }
374
ddr_perf_read_counter(struct ddr_pmu * pmu,int counter)375 static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
376 {
377 u32 val_lower, val_upper;
378 u64 val;
379
380 if (counter != CYCLES_COUNTER) {
381 val = readl_relaxed(pmu->base + PMC(counter));
382 goto out;
383 }
384
385 /* special handling for reading 64bit cycle counter */
386 do {
387 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
388 val_lower = readl_relaxed(pmu->base + PMC(counter));
389 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
390
391 val = val_upper;
392 val = (val << 32);
393 val |= val_lower;
394 out:
395 return val;
396 }
397
ddr_perf_counter_global_config(struct ddr_pmu * pmu,bool enable)398 static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool enable)
399 {
400 u32 ctrl;
401
402 ctrl = readl_relaxed(pmu->base + PMGC0);
403
404 if (enable) {
405 /*
406 * The performance monitor must be reset before event counting
407 * sequences. The performance monitor can be reset by first freezing
408 * one or more counters and then clearing the freeze condition to
409 * allow the counters to count according to the settings in the
410 * performance monitor registers. Counters can be frozen individually
411 * by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC].
412 * Simply clearing these freeze bits will then allow the performance
413 * monitor to begin counting based on the register settings.
414 */
415 ctrl |= PMGC0_FAC;
416 writel(ctrl, pmu->base + PMGC0);
417
418 /*
419 * Freeze all counters disabled, interrupt enabled, and freeze
420 * counters on condition enabled.
421 */
422 ctrl &= ~PMGC0_FAC;
423 ctrl |= PMGC0_PMIE | PMGC0_FCECE;
424 writel(ctrl, pmu->base + PMGC0);
425 } else {
426 ctrl |= PMGC0_FAC;
427 ctrl &= ~(PMGC0_PMIE | PMGC0_FCECE);
428 writel(ctrl, pmu->base + PMGC0);
429 }
430 }
431
ddr_perf_counter_local_config(struct ddr_pmu * pmu,int config,int counter,bool enable)432 static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
433 int counter, bool enable)
434 {
435 u32 ctrl_a;
436 int event;
437
438 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
439 event = FIELD_GET(CONFIG_EVENT_MASK, config);
440
441 if (enable) {
442 ctrl_a |= PMLCA_FC;
443 writel(ctrl_a, pmu->base + PMLCA(counter));
444
445 ddr_perf_clear_counter(pmu, counter);
446
447 /* Freeze counter disabled, condition enabled, and program event.*/
448 ctrl_a &= ~PMLCA_FC;
449 ctrl_a |= PMLCA_CE;
450 ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
451 ctrl_a |= FIELD_PREP(PMLCA_EVENT, event);
452 writel(ctrl_a, pmu->base + PMLCA(counter));
453 } else {
454 /* Freeze counter. */
455 ctrl_a |= PMLCA_FC;
456 writel(ctrl_a, pmu->base + PMLCA(counter));
457 }
458 }
459
imx93_ddr_perf_monitor_config(struct ddr_pmu * pmu,int event,int counter,int axi_id,int axi_mask)460 static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
461 int counter, int axi_id, int axi_mask)
462 {
463 u32 pmcfg1, pmcfg2;
464 static const u32 mask[] = {
465 MX93_PMCFG1_RD_TRANS_FILT_EN,
466 MX93_PMCFG1_WR_TRANS_FILT_EN,
467 MX93_PMCFG1_RD_BT_FILT_EN
468 };
469
470 pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
471
472 if (counter >= 2 && counter <= 4)
473 pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] :
474 pmcfg1 & ~mask[counter - 2];
475
476 pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
477 pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
478 writel_relaxed(pmcfg1, pmu->base + PMCFG1);
479
480 pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
481 pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
482 pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id);
483 writel_relaxed(pmcfg2, pmu->base + PMCFG2);
484 }
485
imx95_ddr_perf_monitor_config(struct ddr_pmu * pmu,int event,int counter,int axi_id,int axi_mask)486 static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
487 int counter, int axi_id, int axi_mask)
488 {
489 u32 pmcfg1, pmcfg, offset = 0;
490
491 pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
492
493 if (event == 73) {
494 switch (counter) {
495 case 2:
496 pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
497 offset = PMCFG3;
498 break;
499 case 3:
500 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
501 offset = PMCFG4;
502 break;
503 case 4:
504 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
505 offset = PMCFG5;
506 break;
507 case 5:
508 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
509 offset = PMCFG6;
510 break;
511 }
512 } else {
513 switch (counter) {
514 case 2:
515 pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
516 break;
517 case 3:
518 case 4:
519 case 5:
520 pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
521 break;
522 }
523 }
524
525 writel_relaxed(pmcfg1, pmu->base + PMCFG1);
526
527 if (offset) {
528 pmcfg = readl_relaxed(pmu->base + offset);
529 pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
530 FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
531 pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) |
532 FIELD_PREP(MX95_PMCFG_ID, axi_id));
533 writel_relaxed(pmcfg, pmu->base + offset);
534 }
535 }
536
ddr_perf_event_update(struct perf_event * event)537 static void ddr_perf_event_update(struct perf_event *event)
538 {
539 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
540 struct hw_perf_event *hwc = &event->hw;
541 int counter = hwc->idx;
542 u64 new_raw_count;
543
544 new_raw_count = ddr_perf_read_counter(pmu, counter);
545 local64_add(new_raw_count, &event->count);
546
547 /* clear counter's value every time */
548 ddr_perf_clear_counter(pmu, counter);
549 }
550
ddr_perf_event_init(struct perf_event * event)551 static int ddr_perf_event_init(struct perf_event *event)
552 {
553 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
554 struct hw_perf_event *hwc = &event->hw;
555 struct perf_event *sibling;
556
557 if (event->attr.type != event->pmu->type)
558 return -ENOENT;
559
560 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
561 return -EOPNOTSUPP;
562
563 if (event->cpu < 0) {
564 dev_warn(pmu->dev, "Can't provide per-task data!\n");
565 return -EOPNOTSUPP;
566 }
567
568 /*
569 * We must NOT create groups containing mixed PMUs, although software
570 * events are acceptable (for example to create a CCN group
571 * periodically read when a hrtimer aka cpu-clock leader triggers).
572 */
573 if (event->group_leader->pmu != event->pmu &&
574 !is_software_event(event->group_leader))
575 return -EINVAL;
576
577 for_each_sibling_event(sibling, event->group_leader) {
578 if (sibling->pmu != event->pmu &&
579 !is_software_event(sibling))
580 return -EINVAL;
581 }
582
583 event->cpu = pmu->cpu;
584 hwc->idx = -1;
585
586 return 0;
587 }
588
ddr_perf_event_start(struct perf_event * event,int flags)589 static void ddr_perf_event_start(struct perf_event *event, int flags)
590 {
591 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
592 struct hw_perf_event *hwc = &event->hw;
593 int counter = hwc->idx;
594
595 local64_set(&hwc->prev_count, 0);
596
597 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true);
598 hwc->state = 0;
599 }
600
ddr_perf_alloc_counter(struct ddr_pmu * pmu,int event,int counter)601 static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter)
602 {
603 int i;
604
605 if (event == CYCLES_EVENT_ID) {
606 // Cycles counter is dedicated for cycle event.
607 if (pmu->events[CYCLES_COUNTER] == NULL)
608 return CYCLES_COUNTER;
609 } else if (counter != 0) {
610 // Counter specific event use specific counter.
611 if (pmu->events[counter] == NULL)
612 return counter;
613 } else {
614 // Auto allocate counter for referene event.
615 for (i = 1; i < NUM_COUNTERS; i++)
616 if (pmu->events[i] == NULL)
617 return i;
618 }
619
620 return -ENOENT;
621 }
622
ddr_perf_event_add(struct perf_event * event,int flags)623 static int ddr_perf_event_add(struct perf_event *event, int flags)
624 {
625 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
626 struct hw_perf_event *hwc = &event->hw;
627 int cfg = event->attr.config;
628 int cfg1 = event->attr.config1;
629 int cfg2 = event->attr.config2;
630 int event_id, counter;
631
632 event_id = FIELD_GET(CONFIG_EVENT_MASK, cfg);
633 counter = FIELD_GET(CONFIG_COUNTER_MASK, cfg);
634
635 counter = ddr_perf_alloc_counter(pmu, event_id, counter);
636 if (counter < 0) {
637 dev_dbg(pmu->dev, "There are not enough counters\n");
638 return -EOPNOTSUPP;
639 }
640
641 pmu->events[counter] = event;
642 pmu->active_events++;
643 hwc->idx = counter;
644 hwc->state |= PERF_HES_STOPPED;
645
646 if (axi_filter_v1(pmu))
647 /* read trans, write trans, read beat */
648 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
649
650 if (axi_filter_v2(pmu))
651 /* write beat, read beat2, read beat1, read beat */
652 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
653
654 if (flags & PERF_EF_START)
655 ddr_perf_event_start(event, flags);
656
657 return 0;
658 }
659
ddr_perf_event_stop(struct perf_event * event,int flags)660 static void ddr_perf_event_stop(struct perf_event *event, int flags)
661 {
662 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
663 struct hw_perf_event *hwc = &event->hw;
664 int counter = hwc->idx;
665
666 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false);
667 ddr_perf_event_update(event);
668
669 hwc->state |= PERF_HES_STOPPED;
670 }
671
ddr_perf_event_del(struct perf_event * event,int flags)672 static void ddr_perf_event_del(struct perf_event *event, int flags)
673 {
674 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
675 struct hw_perf_event *hwc = &event->hw;
676 int counter = hwc->idx;
677
678 ddr_perf_event_stop(event, PERF_EF_UPDATE);
679
680 pmu->events[counter] = NULL;
681 pmu->active_events--;
682 hwc->idx = -1;
683 }
684
ddr_perf_pmu_enable(struct pmu * pmu)685 static void ddr_perf_pmu_enable(struct pmu *pmu)
686 {
687 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
688
689 ddr_perf_counter_global_config(ddr_pmu, true);
690 }
691
ddr_perf_pmu_disable(struct pmu * pmu)692 static void ddr_perf_pmu_disable(struct pmu *pmu)
693 {
694 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
695
696 ddr_perf_counter_global_config(ddr_pmu, false);
697 }
698
ddr_perf_init(struct ddr_pmu * pmu,void __iomem * base,struct device * dev)699 static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
700 struct device *dev)
701 {
702 *pmu = (struct ddr_pmu) {
703 .pmu = (struct pmu) {
704 .module = THIS_MODULE,
705 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
706 .task_ctx_nr = perf_invalid_context,
707 .attr_groups = attr_groups,
708 .event_init = ddr_perf_event_init,
709 .add = ddr_perf_event_add,
710 .del = ddr_perf_event_del,
711 .start = ddr_perf_event_start,
712 .stop = ddr_perf_event_stop,
713 .read = ddr_perf_event_update,
714 .pmu_enable = ddr_perf_pmu_enable,
715 .pmu_disable = ddr_perf_pmu_disable,
716 },
717 .base = base,
718 .dev = dev,
719 };
720 }
721
ddr_perf_irq_handler(int irq,void * p)722 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
723 {
724 struct ddr_pmu *pmu = (struct ddr_pmu *)p;
725 struct perf_event *event;
726 int i;
727
728 /*
729 * Counters can generate an interrupt on an overflow when msb of a
730 * counter changes from 0 to 1. For the interrupt to be signalled,
731 * below condition mush be satisfied:
732 * PMGC0[PMIE] = 1, PMGC0[FCECE] = 1, PMLCAn[CE] = 1
733 * When an interrupt is signalled, PMGC0[FAC] is set by hardware and
734 * all of the registers are frozen.
735 * Software can clear the interrupt condition by resetting the performance
736 * monitor and clearing the most significant bit of the counter that
737 * generate the overflow.
738 */
739 for (i = 0; i < NUM_COUNTERS; i++) {
740 if (!pmu->events[i])
741 continue;
742
743 event = pmu->events[i];
744
745 ddr_perf_event_update(event);
746 }
747
748 ddr_perf_counter_global_config(pmu, true);
749
750 return IRQ_HANDLED;
751 }
752
ddr_perf_offline_cpu(unsigned int cpu,struct hlist_node * node)753 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
754 {
755 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
756 int target;
757
758 if (cpu != pmu->cpu)
759 return 0;
760
761 target = cpumask_any_but(cpu_online_mask, cpu);
762 if (target >= nr_cpu_ids)
763 return 0;
764
765 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
766 pmu->cpu = target;
767
768 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
769
770 return 0;
771 }
772
ddr_perf_probe(struct platform_device * pdev)773 static int ddr_perf_probe(struct platform_device *pdev)
774 {
775 struct ddr_pmu *pmu;
776 void __iomem *base;
777 int ret, irq;
778 char *name;
779
780 base = devm_platform_ioremap_resource(pdev, 0);
781 if (IS_ERR(base))
782 return PTR_ERR(base);
783
784 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
785 if (!pmu)
786 return -ENOMEM;
787
788 ddr_perf_init(pmu, base, &pdev->dev);
789
790 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
791
792 platform_set_drvdata(pdev, pmu);
793
794 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL);
795 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id);
796 if (!name) {
797 ret = -ENOMEM;
798 goto format_string_err;
799 }
800
801 pmu->cpu = raw_smp_processor_id();
802 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DDR_CPUHP_CB_NAME,
803 NULL, ddr_perf_offline_cpu);
804 if (ret < 0) {
805 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n");
806 goto cpuhp_state_err;
807 }
808 pmu->cpuhp_state = ret;
809
810 /* Register the pmu instance for cpu hotplug */
811 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
812 if (ret) {
813 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
814 goto cpuhp_instance_err;
815 }
816
817 /* Request irq */
818 irq = platform_get_irq(pdev, 0);
819 if (irq < 0) {
820 ret = irq;
821 goto ddr_perf_err;
822 }
823
824 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler,
825 IRQF_NOBALANCING | IRQF_NO_THREAD,
826 DDR_CPUHP_CB_NAME, pmu);
827 if (ret < 0) {
828 dev_err(&pdev->dev, "Request irq failed: %d", ret);
829 goto ddr_perf_err;
830 }
831
832 pmu->irq = irq;
833 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
834 if (ret) {
835 dev_err(pmu->dev, "Failed to set interrupt affinity\n");
836 goto ddr_perf_err;
837 }
838
839 ret = perf_pmu_register(&pmu->pmu, name, -1);
840 if (ret)
841 goto ddr_perf_err;
842
843 return 0;
844
845 ddr_perf_err:
846 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
847 cpuhp_instance_err:
848 cpuhp_remove_multi_state(pmu->cpuhp_state);
849 cpuhp_state_err:
850 format_string_err:
851 ida_free(&ddr_ida, pmu->id);
852 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret);
853 return ret;
854 }
855
ddr_perf_remove(struct platform_device * pdev)856 static void ddr_perf_remove(struct platform_device *pdev)
857 {
858 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
859
860 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
861 cpuhp_remove_multi_state(pmu->cpuhp_state);
862
863 perf_pmu_unregister(&pmu->pmu);
864
865 ida_free(&ddr_ida, pmu->id);
866 }
867
868 static struct platform_driver imx_ddr_pmu_driver = {
869 .driver = {
870 .name = "imx9-ddr-pmu",
871 .of_match_table = imx_ddr_pmu_dt_ids,
872 .suppress_bind_attrs = true,
873 },
874 .probe = ddr_perf_probe,
875 .remove = ddr_perf_remove,
876 };
877 module_platform_driver(imx_ddr_pmu_driver);
878
879 MODULE_AUTHOR("Xu Yang <xu.yang_2@nxp.com>");
880 MODULE_LICENSE("GPL v2");
881 MODULE_DESCRIPTION("DDRC PerfMon for i.MX9 SoCs");
882