1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
4 *
5 * Copyright 2020 NXP
6 *
7 */
8
9 #include <linux/clk.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/kernel.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/stmmac.h>
22
23 #include "stmmac_platform.h"
24
25 #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)
26 #define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16)
27 #define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16)
28 #define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16)
29 #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19)
30 #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
31 #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
32
33 #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
34 #define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
35 #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
36 #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
37 #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
38 #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
39 #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0)
40 #define MX93_GPR_CLK_SEL_OFFSET (4)
41
42 #define DMA_BUS_MODE 0x00001000
43 #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
44 #define RMII_RESET_SPEED (0x3 << 14)
45 #define CTRL_SPEED_MASK GENMASK(15, 14)
46
47 struct imx_dwmac_ops {
48 u32 addr_width;
49 u32 flags;
50 bool mac_rgmii_txclk_auto_adj;
51
52 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
53 int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);
54 void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
55 };
56
57 struct imx_priv_data {
58 struct device *dev;
59 struct clk *clk_tx;
60 struct clk *clk_mem;
61 struct regmap *intf_regmap;
62 u32 intf_reg_off;
63 bool rmii_refclk_ext;
64 void __iomem *base_addr;
65
66 const struct imx_dwmac_ops *ops;
67 struct plat_stmmacenet_data *plat_dat;
68 };
69
imx8mp_set_intf_mode(struct plat_stmmacenet_data * plat_dat)70 static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
71 {
72 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
73 int val;
74
75 switch (plat_dat->mac_interface) {
76 case PHY_INTERFACE_MODE_MII:
77 val = GPR_ENET_QOS_INTF_SEL_MII;
78 break;
79 case PHY_INTERFACE_MODE_RMII:
80 val = GPR_ENET_QOS_INTF_SEL_RMII;
81 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
82 break;
83 case PHY_INTERFACE_MODE_RGMII:
84 case PHY_INTERFACE_MODE_RGMII_ID:
85 case PHY_INTERFACE_MODE_RGMII_RXID:
86 case PHY_INTERFACE_MODE_RGMII_TXID:
87 val = GPR_ENET_QOS_INTF_SEL_RGMII |
88 GPR_ENET_QOS_RGMII_EN;
89 break;
90 default:
91 pr_debug("imx dwmac doesn't support %d interface\n",
92 plat_dat->mac_interface);
93 return -EINVAL;
94 }
95
96 val |= GPR_ENET_QOS_CLK_GEN_EN;
97 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
98 GPR_ENET_QOS_INTF_MODE_MASK, val);
99 };
100
101 static int
imx8dxl_set_intf_mode(struct plat_stmmacenet_data * plat_dat)102 imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
103 {
104 int ret = 0;
105
106 /* TBD: depends on imx8dxl scu interfaces to be upstreamed */
107 return ret;
108 }
109
imx93_set_intf_mode(struct plat_stmmacenet_data * plat_dat)110 static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
111 {
112 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
113 int val, ret;
114
115 switch (plat_dat->mac_interface) {
116 case PHY_INTERFACE_MODE_MII:
117 val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
118 break;
119 case PHY_INTERFACE_MODE_RMII:
120 if (dwmac->rmii_refclk_ext) {
121 ret = regmap_clear_bits(dwmac->intf_regmap,
122 dwmac->intf_reg_off +
123 MX93_GPR_CLK_SEL_OFFSET,
124 MX93_GPR_ENET_QOS_CLK_SEL_MASK);
125 if (ret)
126 return ret;
127 }
128 val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
129 break;
130 case PHY_INTERFACE_MODE_RGMII:
131 case PHY_INTERFACE_MODE_RGMII_ID:
132 case PHY_INTERFACE_MODE_RGMII_RXID:
133 case PHY_INTERFACE_MODE_RGMII_TXID:
134 val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
135 break;
136 default:
137 dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
138 plat_dat->mac_interface);
139 return -EINVAL;
140 }
141
142 val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
143 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
144 MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
145 };
146
imx_dwmac_clks_config(void * priv,bool enabled)147 static int imx_dwmac_clks_config(void *priv, bool enabled)
148 {
149 struct imx_priv_data *dwmac = priv;
150 int ret = 0;
151
152 if (enabled) {
153 ret = clk_prepare_enable(dwmac->clk_mem);
154 if (ret) {
155 dev_err(dwmac->dev, "mem clock enable failed\n");
156 return ret;
157 }
158
159 ret = clk_prepare_enable(dwmac->clk_tx);
160 if (ret) {
161 dev_err(dwmac->dev, "tx clock enable failed\n");
162 clk_disable_unprepare(dwmac->clk_mem);
163 return ret;
164 }
165 } else {
166 clk_disable_unprepare(dwmac->clk_tx);
167 clk_disable_unprepare(dwmac->clk_mem);
168 }
169
170 return ret;
171 }
172
imx_dwmac_init(struct platform_device * pdev,void * priv)173 static int imx_dwmac_init(struct platform_device *pdev, void *priv)
174 {
175 struct plat_stmmacenet_data *plat_dat;
176 struct imx_priv_data *dwmac = priv;
177 int ret;
178
179 plat_dat = dwmac->plat_dat;
180
181 if (dwmac->ops->set_intf_mode) {
182 ret = dwmac->ops->set_intf_mode(plat_dat);
183 if (ret)
184 return ret;
185 }
186
187 return 0;
188 }
189
imx_dwmac_exit(struct platform_device * pdev,void * priv)190 static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
191 {
192 /* nothing to do now */
193 }
194
imx_dwmac_set_clk_tx_rate(void * bsp_priv,struct clk * clk_tx_i,phy_interface_t interface,int speed)195 static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
196 phy_interface_t interface, int speed)
197 {
198 struct imx_priv_data *dwmac = bsp_priv;
199
200 interface = dwmac->plat_dat->mac_interface;
201 if (interface == PHY_INTERFACE_MODE_RMII ||
202 interface == PHY_INTERFACE_MODE_MII)
203 return 0;
204
205 return stmmac_set_clk_tx_rate(bsp_priv, clk_tx_i, interface, speed);
206 }
207
imx_dwmac_fix_speed(void * priv,int speed,unsigned int mode)208 static void imx_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
209 {
210 struct plat_stmmacenet_data *plat_dat;
211 struct imx_priv_data *dwmac = priv;
212 long rate;
213 int err;
214
215 plat_dat = dwmac->plat_dat;
216
217 if (dwmac->ops->mac_rgmii_txclk_auto_adj ||
218 (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) ||
219 (plat_dat->mac_interface == PHY_INTERFACE_MODE_MII))
220 return;
221
222 rate = rgmii_clock(speed);
223 if (rate < 0) {
224 dev_err(dwmac->dev, "invalid speed %d\n", speed);
225 return;
226 }
227
228 err = clk_set_rate(dwmac->clk_tx, rate);
229 if (err < 0)
230 dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
231 }
232
imx93_dwmac_fix_speed(void * priv,int speed,unsigned int mode)233 static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
234 {
235 struct imx_priv_data *dwmac = priv;
236 unsigned int iface;
237 int ctrl, old_ctrl;
238
239 imx_dwmac_fix_speed(priv, speed, mode);
240
241 if (!dwmac || mode != MLO_AN_FIXED)
242 return;
243
244 if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
245 return;
246
247 iface &= MX93_GPR_ENET_QOS_INTF_MASK;
248 if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
249 return;
250
251 old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
252 ctrl = old_ctrl & ~CTRL_SPEED_MASK;
253 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
254 MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
255 writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
256
257 /* Ensure the settings for CTRL are applied. */
258 readl(dwmac->base_addr + MAC_CTRL_REG);
259
260 usleep_range(10, 20);
261 iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
262 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
263 MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
264
265 writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
266 }
267
imx_dwmac_mx93_reset(void * priv,void __iomem * ioaddr)268 static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
269 {
270 struct plat_stmmacenet_data *plat_dat = priv;
271 u32 value = readl(ioaddr + DMA_BUS_MODE);
272
273 /* DMA SW reset */
274 value |= DMA_BUS_MODE_SFT_RESET;
275 writel(value, ioaddr + DMA_BUS_MODE);
276
277 if (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) {
278 usleep_range(100, 200);
279 writel(RMII_RESET_SPEED, ioaddr + MAC_CTRL_REG);
280 }
281
282 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
283 !(value & DMA_BUS_MODE_SFT_RESET),
284 10000, 1000000);
285 }
286
287 static int
imx_dwmac_parse_dt(struct imx_priv_data * dwmac,struct device * dev)288 imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
289 {
290 struct device_node *np = dev->of_node;
291 int err = 0;
292
293 dwmac->rmii_refclk_ext = of_property_read_bool(np, "snps,rmii_refclk_ext");
294
295 dwmac->clk_tx = devm_clk_get(dev, "tx");
296 if (IS_ERR(dwmac->clk_tx)) {
297 dev_err(dev, "failed to get tx clock\n");
298 return PTR_ERR(dwmac->clk_tx);
299 }
300
301 dwmac->clk_mem = NULL;
302
303 if (of_machine_is_compatible("fsl,imx8dxl") ||
304 of_machine_is_compatible("fsl,imx93")) {
305 dwmac->clk_mem = devm_clk_get(dev, "mem");
306 if (IS_ERR(dwmac->clk_mem)) {
307 dev_err(dev, "failed to get mem clock\n");
308 return PTR_ERR(dwmac->clk_mem);
309 }
310 }
311
312 if (of_machine_is_compatible("fsl,imx8mp") ||
313 of_machine_is_compatible("fsl,imx93")) {
314 /* Binding doc describes the propety:
315 * is required by i.MX8MP, i.MX93.
316 * is optinoal for i.MX8DXL.
317 */
318 dwmac->intf_regmap =
319 syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,
320 &dwmac->intf_reg_off);
321 if (IS_ERR(dwmac->intf_regmap))
322 return PTR_ERR(dwmac->intf_regmap);
323 }
324
325 return err;
326 }
327
imx_dwmac_probe(struct platform_device * pdev)328 static int imx_dwmac_probe(struct platform_device *pdev)
329 {
330 struct plat_stmmacenet_data *plat_dat;
331 struct stmmac_resources stmmac_res;
332 struct imx_priv_data *dwmac;
333 const struct imx_dwmac_ops *data;
334 int ret;
335
336 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
337 if (ret)
338 return ret;
339
340 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
341 if (!dwmac)
342 return -ENOMEM;
343
344 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
345 if (IS_ERR(plat_dat))
346 return PTR_ERR(plat_dat);
347
348 data = of_device_get_match_data(&pdev->dev);
349 if (!data) {
350 dev_err(&pdev->dev, "failed to get match data\n");
351 return -EINVAL;
352 }
353
354 dwmac->ops = data;
355 dwmac->dev = &pdev->dev;
356
357 ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);
358 if (ret) {
359 dev_err(&pdev->dev, "failed to parse OF data\n");
360 return ret;
361 }
362
363 if (data->flags & STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY)
364 plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
365
366 /* Default TX Q0 to use TSO and rest TXQ for TBS */
367 for (int i = 1; i < plat_dat->tx_queues_to_use; i++)
368 plat_dat->tx_queues_cfg[i].tbs_en = 1;
369
370 plat_dat->host_dma_width = dwmac->ops->addr_width;
371 plat_dat->init = imx_dwmac_init;
372 plat_dat->exit = imx_dwmac_exit;
373 plat_dat->clks_config = imx_dwmac_clks_config;
374 plat_dat->bsp_priv = dwmac;
375 dwmac->plat_dat = plat_dat;
376 dwmac->base_addr = stmmac_res.addr;
377
378 ret = imx_dwmac_clks_config(dwmac, true);
379 if (ret)
380 return ret;
381
382 ret = imx_dwmac_init(pdev, dwmac);
383 if (ret)
384 goto err_dwmac_init;
385
386 if (dwmac->ops->fix_mac_speed) {
387 plat_dat->fix_mac_speed = dwmac->ops->fix_mac_speed;
388 } else if (!dwmac->ops->mac_rgmii_txclk_auto_adj) {
389 plat_dat->clk_tx_i = dwmac->clk_tx;
390 plat_dat->set_clk_tx_rate = imx_dwmac_set_clk_tx_rate;
391 }
392
393 dwmac->plat_dat->fix_soc_reset = dwmac->ops->fix_soc_reset;
394
395 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
396 if (ret)
397 goto err_drv_probe;
398
399 return 0;
400
401 err_drv_probe:
402 imx_dwmac_exit(pdev, plat_dat->bsp_priv);
403 err_dwmac_init:
404 imx_dwmac_clks_config(dwmac, false);
405 return ret;
406 }
407
408 static struct imx_dwmac_ops imx8mp_dwmac_data = {
409 .addr_width = 34,
410 .mac_rgmii_txclk_auto_adj = false,
411 .set_intf_mode = imx8mp_set_intf_mode,
412 .flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY,
413 };
414
415 static struct imx_dwmac_ops imx8dxl_dwmac_data = {
416 .addr_width = 32,
417 .mac_rgmii_txclk_auto_adj = true,
418 .set_intf_mode = imx8dxl_set_intf_mode,
419 };
420
421 static struct imx_dwmac_ops imx93_dwmac_data = {
422 .addr_width = 32,
423 .mac_rgmii_txclk_auto_adj = true,
424 .set_intf_mode = imx93_set_intf_mode,
425 .fix_soc_reset = imx_dwmac_mx93_reset,
426 .fix_mac_speed = imx93_dwmac_fix_speed,
427 };
428
429 static const struct of_device_id imx_dwmac_match[] = {
430 { .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
431 { .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
432 { .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },
433 { }
434 };
435 MODULE_DEVICE_TABLE(of, imx_dwmac_match);
436
437 static struct platform_driver imx_dwmac_driver = {
438 .probe = imx_dwmac_probe,
439 .remove = stmmac_pltfr_remove,
440 .driver = {
441 .name = "imx-dwmac",
442 .pm = &stmmac_pltfr_pm_ops,
443 .of_match_table = imx_dwmac_match,
444 },
445 };
446 module_platform_driver(imx_dwmac_driver);
447
448 MODULE_AUTHOR("NXP");
449 MODULE_DESCRIPTION("NXP imx8 DWMAC Specific Glue layer");
450 MODULE_LICENSE("GPL v2");
451