1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tegra210_ahub.h - TEGRA210 AHUB 4 * 5 * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved. 6 * 7 */ 8 9 #ifndef __TEGRA210_AHUB__H__ 10 #define __TEGRA210_AHUB__H__ 11 12 /* Tegra210 specific */ 13 #define TEGRA210_XBAR_PART1_RX 0x200 14 #define TEGRA210_XBAR_PART2_RX 0x400 15 #define TEGRA210_XBAR_RX_STRIDE 0x4 16 #define TEGRA210_XBAR_AUDIO_RX_COUNT 90 17 #define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff 18 #define TEGRA210_XBAR_REG_MASK_1 0x3f30031f 19 #define TEGRA210_XBAR_REG_MASK_2 0xff1cf313 20 #define TEGRA210_XBAR_REG_MASK_3 0x0 21 #define TEGRA210_XBAR_UPDATE_MAX_REG 3 22 /* Tegra186 specific */ 23 #define TEGRA186_XBAR_PART3_RX 0x600 24 #define TEGRA186_XBAR_AUDIO_RX_COUNT 115 25 #define TEGRA186_XBAR_REG_MASK_0 0xf3fffff 26 #define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f 27 #define TEGRA186_XBAR_REG_MASK_2 0xff3cf311 28 #define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff 29 #define TEGRA186_XBAR_UPDATE_MAX_REG 4 30 31 /* Tegra264 specific */ 32 #define TEGRA264_XBAR_PART1_RX 0x1000 33 #define TEGRA264_XBAR_PART2_RX 0x2000 34 #define TEGRA264_XBAR_PART3_RX 0x3000 35 #define TEGRA264_XBAR_PART4_RX 0x4000 36 #define TEGRA264_XBAR_PART0_ADX6_RX1 0x224 37 #define TEGRA264_XBAR_AUDIO_RX_COUNT ((TEGRA264_XBAR_PART0_ADX6_RX1 / 4) + 1) 38 #define TEGRA264_XBAR_REG_MASK_0 0xfffffff 39 #define TEGRA264_XBAR_REG_MASK_1 0x3f013f1f 40 #define TEGRA264_XBAR_REG_MASK_2 0xff3c0301 41 #define TEGRA264_XBAR_REG_MASK_3 0x3f00ffff 42 #define TEGRA264_XBAR_REG_MASK_4 0x7fff9f 43 #define TEGRA264_XBAR_UPDATE_MAX_REG 5 44 45 #define TEGRA264_AXBAR_ADMAIF_RX1 0x0 46 #define TEGRA264_AXBAR_SFC4_RX1 0x6c 47 #define TEGRA264_AXBAR_MIXER1_RX1 0x80 48 #define TEGRA264_AXBAR_MIXER1_RX10 0xa4 49 #define TEGRA264_AXBAR_DSPK1_RX1 0xc0 50 #define TEGRA264_AXBAR_OPE1_RX1 0x100 51 #define TEGRA264_AXBAR_MVC1_RX1 0x110 52 #define TEGRA264_AXBAR_MVC2_RX1 0x114 53 #define TEGRA264_AXBAR_AMX1_RX1 0x120 54 #define TEGRA264_AXBAR_AMX3_RX4 0x14c 55 #define TEGRA264_AXBAR_ADX1_RX1 0x160 56 #define TEGRA264_AXBAR_ASRC1_RX7 0x1a8 57 #define TEGRA264_AXBAR_ADMAIF_RX21 0x1d0 58 #define TEGRA264_AXBAR_ADX6_RX1 0x224 59 60 #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA264_XBAR_UPDATE_MAX_REG) 61 62 #define TEGRA264_MAX_REGISTER_ADDR (TEGRA264_XBAR_PART4_RX + \ 63 (TEGRA210_XBAR_RX_STRIDE * (TEGRA264_XBAR_AUDIO_RX_COUNT - 1))) 64 65 #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \ 66 (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1))) 67 68 #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \ 69 (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1))) 70 71 #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id)) 72 73 #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32) 74 75 #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \ 76 { \ 77 .reg = xreg, \ 78 .shift_l = shift, \ 79 .shift_r = shift, \ 80 .items = xmax, \ 81 .texts = xtexts, \ 82 .values = xvalues, \ 83 .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \ 84 } 85 86 #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \ 87 static struct soc_enum name = \ 88 SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \ 89 xtexts, xvalues) 90 91 #define MUX_ENUM_CTRL_DECL(ename, id) \ 92 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \ 93 tegra210_ahub_mux_texts, \ 94 tegra210_ahub_mux_values); \ 95 static const struct snd_kcontrol_new ename##_control = \ 96 SOC_DAPM_ENUM_EXT("Route", ename##_enum, \ 97 tegra_ahub_get_value_enum, \ 98 tegra_ahub_put_value_enum) 99 100 #define MUX_ENUM_CTRL_DECL_186(ename, id) \ 101 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \ 102 tegra186_ahub_mux_texts, \ 103 tegra186_ahub_mux_values); \ 104 static const struct snd_kcontrol_new ename##_control = \ 105 SOC_DAPM_ENUM_EXT("Route", ename##_enum, \ 106 tegra_ahub_get_value_enum, \ 107 tegra_ahub_put_value_enum) 108 109 #define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id) 110 111 #define MUX_ENUM_CTRL_DECL_264(ename, id) \ 112 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \ 113 tegra264_ahub_mux_texts, \ 114 tegra264_ahub_mux_values); \ 115 static const struct snd_kcontrol_new ename##_control = \ 116 SOC_DAPM_ENUM_EXT("Route", ename##_enum, \ 117 tegra_ahub_get_value_enum, \ 118 tegra_ahub_put_value_enum) 119 120 #define WIDGETS(sname, ename) \ 121 SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ 122 SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \ 123 SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \ 124 &ename##_control) 125 126 #define TX_WIDGETS(sname) \ 127 SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ 128 SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0) 129 130 #define DAI(sname) \ 131 { \ 132 .name = "XBAR-" #sname, \ 133 .playback = { \ 134 .stream_name = #sname " XBAR-Playback", \ 135 .channels_min = 1, \ 136 .channels_max = 32, \ 137 .rates = SNDRV_PCM_RATE_8000_192000, \ 138 .formats = SNDRV_PCM_FMTBIT_S8 | \ 139 SNDRV_PCM_FMTBIT_S16_LE | \ 140 SNDRV_PCM_FMTBIT_S24_LE | \ 141 SNDRV_PCM_FMTBIT_S32_LE, \ 142 }, \ 143 .capture = { \ 144 .stream_name = #sname " XBAR-Capture", \ 145 .channels_min = 1, \ 146 .channels_max = 32, \ 147 .rates = SNDRV_PCM_RATE_8000_192000, \ 148 .formats = SNDRV_PCM_FMTBIT_S8 | \ 149 SNDRV_PCM_FMTBIT_S16_LE | \ 150 SNDRV_PCM_FMTBIT_S24_LE | \ 151 SNDRV_PCM_FMTBIT_S32_LE, \ 152 }, \ 153 } 154 155 struct tegra_ahub_soc_data { 156 const struct regmap_config *regmap_config; 157 const struct snd_soc_component_driver *cmpnt_drv; 158 struct snd_soc_dai_driver *dai_drv; 159 unsigned int mask[TEGRA_XBAR_UPDATE_MAX_REG]; 160 unsigned int reg_count; 161 unsigned int num_dais; 162 unsigned int xbar_part_size; 163 }; 164 165 struct tegra_ahub { 166 const struct tegra_ahub_soc_data *soc_data; 167 struct regmap *regmap; 168 struct clk *clk; 169 }; 170 171 #endif 172