1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * mtu3.h - MediaTek USB3 DRD header
4 *
5 * Copyright (C) 2016 MediaTek Inc.
6 *
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10 #ifndef __MTU3_H__
11 #define __MTU3_H__
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/dmapool.h>
16 #include <linux/extcon.h>
17 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/of.h>
20 #include <linux/phy/phy.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/usb.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/role.h>
27
28 struct mtu3;
29 struct mtu3_ep;
30 struct mtu3_request;
31
32 #include "mtu3_hw_regs.h"
33 #include "mtu3_qmu.h"
34
35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
38
39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
42
43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
45
46 #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
47 #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
48 #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
49
50 #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
51 #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
52 #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
53
54 #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
55 #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
56
57 #define MTU3_DRIVER_NAME "mtu3"
58 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
59
60 #define MTU3_EP_ENABLED BIT(0)
61 #define MTU3_EP_STALL BIT(1)
62 #define MTU3_EP_WEDGE BIT(2)
63 #define MTU3_EP_BUSY BIT(3)
64
65 #define MTU3_U3_IP_SLOT_DEFAULT 2
66 #define MTU3_U2_IP_SLOT_DEFAULT 1
67
68 /*
69 * IP TRUNK version
70 * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
71 * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
72 * but not backward compatible
73 * 2. QMU extend buffer length supported
74 */
75 #define MTU3_TRUNK_VERS_1003 0x1003
76
77 /*
78 * Normally the device works on HS or SS, to simplify fifo management,
79 * divide fifo into some 512B parts, use bitmap to manage it; And
80 * 128 bits size of bitmap is large enough, that means it can manage
81 * up to 64KB fifo size.
82 * NOTE: MTU3_EP_FIFO_UNIT should be power of two
83 */
84 #define MTU3_EP_FIFO_UNIT (1 << 9)
85 #define MTU3_FIFO_BIT_SIZE 128
86 #define MTU3_U2_IP_EP0_FIFO_SIZE 64
87
88 /*
89 * Maximum size of ep0 response buffer for ch9 requests,
90 * the SET_SEL request uses 6 so far, and GET_STATUS is 2
91 */
92 #define EP0_RESPONSE_BUF 6
93
94 #define BULK_CLKS_CNT 6
95
96 /* device operated link and speed got from DEVICE_CONF register */
97 enum mtu3_speed {
98 MTU3_SPEED_INACTIVE = 0,
99 MTU3_SPEED_FULL = 1,
100 MTU3_SPEED_HIGH = 3,
101 MTU3_SPEED_SUPER = 4,
102 MTU3_SPEED_SUPER_PLUS = 5,
103 };
104
105 /**
106 * enum mtu3_g_ep0_state - endpoint 0 states
107 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
108 * without data stage.
109 * @MU3D_EP0_STATE_TX: IN data stage
110 * @MU3D_EP0_STATE_RX: OUT data stage
111 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
112 * waits for its completion interrupt
113 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
114 * after receives a SETUP.
115 */
116 enum mtu3_g_ep0_state {
117 MU3D_EP0_STATE_SETUP = 1,
118 MU3D_EP0_STATE_TX,
119 MU3D_EP0_STATE_RX,
120 MU3D_EP0_STATE_TX_END,
121 MU3D_EP0_STATE_STALL,
122 };
123
124 /**
125 * enum mtu3_dr_force_mode - indicates host/OTG operating mode
126 * @MTU3_DR_FORCE_NONE: automatically switch host and peripheral mode
127 * by IDPIN signal.
128 * @MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
129 * IDPIN signal.
130 * @MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
131 */
132 enum mtu3_dr_force_mode {
133 MTU3_DR_FORCE_NONE = 0,
134 MTU3_DR_FORCE_HOST,
135 MTU3_DR_FORCE_DEVICE,
136 };
137
138 /**
139 * struct mtu3_fifo_info - HW FIFO description and management data
140 * @base: the base address of fifo
141 * @limit: the bitmap size in bits
142 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
143 */
144 struct mtu3_fifo_info {
145 u32 base;
146 u32 limit;
147 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
148 };
149
150 /**
151 * struct qmu_gpd - General Purpose Descriptor (GPD):
152 * The format of TX GPD is a little different from RX one.
153 * And the size of GPD is 16 bytes.
154 *
155 * @dw0_info:
156 * bit0: Hardware Own (HWO)
157 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
158 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
159 * bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29]
160 * bit7: Interrupt On Completion (IOC)
161 * bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY),
162 * the buffer length of the data to receive
163 * bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY),
164 * lower 4 bits are extension bits of @buffer,
165 * upper 4 bits are extension bits of @next_gpd
166 * @next_gpd: Physical address of the next GPD
167 * @buffer: Physical address of the data buffer
168 * @dw3_info:
169 * bit[15:0]: ([EL] bit[19:0]) data buffer length,
170 * (TX): the buffer length of the data to transmit
171 * (RX): The total length of data received
172 * bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY),
173 * lower 4 bits are extension bits of @buffer,
174 * upper 4 bits are extension bits of @next_gpd
175 * bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY)
176 */
177 struct qmu_gpd {
178 __le32 dw0_info;
179 __le32 next_gpd;
180 __le32 buffer;
181 __le32 dw3_info;
182 } __packed;
183
184 /**
185 * struct mtu3_gpd_ring - GPD ring descriptor
186 * @dma: physical base address of GPD segment
187 * @start: virtual base address of GPD segment
188 * @end: the last GPD element
189 * @enqueue: the first empty GPD to use
190 * @dequeue: the first completed GPD serviced by ISR
191 *
192 * NOTE: the size of GPD ring should be >= 2
193 */
194 struct mtu3_gpd_ring {
195 dma_addr_t dma;
196 struct qmu_gpd *start;
197 struct qmu_gpd *end;
198 struct qmu_gpd *enqueue;
199 struct qmu_gpd *dequeue;
200 };
201
202 /**
203 * struct otg_switch_mtk - OTG/dual-role switch management
204 * @vbus: vbus 5V used by host mode
205 * @edev: external connector used to detect vbus and iddig changes
206 * @id_nb : notifier for iddig(idpin) detection
207 * @dr_work : work for drd mode switch, used to avoid sleep in atomic context
208 * @desired_role : role desired to switch
209 * @default_role : default mode while usb role is USB_ROLE_NONE
210 * @role_sw : use USB Role Switch to support dual-role switch, can't use
211 * extcon at the same time, and extcon is deprecated.
212 * @role_sw_used : true when the USB Role Switch is used.
213 * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
214 * @manual_drd_enabled: it's true when supports dual-role device by debugfs
215 * to switch host/device modes depending on user input.
216 */
217 struct otg_switch_mtk {
218 struct regulator *vbus;
219 struct extcon_dev *edev;
220 struct notifier_block id_nb;
221 struct work_struct dr_work;
222 enum usb_role desired_role;
223 enum usb_role default_role;
224 struct usb_role_switch *role_sw;
225 bool role_sw_used;
226 bool is_u3_drd;
227 bool manual_drd_enabled;
228 };
229
230 /**
231 * struct ssusb_mtk - SuperSpeed USB descriptor (MTK)
232 * @mac_base: register base address of device MAC, exclude xHCI's
233 * @ippc_base: register base address of IP Power and Clock interface (IPPC)
234 * @vusb33: usb3.3V shared by device/host IP
235 * @dr_mode: works in which mode:
236 * host only, device only or dual-role mode
237 * @u2_ports: number of usb2.0 host ports
238 * @u3_ports: number of usb3.0 host ports
239 * @u2p_dis_msk: mask of disabling usb2 ports, e.g. bit0==1 to
240 * disable u2port0, bit1==1 to disable u2port1,... etc,
241 * but when use dual-role mode, can't disable u2port0
242 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
243 * disable u3port0, bit1==1 to disable u3port1,... etc
244 * @dbgfs_root: only used when supports manual dual-role switch via debugfs
245 * @uwk_en: it's true when supports remote wakeup in host mode
246 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM
247 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk
248 * @uwk_vers: the version of the wakeup glue layer
249 */
250 struct ssusb_mtk {
251 struct device *dev;
252 struct mtu3 *u3d;
253 void __iomem *mac_base;
254 void __iomem *ippc_base;
255 struct phy **phys;
256 int num_phys;
257 int wakeup_irq;
258 /* common power & clock */
259 struct regulator *vusb33;
260 struct clk_bulk_data clks[BULK_CLKS_CNT];
261 /* otg */
262 struct otg_switch_mtk otg_switch;
263 enum usb_dr_mode dr_mode;
264 bool is_host;
265 int u2_ports;
266 int u3_ports;
267 int u2p_dis_msk;
268 int u3p_dis_msk;
269 struct dentry *dbgfs_root;
270 /* usb wakeup for host mode */
271 bool uwk_en;
272 struct regmap *uwk;
273 u32 uwk_reg_base;
274 u32 uwk_vers;
275 };
276
277 /**
278 * struct mtu3_ep - common mtu3 endpoint description
279 * @fifo_size: it is (@slot + 1) * @fifo_seg_size
280 * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
281 */
282 struct mtu3_ep {
283 struct usb_ep ep;
284 char name[12];
285 struct mtu3 *mtu;
286 u8 epnum;
287 u8 type;
288 u8 is_in;
289 u16 maxp;
290 int slot;
291 u32 fifo_size;
292 u32 fifo_addr;
293 u32 fifo_seg_size;
294 struct mtu3_fifo_info *fifo;
295
296 struct list_head req_list;
297 struct mtu3_gpd_ring gpd_ring;
298 const struct usb_ss_ep_comp_descriptor *comp_desc;
299 const struct usb_endpoint_descriptor *desc;
300
301 int flags;
302 };
303
304 struct mtu3_request {
305 struct usb_request request;
306 struct list_head list;
307 struct mtu3_ep *mep;
308 struct mtu3 *mtu;
309 struct qmu_gpd *gpd;
310 int epnum;
311 };
312
dev_to_ssusb(struct device * dev)313 static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev)
314 {
315 return dev_get_drvdata(dev);
316 }
317
318 /**
319 * struct mtu3 - device driver instance data.
320 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
321 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP
322 * @may_wakeup: means device's remote wakeup is enabled
323 * @is_self_powered: is reported in device status and the config descriptor
324 * @delayed_status: true when function drivers ask for delayed status
325 * @gen2cp: compatible with USB3 Gen2 IP
326 * @ep0_req: dummy request used while handling standard USB requests
327 * for GET_STATUS and SET_SEL
328 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
329 * @u3_capable: is capable of supporting USB3
330 */
331 struct mtu3 {
332 spinlock_t lock;
333 struct ssusb_mtk *ssusb;
334 struct device *dev;
335 void __iomem *mac_base;
336 void __iomem *ippc_base;
337 int irq;
338
339 struct mtu3_fifo_info tx_fifo;
340 struct mtu3_fifo_info rx_fifo;
341
342 struct mtu3_ep *ep_array;
343 struct mtu3_ep *in_eps;
344 struct mtu3_ep *out_eps;
345 struct mtu3_ep *ep0;
346 int num_eps;
347 int slot;
348 int active_ep;
349
350 struct dma_pool *qmu_gpd_pool;
351 enum mtu3_g_ep0_state ep0_state;
352 struct usb_gadget g; /* the gadget */
353 struct usb_gadget_driver *gadget_driver;
354 struct mtu3_request ep0_req;
355 u8 setup_buf[EP0_RESPONSE_BUF];
356 enum usb_device_speed max_speed;
357 enum usb_device_speed speed;
358
359 unsigned is_active:1;
360 unsigned may_wakeup:1;
361 unsigned is_self_powered:1;
362 unsigned test_mode:1;
363 unsigned softconnect:1;
364 unsigned u1_enable:1;
365 unsigned u2_enable:1;
366 unsigned u3_capable:1;
367 unsigned delayed_status:1;
368 unsigned gen2cp:1;
369 unsigned connected:1;
370 unsigned async_callbacks:1;
371 unsigned separate_fifo:1;
372
373 u8 address;
374 u8 test_mode_nr;
375 u32 hw_version;
376 };
377
gadget_to_mtu3(struct usb_gadget * g)378 static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
379 {
380 return container_of(g, struct mtu3, g);
381 }
382
to_mtu3_request(struct usb_request * req)383 static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
384 {
385 return req ? container_of(req, struct mtu3_request, request) : NULL;
386 }
387
to_mtu3_ep(struct usb_ep * ep)388 static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
389 {
390 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
391 }
392
next_request(struct mtu3_ep * mep)393 static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
394 {
395 return list_first_entry_or_null(&mep->req_list, struct mtu3_request,
396 list);
397 }
398
mtu3_writel(void __iomem * base,u32 offset,u32 data)399 static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
400 {
401 writel(data, base + offset);
402 }
403
mtu3_readl(void __iomem * base,u32 offset)404 static inline u32 mtu3_readl(void __iomem *base, u32 offset)
405 {
406 return readl(base + offset);
407 }
408
mtu3_setbits(void __iomem * base,u32 offset,u32 bits)409 static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
410 {
411 void __iomem *addr = base + offset;
412 u32 tmp = readl(addr);
413
414 writel((tmp | (bits)), addr);
415 }
416
mtu3_clrbits(void __iomem * base,u32 offset,u32 bits)417 static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
418 {
419 void __iomem *addr = base + offset;
420 u32 tmp = readl(addr);
421
422 writel((tmp & ~(bits)), addr);
423 }
424
425 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
426 struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
427 void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
428 void mtu3_req_complete(struct mtu3_ep *mep,
429 struct usb_request *req, int status);
430
431 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
432 int interval, int burst, int mult);
433 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
434 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
435 void mtu3_start(struct mtu3 *mtu);
436 void mtu3_stop(struct mtu3 *mtu);
437 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
438
439 int mtu3_gadget_setup(struct mtu3 *mtu);
440 void mtu3_gadget_cleanup(struct mtu3 *mtu);
441 void mtu3_gadget_reset(struct mtu3 *mtu);
442 void mtu3_gadget_suspend(struct mtu3 *mtu);
443 void mtu3_gadget_resume(struct mtu3 *mtu);
444 void mtu3_gadget_disconnect(struct mtu3 *mtu);
445
446 irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
447 extern const struct usb_ep_ops mtu3_ep0_ops;
448
449 #endif
450