1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2022 MediaTek Inc. */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/pinctrl/consumer.h>
8 #include <linux/of.h>
9 #include <linux/of_reserved_mem.h>
10 #include <linux/iopoll.h>
11 #include <linux/reset.h>
12 #include <linux/of_net.h>
13 #include <linux/clk.h>
14
15 #include "mt7915.h"
16
17 #define MT7981_CON_INFRA_VERSION 0x02090000
18 #define MT7986_CON_INFRA_VERSION 0x02070000
19
20 /* INFRACFG */
21 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0
22 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4
23
24 #define MT_INFRACFG_RX_EN_MASK BIT(16)
25 #define MT_INFRACFG_TX_RDY_MASK BIT(4)
26 #define MT_INFRACFG_TX_EN_MASK BIT(0)
27
28 /* TOP POS */
29 #define MT_TOP_POS_FAST_CTRL 0x114
30 #define MT_TOP_POS_FAST_EN_MASK BIT(3)
31
32 #define MT_TOP_POS_SKU 0x21c
33 #define MT_TOP_POS_SKU_MASK GENMASK(31, 28)
34 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2)
35
36 enum {
37 ADIE_SB,
38 ADIE_DBDC
39 };
40
41 static int
mt76_wmac_spi_read(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * val)42 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val)
43 {
44 int ret;
45 u32 cur;
46
47 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
48 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
49 dev, MT_TOP_SPI_BUSY_CR(adie));
50 if (ret)
51 return ret;
52
53 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
54 MT_TOP_SPI_READ_ADDR_FORMAT | addr);
55 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0);
56
57 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
58 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
59 dev, MT_TOP_SPI_BUSY_CR(adie));
60 if (ret)
61 return ret;
62
63 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie));
64
65 return 0;
66 }
67
68 static int
mt76_wmac_spi_write(struct mt7915_dev * dev,u8 adie,u32 addr,u32 val)69 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val)
70 {
71 int ret;
72 u32 cur;
73
74 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
75 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
76 dev, MT_TOP_SPI_BUSY_CR(adie));
77 if (ret)
78 return ret;
79
80 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
81 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr);
82 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val);
83
84 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
85 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
86 dev, MT_TOP_SPI_BUSY_CR(adie));
87 }
88
89 static int
mt76_wmac_spi_rmw(struct mt7915_dev * dev,u8 adie,u32 addr,u32 mask,u32 val)90 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie,
91 u32 addr, u32 mask, u32 val)
92 {
93 u32 cur, ret;
94
95 ret = mt76_wmac_spi_read(dev, adie, addr, &cur);
96 if (ret)
97 return ret;
98
99 cur &= ~mask;
100 cur |= val;
101
102 return mt76_wmac_spi_write(dev, adie, addr, cur);
103 }
104
105 static int
mt7986_wmac_adie_efuse_read(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * data)106 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie,
107 u32 addr, u32 *data)
108 {
109 int ret, temp;
110 u32 val, mask;
111
112 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG,
113 MT_ADIE_EFUSE_CTRL_MASK);
114 if (ret)
115 return ret;
116
117 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0);
118 if (ret)
119 return ret;
120
121 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK |
122 MT_ADIE_EFUSE_KICK_MASK);
123 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) |
124 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) |
125 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1);
126 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val);
127 if (ret)
128 return ret;
129
130 ret = read_poll_timeout(mt76_wmac_spi_read, temp,
131 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val),
132 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
133 dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
134 if (ret)
135 return ret;
136
137 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
138 if (ret)
139 return ret;
140
141 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1)
142 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0,
143 data);
144
145 return ret;
146 }
147
mt76_wmac_spi_lock(struct mt7915_dev * dev)148 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev)
149 {
150 u32 cur;
151
152 read_poll_timeout(mt76_rr, cur,
153 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur),
154 1000, 1000 * MSEC_PER_SEC, false, dev,
155 MT_SEMA_RFSPI_STATUS);
156 }
157
mt76_wmac_spi_unlock(struct mt7915_dev * dev)158 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev)
159 {
160 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1);
161 }
162
mt76_wmac_rmw(void __iomem * base,u32 offset,u32 mask,u32 val)163 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
164 {
165 val |= readl(base + offset) & ~mask;
166 writel(val, base + offset);
167
168 return val;
169 }
170
mt798x_wmac_check_adie_type(struct mt7915_dev * dev)171 static u8 mt798x_wmac_check_adie_type(struct mt7915_dev *dev)
172 {
173 u32 val;
174
175 /* Only DBDC A-die is used with MT7981 */
176 if (is_mt7981(&dev->mt76))
177 return ADIE_DBDC;
178
179 val = readl(dev->sku + MT_TOP_POS_SKU);
180
181 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val);
182 }
183
mt7986_wmac_consys_reset(struct mt7915_dev * dev,bool enable)184 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable)
185 {
186 if (!enable)
187 return reset_control_assert(dev->rstc);
188
189 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL,
190 MT_TOP_POS_FAST_EN_MASK,
191 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1));
192
193 return reset_control_deassert(dev->rstc);
194 }
195
mt7986_wmac_gpio_setup(struct mt7915_dev * dev)196 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev)
197 {
198 struct pinctrl_state *state;
199 struct pinctrl *pinctrl;
200 int ret;
201 u8 type;
202
203 type = mt798x_wmac_check_adie_type(dev);
204 pinctrl = devm_pinctrl_get(dev->mt76.dev);
205 if (IS_ERR(pinctrl))
206 return PTR_ERR(pinctrl);
207
208 switch (type) {
209 case ADIE_SB:
210 state = pinctrl_lookup_state(pinctrl, "default");
211 if (IS_ERR_OR_NULL(state))
212 return -EINVAL;
213 break;
214 case ADIE_DBDC:
215 state = pinctrl_lookup_state(pinctrl, "dbdc");
216 if (IS_ERR_OR_NULL(state))
217 return -EINVAL;
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 ret = pinctrl_select_state(pinctrl, state);
224 if (ret)
225 return ret;
226
227 usleep_range(500, 1000);
228
229 return 0;
230 }
231
mt7986_wmac_consys_lockup(struct mt7915_dev * dev,bool enable)232 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable)
233 {
234 int ret;
235 u32 cur;
236
237 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
238 MT_INFRACFG_RX_EN_MASK,
239 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
240 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK),
241 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
242 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
243 if (ret)
244 return ret;
245
246 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
247 MT_INFRACFG_TX_EN_MASK,
248 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
249 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK),
250 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
251 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
252 if (ret)
253 return ret;
254
255 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
256 MT_INFRACFG_RX_EN_MASK,
257 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
258 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
259 MT_INFRACFG_TX_EN_MASK,
260 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
261
262 return 0;
263 }
264
mt798x_wmac_coninfra_check(struct mt7915_dev * dev)265 static int mt798x_wmac_coninfra_check(struct mt7915_dev *dev)
266 {
267 u32 cur;
268 u32 con_infra_version;
269
270 if (is_mt7981(&dev->mt76)) {
271 con_infra_version = MT7981_CON_INFRA_VERSION;
272 } else if (is_mt7986(&dev->mt76)) {
273 con_infra_version = MT7986_CON_INFRA_VERSION;
274 } else {
275 WARN_ON(1);
276 return -EINVAL;
277 }
278
279 return read_poll_timeout(mt76_rr, cur, (cur == con_infra_version),
280 USEC_PER_MSEC, 50 * USEC_PER_MSEC,
281 false, dev, MT_CONN_INFRA_BASE);
282 }
283
mt798x_wmac_coninfra_setup(struct mt7915_dev * dev)284 static int mt798x_wmac_coninfra_setup(struct mt7915_dev *dev)
285 {
286 struct device *pdev = dev->mt76.dev;
287 struct reserved_mem *rmem;
288 struct device_node *np;
289 u32 val;
290
291 np = of_parse_phandle(pdev->of_node, "memory-region", 0);
292 if (!np)
293 return -EINVAL;
294
295 rmem = of_reserved_mem_lookup(np);
296 of_node_put(np);
297 if (!rmem)
298 return -EINVAL;
299
300 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK;
301
302 if (is_mt7986(&dev->mt76)) {
303 /* Set conninfra subsys PLL check */
304 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
305 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
306 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
307 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
308 }
309
310 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE,
311 MT_TOP_MCU_EMI_BASE_MASK, val);
312
313 if (is_mt7981(&dev->mt76)) {
314 mt76_rmw_field(dev, MT_TOP_WF_AP_PERI_BASE,
315 MT_TOP_WF_AP_PERI_BASE_MASK, 0x300d0000 >> 16);
316
317 mt76_rmw_field(dev, MT_TOP_EFUSE_BASE,
318 MT_TOP_EFUSE_BASE_MASK, 0x11f20000 >> 16);
319 }
320
321 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base);
322 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size);
323
324 mt76_rr(dev, MT_CONN_INFRA_EFUSE);
325
326 /* Set conninfra sysram */
327 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0);
328 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1);
329
330 return 0;
331 }
332
mt798x_wmac_sku_setup(struct mt7915_dev * dev,u32 * adie_type)333 static int mt798x_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type)
334 {
335 int ret;
336 u32 adie_main = 0, adie_ext = 0;
337
338 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
339 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1);
340
341 if (is_mt7986(&dev->mt76)) {
342 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
343 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1);
344 }
345
346 mt76_wmac_spi_lock(dev);
347
348 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main);
349 if (ret)
350 goto out;
351
352 if (is_mt7986(&dev->mt76)) {
353 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext);
354 if (ret)
355 goto out;
356 }
357
358 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) |
359 (MT_ADIE_CHIP_ID_MASK & adie_ext);
360
361 out:
362 mt76_wmac_spi_unlock(dev);
363
364 return 0;
365 }
366
mt7986_adie_idx(u8 adie,u32 adie_type)367 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type)
368 {
369 if (adie == 0)
370 return u32_get_bits(adie_type, MT_ADIE_IDX0);
371 else
372 return u32_get_bits(adie_type, MT_ADIE_IDX1);
373 }
374
is_7975(struct mt7915_dev * dev,u8 adie,u32 adie_type)375 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type)
376 {
377 return mt7986_adie_idx(adie, adie_type) == 0x7975;
378 }
379
is_7976(struct mt7915_dev * dev,u8 adie,u32 adie_type)380 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type)
381 {
382 return mt7986_adie_idx(adie, adie_type) == 0x7976;
383 }
384
mt7986_wmac_adie_thermal_cal(struct mt7915_dev * dev,u8 adie)385 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie)
386 {
387 int ret;
388 u32 data, val;
389
390 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG,
391 &data);
392 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
393 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data);
394 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG,
395 MT_ADIE_VRPI_SEL_CR_MASK,
396 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val));
397 if (ret)
398 return ret;
399
400 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data);
401 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
402 MT_ADIE_PGA_GAIN_MASK,
403 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val));
404 if (ret)
405 return ret;
406 }
407
408 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP,
409 &data);
410 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
411 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data);
412
413 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
414 MT_ADIE_LDO_CTRL_MASK,
415 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val));
416 }
417
418 return 0;
419 }
420
421 static int
mt7986_read_efuse_xo_trim_7976(struct mt7915_dev * dev,u8 adie,bool is_40m,int * result)422 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie,
423 bool is_40m, int *result)
424 {
425 int ret;
426 u32 data, addr;
427
428 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC;
429 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
430 if (ret)
431 return ret;
432
433 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) {
434 *result = 64;
435 } else {
436 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data);
437 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC :
438 MT_ADIE_XTAL_TRIM1_80M_OSC;
439 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
440 if (ret)
441 return ret;
442
443 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) &&
444 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data))
445 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
446 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data))
447 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
448
449 *result = max(0, min(127, *result));
450 }
451
452 return 0;
453 }
454
mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev * dev,u8 adie)455 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie)
456 {
457 int ret, trim_80m, trim_40m;
458 u32 data, val, mode;
459
460 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW,
461 &data);
462 if (ret || !FIELD_GET(BIT(1), data))
463 return 0;
464
465 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m);
466 if (ret)
467 return ret;
468
469 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m);
470 if (ret)
471 return ret;
472
473 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val);
474 if (ret)
475 return ret;
476
477 mode = FIELD_PREP(GENMASK(6, 4), val);
478 if (!mode || mode == 0x2) {
479 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
480 GENMASK(31, 24),
481 FIELD_PREP(GENMASK(31, 24), trim_80m));
482 if (ret)
483 return ret;
484
485 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
486 GENMASK(31, 24),
487 FIELD_PREP(GENMASK(31, 24), trim_80m));
488 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) {
489 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
490 GENMASK(23, 16),
491 FIELD_PREP(GENMASK(23, 16), trim_40m));
492 if (ret)
493 return ret;
494
495 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
496 GENMASK(23, 16),
497 FIELD_PREP(GENMASK(23, 16), trim_40m));
498 }
499
500 return ret;
501 }
502
mt798x_wmac_adie_patch_7976(struct mt7915_dev * dev,u8 adie)503 static int mt798x_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie)
504 {
505 u32 id, version, rg_xo_01, rg_xo_03;
506 int ret;
507
508 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id);
509 if (ret)
510 return ret;
511
512 version = FIELD_GET(MT_ADIE_VERSION_MASK, id);
513
514 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00);
515 if (ret)
516 return ret;
517
518 if (version == 0x8a00 || version == 0x8a10 ||
519 version == 0x8b00 || version == 0x8c10) {
520 rg_xo_01 = 0x1d59080f;
521 rg_xo_03 = 0x34c00fe0;
522 } else {
523 if (is_mt7981(&dev->mt76)) {
524 rg_xo_01 = 0x1959c80f;
525 } else if (is_mt7986(&dev->mt76)) {
526 rg_xo_01 = 0x1959f80f;
527 } else {
528 WARN_ON(1);
529 return -EINVAL;
530 }
531 rg_xo_03 = 0x34d00fe0;
532 }
533
534 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01);
535 if (ret)
536 return ret;
537
538 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03);
539 }
540
541 static int
mt7986_read_efuse_xo_trim_7975(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * result)542 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie,
543 u32 addr, u32 *result)
544 {
545 int ret;
546 u32 data;
547
548 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
549 if (ret)
550 return ret;
551
552 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) {
553 if ((data & MT_ADIE_XTAL_DECREASE_MASK))
554 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK);
555 else
556 *result += (data & MT_ADIE_EFUSE_TRIM_MASK);
557
558 *result = (*result & MT_ADIE_TRIM_MASK);
559 }
560
561 return 0;
562 }
563
mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev * dev,u8 adie)564 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie)
565 {
566 int ret;
567 u32 data, result = 0, value;
568
569 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN,
570 &data);
571 if (ret || !(data & BIT(1)))
572 return 0;
573
574 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL,
575 &data);
576 if (ret)
577 return ret;
578
579 if (data & MT_ADIE_XO_TRIM_EN_MASK)
580 result = (data & MT_ADIE_TRIM_MASK);
581
582 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2,
583 &result);
584 if (ret)
585 return ret;
586
587 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3,
588 &result);
589 if (ret)
590 return ret;
591
592 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4,
593 &result);
594 if (ret)
595 return ret;
596
597 /* Update trim value to C1 and C2*/
598 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) |
599 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result);
600 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2,
601 MT_ADIE_7975_XO_CTRL2_MASK, value);
602 if (ret)
603 return ret;
604
605 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value);
606 if (ret)
607 return ret;
608
609 if (value & MT_ADIE_7975_XTAL_EN_MASK) {
610 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2,
611 MT_ADIE_7975_XO_2_FIX_EN, 0x0);
612 if (ret)
613 return ret;
614 }
615
616 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6,
617 MT_ADIE_7975_XO_CTRL6_MASK, 0x1);
618 }
619
mt7986_wmac_adie_patch_7975(struct mt7915_dev * dev,u8 adie)620 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie)
621 {
622 int ret;
623
624 /* disable CAL LDO and fine tune RFDIG LDO */
625 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002);
626 if (ret)
627 return ret;
628
629 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002);
630 if (ret)
631 return ret;
632
633 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002);
634 if (ret)
635 return ret;
636
637 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002);
638 if (ret)
639 return ret;
640
641 /* set CKA driving and filter */
642 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa);
643 if (ret)
644 return ret;
645
646 /* set CKB LDO to 1.4V */
647 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a);
648 if (ret)
649 return ret;
650
651 /* turn on SX0 LTBUF */
652 if (is_mt7981(&dev->mt76)) {
653 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000007);
654 } else if (is_mt7986(&dev->mt76)) {
655 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002);
656 } else {
657 WARN_ON(1);
658 return -EINVAL;
659 }
660
661 if (ret)
662 return ret;
663
664 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */
665 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0);
666 if (ret)
667 return ret;
668
669 /* BT mode/WF normal mode 00000005 */
670 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005);
671 if (ret)
672 return ret;
673
674 /* BG thermal sensor offset update */
675 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088);
676 if (ret)
677 return ret;
678
679 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088);
680 if (ret)
681 return ret;
682
683 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088);
684 if (ret)
685 return ret;
686
687 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088);
688 if (ret)
689 return ret;
690
691 /* set WCON VDD IPTAT to "0000" */
692 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000);
693 if (ret)
694 return ret;
695
696 /* change back LTBUF SX3 drving to default value */
697 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa);
698 if (ret)
699 return ret;
700
701 /* SM input cap off */
702 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000);
703 if (ret)
704 return ret;
705
706 /* set CKB driving and filter */
707 if (is_mt7986(&dev->mt76))
708 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072);
709
710 return ret;
711 }
712
mt7986_wmac_adie_cfg(struct mt7915_dev * dev,u8 adie,u32 adie_type)713 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type)
714 {
715 int ret;
716
717 mt76_wmac_spi_lock(dev);
718 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0);
719 if (ret)
720 goto out;
721
722 if (is_7975(dev, adie, adie_type)) {
723 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK,
724 BIT(1), 0x1);
725 if (ret)
726 goto out;
727
728 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
729 if (ret)
730 goto out;
731
732 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie);
733 if (ret)
734 goto out;
735
736 ret = mt7986_wmac_adie_patch_7975(dev, adie);
737 } else if (is_7976(dev, adie, adie_type)) {
738 if (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC) {
739 ret = mt76_wmac_spi_write(dev, adie,
740 MT_ADIE_WRI_CK_SEL, 0x1c);
741 if (ret)
742 goto out;
743 }
744
745 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
746 if (ret)
747 goto out;
748
749 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie);
750 if (ret)
751 goto out;
752
753 ret = mt798x_wmac_adie_patch_7976(dev, adie);
754 }
755 out:
756 mt76_wmac_spi_unlock(dev);
757
758 return ret;
759 }
760
761 static int
mt7986_wmac_afe_cal(struct mt7915_dev * dev,u8 adie,bool dbdc,u32 adie_type)762 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type)
763 {
764 int ret;
765 u8 idx;
766 u32 txcal;
767
768 mt76_wmac_spi_lock(dev);
769 if (is_7975(dev, adie, adie_type))
770 ret = mt76_wmac_spi_write(dev, adie,
771 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
772 0x80000000);
773 else
774 ret = mt76_wmac_spi_write(dev, adie,
775 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
776 0x88888005);
777 if (ret)
778 goto out;
779
780 idx = dbdc ? ADIE_DBDC : adie;
781
782 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
783 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1);
784 usleep_range(60, 100);
785
786 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
787 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0);
788
789 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
790 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1);
791 usleep_range(30, 100);
792
793 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
794 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1);
795 usleep_range(60, 100);
796
797 txcal = (MT_AFE_RG_WBG_EN_TXCAL_BT |
798 MT_AFE_RG_WBG_EN_TXCAL_WF0 |
799 MT_AFE_RG_WBG_EN_TXCAL_WF1 |
800 MT_AFE_RG_WBG_EN_TXCAL_WF2 |
801 MT_AFE_RG_WBG_EN_TXCAL_WF3);
802 if (is_mt7981(&dev->mt76))
803 txcal |= MT_AFE_RG_WBG_EN_TXCAL_WF4;
804
805 mt76_set(dev, MT_AFE_DIG_EN_01(idx), txcal);
806 usleep_range(800, 1000);
807
808 mt76_clear(dev, MT_AFE_DIG_EN_01(idx), txcal);
809 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx),
810 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0);
811
812 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW,
813 0x5);
814
815 out:
816 mt76_wmac_spi_unlock(dev);
817
818 return ret;
819 }
820
mt7986_wmac_subsys_pll_initial(struct mt7915_dev * dev,u8 band)821 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band)
822 {
823 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band),
824 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL);
825
826 mt76_rmw(dev, MT_AFE_DIG_EN_02(band),
827 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL);
828
829 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band),
830 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL);
831 }
832
mt7986_wmac_subsys_setting(struct mt7915_dev * dev)833 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev)
834 {
835 /* Subsys pll init */
836 mt7986_wmac_subsys_pll_initial(dev, 0);
837 mt7986_wmac_subsys_pll_initial(dev, 1);
838
839 /* Set legacy OSC control stable time*/
840 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN,
841 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0);
842 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL,
843 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706);
844
845 /* prevent subsys from power on/of in a short time interval */
846 mt76_rmw(dev, MT_TOP_WFSYS_PWR,
847 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK,
848 MT_TOP_PWR_KEY);
849 }
850
mt7986_wmac_bus_timeout(struct mt7915_dev * dev)851 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev)
852 {
853 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
854 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2);
855
856 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
857 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
858
859 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
860 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc);
861
862 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
863 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
864
865 return mt798x_wmac_coninfra_check(dev);
866 }
867
mt7986_wmac_clock_enable(struct mt7915_dev * dev,u32 adie_type)868 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type)
869 {
870 u32 cur;
871
872 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
873 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
874
875 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
876 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
877
878 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
879 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
880
881 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
882 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
883
884 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
885 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8);
886
887 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
888 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
889
890 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
891 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0);
892
893 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL,
894 MT_CONN_INFRA_HW_CTRL_MASK, 0x1);
895
896 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
897 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1);
898
899 usleep_range(900, 1000);
900
901 mt76_wmac_spi_lock(dev);
902 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) {
903 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),
904 MT_SLP_CTRL_EN_MASK, 0x1);
905
906 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
907 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
908 dev, MT_ADIE_SLP_CTRL_CK0(0));
909 }
910 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) {
911 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1),
912 MT_SLP_CTRL_EN_MASK, 0x1);
913
914 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
915 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
916 dev, MT_ADIE_SLP_CTRL_CK0(0));
917 }
918 mt76_wmac_spi_unlock(dev);
919
920 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
921 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0);
922 usleep_range(900, 1000);
923 }
924
mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev * dev,bool enable)925 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable)
926 {
927 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP,
928 MT_TOP_WFSYS_WAKEUP_MASK, enable);
929
930 usleep_range(900, 1000);
931
932 if (!enable)
933 return 0;
934
935 return mt798x_wmac_coninfra_check(dev);
936 }
937
mt7986_wmac_wm_enable(struct mt7915_dev * dev,bool enable)938 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable)
939 {
940 u32 cur;
941
942 if (is_mt7986(&dev->mt76))
943 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, 0);
944
945 mt76_rmw_field(dev, MT7986_TOP_WM_RESET,
946 MT7986_TOP_WM_RESET_MASK, enable);
947 if (!enable)
948 return 0;
949
950 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e),
951 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false,
952 dev, MT_TOP_CFG_ON_ROM_IDX);
953 }
954
mt7986_wmac_wfsys_poweron(struct mt7915_dev * dev,bool enable)955 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable)
956 {
957 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK;
958 u32 cur;
959
960 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask,
961 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable));
962
963 return read_poll_timeout(mt76_rr, cur,
964 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable),
965 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
966 dev, MT_TOP_WFSYS_RESET_STATUS);
967 }
968
mt7986_wmac_wfsys_setting(struct mt7915_dev * dev)969 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev)
970 {
971 int ret;
972 u32 cur;
973
974 /* Turn off wfsys2conn bus sleep protect */
975 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT,
976 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0);
977
978 ret = mt7986_wmac_wfsys_poweron(dev, true);
979 if (ret)
980 return ret;
981
982 /* Check bus sleep protect */
983
984 ret = read_poll_timeout(mt76_rr, cur,
985 !(cur & MT_CONN_INFRA_CONN_WF_MASK),
986 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
987 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
988 if (ret)
989 return ret;
990
991 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK),
992 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
993 dev, MT_SLP_STATUS);
994 if (ret)
995 return ret;
996
997 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000),
998 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
999 dev, MT_TOP_CFG_IP_VERSION_ADDR);
1000 }
1001
mt7986_wmac_wfsys_set_timeout(struct mt7915_dev * dev)1002 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev)
1003 {
1004 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK |
1005 MT_MCU_BUS_TIMEOUT_CG_EN_MASK |
1006 MT_MCU_BUS_TIMEOUT_EN_MASK;
1007 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) |
1008 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) |
1009 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1);
1010
1011 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val);
1012
1013 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000);
1014
1015 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK |
1016 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK |
1017 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK;
1018 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) |
1019 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) |
1020 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1);
1021
1022 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val);
1023 }
1024
mt7986_wmac_sku_update(struct mt7915_dev * dev,u32 adie_type)1025 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type)
1026 {
1027 u32 val;
1028
1029 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type))
1030 val = 0xf;
1031 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type))
1032 val = 0xd;
1033 else if (is_7976(dev, 0, adie_type))
1034 val = 0x7;
1035 else if (is_7975(dev, 1, adie_type))
1036 val = 0x8;
1037 else if (is_7976(dev, 1, adie_type))
1038 val = 0xa;
1039 else
1040 return -EINVAL;
1041
1042 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK,
1043 FIELD_PREP(MT_TOP_POS_SKU_MASK, val));
1044
1045 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val);
1046
1047 return 0;
1048 }
1049
1050 static int
mt7986_wmac_adie_setup(struct mt7915_dev * dev,u8 adie,u32 adie_type)1051 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type)
1052 {
1053 int ret;
1054
1055 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type)))
1056 return 0;
1057
1058 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type);
1059 if (ret)
1060 return ret;
1061
1062 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type);
1063 if (ret)
1064 return ret;
1065
1066 if (!adie && (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC))
1067 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type);
1068
1069 return ret;
1070 }
1071
mt7986_wmac_subsys_powerup(struct mt7915_dev * dev,u32 adie_type)1072 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type)
1073 {
1074 int ret;
1075
1076 mt7986_wmac_subsys_setting(dev);
1077
1078 ret = mt7986_wmac_bus_timeout(dev);
1079 if (ret)
1080 return ret;
1081
1082 mt7986_wmac_clock_enable(dev, adie_type);
1083
1084 return 0;
1085 }
1086
mt7986_wmac_wfsys_powerup(struct mt7915_dev * dev)1087 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev)
1088 {
1089 int ret;
1090
1091 ret = mt7986_wmac_wm_enable(dev, false);
1092 if (ret)
1093 return ret;
1094
1095 ret = mt7986_wmac_wfsys_setting(dev);
1096 if (ret)
1097 return ret;
1098
1099 mt7986_wmac_wfsys_set_timeout(dev);
1100
1101 return mt7986_wmac_wm_enable(dev, true);
1102 }
1103
mt7986_wmac_enable(struct mt7915_dev * dev)1104 int mt7986_wmac_enable(struct mt7915_dev *dev)
1105 {
1106 int ret;
1107 u32 adie_type;
1108
1109 ret = mt7986_wmac_consys_reset(dev, true);
1110 if (ret)
1111 return ret;
1112
1113 ret = mt7986_wmac_gpio_setup(dev);
1114 if (ret)
1115 return ret;
1116
1117 ret = mt7986_wmac_consys_lockup(dev, false);
1118 if (ret)
1119 return ret;
1120
1121 ret = mt798x_wmac_coninfra_check(dev);
1122 if (ret)
1123 return ret;
1124
1125 ret = mt798x_wmac_coninfra_setup(dev);
1126 if (ret)
1127 return ret;
1128
1129 ret = mt798x_wmac_sku_setup(dev, &adie_type);
1130 if (ret)
1131 return ret;
1132
1133 ret = mt7986_wmac_adie_setup(dev, 0, adie_type);
1134 if (ret)
1135 return ret;
1136
1137 /* mt7981 doesn't support a second a-die */
1138 if (is_mt7986(&dev->mt76)) {
1139 ret = mt7986_wmac_adie_setup(dev, 1, adie_type);
1140 if (ret)
1141 return ret;
1142 }
1143
1144 ret = mt7986_wmac_subsys_powerup(dev, adie_type);
1145 if (ret)
1146 return ret;
1147
1148 ret = mt7986_wmac_top_wfsys_wakeup(dev, true);
1149 if (ret)
1150 return ret;
1151
1152 ret = mt7986_wmac_wfsys_powerup(dev);
1153 if (ret)
1154 return ret;
1155
1156 return mt7986_wmac_sku_update(dev, adie_type);
1157 }
1158
mt7986_wmac_disable(struct mt7915_dev * dev)1159 void mt7986_wmac_disable(struct mt7915_dev *dev)
1160 {
1161 u32 cur;
1162
1163 mt7986_wmac_top_wfsys_wakeup(dev, true);
1164
1165 /* Turn on wfsys2conn bus sleep protect */
1166 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT,
1167 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1);
1168
1169 /* Check wfsys2conn bus sleep protect */
1170 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN),
1171 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
1172 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
1173
1174 mt7986_wmac_wfsys_poweron(dev, false);
1175
1176 /* Turn back wpll setting */
1177 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);
1178 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);
1179
1180 /* Reset EMI */
1181 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1182 MT_CONN_INFRA_EMI_REQ_MASK, 0x1);
1183 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1184 MT_CONN_INFRA_EMI_REQ_MASK, 0x0);
1185 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1186 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1);
1187 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1188 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0);
1189
1190 mt7986_wmac_top_wfsys_wakeup(dev, false);
1191 mt7986_wmac_consys_lockup(dev, true);
1192 mt7986_wmac_consys_reset(dev, false);
1193 }
1194
mt798x_wmac_init(struct mt7915_dev * dev)1195 static int mt798x_wmac_init(struct mt7915_dev *dev)
1196 {
1197 struct device *pdev = dev->mt76.dev;
1198 struct platform_device *pfdev = to_platform_device(pdev);
1199 struct clk *mcu_clk, *ap_conn_clk;
1200
1201 mcu_clk = devm_clk_get(pdev, "mcu");
1202 if (IS_ERR(mcu_clk))
1203 dev_err(pdev, "mcu clock not found\n");
1204 else if (clk_prepare_enable(mcu_clk))
1205 dev_err(pdev, "mcu clock configuration failed\n");
1206
1207 ap_conn_clk = devm_clk_get(pdev, "ap2conn");
1208 if (IS_ERR(ap_conn_clk))
1209 dev_err(pdev, "ap2conn clock not found\n");
1210 else if (clk_prepare_enable(ap_conn_clk))
1211 dev_err(pdev, "ap2conn clock configuration failed\n");
1212
1213 dev->dcm = devm_platform_ioremap_resource(pfdev, 1);
1214 if (IS_ERR(dev->dcm))
1215 return PTR_ERR(dev->dcm);
1216
1217 dev->sku = devm_platform_ioremap_resource(pfdev, 2);
1218 if (IS_ERR(dev->sku))
1219 return PTR_ERR(dev->sku);
1220
1221 dev->rstc = devm_reset_control_get(pdev, "consys");
1222 return PTR_ERR_OR_ZERO(dev->rstc);
1223 }
1224
mt798x_wmac_probe(struct platform_device * pdev)1225 static int mt798x_wmac_probe(struct platform_device *pdev)
1226 {
1227 void __iomem *mem_base;
1228 struct mt7915_dev *dev;
1229 struct mt76_dev *mdev;
1230 int irq, ret;
1231 u32 chip_id;
1232
1233 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1234
1235 mem_base = devm_platform_ioremap_resource(pdev, 0);
1236 if (IS_ERR(mem_base)) {
1237 dev_err(&pdev->dev, "Failed to get memory resource\n");
1238 return PTR_ERR(mem_base);
1239 }
1240
1241 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id);
1242 if (IS_ERR(dev))
1243 return PTR_ERR(dev);
1244
1245 mdev = &dev->mt76;
1246 ret = mt7915_mmio_wed_init(dev, pdev, false, &irq);
1247 if (ret < 0)
1248 goto free_device;
1249
1250 if (!ret) {
1251 irq = platform_get_irq(pdev, 0);
1252 if (irq < 0) {
1253 ret = irq;
1254 goto free_device;
1255 }
1256 }
1257
1258 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
1259 IRQF_SHARED, KBUILD_MODNAME, dev);
1260 if (ret)
1261 goto free_device;
1262
1263 ret = mt798x_wmac_init(dev);
1264 if (ret)
1265 goto free_irq;
1266
1267 mt7915_wfsys_reset(dev);
1268
1269 ret = mt7915_register_device(dev);
1270 if (ret)
1271 goto free_irq;
1272
1273 return 0;
1274
1275 free_irq:
1276 devm_free_irq(mdev->dev, irq, dev);
1277 free_device:
1278 if (mtk_wed_device_active(&mdev->mmio.wed))
1279 mtk_wed_device_detach(&mdev->mmio.wed);
1280 mt76_free_device(mdev);
1281
1282 return ret;
1283 }
1284
mt798x_wmac_remove(struct platform_device * pdev)1285 static void mt798x_wmac_remove(struct platform_device *pdev)
1286 {
1287 struct mt7915_dev *dev = platform_get_drvdata(pdev);
1288
1289 mt7915_unregister_device(dev);
1290 }
1291
1292 static const struct of_device_id mt798x_wmac_of_match[] = {
1293 { .compatible = "mediatek,mt7981-wmac", .data = (u32 *)0x7981 },
1294 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 },
1295 {},
1296 };
1297
1298 MODULE_DEVICE_TABLE(of, mt798x_wmac_of_match);
1299
1300 struct platform_driver mt798x_wmac_driver = {
1301 .driver = {
1302 .name = "mt798x-wmac",
1303 .of_match_table = mt798x_wmac_of_match,
1304 },
1305 .probe = mt798x_wmac_probe,
1306 .remove_new = mt798x_wmac_remove,
1307 };
1308
1309 MODULE_FIRMWARE(MT7986_FIRMWARE_WA);
1310 MODULE_FIRMWARE(MT7986_FIRMWARE_WM);
1311 MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975);
1312 MODULE_FIRMWARE(MT7986_ROM_PATCH);
1313 MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975);
1314
1315 MODULE_FIRMWARE(MT7981_FIRMWARE_WA);
1316 MODULE_FIRMWARE(MT7981_FIRMWARE_WM);
1317 MODULE_FIRMWARE(MT7981_ROM_PATCH);
1318