1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* Copyright (C) 2023 MediaTek Inc. */ 3 4 #ifndef __MT7925_REGS_H 5 #define __MT7925_REGS_H 6 7 #include "../mt792x_regs.h" 8 9 #define MT_MDP_BASE 0x820cc800 10 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 11 12 #define MT_MDP_DCR0 MT_MDP(0x000) 13 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 14 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) 15 16 #define MT_MDP_DCR1 MT_MDP(0x004) 17 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 18 19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8)) 20 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 21 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 22 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 23 24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8)) 25 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 26 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 27 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 28 #define MT_MDP_TO_HIF 0 29 #define MT_MDP_TO_WM 1 30 31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204) 32 #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c) 33 #define HOST_RX_DONE_INT_ENA4 BIT(12) 34 #define HOST_RX_DONE_INT_ENA5 BIT(13) 35 #define HOST_RX_DONE_INT_ENA6 BIT(14) 36 #define HOST_RX_DONE_INT_ENA7 BIT(15) 37 #define HOST_RX_DONE_INT_ENA8 BIT(16) 38 #define HOST_RX_DONE_INT_ENA9 BIT(17) 39 #define HOST_RX_DONE_INT_ENA10 BIT(18) 40 #define HOST_RX_DONE_INT_ENA11 BIT(19) 41 #define HOST_TX_DONE_INT_ENA15 BIT(25) 42 #define HOST_TX_DONE_INT_ENA16 BIT(26) 43 #define HOST_TX_DONE_INT_ENA17 BIT(27) 44 45 /* WFDMA interrupt */ 46 #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA1 47 48 #define MT7925_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 49 #define MT7925_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 50 #define MT7925_INT_RX_DONE_ALL (MT7925_INT_RX_DONE_DATA | \ 51 MT7925_INT_RX_DONE_WM | \ 52 MT_INT_RX_DONE_WM2) 53 54 #define MT7927_INT_RX_DONE_DATA MT7927_RX_DONE_INT_ENA4 55 #define MT7927_INT_RX_DONE_WM MT7927_RX_DONE_INT_ENA6 56 #define MT7927_INT_RX_DONE_WM2 MT7927_RX_DONE_INT_ENA7 57 #define MT7927_INT_RX_DONE_ALL (MT7927_INT_RX_DONE_DATA | \ 58 MT7927_INT_RX_DONE_WM | \ 59 MT7927_INT_RX_DONE_WM2) 60 61 #define MT7928_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA0 62 #define MT7928_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA3 63 #define MT7928_INT_RX_DONE_ALL (MT7928_INT_RX_DONE_DATA | \ 64 MT7928_INT_RX_DONE_WM | \ 65 MT_INT_RX_DONE_WM2) 66 67 #define MT_INT_TX_DONE_MCU_WM (HOST_TX_DONE_INT_ENA15 | \ 68 HOST_TX_DONE_INT_ENA17) 69 70 #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 71 #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 72 73 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ 74 MT_INT_TX_DONE_FWDL) 75 #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU | \ 76 MT_INT_TX_DONE_BAND0 | \ 77 GENMASK(18, 4)) 78 79 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500) 80 81 #define MT_INFRA_CFG_BASE 0xd1000 82 #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) 83 84 #define MT_HIF_REMAP_L1 0x155024 85 #define MT_HIF_REMAP_L1_MASK GENMASK(31, 16) 86 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 87 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 88 #define MT_HIF_REMAP_BASE_L1 0x130000 89 90 #define MT_HIF_REMAP_L2 0x0120 91 #define MT_HIF_REMAP_BASE_L2 0x18500000 92 93 #define MT_WFSYS_SW_RST_B 0x7c000140 94 95 #define MT7925_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370) 96 #define MT7928_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x400) 97 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) 98 99 #define MT7925_WTBL_UPDATE MT_WTBLON_TOP(0x380) 100 #define MT7928_WTBL_UPDATE MT_WTBLON_TOP(0x410) 101 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) 102 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) 103 104 #define MT7928_WTBL_ITCR MT_WTBLON_TOP(0x440) 105 #define MT7928_WTBL_ITDR0 MT_WTBLON_TOP(0x448) 106 #define MT7928_WTBL_ITDR1 MT_WTBLON_TOP(0x44c) 107 108 #define MT7925_PCIE_MAC_BASE 0x10000 109 #define MT7925_PCIE_MAC(ofs) (MT7925_PCIE_MAC_BASE + (ofs)) 110 #define MT7925_PCIE_MAC_INT_ENABLE MT7925_PCIE_MAC(0x188) 111 #define MT7925_PCIE_MAC_PM MT7925_PCIE_MAC(0x194) 112 113 #define MT7928_PCIE_MAC_BASE 0x74040000 114 #define MT7928_PCIE_MAC(ofs) (MT7928_PCIE_MAC_BASE + (ofs)) 115 #define MT7928_PCIE_MAC_INT_ENABLE MT7928_PCIE_MAC(0x188) 116 #define MT7928_PCIE_MAC_PM MT7928_PCIE_MAC(0x194) 117 118 #define MT_DMASHDL_LITE_BASE 0x20026200 119 #define MT_DMASHDL_LITE(ofs) (MT_DMASHDL_LITE_BASE + (ofs)) 120 #define MT_DMASHDL_LITE_MAIN_CONTROL MT_DMASHDL_LITE(0x004) 121 #define MT_DMASHDL_LITE_MAIN_CONTROL_SW_RST BIT(18) 122 #define MT_DMASHDL_LITE_PAGE_SIZE MT_DMASHDL_LITE(0x008) 123 #define MT_DMASHDL_LITE_PLE_PAGE_SIZE_MASK GENMASK(12, 0) 124 #define MT_DMASHDL_LITE_PSE_PAGE_SIZE_MASK GENMASK(28, 16) 125 #define MT_DMASHDL_LITE_PKT_MAX_SIZE MT_DMASHDL_LITE(0x00c) 126 #define MT_DMASHDL_LITE_PLE_PKT_MAX_SIZE_MASK GENMASK(12, 0) 127 #define MT_DMASHDL_LITE_PSE_PKT_MAX_SIZE_MASK GENMASK(28, 16) 128 #define MT_DMASHDL_LITE_GROUP_DISABLE0 MT_DMASHDL_LITE(0x010) 129 #define MT_DMASHDL_LITE_GROUP_DISABLE1 MT_DMASHDL_LITE(0x014) 130 #define MT_DMASHDL_LITE_GROUP_SN_CHK0 MT_DMASHDL_LITE(0x018) 131 #define MT_DMASHDL_LITE_GROUP_SN_CHK1 MT_DMASHDL_LITE(0x01c) 132 #define MT_DMASHDL_LITE_GROUP_UDF_CHK0 MT_DMASHDL_LITE(0x020) 133 #define MT_DMASHDL_LITE_GROUP_UDF_CHK1 MT_DMASHDL_LITE(0x024) 134 #define MT_DMASHDL_LITE_Q_MAPPING0 MT_DMASHDL_LITE(0x028) 135 #define MT_DMASHDL_LITE_GROUP0_QUOTA MT_DMASHDL_LITE(0x100) 136 #define MT_DMASHDL_LITE_GROUP_MIN_QUOTA_MASK GENMASK(12, 0) 137 #define MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK GENMASK(28, 16) 138 139 #endif 140