1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 // Copyright (c) 2017 Synopsys, Inc. and/or its affiliates. 3 // stmmac Support for 5.xx Ethernet QoS cores 4 5 #ifndef __DWMAC5_H__ 6 #define __DWMAC5_H__ 7 8 #define MAC_DPP_FSM_INT_STATUS 0x00000140 9 #define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144 10 #define MAC_FSM_CONTROL 0x00000148 11 #define PRTYEN BIT(1) 12 #define TMOUTEN BIT(0) 13 14 #define MAC_PPS_CONTROL 0x00000b70 15 #define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1) 16 #define PPS_MINIDX(x) ((x) * 8) 17 #define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x)) 18 #define MCGRENx(x) BIT(PPS_MAXIDX(x)) 19 #define TRGTMODSELx(x, val) \ 20 GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \ 21 ((val) << (PPS_MAXIDX(x) - 2)) 22 #define PPSCMDx(x, val) \ 23 GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \ 24 ((val) << PPS_MINIDX(x)) 25 #define PPSEN0 BIT(4) 26 #define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10)) 27 #define MAC_PPSx_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10)) 28 #define TRGTBUSY0 BIT(31) 29 #define TTSL0 GENMASK(30, 0) 30 #define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10)) 31 #define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10)) 32 33 #define MTL_RXP_CONTROL_STATUS 0x00000ca0 34 #define RXPI BIT(31) 35 #define NPE GENMASK(23, 16) 36 #define NVE GENMASK(7, 0) 37 #define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0 38 #define STARTBUSY BIT(31) 39 #define RXPEIEC GENMASK(22, 21) 40 #define RXPEIEE BIT(20) 41 #define WRRDN BIT(16) 42 #define ADDR GENMASK(15, 0) 43 #define MTL_RXP_IACC_DATA 0x00000cb4 44 #define MTL_ECC_CONTROL 0x00000cc0 45 #define MEEAO BIT(8) 46 #define TSOEE BIT(4) 47 #define MRXPEE BIT(3) 48 #define MESTEE BIT(2) 49 #define MRXEE BIT(1) 50 #define MTXEE BIT(0) 51 52 #define MTL_SAFETY_INT_STATUS 0x00000cc4 53 #define MCSIS BIT(31) 54 #define MEUIS BIT(1) 55 #define MECIS BIT(0) 56 #define MTL_ECC_INT_ENABLE 0x00000cc8 57 #define RPCEIE BIT(12) 58 #define ECEIE BIT(8) 59 #define RXCEIE BIT(4) 60 #define TXCEIE BIT(0) 61 #define MTL_ECC_INT_STATUS 0x00000ccc 62 #define MTL_DPP_CONTROL 0x00000ce0 63 #define EPSI BIT(2) 64 #define OPE BIT(1) 65 #define EDPP BIT(0) 66 67 #define DMA_SAFETY_INT_STATUS 0x00001080 68 #define MSUIS BIT(29) 69 #define MSCIS BIT(28) 70 #define DEUIS BIT(1) 71 #define DECIS BIT(0) 72 #define DMA_ECC_INT_ENABLE 0x00001084 73 #define TCEIE BIT(0) 74 #define DMA_ECC_INT_STATUS 0x00001088 75 76 /* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */ 77 #define GMAC_RXQ_CTRL4 0x00000094 78 #define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17) 79 #define GMAC_RXQCTRL_VFFQ_SHIFT 17 80 #define GMAC_RXQCTRL_VFFQE BIT(16) 81 82 #define GMAC_INT_FPE_EN BIT(17) 83 84 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp, 85 struct stmmac_safety_feature_cfg *safety_cfg); 86 int dwmac5_safety_feat_irq_status(struct net_device *ndev, 87 void __iomem *ioaddr, unsigned int asp, 88 struct stmmac_safety_stats *stats); 89 int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats, 90 int index, unsigned long *count, const char **desc); 91 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, 92 unsigned int count); 93 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, 94 struct stmmac_pps_cfg *cfg, bool enable, 95 u32 sub_second_inc, u32 systime_flags); 96 97 #endif /* __DWMAC5_H__ */ 98