1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */ 3 4 #ifndef __MTK_PPE_REGS_H 5 #define __MTK_PPE_REGS_H 6 7 #define MTK_PPE_GLO_CFG 0x200 8 #define MTK_PPE_GLO_CFG_EN BIT(0) 9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1) 10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2) 11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3) 12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4) 13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5) 14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6) 15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7) 16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8) 17 #define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9) 18 #define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10) 19 #define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11) 20 #define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12) 21 #define MTK_PPE_GLO_CFG_BUSY BIT(31) 22 23 #define MTK_PPE_FLOW_CFG 0x204 24 #define MTK_PPE_MD_TOAP_BYP_CRSN0 BIT(1) 25 #define MTK_PPE_MD_TOAP_BYP_CRSN1 BIT(2) 26 #define MTK_PPE_MD_TOAP_BYP_CRSN2 BIT(3) 27 #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6) 28 #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7) 29 #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8) 30 #define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9) 31 #define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10) 32 #define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12) 33 #define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13) 34 #define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14) 35 #define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15) 36 #define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16) 37 #define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17) 38 #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18) 39 #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19) 40 #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20) 41 42 #define MTK_PPE_IP_PROTO_CHK 0x208 43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0) 44 #define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16) 45 46 #define MTK_PPE_TB_CFG 0x21c 47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0) 48 #define MTK_PPE_TB_CFG_ENTRY_80B BIT(3) 49 #define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4) 50 #define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6) 51 #define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7) 52 #define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8) 53 #define MTK_PPE_TB_CFG_AGE_TCP BIT(9) 54 #define MTK_PPE_TB_CFG_AGE_UDP BIT(10) 55 #define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11) 56 #define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12) 57 #define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14) 58 #define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16) 59 #define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18) 60 #define MTK_PPE_TB_CFG_INFO_SEL BIT(20) 61 #define MTK_PPE_TB_TICK_SEL BIT(24) 62 63 #define MTK_PPE_BIND_LMT1 0x230 64 #define MTK_PPE_NTU_KEEPALIVE GENMASK(23, 16) 65 66 #define MTK_PPE_KEEPALIVE 0x234 67 68 enum { 69 MTK_PPE_SCAN_MODE_DISABLED, 70 MTK_PPE_SCAN_MODE_CHECK_AGE, 71 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE, 72 }; 73 74 enum { 75 MTK_PPE_KEEPALIVE_DISABLE, 76 MTK_PPE_KEEPALIVE_UNICAST_CPU, 77 MTK_PPE_KEEPALIVE_DUP_CPU = 3, 78 }; 79 80 enum { 81 MTK_PPE_SEARCH_MISS_ACTION_DROP, 82 MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2, 83 MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3, 84 }; 85 86 #define MTK_PPE_TB_BASE 0x220 87 88 #define MTK_PPE_TB_USED 0x224 89 #define MTK_PPE_TB_USED_NUM GENMASK(13, 0) 90 91 #define MTK_PPE_BIND_RATE 0x228 92 #define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0) 93 #define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16) 94 95 #define MTK_PPE_BIND_LIMIT0 0x22c 96 #define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0) 97 #define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16) 98 99 #define MTK_PPE_BIND_LIMIT1 0x230 100 #define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0) 101 #define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16) 102 103 #define MTK_PPE_KEEPALIVE 0x234 104 #define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0) 105 #define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16) 106 #define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24) 107 108 #define MTK_PPE_UNBIND_AGE 0x238 109 #define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16) 110 #define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0) 111 112 #define MTK_PPE_BIND_AGE0 0x23c 113 #define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16) 114 #define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0) 115 116 #define MTK_PPE_BIND_AGE1 0x240 117 #define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16) 118 #define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0) 119 120 #define MTK_PPE_HASH_SEED 0x244 121 122 #define MTK_PPE_DEFAULT_CPU_PORT 0x248 123 #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) 124 125 #define MTK_PPE_DEFAULT_CPU_PORT1 0x24c 126 127 #define MTK_PPE_MTU_DROP 0x308 128 129 #define MTK_PPE_VLAN_MTU0 0x30c 130 #define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0) 131 #define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16) 132 133 #define MTK_PPE_VLAN_MTU1 0x310 134 #define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0) 135 #define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16) 136 137 #define MTK_PPE_VPM_TPID 0x318 138 139 #define MTK_PPE_CACHE_CTL 0x320 140 #define MTK_PPE_CACHE_CTL_EN BIT(0) 141 #define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4) 142 #define MTK_PPE_CACHE_CTL_REQ BIT(8) 143 #define MTK_PPE_CACHE_CTL_CLEAR BIT(9) 144 #define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12) 145 146 #define MTK_PPE_MIB_CFG 0x334 147 #define MTK_PPE_MIB_CFG_EN BIT(0) 148 #define MTK_PPE_MIB_CFG_RD_CLR BIT(1) 149 150 #define MTK_PPE_MIB_TB_BASE 0x338 151 152 #define MTK_PPE_MIB_SER_CR 0x33C 153 #define MTK_PPE_MIB_SER_CR_ST BIT(16) 154 #define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0) 155 156 #define MTK_PPE_MIB_SER_R0 0x340 157 #define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0) 158 159 #define MTK_PPE_MIB_SER_R1 0x344 160 #define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16) 161 #define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0) 162 163 #define MTK_PPE_MIB_SER_R2 0x348 164 #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) 165 166 #define MTK_PPE_MIB_SER_R3 0x34c 167 168 #define MTK_PPE_MIB_CACHE_CTL 0x350 169 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) 170 #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) 171 172 #define MTK_PPE_SBW_CTRL 0x374 173 174 #endif 175