1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/iopoll.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15
16 #define MTK_MUTEX_MAX_HANDLES 10
17
18 #define MT2701_MUTEX0_MOD0 0x2c
19 #define MT2701_MUTEX0_SOF0 0x30
20 #define MT2701_MUTEX0_MOD1 0x34
21
22 #define MT8183_MUTEX0_MOD0 0x30
23 #define MT8183_MUTEX0_MOD1 0x34
24 #define MT8183_MUTEX0_SOF0 0x2c
25
26 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
27 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
28 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
29 /*
30 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
31 * are present, hence requiring multiple 32-bits registers.
32 *
33 * The mutex_table_mod fully represents that by defining the number of
34 * the mod sequentially, later used as a bit number, which can be more
35 * than 0..31.
36 *
37 * In order to retain compatibility with older SoCs, we perform R/W on
38 * the single 32 bits registers, but this requires us to translate the
39 * mutex ID bit accordingly.
40 */
41 #define DISP_REG_MUTEX_MOD(mutex, id, n) ({ \
42 const typeof(mutex) _mutex = (mutex); \
43 u32 _offset = (id) < 32 ? \
44 _mutex->data->mutex_mod_reg : \
45 _mutex->data->mutex_mod1_reg; \
46 _offset + 0x20 * (n); \
47 })
48 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
49
50 #define INT_MUTEX BIT(1)
51
52 #define MT8186_MUTEX_MOD_DISP_OVL0 0
53 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
54 #define MT8186_MUTEX_MOD_DISP_RDMA0 2
55 #define MT8186_MUTEX_MOD_DISP_COLOR0 4
56 #define MT8186_MUTEX_MOD_DISP_CCORR0 5
57 #define MT8186_MUTEX_MOD_DISP_AAL0 7
58 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8
59 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
60 #define MT8186_MUTEX_MOD_DISP_DITHER0 10
61 #define MT8186_MUTEX_MOD_DISP_RDMA1 17
62
63 #define MT8186_MUTEX_SOF_SINGLE_MODE 0
64 #define MT8186_MUTEX_SOF_DSI0 1
65 #define MT8186_MUTEX_SOF_DPI0 2
66 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
67 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
68
69 #define MT8167_MUTEX_MOD_DISP_PWM 1
70 #define MT8167_MUTEX_MOD_DISP_OVL0 6
71 #define MT8167_MUTEX_MOD_DISP_OVL1 7
72 #define MT8167_MUTEX_MOD_DISP_RDMA0 8
73 #define MT8167_MUTEX_MOD_DISP_RDMA1 9
74 #define MT8167_MUTEX_MOD_DISP_WDMA0 10
75 #define MT8167_MUTEX_MOD_DISP_CCORR 11
76 #define MT8167_MUTEX_MOD_DISP_COLOR 12
77 #define MT8167_MUTEX_MOD_DISP_AAL 13
78 #define MT8167_MUTEX_MOD_DISP_GAMMA 14
79 #define MT8167_MUTEX_MOD_DISP_DITHER 15
80 #define MT8167_MUTEX_MOD_DISP_UFOE 16
81
82 #define MT8192_MUTEX_MOD_DISP_OVL0 0
83 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
84 #define MT8192_MUTEX_MOD_DISP_RDMA0 2
85 #define MT8192_MUTEX_MOD_DISP_COLOR0 4
86 #define MT8192_MUTEX_MOD_DISP_CCORR0 5
87 #define MT8192_MUTEX_MOD_DISP_AAL0 6
88 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7
89 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
90 #define MT8192_MUTEX_MOD_DISP_DITHER0 9
91 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
92 #define MT8192_MUTEX_MOD_DISP_RDMA4 17
93
94 #define MT8183_MUTEX_MOD_DISP_RDMA0 0
95 #define MT8183_MUTEX_MOD_DISP_RDMA1 1
96 #define MT8183_MUTEX_MOD_DISP_OVL0 9
97 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
98 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
99 #define MT8183_MUTEX_MOD_DISP_WDMA0 12
100 #define MT8183_MUTEX_MOD_DISP_COLOR0 13
101 #define MT8183_MUTEX_MOD_DISP_CCORR0 14
102 #define MT8183_MUTEX_MOD_DISP_AAL0 15
103 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16
104 #define MT8183_MUTEX_MOD_DISP_DITHER0 17
105
106 #define MT8183_MUTEX_MOD_MDP_RDMA0 2
107 #define MT8183_MUTEX_MOD_MDP_RSZ0 4
108 #define MT8183_MUTEX_MOD_MDP_RSZ1 5
109 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6
110 #define MT8183_MUTEX_MOD_MDP_WROT0 7
111 #define MT8183_MUTEX_MOD_MDP_WDMA 8
112 #define MT8183_MUTEX_MOD_MDP_AAL0 23
113 #define MT8183_MUTEX_MOD_MDP_CCORR0 24
114
115 #define MT8186_MUTEX_MOD_MDP_RDMA0 0
116 #define MT8186_MUTEX_MOD_MDP_AAL0 2
117 #define MT8186_MUTEX_MOD_MDP_HDR0 4
118 #define MT8186_MUTEX_MOD_MDP_RSZ0 5
119 #define MT8186_MUTEX_MOD_MDP_RSZ1 6
120 #define MT8186_MUTEX_MOD_MDP_WROT0 7
121 #define MT8186_MUTEX_MOD_MDP_TDSHP0 9
122 #define MT8186_MUTEX_MOD_MDP_COLOR0 14
123
124 #define MT8173_MUTEX_MOD_DISP_OVL0 11
125 #define MT8173_MUTEX_MOD_DISP_OVL1 12
126 #define MT8173_MUTEX_MOD_DISP_RDMA0 13
127 #define MT8173_MUTEX_MOD_DISP_RDMA1 14
128 #define MT8173_MUTEX_MOD_DISP_RDMA2 15
129 #define MT8173_MUTEX_MOD_DISP_WDMA0 16
130 #define MT8173_MUTEX_MOD_DISP_WDMA1 17
131 #define MT8173_MUTEX_MOD_DISP_COLOR0 18
132 #define MT8173_MUTEX_MOD_DISP_COLOR1 19
133 #define MT8173_MUTEX_MOD_DISP_AAL 20
134 #define MT8173_MUTEX_MOD_DISP_GAMMA 21
135 #define MT8173_MUTEX_MOD_DISP_UFOE 22
136 #define MT8173_MUTEX_MOD_DISP_PWM0 23
137 #define MT8173_MUTEX_MOD_DISP_PWM1 24
138 #define MT8173_MUTEX_MOD_DISP_OD 25
139
140 #define MT8188_MUTEX_MOD_DISP_OVL0 0
141 #define MT8188_MUTEX_MOD_DISP_WDMA0 1
142 #define MT8188_MUTEX_MOD_DISP_RDMA0 2
143 #define MT8188_MUTEX_MOD_DISP_COLOR0 3
144 #define MT8188_MUTEX_MOD_DISP_CCORR0 4
145 #define MT8188_MUTEX_MOD_DISP_AAL0 5
146 #define MT8188_MUTEX_MOD_DISP_GAMMA0 6
147 #define MT8188_MUTEX_MOD_DISP_DITHER0 7
148 #define MT8188_MUTEX_MOD_DISP_DSI0 8
149 #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
150 #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20
151 #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21
152 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
153 #define MT8188_MUTEX_MOD2_DISP_PWM0 33
154
155 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0
156 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1
157 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2
158 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3
159 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4
160 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
161 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
162 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
163 #define MT8188_MUTEX_MOD_DISP1_PADDING0 8
164 #define MT8188_MUTEX_MOD_DISP1_PADDING1 9
165 #define MT8188_MUTEX_MOD_DISP1_PADDING2 10
166 #define MT8188_MUTEX_MOD_DISP1_PADDING3 11
167 #define MT8188_MUTEX_MOD_DISP1_PADDING4 12
168 #define MT8188_MUTEX_MOD_DISP1_PADDING5 13
169 #define MT8188_MUTEX_MOD_DISP1_PADDING6 14
170 #define MT8188_MUTEX_MOD_DISP1_PADDING7 15
171 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
172 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
173 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
174 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
175 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
176 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
177 #define MT8188_MUTEX_MOD_DISP1_DPI1 38
178 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
179
180 #define MT8195_MUTEX_MOD_DISP_OVL0 0
181 #define MT8195_MUTEX_MOD_DISP_WDMA0 1
182 #define MT8195_MUTEX_MOD_DISP_RDMA0 2
183 #define MT8195_MUTEX_MOD_DISP_COLOR0 3
184 #define MT8195_MUTEX_MOD_DISP_CCORR0 4
185 #define MT8195_MUTEX_MOD_DISP_AAL0 5
186 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6
187 #define MT8195_MUTEX_MOD_DISP_DITHER0 7
188 #define MT8195_MUTEX_MOD_DISP_DSI0 8
189 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
190 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
191 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
192 #define MT8195_MUTEX_MOD_DISP_PWM0 27
193
194 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
195 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
196 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
197 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
198 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
199 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
200 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
201 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
202 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
203 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
204 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
205 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
206 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
207 #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
208 #define MT8195_MUTEX_MOD_DISP1_DPI0 25
209 #define MT8195_MUTEX_MOD_DISP1_DPI1 26
210 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
211
212 /* VPPSYS0 */
213 #define MT8195_MUTEX_MOD_MDP_RDMA0 0
214 #define MT8195_MUTEX_MOD_MDP_FG0 1
215 #define MT8195_MUTEX_MOD_MDP_STITCH0 2
216 #define MT8195_MUTEX_MOD_MDP_HDR0 3
217 #define MT8195_MUTEX_MOD_MDP_AAL0 4
218 #define MT8195_MUTEX_MOD_MDP_RSZ0 5
219 #define MT8195_MUTEX_MOD_MDP_TDSHP0 6
220 #define MT8195_MUTEX_MOD_MDP_COLOR0 7
221 #define MT8195_MUTEX_MOD_MDP_OVL0 8
222 #define MT8195_MUTEX_MOD_MDP_PAD0 9
223 #define MT8195_MUTEX_MOD_MDP_TCC0 10
224 #define MT8195_MUTEX_MOD_MDP_WROT0 11
225
226 /* VPPSYS1 */
227 #define MT8195_MUTEX_MOD_MDP_TCC1 3
228 #define MT8195_MUTEX_MOD_MDP_RDMA1 4
229 #define MT8195_MUTEX_MOD_MDP_RDMA2 5
230 #define MT8195_MUTEX_MOD_MDP_RDMA3 6
231 #define MT8195_MUTEX_MOD_MDP_FG1 7
232 #define MT8195_MUTEX_MOD_MDP_FG2 8
233 #define MT8195_MUTEX_MOD_MDP_FG3 9
234 #define MT8195_MUTEX_MOD_MDP_HDR1 10
235 #define MT8195_MUTEX_MOD_MDP_HDR2 11
236 #define MT8195_MUTEX_MOD_MDP_HDR3 12
237 #define MT8195_MUTEX_MOD_MDP_AAL1 13
238 #define MT8195_MUTEX_MOD_MDP_AAL2 14
239 #define MT8195_MUTEX_MOD_MDP_AAL3 15
240 #define MT8195_MUTEX_MOD_MDP_RSZ1 16
241 #define MT8195_MUTEX_MOD_MDP_RSZ2 17
242 #define MT8195_MUTEX_MOD_MDP_RSZ3 18
243 #define MT8195_MUTEX_MOD_MDP_TDSHP1 19
244 #define MT8195_MUTEX_MOD_MDP_TDSHP2 20
245 #define MT8195_MUTEX_MOD_MDP_TDSHP3 21
246 #define MT8195_MUTEX_MOD_MDP_MERGE2 22
247 #define MT8195_MUTEX_MOD_MDP_MERGE3 23
248 #define MT8195_MUTEX_MOD_MDP_COLOR1 24
249 #define MT8195_MUTEX_MOD_MDP_COLOR2 25
250 #define MT8195_MUTEX_MOD_MDP_COLOR3 26
251 #define MT8195_MUTEX_MOD_MDP_OVL1 27
252 #define MT8195_MUTEX_MOD_MDP_PAD1 28
253 #define MT8195_MUTEX_MOD_MDP_PAD2 29
254 #define MT8195_MUTEX_MOD_MDP_PAD3 30
255 #define MT8195_MUTEX_MOD_MDP_WROT1 31
256 #define MT8195_MUTEX_MOD_MDP_WROT2 32
257 #define MT8195_MUTEX_MOD_MDP_WROT3 33
258
259 #define MT8365_MUTEX_MOD_DISP_OVL0 7
260 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
261 #define MT8365_MUTEX_MOD_DISP_RDMA0 9
262 #define MT8365_MUTEX_MOD_DISP_RDMA1 10
263 #define MT8365_MUTEX_MOD_DISP_WDMA0 11
264 #define MT8365_MUTEX_MOD_DISP_COLOR0 12
265 #define MT8365_MUTEX_MOD_DISP_CCORR 13
266 #define MT8365_MUTEX_MOD_DISP_AAL 14
267 #define MT8365_MUTEX_MOD_DISP_GAMMA 15
268 #define MT8365_MUTEX_MOD_DISP_DITHER 16
269 #define MT8365_MUTEX_MOD_DISP_DSI0 17
270 #define MT8365_MUTEX_MOD_DISP_PWM0 20
271 #define MT8365_MUTEX_MOD_DISP_DPI0 22
272
273 #define MT2712_MUTEX_MOD_DISP_PWM2 10
274 #define MT2712_MUTEX_MOD_DISP_OVL0 11
275 #define MT2712_MUTEX_MOD_DISP_OVL1 12
276 #define MT2712_MUTEX_MOD_DISP_RDMA0 13
277 #define MT2712_MUTEX_MOD_DISP_RDMA1 14
278 #define MT2712_MUTEX_MOD_DISP_RDMA2 15
279 #define MT2712_MUTEX_MOD_DISP_WDMA0 16
280 #define MT2712_MUTEX_MOD_DISP_WDMA1 17
281 #define MT2712_MUTEX_MOD_DISP_COLOR0 18
282 #define MT2712_MUTEX_MOD_DISP_COLOR1 19
283 #define MT2712_MUTEX_MOD_DISP_AAL0 20
284 #define MT2712_MUTEX_MOD_DISP_UFOE 22
285 #define MT2712_MUTEX_MOD_DISP_PWM0 23
286 #define MT2712_MUTEX_MOD_DISP_PWM1 24
287 #define MT2712_MUTEX_MOD_DISP_OD0 25
288 #define MT2712_MUTEX_MOD2_DISP_AAL1 33
289 #define MT2712_MUTEX_MOD2_DISP_OD1 34
290
291 #define MT2701_MUTEX_MOD_DISP_OVL 3
292 #define MT2701_MUTEX_MOD_DISP_WDMA 6
293 #define MT2701_MUTEX_MOD_DISP_COLOR 7
294 #define MT2701_MUTEX_MOD_DISP_BLS 9
295 #define MT2701_MUTEX_MOD_DISP_RDMA0 10
296 #define MT2701_MUTEX_MOD_DISP_RDMA1 12
297
298 #define MT2712_MUTEX_SOF_SINGLE_MODE 0
299 #define MT2712_MUTEX_SOF_DSI0 1
300 #define MT2712_MUTEX_SOF_DSI1 2
301 #define MT2712_MUTEX_SOF_DPI0 3
302 #define MT2712_MUTEX_SOF_DPI1 4
303 #define MT2712_MUTEX_SOF_DSI2 5
304 #define MT2712_MUTEX_SOF_DSI3 6
305 #define MT8167_MUTEX_SOF_DPI0 2
306 #define MT8167_MUTEX_SOF_DPI1 3
307 #define MT8183_MUTEX_SOF_DSI0 1
308 #define MT8183_MUTEX_SOF_DPI0 2
309 #define MT8188_MUTEX_SOF_DSI0 1
310 #define MT8188_MUTEX_SOF_DP_INTF0 3
311 #define MT8188_MUTEX_SOF_DP_INTF1 4
312 #define MT8188_MUTEX_SOF_DPI1 5
313 #define MT8195_MUTEX_SOF_DSI0 1
314 #define MT8195_MUTEX_SOF_DSI1 2
315 #define MT8195_MUTEX_SOF_DP_INTF0 3
316 #define MT8195_MUTEX_SOF_DP_INTF1 4
317 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
318 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
319
320 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
321 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
322 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
323 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
324 #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
325 #define MT8188_MUTEX_EOF_DPI1 (MT8188_MUTEX_SOF_DPI1 << 7)
326 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
327 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
328 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
329 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
330 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
331 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
332
333 struct mtk_mutex {
334 u8 id;
335 bool claimed;
336 };
337
338 enum mtk_mutex_sof_id {
339 MUTEX_SOF_SINGLE_MODE,
340 MUTEX_SOF_DSI0,
341 MUTEX_SOF_DSI1,
342 MUTEX_SOF_DPI0,
343 MUTEX_SOF_DPI1,
344 MUTEX_SOF_DSI2,
345 MUTEX_SOF_DSI3,
346 MUTEX_SOF_DP_INTF0,
347 MUTEX_SOF_DP_INTF1,
348 DDP_MUTEX_SOF_MAX,
349 };
350
351 struct mtk_mutex_data {
352 const u8 *mutex_mod;
353 const u8 *mutex_table_mod;
354 const u16 *mutex_sof;
355 const u16 mutex_mod_reg;
356 const u16 mutex_mod1_reg;
357 const u16 mutex_sof_reg;
358 const bool no_clk;
359 };
360
361 struct mtk_mutex_ctx {
362 struct device *dev;
363 struct clk *clk;
364 void __iomem *regs;
365 struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES];
366 const struct mtk_mutex_data *data;
367 phys_addr_t addr;
368 struct cmdq_client_reg cmdq_reg;
369 };
370
371 static const u8 mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
372 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
373 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
374 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
375 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
376 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
377 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
378 };
379
380 static const u8 mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
381 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
382 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
383 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
384 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
385 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
386 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
387 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
388 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
389 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
390 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
391 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
392 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
393 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
394 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
395 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
396 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
397 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
398 };
399
400 static const u8 mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
401 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
402 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
403 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
404 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
405 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
406 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
407 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
408 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
409 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
410 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
411 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
412 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
413 };
414
415 static const u8 mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
416 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
417 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
418 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
419 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
420 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
421 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
422 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
423 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
424 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
425 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
426 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
427 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
428 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
429 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
430 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
431 };
432
433 static const u8 mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
434 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
435 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
436 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
437 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
438 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
439 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
440 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
441 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
442 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
443 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
444 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
445 };
446
447 static const u8 mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
448 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
449 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
450 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
451 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
452 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
453 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
454 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
455 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
456 };
457
458 static const u8 mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
459 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
460 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
461 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
462 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
463 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
464 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
465 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
466 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
467 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
468 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
469 };
470
471 static const u8 mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
472 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0,
473 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0,
474 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1,
475 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0,
476 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0,
477 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0,
478 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0,
479 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0,
480 };
481
482 static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
483 [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0,
484 [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0,
485 [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0,
486 [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0,
487 [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0,
488 [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0,
489 [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0,
490 [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0,
491 [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0,
492 [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE,
493 [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
494 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
495 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
496 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
497 [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
498 [DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1,
499 [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
500 [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
501 [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
502 [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
503 [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
504 [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
505 [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
506 [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
507 [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
508 [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
509 [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
510 [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
511 [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
512 [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
513 [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
514 [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
515 [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
516 [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
517 [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
518 [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
519 [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
520 [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
521 };
522
523 static const u8 mt8188_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
524 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
525 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
526 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
527 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
528 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
529 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
530 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
531 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
532 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
533 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
534 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
535 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
536 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
537 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
538 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
539 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
540 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
541 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
542 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
543 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
544 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
545 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
546 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
547 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
548 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
549 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
550 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
551 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
552 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
553 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
554 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
555 };
556
557 static const u8 mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
558 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
559 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
560 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
561 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
562 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
563 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
564 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
565 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
566 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
567 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
568 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
569 };
570
571 static const u8 mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
572 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
573 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
574 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
575 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
576 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
577 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
578 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
579 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
580 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
581 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
582 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
583 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
584 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
585 [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
586 [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
587 [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
588 [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
589 [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
590 [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
591 [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
592 [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
593 [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
594 [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
595 [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
596 [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
597 [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
598 [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
599 [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
600 };
601
602 static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
603 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
604 [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
605 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
606 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
607 [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
608 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
609 [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
610 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
611 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
612 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
613 [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
614 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
615 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
616 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
617 [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
618 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
619 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
620 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
621 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
622 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
623 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
624 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
625 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
626 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
627 [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
628 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
629 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
630 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
631 [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
632 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
633 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
634 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
635 [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
636 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
637 [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
638 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
639 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
640 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
641 [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
642 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
643 [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
644 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
645 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
646 };
647
648 static const u8 mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
649 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
650 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
651 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
652 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
653 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
654 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
655 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
656 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
657 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
658 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
659 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
660 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
661 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
662 };
663
664 static const u16 mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
665 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
666 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
667 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
668 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
669 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
670 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
671 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
672 };
673
674 static const u16 mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = {
675 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
676 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
677 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
678 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
679 };
680
681 static const u16 mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
682 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
683 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
684 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
685 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
686 };
687
688 /* Add EOF setting so overlay hardware can receive frame done irq */
689 static const u16 mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
690 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
691 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
692 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
693 };
694
695 static const u16 mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
696 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
697 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
698 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
699 };
700
701 /*
702 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
703 * select the EOF source and configure the EOF plus timing from the
704 * module that provides the timing signal.
705 * So that MUTEX can not only send a STREAM_DONE event to GCE
706 * but also detect the error at end of frame(EAEOF) when EOF signal
707 * arrives.
708 */
709 static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
710 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
711 [MUTEX_SOF_DSI0] =
712 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
713 [MUTEX_SOF_DPI1] =
714 MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1,
715 [MUTEX_SOF_DP_INTF0] =
716 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
717 [MUTEX_SOF_DP_INTF1] =
718 MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
719 };
720
721 static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
722 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
723 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
724 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
725 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
726 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
727 [MUTEX_SOF_DP_INTF0] =
728 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
729 [MUTEX_SOF_DP_INTF1] =
730 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
731 };
732
733 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
734 .mutex_mod = mt2701_mutex_mod,
735 .mutex_sof = mt2712_mutex_sof,
736 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
737 .mutex_mod1_reg = MT2701_MUTEX0_MOD1,
738 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
739 };
740
741 static const struct mtk_mutex_data mt2712_mutex_driver_data = {
742 .mutex_mod = mt2712_mutex_mod,
743 .mutex_sof = mt2712_mutex_sof,
744 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
745 .mutex_mod1_reg = MT2701_MUTEX0_MOD1,
746 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
747 };
748
749 static const struct mtk_mutex_data mt6795_mutex_driver_data = {
750 .mutex_mod = mt8173_mutex_mod,
751 .mutex_sof = mt6795_mutex_sof,
752 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
753 .mutex_mod1_reg = MT2701_MUTEX0_MOD1,
754 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
755 };
756
757 static const struct mtk_mutex_data mt8167_mutex_driver_data = {
758 .mutex_mod = mt8167_mutex_mod,
759 .mutex_sof = mt8167_mutex_sof,
760 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
761 .mutex_mod1_reg = MT2701_MUTEX0_MOD1,
762 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
763 .no_clk = true,
764 };
765
766 static const struct mtk_mutex_data mt8173_mutex_driver_data = {
767 .mutex_mod = mt8173_mutex_mod,
768 .mutex_sof = mt2712_mutex_sof,
769 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
770 .mutex_mod1_reg = MT2701_MUTEX0_MOD1,
771 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
772 };
773
774 static const struct mtk_mutex_data mt8183_mutex_driver_data = {
775 .mutex_mod = mt8183_mutex_mod,
776 .mutex_sof = mt8183_mutex_sof,
777 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
778 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
779 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
780 .mutex_table_mod = mt8183_mutex_table_mod,
781 .no_clk = true,
782 };
783
784 static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = {
785 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
786 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
787 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
788 .mutex_table_mod = mt8186_mdp_mutex_table_mod,
789 };
790
791 static const struct mtk_mutex_data mt8186_mutex_driver_data = {
792 .mutex_mod = mt8186_mutex_mod,
793 .mutex_sof = mt8186_mutex_sof,
794 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
795 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
796 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
797 };
798
799 static const struct mtk_mutex_data mt8188_mutex_driver_data = {
800 .mutex_mod = mt8188_mutex_mod,
801 .mutex_sof = mt8188_mutex_sof,
802 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
803 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
804 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
805 };
806
807 static const struct mtk_mutex_data mt8188_vpp_mutex_driver_data = {
808 .mutex_sof = mt8188_mutex_sof,
809 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
810 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
811 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
812 .mutex_table_mod = mt8188_mdp_mutex_table_mod,
813 };
814
815 static const struct mtk_mutex_data mt8192_mutex_driver_data = {
816 .mutex_mod = mt8192_mutex_mod,
817 .mutex_sof = mt8183_mutex_sof,
818 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
819 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
820 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
821 };
822
823 static const struct mtk_mutex_data mt8195_mutex_driver_data = {
824 .mutex_mod = mt8195_mutex_mod,
825 .mutex_sof = mt8195_mutex_sof,
826 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
827 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
828 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
829 };
830
831 static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
832 .mutex_sof = mt8195_mutex_sof,
833 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
834 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
835 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
836 .mutex_table_mod = mt8195_mutex_table_mod,
837 };
838
839 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
840 .mutex_mod = mt8365_mutex_mod,
841 .mutex_sof = mt8183_mutex_sof,
842 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
843 .mutex_mod1_reg = MT8183_MUTEX0_MOD1,
844 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
845 .no_clk = true,
846 };
847
mtk_mutex_get(struct device * dev)848 struct mtk_mutex *mtk_mutex_get(struct device *dev)
849 {
850 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
851 int i;
852
853 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
854 if (!mtx->mutex[i].claimed) {
855 mtx->mutex[i].claimed = true;
856 return &mtx->mutex[i];
857 }
858
859 return ERR_PTR(-EBUSY);
860 }
861 EXPORT_SYMBOL_GPL(mtk_mutex_get);
862
mtk_mutex_put(struct mtk_mutex * mutex)863 void mtk_mutex_put(struct mtk_mutex *mutex)
864 {
865 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
866 mutex[mutex->id]);
867
868 WARN_ON(&mtx->mutex[mutex->id] != mutex);
869
870 mutex->claimed = false;
871 }
872 EXPORT_SYMBOL_GPL(mtk_mutex_put);
873
mtk_mutex_prepare(struct mtk_mutex * mutex)874 int mtk_mutex_prepare(struct mtk_mutex *mutex)
875 {
876 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
877 mutex[mutex->id]);
878 return clk_prepare_enable(mtx->clk);
879 }
880 EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
881
mtk_mutex_unprepare(struct mtk_mutex * mutex)882 void mtk_mutex_unprepare(struct mtk_mutex *mutex)
883 {
884 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
885 mutex[mutex->id]);
886 clk_disable_unprepare(mtx->clk);
887 }
888 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
889
mtk_mutex_add_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)890 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
891 enum mtk_ddp_comp_id id)
892 {
893 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
894 mutex[mutex->id]);
895 unsigned int reg;
896 unsigned int sof_id, mod_id;
897 unsigned int offset;
898
899 WARN_ON(&mtx->mutex[mutex->id] != mutex);
900
901 switch (id) {
902 case DDP_COMPONENT_DSI0:
903 sof_id = MUTEX_SOF_DSI0;
904 break;
905 case DDP_COMPONENT_DSI1:
906 sof_id = MUTEX_SOF_DSI0;
907 break;
908 case DDP_COMPONENT_DSI2:
909 sof_id = MUTEX_SOF_DSI2;
910 break;
911 case DDP_COMPONENT_DSI3:
912 sof_id = MUTEX_SOF_DSI3;
913 break;
914 case DDP_COMPONENT_DPI0:
915 sof_id = MUTEX_SOF_DPI0;
916 break;
917 case DDP_COMPONENT_DPI1:
918 sof_id = MUTEX_SOF_DPI1;
919 break;
920 case DDP_COMPONENT_DP_INTF0:
921 sof_id = MUTEX_SOF_DP_INTF0;
922 break;
923 case DDP_COMPONENT_DP_INTF1:
924 sof_id = MUTEX_SOF_DP_INTF1;
925 break;
926 default:
927 offset = DISP_REG_MUTEX_MOD(mtx, mtx->data->mutex_mod[id], mutex->id);
928 mod_id = mtx->data->mutex_mod[id] % 32;
929 reg = readl_relaxed(mtx->regs + offset);
930 reg |= BIT(mod_id);
931 writel_relaxed(reg, mtx->regs + offset);
932 return;
933 }
934
935 writel_relaxed(mtx->data->mutex_sof[sof_id],
936 mtx->regs +
937 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
938 }
939 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
940
mtk_mutex_remove_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)941 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
942 enum mtk_ddp_comp_id id)
943 {
944 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
945 mutex[mutex->id]);
946 unsigned int reg;
947 unsigned int mod_id;
948 unsigned int offset;
949
950 WARN_ON(&mtx->mutex[mutex->id] != mutex);
951
952 switch (id) {
953 case DDP_COMPONENT_DSI0:
954 case DDP_COMPONENT_DSI1:
955 case DDP_COMPONENT_DSI2:
956 case DDP_COMPONENT_DSI3:
957 case DDP_COMPONENT_DPI0:
958 case DDP_COMPONENT_DPI1:
959 case DDP_COMPONENT_DP_INTF0:
960 case DDP_COMPONENT_DP_INTF1:
961 writel_relaxed(MUTEX_SOF_SINGLE_MODE,
962 mtx->regs +
963 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
964 mutex->id));
965 break;
966 default:
967 offset = DISP_REG_MUTEX_MOD(mtx, mtx->data->mutex_mod[id], mutex->id);
968 mod_id = mtx->data->mutex_mod[id] % 32;
969 reg = readl_relaxed(mtx->regs + offset);
970 reg &= ~BIT(mod_id);
971 writel_relaxed(reg, mtx->regs + offset);
972 break;
973 }
974 }
975 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
976
mtk_mutex_enable(struct mtk_mutex * mutex)977 void mtk_mutex_enable(struct mtk_mutex *mutex)
978 {
979 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
980 mutex[mutex->id]);
981
982 WARN_ON(&mtx->mutex[mutex->id] != mutex);
983
984 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
985 }
986 EXPORT_SYMBOL_GPL(mtk_mutex_enable);
987
mtk_mutex_enable_by_cmdq(struct mtk_mutex * mutex,void * pkt)988 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
989 {
990 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
991 mutex[mutex->id]);
992 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
993
994 WARN_ON(&mtx->mutex[mutex->id] != mutex);
995
996 if (!mtx->cmdq_reg.size) {
997 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
998 return -ENODEV;
999 }
1000
1001 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
1002 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
1003 return 0;
1004 }
1005 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
1006
mtk_mutex_disable(struct mtk_mutex * mutex)1007 void mtk_mutex_disable(struct mtk_mutex *mutex)
1008 {
1009 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1010 mutex[mutex->id]);
1011
1012 WARN_ON(&mtx->mutex[mutex->id] != mutex);
1013
1014 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
1015 }
1016 EXPORT_SYMBOL_GPL(mtk_mutex_disable);
1017
mtk_mutex_acquire(struct mtk_mutex * mutex)1018 void mtk_mutex_acquire(struct mtk_mutex *mutex)
1019 {
1020 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1021 mutex[mutex->id]);
1022 u32 tmp;
1023
1024 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
1025 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
1026 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
1027 tmp, tmp & INT_MUTEX, 1, 10000))
1028 pr_err("could not acquire mutex %d\n", mutex->id);
1029 }
1030 EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
1031
mtk_mutex_release(struct mtk_mutex * mutex)1032 void mtk_mutex_release(struct mtk_mutex *mutex)
1033 {
1034 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1035 mutex[mutex->id]);
1036
1037 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
1038 }
1039 EXPORT_SYMBOL_GPL(mtk_mutex_release);
1040
mtk_mutex_write_mod(struct mtk_mutex * mutex,enum mtk_mutex_mod_index idx,bool clear)1041 int mtk_mutex_write_mod(struct mtk_mutex *mutex,
1042 enum mtk_mutex_mod_index idx, bool clear)
1043 {
1044 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1045 mutex[mutex->id]);
1046 unsigned int reg;
1047 u32 offset, mod_id;
1048
1049 WARN_ON(&mtx->mutex[mutex->id] != mutex);
1050
1051 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
1052 idx >= MUTEX_MOD_IDX_MAX) {
1053 dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
1054 return -EINVAL;
1055 }
1056
1057 offset = DISP_REG_MUTEX_MOD(mtx, mtx->data->mutex_table_mod[idx], mutex->id);
1058 mod_id = mtx->data->mutex_table_mod[idx] % 32;
1059
1060 reg = readl_relaxed(mtx->regs + offset);
1061 if (clear)
1062 reg &= ~BIT(mod_id);
1063 else
1064 reg |= BIT(mod_id);
1065
1066 writel_relaxed(reg, mtx->regs + offset);
1067
1068 return 0;
1069 }
1070 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
1071
mtk_mutex_write_sof(struct mtk_mutex * mutex,enum mtk_mutex_sof_index idx)1072 int mtk_mutex_write_sof(struct mtk_mutex *mutex,
1073 enum mtk_mutex_sof_index idx)
1074 {
1075 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1076 mutex[mutex->id]);
1077
1078 WARN_ON(&mtx->mutex[mutex->id] != mutex);
1079
1080 if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
1081 idx >= MUTEX_SOF_IDX_MAX) {
1082 dev_err(mtx->dev, "Not supported SOF index : %d", idx);
1083 return -EINVAL;
1084 }
1085
1086 writel_relaxed(idx, mtx->regs +
1087 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
1088
1089 return 0;
1090 }
1091 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
1092
mtk_mutex_probe(struct platform_device * pdev)1093 static int mtk_mutex_probe(struct platform_device *pdev)
1094 {
1095 struct device *dev = &pdev->dev;
1096 struct mtk_mutex_ctx *mtx;
1097 struct resource *regs;
1098 int i, ret;
1099
1100 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
1101 if (!mtx)
1102 return -ENOMEM;
1103
1104 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
1105 mtx->mutex[i].id = i;
1106
1107 mtx->data = of_device_get_match_data(dev);
1108
1109 if (!mtx->data->no_clk) {
1110 mtx->clk = devm_clk_get(dev, NULL);
1111 if (IS_ERR(mtx->clk))
1112 return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n");
1113 }
1114
1115 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1116 if (IS_ERR(mtx->regs)) {
1117 dev_err(dev, "Failed to map mutex registers\n");
1118 return PTR_ERR(mtx->regs);
1119 }
1120 mtx->addr = regs->start;
1121
1122 /* CMDQ is optional */
1123 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
1124 if (ret)
1125 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
1126
1127 platform_set_drvdata(pdev, mtx);
1128
1129 return 0;
1130 }
1131
1132 static const struct of_device_id mutex_driver_dt_match[] = {
1133 { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data },
1134 { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data },
1135 { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data },
1136 { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data },
1137 { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data },
1138 { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data },
1139 { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data },
1140 { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data },
1141 { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data },
1142 { .compatible = "mediatek,mt8188-vpp-mutex", .data = &mt8188_vpp_mutex_driver_data },
1143 { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
1144 { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
1145 { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data },
1146 { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data },
1147 { /* sentinel */ },
1148 };
1149 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
1150
1151 static struct platform_driver mtk_mutex_driver = {
1152 .probe = mtk_mutex_probe,
1153 .driver = {
1154 .name = "mediatek-mutex",
1155 .of_match_table = mutex_driver_dt_match,
1156 },
1157 };
1158 module_platform_driver(mtk_mutex_driver);
1159
1160 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
1161 MODULE_DESCRIPTION("MediaTek SoC MUTEX driver");
1162 MODULE_LICENSE("GPL");
1163