1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/iopoll.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15
16 #define MTK_MUTEX_MAX_HANDLES 10
17
18 #define MT2701_MUTEX0_MOD0 0x2c
19 #define MT2701_MUTEX0_SOF0 0x30
20 #define MT8183_MUTEX0_MOD0 0x30
21 #define MT8183_MUTEX0_SOF0 0x2c
22
23 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
24 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
25 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
26 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
27 #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4)
28 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
29 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
30
31 #define INT_MUTEX BIT(1)
32
33 #define MT8186_MUTEX_MOD_DISP_OVL0 0
34 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
35 #define MT8186_MUTEX_MOD_DISP_RDMA0 2
36 #define MT8186_MUTEX_MOD_DISP_COLOR0 4
37 #define MT8186_MUTEX_MOD_DISP_CCORR0 5
38 #define MT8186_MUTEX_MOD_DISP_AAL0 7
39 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8
40 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
41 #define MT8186_MUTEX_MOD_DISP_DITHER0 10
42 #define MT8186_MUTEX_MOD_DISP_RDMA1 17
43
44 #define MT8186_MUTEX_SOF_SINGLE_MODE 0
45 #define MT8186_MUTEX_SOF_DSI0 1
46 #define MT8186_MUTEX_SOF_DPI0 2
47 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
48 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
49
50 #define MT8167_MUTEX_MOD_DISP_PWM 1
51 #define MT8167_MUTEX_MOD_DISP_OVL0 6
52 #define MT8167_MUTEX_MOD_DISP_OVL1 7
53 #define MT8167_MUTEX_MOD_DISP_RDMA0 8
54 #define MT8167_MUTEX_MOD_DISP_RDMA1 9
55 #define MT8167_MUTEX_MOD_DISP_WDMA0 10
56 #define MT8167_MUTEX_MOD_DISP_CCORR 11
57 #define MT8167_MUTEX_MOD_DISP_COLOR 12
58 #define MT8167_MUTEX_MOD_DISP_AAL 13
59 #define MT8167_MUTEX_MOD_DISP_GAMMA 14
60 #define MT8167_MUTEX_MOD_DISP_DITHER 15
61 #define MT8167_MUTEX_MOD_DISP_UFOE 16
62
63 #define MT8192_MUTEX_MOD_DISP_OVL0 0
64 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
65 #define MT8192_MUTEX_MOD_DISP_RDMA0 2
66 #define MT8192_MUTEX_MOD_DISP_COLOR0 4
67 #define MT8192_MUTEX_MOD_DISP_CCORR0 5
68 #define MT8192_MUTEX_MOD_DISP_AAL0 6
69 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7
70 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
71 #define MT8192_MUTEX_MOD_DISP_DITHER0 9
72 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
73 #define MT8192_MUTEX_MOD_DISP_RDMA4 17
74
75 #define MT8183_MUTEX_MOD_DISP_RDMA0 0
76 #define MT8183_MUTEX_MOD_DISP_RDMA1 1
77 #define MT8183_MUTEX_MOD_DISP_OVL0 9
78 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
79 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
80 #define MT8183_MUTEX_MOD_DISP_WDMA0 12
81 #define MT8183_MUTEX_MOD_DISP_COLOR0 13
82 #define MT8183_MUTEX_MOD_DISP_CCORR0 14
83 #define MT8183_MUTEX_MOD_DISP_AAL0 15
84 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16
85 #define MT8183_MUTEX_MOD_DISP_DITHER0 17
86
87 #define MT8183_MUTEX_MOD_MDP_RDMA0 2
88 #define MT8183_MUTEX_MOD_MDP_RSZ0 4
89 #define MT8183_MUTEX_MOD_MDP_RSZ1 5
90 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6
91 #define MT8183_MUTEX_MOD_MDP_WROT0 7
92 #define MT8183_MUTEX_MOD_MDP_WDMA 8
93 #define MT8183_MUTEX_MOD_MDP_AAL0 23
94 #define MT8183_MUTEX_MOD_MDP_CCORR0 24
95
96 #define MT8186_MUTEX_MOD_MDP_RDMA0 0
97 #define MT8186_MUTEX_MOD_MDP_AAL0 2
98 #define MT8186_MUTEX_MOD_MDP_HDR0 4
99 #define MT8186_MUTEX_MOD_MDP_RSZ0 5
100 #define MT8186_MUTEX_MOD_MDP_RSZ1 6
101 #define MT8186_MUTEX_MOD_MDP_WROT0 7
102 #define MT8186_MUTEX_MOD_MDP_TDSHP0 9
103 #define MT8186_MUTEX_MOD_MDP_COLOR0 14
104
105 #define MT8173_MUTEX_MOD_DISP_OVL0 11
106 #define MT8173_MUTEX_MOD_DISP_OVL1 12
107 #define MT8173_MUTEX_MOD_DISP_RDMA0 13
108 #define MT8173_MUTEX_MOD_DISP_RDMA1 14
109 #define MT8173_MUTEX_MOD_DISP_RDMA2 15
110 #define MT8173_MUTEX_MOD_DISP_WDMA0 16
111 #define MT8173_MUTEX_MOD_DISP_WDMA1 17
112 #define MT8173_MUTEX_MOD_DISP_COLOR0 18
113 #define MT8173_MUTEX_MOD_DISP_COLOR1 19
114 #define MT8173_MUTEX_MOD_DISP_AAL 20
115 #define MT8173_MUTEX_MOD_DISP_GAMMA 21
116 #define MT8173_MUTEX_MOD_DISP_UFOE 22
117 #define MT8173_MUTEX_MOD_DISP_PWM0 23
118 #define MT8173_MUTEX_MOD_DISP_PWM1 24
119 #define MT8173_MUTEX_MOD_DISP_OD 25
120
121 #define MT8188_MUTEX_MOD_DISP_OVL0 0
122 #define MT8188_MUTEX_MOD_DISP_WDMA0 1
123 #define MT8188_MUTEX_MOD_DISP_RDMA0 2
124 #define MT8188_MUTEX_MOD_DISP_COLOR0 3
125 #define MT8188_MUTEX_MOD_DISP_CCORR0 4
126 #define MT8188_MUTEX_MOD_DISP_AAL0 5
127 #define MT8188_MUTEX_MOD_DISP_GAMMA0 6
128 #define MT8188_MUTEX_MOD_DISP_DITHER0 7
129 #define MT8188_MUTEX_MOD_DISP_DSI0 8
130 #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
131 #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20
132 #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21
133 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
134 #define MT8188_MUTEX_MOD2_DISP_PWM0 33
135
136 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0
137 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1
138 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2
139 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3
140 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4
141 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
142 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
143 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
144 #define MT8188_MUTEX_MOD_DISP1_PADDING0 8
145 #define MT8188_MUTEX_MOD_DISP1_PADDING1 9
146 #define MT8188_MUTEX_MOD_DISP1_PADDING2 10
147 #define MT8188_MUTEX_MOD_DISP1_PADDING3 11
148 #define MT8188_MUTEX_MOD_DISP1_PADDING4 12
149 #define MT8188_MUTEX_MOD_DISP1_PADDING5 13
150 #define MT8188_MUTEX_MOD_DISP1_PADDING6 14
151 #define MT8188_MUTEX_MOD_DISP1_PADDING7 15
152 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
153 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
154 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
155 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
156 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
157 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
158 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
159
160 #define MT8195_MUTEX_MOD_DISP_OVL0 0
161 #define MT8195_MUTEX_MOD_DISP_WDMA0 1
162 #define MT8195_MUTEX_MOD_DISP_RDMA0 2
163 #define MT8195_MUTEX_MOD_DISP_COLOR0 3
164 #define MT8195_MUTEX_MOD_DISP_CCORR0 4
165 #define MT8195_MUTEX_MOD_DISP_AAL0 5
166 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6
167 #define MT8195_MUTEX_MOD_DISP_DITHER0 7
168 #define MT8195_MUTEX_MOD_DISP_DSI0 8
169 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
170 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
171 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
172 #define MT8195_MUTEX_MOD_DISP_PWM0 27
173
174 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
175 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
176 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
177 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
178 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
179 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
180 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
181 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
182 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
183 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
184 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
185 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
186 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
187 #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
188 #define MT8195_MUTEX_MOD_DISP1_DPI0 25
189 #define MT8195_MUTEX_MOD_DISP1_DPI1 26
190 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
191
192 /* VPPSYS0 */
193 #define MT8195_MUTEX_MOD_MDP_RDMA0 0
194 #define MT8195_MUTEX_MOD_MDP_FG0 1
195 #define MT8195_MUTEX_MOD_MDP_STITCH0 2
196 #define MT8195_MUTEX_MOD_MDP_HDR0 3
197 #define MT8195_MUTEX_MOD_MDP_AAL0 4
198 #define MT8195_MUTEX_MOD_MDP_RSZ0 5
199 #define MT8195_MUTEX_MOD_MDP_TDSHP0 6
200 #define MT8195_MUTEX_MOD_MDP_COLOR0 7
201 #define MT8195_MUTEX_MOD_MDP_OVL0 8
202 #define MT8195_MUTEX_MOD_MDP_PAD0 9
203 #define MT8195_MUTEX_MOD_MDP_TCC0 10
204 #define MT8195_MUTEX_MOD_MDP_WROT0 11
205
206 /* VPPSYS1 */
207 #define MT8195_MUTEX_MOD_MDP_TCC1 3
208 #define MT8195_MUTEX_MOD_MDP_RDMA1 4
209 #define MT8195_MUTEX_MOD_MDP_RDMA2 5
210 #define MT8195_MUTEX_MOD_MDP_RDMA3 6
211 #define MT8195_MUTEX_MOD_MDP_FG1 7
212 #define MT8195_MUTEX_MOD_MDP_FG2 8
213 #define MT8195_MUTEX_MOD_MDP_FG3 9
214 #define MT8195_MUTEX_MOD_MDP_HDR1 10
215 #define MT8195_MUTEX_MOD_MDP_HDR2 11
216 #define MT8195_MUTEX_MOD_MDP_HDR3 12
217 #define MT8195_MUTEX_MOD_MDP_AAL1 13
218 #define MT8195_MUTEX_MOD_MDP_AAL2 14
219 #define MT8195_MUTEX_MOD_MDP_AAL3 15
220 #define MT8195_MUTEX_MOD_MDP_RSZ1 16
221 #define MT8195_MUTEX_MOD_MDP_RSZ2 17
222 #define MT8195_MUTEX_MOD_MDP_RSZ3 18
223 #define MT8195_MUTEX_MOD_MDP_TDSHP1 19
224 #define MT8195_MUTEX_MOD_MDP_TDSHP2 20
225 #define MT8195_MUTEX_MOD_MDP_TDSHP3 21
226 #define MT8195_MUTEX_MOD_MDP_MERGE2 22
227 #define MT8195_MUTEX_MOD_MDP_MERGE3 23
228 #define MT8195_MUTEX_MOD_MDP_COLOR1 24
229 #define MT8195_MUTEX_MOD_MDP_COLOR2 25
230 #define MT8195_MUTEX_MOD_MDP_COLOR3 26
231 #define MT8195_MUTEX_MOD_MDP_OVL1 27
232 #define MT8195_MUTEX_MOD_MDP_PAD1 28
233 #define MT8195_MUTEX_MOD_MDP_PAD2 29
234 #define MT8195_MUTEX_MOD_MDP_PAD3 30
235 #define MT8195_MUTEX_MOD_MDP_WROT1 31
236 #define MT8195_MUTEX_MOD_MDP_WROT2 32
237 #define MT8195_MUTEX_MOD_MDP_WROT3 33
238
239 #define MT8365_MUTEX_MOD_DISP_OVL0 7
240 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
241 #define MT8365_MUTEX_MOD_DISP_RDMA0 9
242 #define MT8365_MUTEX_MOD_DISP_RDMA1 10
243 #define MT8365_MUTEX_MOD_DISP_WDMA0 11
244 #define MT8365_MUTEX_MOD_DISP_COLOR0 12
245 #define MT8365_MUTEX_MOD_DISP_CCORR 13
246 #define MT8365_MUTEX_MOD_DISP_AAL 14
247 #define MT8365_MUTEX_MOD_DISP_GAMMA 15
248 #define MT8365_MUTEX_MOD_DISP_DITHER 16
249 #define MT8365_MUTEX_MOD_DISP_DSI0 17
250 #define MT8365_MUTEX_MOD_DISP_PWM0 20
251 #define MT8365_MUTEX_MOD_DISP_DPI0 22
252
253 #define MT2712_MUTEX_MOD_DISP_PWM2 10
254 #define MT2712_MUTEX_MOD_DISP_OVL0 11
255 #define MT2712_MUTEX_MOD_DISP_OVL1 12
256 #define MT2712_MUTEX_MOD_DISP_RDMA0 13
257 #define MT2712_MUTEX_MOD_DISP_RDMA1 14
258 #define MT2712_MUTEX_MOD_DISP_RDMA2 15
259 #define MT2712_MUTEX_MOD_DISP_WDMA0 16
260 #define MT2712_MUTEX_MOD_DISP_WDMA1 17
261 #define MT2712_MUTEX_MOD_DISP_COLOR0 18
262 #define MT2712_MUTEX_MOD_DISP_COLOR1 19
263 #define MT2712_MUTEX_MOD_DISP_AAL0 20
264 #define MT2712_MUTEX_MOD_DISP_UFOE 22
265 #define MT2712_MUTEX_MOD_DISP_PWM0 23
266 #define MT2712_MUTEX_MOD_DISP_PWM1 24
267 #define MT2712_MUTEX_MOD_DISP_OD0 25
268 #define MT2712_MUTEX_MOD2_DISP_AAL1 33
269 #define MT2712_MUTEX_MOD2_DISP_OD1 34
270
271 #define MT2701_MUTEX_MOD_DISP_OVL 3
272 #define MT2701_MUTEX_MOD_DISP_WDMA 6
273 #define MT2701_MUTEX_MOD_DISP_COLOR 7
274 #define MT2701_MUTEX_MOD_DISP_BLS 9
275 #define MT2701_MUTEX_MOD_DISP_RDMA0 10
276 #define MT2701_MUTEX_MOD_DISP_RDMA1 12
277
278 #define MT2712_MUTEX_SOF_SINGLE_MODE 0
279 #define MT2712_MUTEX_SOF_DSI0 1
280 #define MT2712_MUTEX_SOF_DSI1 2
281 #define MT2712_MUTEX_SOF_DPI0 3
282 #define MT2712_MUTEX_SOF_DPI1 4
283 #define MT2712_MUTEX_SOF_DSI2 5
284 #define MT2712_MUTEX_SOF_DSI3 6
285 #define MT8167_MUTEX_SOF_DPI0 2
286 #define MT8167_MUTEX_SOF_DPI1 3
287 #define MT8183_MUTEX_SOF_DSI0 1
288 #define MT8183_MUTEX_SOF_DPI0 2
289 #define MT8188_MUTEX_SOF_DSI0 1
290 #define MT8188_MUTEX_SOF_DP_INTF0 3
291 #define MT8188_MUTEX_SOF_DP_INTF1 4
292 #define MT8195_MUTEX_SOF_DSI0 1
293 #define MT8195_MUTEX_SOF_DSI1 2
294 #define MT8195_MUTEX_SOF_DP_INTF0 3
295 #define MT8195_MUTEX_SOF_DP_INTF1 4
296 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
297 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
298
299 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
300 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
301 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
302 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
303 #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
304 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
305 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
306 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
307 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
308 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
309 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
310
311 struct mtk_mutex {
312 u8 id;
313 bool claimed;
314 };
315
316 enum mtk_mutex_sof_id {
317 MUTEX_SOF_SINGLE_MODE,
318 MUTEX_SOF_DSI0,
319 MUTEX_SOF_DSI1,
320 MUTEX_SOF_DPI0,
321 MUTEX_SOF_DPI1,
322 MUTEX_SOF_DSI2,
323 MUTEX_SOF_DSI3,
324 MUTEX_SOF_DP_INTF0,
325 MUTEX_SOF_DP_INTF1,
326 DDP_MUTEX_SOF_MAX,
327 };
328
329 struct mtk_mutex_data {
330 const u8 *mutex_mod;
331 const u8 *mutex_table_mod;
332 const u16 *mutex_sof;
333 const u16 mutex_mod_reg;
334 const u16 mutex_sof_reg;
335 const bool no_clk;
336 };
337
338 struct mtk_mutex_ctx {
339 struct device *dev;
340 struct clk *clk;
341 void __iomem *regs;
342 struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES];
343 const struct mtk_mutex_data *data;
344 phys_addr_t addr;
345 struct cmdq_client_reg cmdq_reg;
346 };
347
348 static const u8 mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
349 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
350 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
351 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
352 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
353 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
354 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
355 };
356
357 static const u8 mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
358 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
359 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
360 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
361 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
362 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
363 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
364 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
365 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
366 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
367 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
368 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
369 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
370 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
371 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
372 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
373 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
374 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
375 };
376
377 static const u8 mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
378 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
379 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
380 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
381 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
382 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
383 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
384 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
385 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
386 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
387 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
388 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
389 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
390 };
391
392 static const u8 mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
393 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
394 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
395 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
396 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
397 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
398 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
399 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
400 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
401 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
402 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
403 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
404 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
405 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
406 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
407 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
408 };
409
410 static const u8 mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
411 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
412 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
413 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
414 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
415 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
416 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
417 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
418 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
419 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
420 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
421 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
422 };
423
424 static const u8 mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
425 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
426 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
427 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
428 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
429 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
430 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
431 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
432 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
433 };
434
435 static const u8 mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
436 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
437 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
438 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
439 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
440 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
441 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
442 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
443 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
444 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
445 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
446 };
447
448 static const u8 mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
449 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0,
450 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0,
451 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1,
452 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0,
453 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0,
454 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0,
455 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0,
456 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0,
457 };
458
459 static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
460 [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0,
461 [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0,
462 [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0,
463 [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0,
464 [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0,
465 [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0,
466 [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0,
467 [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0,
468 [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0,
469 [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE,
470 [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
471 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
472 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
473 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
474 [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
475 [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
476 [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
477 [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
478 [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
479 [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
480 [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
481 [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
482 [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
483 [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
484 [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
485 [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
486 [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
487 [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
488 [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
489 [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
490 [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
491 [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
492 [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
493 [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
494 [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
495 [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
496 [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
497 };
498
499 static const u8 mt8188_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
500 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
501 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
502 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
503 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
504 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
505 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
506 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
507 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
508 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
509 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
510 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
511 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
512 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
513 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
514 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
515 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
516 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
517 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
518 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
519 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
520 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
521 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
522 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
523 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
524 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
525 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
526 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
527 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
528 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
529 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
530 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
531 };
532
533 static const u8 mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
534 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
535 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
536 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
537 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
538 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
539 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
540 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
541 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
542 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
543 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
544 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
545 };
546
547 static const u8 mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
548 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
549 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
550 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
551 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
552 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
553 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
554 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
555 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
556 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
557 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
558 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
559 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
560 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
561 [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
562 [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
563 [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
564 [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
565 [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
566 [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
567 [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
568 [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
569 [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
570 [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
571 [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
572 [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
573 [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
574 [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
575 [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
576 };
577
578 static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
579 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
580 [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
581 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
582 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
583 [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
584 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
585 [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
586 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
587 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
588 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
589 [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
590 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
591 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
592 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
593 [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
594 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
595 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
596 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
597 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
598 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
599 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
600 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
601 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
602 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
603 [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
604 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
605 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
606 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
607 [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
608 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
609 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
610 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
611 [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
612 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
613 [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
614 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
615 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
616 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
617 [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
618 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
619 [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
620 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
621 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
622 };
623
624 static const u8 mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
625 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
626 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
627 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
628 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
629 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
630 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
631 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
632 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
633 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
634 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
635 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
636 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
637 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
638 };
639
640 static const u16 mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
641 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
642 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
643 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
644 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
645 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
646 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
647 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
648 };
649
650 static const u16 mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = {
651 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
652 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
653 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
654 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
655 };
656
657 static const u16 mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
658 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
659 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
660 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
661 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
662 };
663
664 /* Add EOF setting so overlay hardware can receive frame done irq */
665 static const u16 mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
666 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
667 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
668 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
669 };
670
671 static const u16 mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
672 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
673 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
674 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
675 };
676
677 /*
678 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
679 * select the EOF source and configure the EOF plus timing from the
680 * module that provides the timing signal.
681 * So that MUTEX can not only send a STREAM_DONE event to GCE
682 * but also detect the error at end of frame(EAEOF) when EOF signal
683 * arrives.
684 */
685 static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
686 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
687 [MUTEX_SOF_DSI0] =
688 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
689 [MUTEX_SOF_DP_INTF0] =
690 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
691 [MUTEX_SOF_DP_INTF1] =
692 MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
693 };
694
695 static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
696 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
697 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
698 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
699 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
700 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
701 [MUTEX_SOF_DP_INTF0] =
702 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
703 [MUTEX_SOF_DP_INTF1] =
704 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
705 };
706
707 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
708 .mutex_mod = mt2701_mutex_mod,
709 .mutex_sof = mt2712_mutex_sof,
710 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
711 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
712 };
713
714 static const struct mtk_mutex_data mt2712_mutex_driver_data = {
715 .mutex_mod = mt2712_mutex_mod,
716 .mutex_sof = mt2712_mutex_sof,
717 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
718 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
719 };
720
721 static const struct mtk_mutex_data mt6795_mutex_driver_data = {
722 .mutex_mod = mt8173_mutex_mod,
723 .mutex_sof = mt6795_mutex_sof,
724 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
725 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
726 };
727
728 static const struct mtk_mutex_data mt8167_mutex_driver_data = {
729 .mutex_mod = mt8167_mutex_mod,
730 .mutex_sof = mt8167_mutex_sof,
731 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
732 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
733 .no_clk = true,
734 };
735
736 static const struct mtk_mutex_data mt8173_mutex_driver_data = {
737 .mutex_mod = mt8173_mutex_mod,
738 .mutex_sof = mt2712_mutex_sof,
739 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
740 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
741 };
742
743 static const struct mtk_mutex_data mt8183_mutex_driver_data = {
744 .mutex_mod = mt8183_mutex_mod,
745 .mutex_sof = mt8183_mutex_sof,
746 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
747 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
748 .mutex_table_mod = mt8183_mutex_table_mod,
749 .no_clk = true,
750 };
751
752 static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = {
753 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
754 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
755 .mutex_table_mod = mt8186_mdp_mutex_table_mod,
756 };
757
758 static const struct mtk_mutex_data mt8186_mutex_driver_data = {
759 .mutex_mod = mt8186_mutex_mod,
760 .mutex_sof = mt8186_mutex_sof,
761 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
762 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
763 };
764
765 static const struct mtk_mutex_data mt8188_mutex_driver_data = {
766 .mutex_mod = mt8188_mutex_mod,
767 .mutex_sof = mt8188_mutex_sof,
768 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
769 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
770 };
771
772 static const struct mtk_mutex_data mt8188_vpp_mutex_driver_data = {
773 .mutex_sof = mt8188_mutex_sof,
774 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
775 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
776 .mutex_table_mod = mt8188_mdp_mutex_table_mod,
777 };
778
779 static const struct mtk_mutex_data mt8192_mutex_driver_data = {
780 .mutex_mod = mt8192_mutex_mod,
781 .mutex_sof = mt8183_mutex_sof,
782 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
783 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
784 };
785
786 static const struct mtk_mutex_data mt8195_mutex_driver_data = {
787 .mutex_mod = mt8195_mutex_mod,
788 .mutex_sof = mt8195_mutex_sof,
789 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
790 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
791 };
792
793 static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
794 .mutex_sof = mt8195_mutex_sof,
795 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
796 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
797 .mutex_table_mod = mt8195_mutex_table_mod,
798 };
799
800 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
801 .mutex_mod = mt8365_mutex_mod,
802 .mutex_sof = mt8183_mutex_sof,
803 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
804 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
805 .no_clk = true,
806 };
807
mtk_mutex_get(struct device * dev)808 struct mtk_mutex *mtk_mutex_get(struct device *dev)
809 {
810 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
811 int i;
812
813 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
814 if (!mtx->mutex[i].claimed) {
815 mtx->mutex[i].claimed = true;
816 return &mtx->mutex[i];
817 }
818
819 return ERR_PTR(-EBUSY);
820 }
821 EXPORT_SYMBOL_GPL(mtk_mutex_get);
822
mtk_mutex_put(struct mtk_mutex * mutex)823 void mtk_mutex_put(struct mtk_mutex *mutex)
824 {
825 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
826 mutex[mutex->id]);
827
828 WARN_ON(&mtx->mutex[mutex->id] != mutex);
829
830 mutex->claimed = false;
831 }
832 EXPORT_SYMBOL_GPL(mtk_mutex_put);
833
mtk_mutex_prepare(struct mtk_mutex * mutex)834 int mtk_mutex_prepare(struct mtk_mutex *mutex)
835 {
836 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
837 mutex[mutex->id]);
838 return clk_prepare_enable(mtx->clk);
839 }
840 EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
841
mtk_mutex_unprepare(struct mtk_mutex * mutex)842 void mtk_mutex_unprepare(struct mtk_mutex *mutex)
843 {
844 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
845 mutex[mutex->id]);
846 clk_disable_unprepare(mtx->clk);
847 }
848 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
849
mtk_mutex_add_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)850 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
851 enum mtk_ddp_comp_id id)
852 {
853 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
854 mutex[mutex->id]);
855 unsigned int reg;
856 unsigned int sof_id;
857 unsigned int offset;
858
859 WARN_ON(&mtx->mutex[mutex->id] != mutex);
860
861 switch (id) {
862 case DDP_COMPONENT_DSI0:
863 sof_id = MUTEX_SOF_DSI0;
864 break;
865 case DDP_COMPONENT_DSI1:
866 sof_id = MUTEX_SOF_DSI0;
867 break;
868 case DDP_COMPONENT_DSI2:
869 sof_id = MUTEX_SOF_DSI2;
870 break;
871 case DDP_COMPONENT_DSI3:
872 sof_id = MUTEX_SOF_DSI3;
873 break;
874 case DDP_COMPONENT_DPI0:
875 sof_id = MUTEX_SOF_DPI0;
876 break;
877 case DDP_COMPONENT_DPI1:
878 sof_id = MUTEX_SOF_DPI1;
879 break;
880 case DDP_COMPONENT_DP_INTF0:
881 sof_id = MUTEX_SOF_DP_INTF0;
882 break;
883 case DDP_COMPONENT_DP_INTF1:
884 sof_id = MUTEX_SOF_DP_INTF1;
885 break;
886 default:
887 if (mtx->data->mutex_mod[id] < 32) {
888 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
889 mutex->id);
890 reg = readl_relaxed(mtx->regs + offset);
891 reg |= 1 << mtx->data->mutex_mod[id];
892 writel_relaxed(reg, mtx->regs + offset);
893 } else {
894 offset = DISP_REG_MUTEX_MOD2(mutex->id);
895 reg = readl_relaxed(mtx->regs + offset);
896 reg |= 1 << (mtx->data->mutex_mod[id] - 32);
897 writel_relaxed(reg, mtx->regs + offset);
898 }
899 return;
900 }
901
902 writel_relaxed(mtx->data->mutex_sof[sof_id],
903 mtx->regs +
904 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
905 }
906 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
907
mtk_mutex_remove_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)908 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
909 enum mtk_ddp_comp_id id)
910 {
911 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
912 mutex[mutex->id]);
913 unsigned int reg;
914 unsigned int offset;
915
916 WARN_ON(&mtx->mutex[mutex->id] != mutex);
917
918 switch (id) {
919 case DDP_COMPONENT_DSI0:
920 case DDP_COMPONENT_DSI1:
921 case DDP_COMPONENT_DSI2:
922 case DDP_COMPONENT_DSI3:
923 case DDP_COMPONENT_DPI0:
924 case DDP_COMPONENT_DPI1:
925 case DDP_COMPONENT_DP_INTF0:
926 case DDP_COMPONENT_DP_INTF1:
927 writel_relaxed(MUTEX_SOF_SINGLE_MODE,
928 mtx->regs +
929 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
930 mutex->id));
931 break;
932 default:
933 if (mtx->data->mutex_mod[id] < 32) {
934 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
935 mutex->id);
936 reg = readl_relaxed(mtx->regs + offset);
937 reg &= ~(1 << mtx->data->mutex_mod[id]);
938 writel_relaxed(reg, mtx->regs + offset);
939 } else {
940 offset = DISP_REG_MUTEX_MOD2(mutex->id);
941 reg = readl_relaxed(mtx->regs + offset);
942 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
943 writel_relaxed(reg, mtx->regs + offset);
944 }
945 break;
946 }
947 }
948 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
949
mtk_mutex_enable(struct mtk_mutex * mutex)950 void mtk_mutex_enable(struct mtk_mutex *mutex)
951 {
952 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
953 mutex[mutex->id]);
954
955 WARN_ON(&mtx->mutex[mutex->id] != mutex);
956
957 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
958 }
959 EXPORT_SYMBOL_GPL(mtk_mutex_enable);
960
mtk_mutex_enable_by_cmdq(struct mtk_mutex * mutex,void * pkt)961 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
962 {
963 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
964 mutex[mutex->id]);
965 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
966
967 WARN_ON(&mtx->mutex[mutex->id] != mutex);
968
969 if (!mtx->cmdq_reg.size) {
970 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
971 return -ENODEV;
972 }
973
974 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
975 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
976 return 0;
977 }
978 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
979
mtk_mutex_disable(struct mtk_mutex * mutex)980 void mtk_mutex_disable(struct mtk_mutex *mutex)
981 {
982 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
983 mutex[mutex->id]);
984
985 WARN_ON(&mtx->mutex[mutex->id] != mutex);
986
987 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
988 }
989 EXPORT_SYMBOL_GPL(mtk_mutex_disable);
990
mtk_mutex_acquire(struct mtk_mutex * mutex)991 void mtk_mutex_acquire(struct mtk_mutex *mutex)
992 {
993 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
994 mutex[mutex->id]);
995 u32 tmp;
996
997 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
998 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
999 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
1000 tmp, tmp & INT_MUTEX, 1, 10000))
1001 pr_err("could not acquire mutex %d\n", mutex->id);
1002 }
1003 EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
1004
mtk_mutex_release(struct mtk_mutex * mutex)1005 void mtk_mutex_release(struct mtk_mutex *mutex)
1006 {
1007 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1008 mutex[mutex->id]);
1009
1010 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
1011 }
1012 EXPORT_SYMBOL_GPL(mtk_mutex_release);
1013
mtk_mutex_write_mod(struct mtk_mutex * mutex,enum mtk_mutex_mod_index idx,bool clear)1014 int mtk_mutex_write_mod(struct mtk_mutex *mutex,
1015 enum mtk_mutex_mod_index idx, bool clear)
1016 {
1017 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1018 mutex[mutex->id]);
1019 unsigned int reg;
1020 u32 reg_offset, id_offset = 0;
1021
1022 WARN_ON(&mtx->mutex[mutex->id] != mutex);
1023
1024 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
1025 idx >= MUTEX_MOD_IDX_MAX) {
1026 dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
1027 return -EINVAL;
1028 }
1029
1030 /*
1031 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
1032 * are present, hence requiring multiple 32-bits registers.
1033 *
1034 * The mutex_table_mod fully represents that by defining the number of
1035 * the mod sequentially, later used as a bit number, which can be more
1036 * than 0..31.
1037 *
1038 * In order to retain compatibility with older SoCs, we perform R/W on
1039 * the single 32 bits registers, but this requires us to translate the
1040 * mutex ID bit accordingly.
1041 */
1042 if (mtx->data->mutex_table_mod[idx] < 32) {
1043 reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
1044 mutex->id);
1045 } else {
1046 reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
1047 mutex->id);
1048 id_offset = 32;
1049 }
1050
1051 reg = readl_relaxed(mtx->regs + reg_offset);
1052 if (clear)
1053 reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
1054 else
1055 reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);
1056
1057 writel_relaxed(reg, mtx->regs + reg_offset);
1058
1059 return 0;
1060 }
1061 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
1062
mtk_mutex_write_sof(struct mtk_mutex * mutex,enum mtk_mutex_sof_index idx)1063 int mtk_mutex_write_sof(struct mtk_mutex *mutex,
1064 enum mtk_mutex_sof_index idx)
1065 {
1066 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
1067 mutex[mutex->id]);
1068
1069 WARN_ON(&mtx->mutex[mutex->id] != mutex);
1070
1071 if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
1072 idx >= MUTEX_SOF_IDX_MAX) {
1073 dev_err(mtx->dev, "Not supported SOF index : %d", idx);
1074 return -EINVAL;
1075 }
1076
1077 writel_relaxed(idx, mtx->regs +
1078 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
1079
1080 return 0;
1081 }
1082 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
1083
mtk_mutex_probe(struct platform_device * pdev)1084 static int mtk_mutex_probe(struct platform_device *pdev)
1085 {
1086 struct device *dev = &pdev->dev;
1087 struct mtk_mutex_ctx *mtx;
1088 struct resource *regs;
1089 int i, ret;
1090
1091 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
1092 if (!mtx)
1093 return -ENOMEM;
1094
1095 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
1096 mtx->mutex[i].id = i;
1097
1098 mtx->data = of_device_get_match_data(dev);
1099
1100 if (!mtx->data->no_clk) {
1101 mtx->clk = devm_clk_get(dev, NULL);
1102 if (IS_ERR(mtx->clk))
1103 return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n");
1104 }
1105
1106 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1107 if (IS_ERR(mtx->regs)) {
1108 dev_err(dev, "Failed to map mutex registers\n");
1109 return PTR_ERR(mtx->regs);
1110 }
1111 mtx->addr = regs->start;
1112
1113 /* CMDQ is optional */
1114 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
1115 if (ret)
1116 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
1117
1118 platform_set_drvdata(pdev, mtx);
1119
1120 return 0;
1121 }
1122
1123 static const struct of_device_id mutex_driver_dt_match[] = {
1124 { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data },
1125 { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data },
1126 { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data },
1127 { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data },
1128 { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data },
1129 { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data },
1130 { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data },
1131 { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data },
1132 { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data },
1133 { .compatible = "mediatek,mt8188-vpp-mutex", .data = &mt8188_vpp_mutex_driver_data },
1134 { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
1135 { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
1136 { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data },
1137 { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data },
1138 { /* sentinel */ },
1139 };
1140 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
1141
1142 static struct platform_driver mtk_mutex_driver = {
1143 .probe = mtk_mutex_probe,
1144 .driver = {
1145 .name = "mediatek-mutex",
1146 .of_match_table = mutex_driver_dt_match,
1147 },
1148 };
1149 module_platform_driver(mtk_mutex_driver);
1150
1151 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
1152 MODULE_DESCRIPTION("MediaTek SoC MUTEX driver");
1153 MODULE_LICENSE("GPL");
1154