xref: /linux/include/linux/mfd/mt6397/registers.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Flora Fu, MediaTek
5  */
6 
7 #ifndef __MFD_MT6397_REGISTERS_H__
8 #define __MFD_MT6397_REGISTERS_H__
9 
10 /* PMIC Registers */
11 #define MT6397_CID			0x0100
12 #define MT6397_TOP_CKPDN		0x0102
13 #define MT6397_TOP_CKPDN_SET		0x0104
14 #define MT6397_TOP_CKPDN_CLR		0x0106
15 #define MT6397_TOP_CKPDN2		0x0108
16 #define MT6397_TOP_CKPDN2_SET		0x010A
17 #define MT6397_TOP_CKPDN2_CLR		0x010C
18 #define MT6397_TOP_GPIO_CKPDN		0x010E
19 #define MT6397_TOP_RST_CON		0x0114
20 #define MT6397_WRP_CKPDN		0x011A
21 #define MT6397_WRP_RST_CON		0x0120
22 #define MT6397_TOP_RST_MISC		0x0126
23 #define MT6397_TOP_CKCON1		0x0128
24 #define MT6397_TOP_CKCON2		0x012A
25 #define MT6397_TOP_CKTST1		0x012C
26 #define MT6397_TOP_CKTST2		0x012E
27 #define MT6397_OC_DEG_EN		0x0130
28 #define MT6397_OC_CTL0			0x0132
29 #define MT6397_OC_CTL1			0x0134
30 #define MT6397_OC_CTL2			0x0136
31 #define MT6397_INT_RSV			0x0138
32 #define MT6397_TEST_CON0		0x013A
33 #define MT6397_TEST_CON1		0x013C
34 #define MT6397_STATUS0			0x013E
35 #define MT6397_STATUS1			0x0140
36 #define MT6397_PGSTATUS			0x0142
37 #define MT6397_CHRSTATUS		0x0144
38 #define MT6397_OCSTATUS0		0x0146
39 #define MT6397_OCSTATUS1		0x0148
40 #define MT6397_OCSTATUS2		0x014A
41 #define MT6397_HDMI_PAD_IE		0x014C
42 #define MT6397_TEST_OUT_L		0x014E
43 #define MT6397_TEST_OUT_H		0x0150
44 #define MT6397_TDSEL_CON		0x0152
45 #define MT6397_RDSEL_CON		0x0154
46 #define MT6397_GPIO_SMT_CON0		0x0156
47 #define MT6397_GPIO_SMT_CON1		0x0158
48 #define MT6397_GPIO_SMT_CON2		0x015A
49 #define MT6397_GPIO_SMT_CON3		0x015C
50 #define MT6397_DRV_CON0			0x015E
51 #define MT6397_DRV_CON1			0x0160
52 #define MT6397_DRV_CON2			0x0162
53 #define MT6397_DRV_CON3			0x0164
54 #define MT6397_DRV_CON4			0x0166
55 #define MT6397_DRV_CON5			0x0168
56 #define MT6397_DRV_CON6			0x016A
57 #define MT6397_DRV_CON7			0x016C
58 #define MT6397_DRV_CON8			0x016E
59 #define MT6397_DRV_CON9			0x0170
60 #define MT6397_DRV_CON10		0x0172
61 #define MT6397_DRV_CON11		0x0174
62 #define MT6397_DRV_CON12		0x0176
63 #define MT6397_INT_CON0			0x0178
64 #define MT6397_INT_CON1			0x017E
65 #define MT6397_INT_STATUS0		0x0184
66 #define MT6397_INT_STATUS1		0x0186
67 #define MT6397_FQMTR_CON0		0x0188
68 #define MT6397_FQMTR_CON1		0x018A
69 #define MT6397_FQMTR_CON2		0x018C
70 #define MT6397_EFUSE_DOUT_0_15		0x01C4
71 #define MT6397_EFUSE_DOUT_16_31		0x01C6
72 #define MT6397_EFUSE_DOUT_32_47		0x01C8
73 #define MT6397_EFUSE_DOUT_48_63		0x01CA
74 #define MT6397_SPI_CON			0x01CC
75 #define MT6397_TOP_CKPDN3		0x01CE
76 #define MT6397_TOP_CKCON3		0x01D4
77 #define MT6397_EFUSE_DOUT_64_79		0x01D6
78 #define MT6397_EFUSE_DOUT_80_95		0x01D8
79 #define MT6397_EFUSE_DOUT_96_111	0x01DA
80 #define MT6397_EFUSE_DOUT_112_127	0x01DC
81 #define MT6397_EFUSE_DOUT_128_143	0x01DE
82 #define MT6397_EFUSE_DOUT_144_159	0x01E0
83 #define MT6397_EFUSE_DOUT_160_175	0x01E2
84 #define MT6397_EFUSE_DOUT_176_191	0x01E4
85 #define MT6397_EFUSE_DOUT_192_207	0x01E6
86 #define MT6397_EFUSE_DOUT_208_223	0x01E8
87 #define MT6397_EFUSE_DOUT_224_239	0x01EA
88 #define MT6397_EFUSE_DOUT_240_255	0x01EC
89 #define MT6397_EFUSE_DOUT_256_271	0x01EE
90 #define MT6397_EFUSE_DOUT_272_287	0x01F0
91 #define MT6397_EFUSE_DOUT_288_300	0x01F2
92 #define MT6397_EFUSE_DOUT_304_319	0x01F4
93 #define MT6397_BUCK_CON0		0x0200
94 #define MT6397_BUCK_CON1		0x0202
95 #define MT6397_BUCK_CON2		0x0204
96 #define MT6397_BUCK_CON3		0x0206
97 #define MT6397_BUCK_CON4		0x0208
98 #define MT6397_BUCK_CON5		0x020A
99 #define MT6397_BUCK_CON6		0x020C
100 #define MT6397_BUCK_CON7		0x020E
101 #define MT6397_BUCK_CON8		0x0210
102 #define MT6397_BUCK_CON9		0x0212
103 #define MT6397_VCA15_CON0		0x0214
104 #define MT6397_VCA15_CON1		0x0216
105 #define MT6397_VCA15_CON2		0x0218
106 #define MT6397_VCA15_CON3		0x021A
107 #define MT6397_VCA15_CON4		0x021C
108 #define MT6397_VCA15_CON5		0x021E
109 #define MT6397_VCA15_CON6		0x0220
110 #define MT6397_VCA15_CON7		0x0222
111 #define MT6397_VCA15_CON8		0x0224
112 #define MT6397_VCA15_CON9		0x0226
113 #define MT6397_VCA15_CON10		0x0228
114 #define MT6397_VCA15_CON11		0x022A
115 #define MT6397_VCA15_CON12		0x022C
116 #define MT6397_VCA15_CON13		0x022E
117 #define MT6397_VCA15_CON14		0x0230
118 #define MT6397_VCA15_CON15		0x0232
119 #define MT6397_VCA15_CON16		0x0234
120 #define MT6397_VCA15_CON17		0x0236
121 #define MT6397_VCA15_CON18		0x0238
122 #define MT6397_VSRMCA15_CON0		0x023A
123 #define MT6397_VSRMCA15_CON1		0x023C
124 #define MT6397_VSRMCA15_CON2		0x023E
125 #define MT6397_VSRMCA15_CON3		0x0240
126 #define MT6397_VSRMCA15_CON4		0x0242
127 #define MT6397_VSRMCA15_CON5		0x0244
128 #define MT6397_VSRMCA15_CON6		0x0246
129 #define MT6397_VSRMCA15_CON7		0x0248
130 #define MT6397_VSRMCA15_CON8		0x024A
131 #define MT6397_VSRMCA15_CON9		0x024C
132 #define MT6397_VSRMCA15_CON10		0x024E
133 #define MT6397_VSRMCA15_CON11		0x0250
134 #define MT6397_VSRMCA15_CON12		0x0252
135 #define MT6397_VSRMCA15_CON13		0x0254
136 #define MT6397_VSRMCA15_CON14		0x0256
137 #define MT6397_VSRMCA15_CON15		0x0258
138 #define MT6397_VSRMCA15_CON16		0x025A
139 #define MT6397_VSRMCA15_CON17		0x025C
140 #define MT6397_VSRMCA15_CON18		0x025E
141 #define MT6397_VSRMCA15_CON19		0x0260
142 #define MT6397_VSRMCA15_CON20		0x0262
143 #define MT6397_VSRMCA15_CON21		0x0264
144 #define MT6397_VCORE_CON0		0x0266
145 #define MT6397_VCORE_CON1		0x0268
146 #define MT6397_VCORE_CON2		0x026A
147 #define MT6397_VCORE_CON3		0x026C
148 #define MT6397_VCORE_CON4		0x026E
149 #define MT6397_VCORE_CON5		0x0270
150 #define MT6397_VCORE_CON6		0x0272
151 #define MT6397_VCORE_CON7		0x0274
152 #define MT6397_VCORE_CON8		0x0276
153 #define MT6397_VCORE_CON9		0x0278
154 #define MT6397_VCORE_CON10		0x027A
155 #define MT6397_VCORE_CON11		0x027C
156 #define MT6397_VCORE_CON12		0x027E
157 #define MT6397_VCORE_CON13		0x0280
158 #define MT6397_VCORE_CON14		0x0282
159 #define MT6397_VCORE_CON15		0x0284
160 #define MT6397_VCORE_CON16		0x0286
161 #define MT6397_VCORE_CON17		0x0288
162 #define MT6397_VCORE_CON18		0x028A
163 #define MT6397_VGPU_CON0		0x028C
164 #define MT6397_VGPU_CON1		0x028E
165 #define MT6397_VGPU_CON2		0x0290
166 #define MT6397_VGPU_CON3		0x0292
167 #define MT6397_VGPU_CON4		0x0294
168 #define MT6397_VGPU_CON5		0x0296
169 #define MT6397_VGPU_CON6		0x0298
170 #define MT6397_VGPU_CON7		0x029A
171 #define MT6397_VGPU_CON8		0x029C
172 #define MT6397_VGPU_CON9		0x029E
173 #define MT6397_VGPU_CON10		0x02A0
174 #define MT6397_VGPU_CON11		0x02A2
175 #define MT6397_VGPU_CON12		0x02A4
176 #define MT6397_VGPU_CON13		0x02A6
177 #define MT6397_VGPU_CON14		0x02A8
178 #define MT6397_VGPU_CON15		0x02AA
179 #define MT6397_VGPU_CON16		0x02AC
180 #define MT6397_VGPU_CON17		0x02AE
181 #define MT6397_VGPU_CON18		0x02B0
182 #define MT6397_VIO18_CON0		0x0300
183 #define MT6397_VIO18_CON1		0x0302
184 #define MT6397_VIO18_CON2		0x0304
185 #define MT6397_VIO18_CON3		0x0306
186 #define MT6397_VIO18_CON4		0x0308
187 #define MT6397_VIO18_CON5		0x030A
188 #define MT6397_VIO18_CON6		0x030C
189 #define MT6397_VIO18_CON7		0x030E
190 #define MT6397_VIO18_CON8		0x0310
191 #define MT6397_VIO18_CON9		0x0312
192 #define MT6397_VIO18_CON10		0x0314
193 #define MT6397_VIO18_CON11		0x0316
194 #define MT6397_VIO18_CON12		0x0318
195 #define MT6397_VIO18_CON13		0x031A
196 #define MT6397_VIO18_CON14		0x031C
197 #define MT6397_VIO18_CON15		0x031E
198 #define MT6397_VIO18_CON16		0x0320
199 #define MT6397_VIO18_CON17		0x0322
200 #define MT6397_VIO18_CON18		0x0324
201 #define MT6397_VPCA7_CON0		0x0326
202 #define MT6397_VPCA7_CON1		0x0328
203 #define MT6397_VPCA7_CON2		0x032A
204 #define MT6397_VPCA7_CON3		0x032C
205 #define MT6397_VPCA7_CON4		0x032E
206 #define MT6397_VPCA7_CON5		0x0330
207 #define MT6397_VPCA7_CON6		0x0332
208 #define MT6397_VPCA7_CON7		0x0334
209 #define MT6397_VPCA7_CON8		0x0336
210 #define MT6397_VPCA7_CON9		0x0338
211 #define MT6397_VPCA7_CON10		0x033A
212 #define MT6397_VPCA7_CON11		0x033C
213 #define MT6397_VPCA7_CON12		0x033E
214 #define MT6397_VPCA7_CON13		0x0340
215 #define MT6397_VPCA7_CON14		0x0342
216 #define MT6397_VPCA7_CON15		0x0344
217 #define MT6397_VPCA7_CON16		0x0346
218 #define MT6397_VPCA7_CON17		0x0348
219 #define MT6397_VPCA7_CON18		0x034A
220 #define MT6397_VSRMCA7_CON0		0x034C
221 #define MT6397_VSRMCA7_CON1		0x034E
222 #define MT6397_VSRMCA7_CON2		0x0350
223 #define MT6397_VSRMCA7_CON3		0x0352
224 #define MT6397_VSRMCA7_CON4		0x0354
225 #define MT6397_VSRMCA7_CON5		0x0356
226 #define MT6397_VSRMCA7_CON6		0x0358
227 #define MT6397_VSRMCA7_CON7		0x035A
228 #define MT6397_VSRMCA7_CON8		0x035C
229 #define MT6397_VSRMCA7_CON9		0x035E
230 #define MT6397_VSRMCA7_CON10		0x0360
231 #define MT6397_VSRMCA7_CON11		0x0362
232 #define MT6397_VSRMCA7_CON12		0x0364
233 #define MT6397_VSRMCA7_CON13		0x0366
234 #define MT6397_VSRMCA7_CON14		0x0368
235 #define MT6397_VSRMCA7_CON15		0x036A
236 #define MT6397_VSRMCA7_CON16		0x036C
237 #define MT6397_VSRMCA7_CON17		0x036E
238 #define MT6397_VSRMCA7_CON18		0x0370
239 #define MT6397_VSRMCA7_CON19		0x0372
240 #define MT6397_VSRMCA7_CON20		0x0374
241 #define MT6397_VSRMCA7_CON21		0x0376
242 #define MT6397_VDRM_CON0		0x0378
243 #define MT6397_VDRM_CON1		0x037A
244 #define MT6397_VDRM_CON2		0x037C
245 #define MT6397_VDRM_CON3		0x037E
246 #define MT6397_VDRM_CON4		0x0380
247 #define MT6397_VDRM_CON5		0x0382
248 #define MT6397_VDRM_CON6		0x0384
249 #define MT6397_VDRM_CON7		0x0386
250 #define MT6397_VDRM_CON8		0x0388
251 #define MT6397_VDRM_CON9		0x038A
252 #define MT6397_VDRM_CON10		0x038C
253 #define MT6397_VDRM_CON11		0x038E
254 #define MT6397_VDRM_CON12		0x0390
255 #define MT6397_VDRM_CON13		0x0392
256 #define MT6397_VDRM_CON14		0x0394
257 #define MT6397_VDRM_CON15		0x0396
258 #define MT6397_VDRM_CON16		0x0398
259 #define MT6397_VDRM_CON17		0x039A
260 #define MT6397_VDRM_CON18		0x039C
261 #define MT6397_BUCK_K_CON0		0x039E
262 #define MT6397_BUCK_K_CON1		0x03A0
263 #define MT6397_ANALDO_CON0		0x0400
264 #define MT6397_ANALDO_CON1		0x0402
265 #define MT6397_ANALDO_CON2		0x0404
266 #define MT6397_ANALDO_CON3		0x0406
267 #define MT6397_ANALDO_CON4		0x0408
268 #define MT6397_ANALDO_CON5		0x040A
269 #define MT6397_ANALDO_CON6		0x040C
270 #define MT6397_ANALDO_CON7		0x040E
271 #define MT6397_DIGLDO_CON0		0x0410
272 #define MT6397_DIGLDO_CON1		0x0412
273 #define MT6397_DIGLDO_CON2		0x0414
274 #define MT6397_DIGLDO_CON3		0x0416
275 #define MT6397_DIGLDO_CON4		0x0418
276 #define MT6397_DIGLDO_CON5		0x041A
277 #define MT6397_DIGLDO_CON6		0x041C
278 #define MT6397_DIGLDO_CON7		0x041E
279 #define MT6397_DIGLDO_CON8		0x0420
280 #define MT6397_DIGLDO_CON9		0x0422
281 #define MT6397_DIGLDO_CON10		0x0424
282 #define MT6397_DIGLDO_CON11		0x0426
283 #define MT6397_DIGLDO_CON12		0x0428
284 #define MT6397_DIGLDO_CON13		0x042A
285 #define MT6397_DIGLDO_CON14		0x042C
286 #define MT6397_DIGLDO_CON15		0x042E
287 #define MT6397_DIGLDO_CON16		0x0430
288 #define MT6397_DIGLDO_CON17		0x0432
289 #define MT6397_DIGLDO_CON18		0x0434
290 #define MT6397_DIGLDO_CON19		0x0436
291 #define MT6397_DIGLDO_CON20		0x0438
292 #define MT6397_DIGLDO_CON21		0x043A
293 #define MT6397_DIGLDO_CON22		0x043C
294 #define MT6397_DIGLDO_CON23		0x043E
295 #define MT6397_DIGLDO_CON24		0x0440
296 #define MT6397_DIGLDO_CON25		0x0442
297 #define MT6397_DIGLDO_CON26		0x0444
298 #define MT6397_DIGLDO_CON27		0x0446
299 #define MT6397_DIGLDO_CON28		0x0448
300 #define MT6397_DIGLDO_CON29		0x044A
301 #define MT6397_DIGLDO_CON30		0x044C
302 #define MT6397_DIGLDO_CON31		0x044E
303 #define MT6397_DIGLDO_CON32		0x0450
304 #define MT6397_DIGLDO_CON33		0x045A
305 #define MT6397_SPK_CON0			0x0600
306 #define MT6397_SPK_CON1			0x0602
307 #define MT6397_SPK_CON2			0x0604
308 #define MT6397_SPK_CON3			0x0606
309 #define MT6397_SPK_CON4			0x0608
310 #define MT6397_SPK_CON5			0x060A
311 #define MT6397_SPK_CON6			0x060C
312 #define MT6397_SPK_CON7			0x060E
313 #define MT6397_SPK_CON8			0x0610
314 #define MT6397_SPK_CON9			0x0612
315 #define MT6397_SPK_CON10		0x0614
316 #define MT6397_SPK_CON11		0x0616
317 #define MT6397_AUDDAC_CON0		0x0700
318 #define MT6397_AUDBUF_CFG0		0x0702
319 #define MT6397_AUDBUF_CFG1		0x0704
320 #define MT6397_AUDBUF_CFG2		0x0706
321 #define MT6397_AUDBUF_CFG3		0x0708
322 #define MT6397_AUDBUF_CFG4		0x070A
323 #define MT6397_IBIASDIST_CFG0		0x070C
324 #define MT6397_AUDACCDEPOP_CFG0		0x070E
325 #define MT6397_AUD_IV_CFG0		0x0710
326 #define MT6397_AUDCLKGEN_CFG0		0x0712
327 #define MT6397_AUDLDO_CFG0		0x0714
328 #define MT6397_AUDLDO_CFG1		0x0716
329 #define MT6397_AUDNVREGGLB_CFG0		0x0718
330 #define MT6397_AUD_NCP0			0x071A
331 #define MT6397_AUDPREAMP_CON0		0x071C
332 #define MT6397_AUDADC_CON0		0x071E
333 #define MT6397_AUDADC_CON1		0x0720
334 #define MT6397_AUDADC_CON2		0x0722
335 #define MT6397_AUDADC_CON3		0x0724
336 #define MT6397_AUDADC_CON4		0x0726
337 #define MT6397_AUDADC_CON5		0x0728
338 #define MT6397_AUDADC_CON6		0x072A
339 #define MT6397_AUDDIGMI_CON0		0x072C
340 #define MT6397_AUDLSBUF_CON0		0x072E
341 #define MT6397_AUDLSBUF_CON1		0x0730
342 #define MT6397_AUDENCSPARE_CON0		0x0732
343 #define MT6397_AUDENCCLKSQ_CON0		0x0734
344 #define MT6397_AUDPREAMPGAIN_CON0	0x0736
345 #define MT6397_ZCD_CON0			0x0738
346 #define MT6397_ZCD_CON1			0x073A
347 #define MT6397_ZCD_CON2			0x073C
348 #define MT6397_ZCD_CON3			0x073E
349 #define MT6397_ZCD_CON4			0x0740
350 #define MT6397_ZCD_CON5			0x0742
351 #define MT6397_NCP_CLKDIV_CON0		0x0744
352 #define MT6397_NCP_CLKDIV_CON1		0x0746
353 
354 #endif /* __MFD_MT6397_REGISTERS_H__ */
355