1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> 5 */ 6 7 #ifndef __MFD_MT6328_CORE_H__ 8 #define __MFD_MT6328_CORE_H__ 9 10 enum mt6328_irq_status_numbers { 11 MT6328_IRQ_STATUS_PWRKEY = 0, 12 MT6328_IRQ_STATUS_HOMEKEY, 13 MT6328_IRQ_STATUS_PWRKEY_R, 14 MT6328_IRQ_STATUS_HOMEKEY_R, 15 MT6328_IRQ_STATUS_THR_H, 16 MT6328_IRQ_STATUS_THR_L, 17 MT6328_IRQ_STATUS_BAT_H, 18 MT6328_IRQ_STATUS_BAT_L, 19 MT6328_IRQ_STATUS_RTC, 20 MT6328_IRQ_STATUS_AUDIO, 21 MT6328_IRQ_STATUS_ACCDET, 22 MT6328_IRQ_STATUS_ACCDET_EINT, 23 MT6328_IRQ_STATUS_ACCDET_NEGV, 24 MT6328_IRQ_STATUS_NI_LBAT_INT, 25 MT6328_IRQ_STATUS_VPROC_OC = 16, 26 MT6328_IRQ_STATUS_VSYS_OC, 27 MT6328_IRQ_STATUS_VLTE_OC, 28 MT6328_IRQ_STATUS_VCORE_OC, 29 MT6328_IRQ_STATUS_VPA_OC, 30 MT6328_IRQ_STATUS_LDO_OC, 31 MT6328_IRQ_STATUS_BAT2_H, 32 MT6328_IRQ_STATUS_BAT2_L, 33 MT6328_IRQ_STATUS_VISMPS0_H, 34 MT6328_IRQ_STATUS_VISMPS0_L, 35 MT6328_IRQ_STATUS_AUXADC_IMP, 36 MT6328_IRQ_STATUS_OV = 32, 37 MT6328_IRQ_STATUS_BVALID_DET, 38 MT6328_IRQ_STATUS_VBATON_HV, 39 MT6328_IRQ_STATUS_VBATON_UNDET, 40 MT6328_IRQ_STATUS_WATCHDOG, 41 MT6328_IRQ_STATUS_PCHR_CM_VDEC, 42 MT6328_IRQ_STATUS_CHRDET, 43 MT6328_IRQ_STATUS_PCHR_CM_VINC, 44 MT6328_IRQ_STATUS_FG_BAT_H, 45 MT6328_IRQ_STATUS_FG_BAT_L, 46 MT6328_IRQ_STATUS_FG_CUR_H, 47 MT6328_IRQ_STATUS_FG_CUR_L, 48 MT6328_IRQ_STATUS_FG_ZCV, 49 MT6328_IRQ_STATUS_SPKL_D, 50 MT6328_IRQ_STATUS_SPKL_AB, 51 }; 52 53 #endif /* __MFD_MT6323_CORE_H__ */ 54