1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 #include <linux/bits.h> 6 7 /* CPU model specific register (MSR) numbers. */ 8 9 /* x86-64 specific MSRs */ 10 #define MSR_EFER 0xc0000080 /* extended feature register */ 11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19 20 /* EFER bits: */ 21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22 #define _EFER_LME 8 /* Long mode enable */ 23 #define _EFER_LMA 10 /* Long mode active (read-only) */ 24 #define _EFER_NX 11 /* No execute enable */ 25 #define _EFER_SVME 12 /* Enable virtualization */ 26 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28 #define _EFER_TCE 15 /* Enable Translation Cache Extensions */ 29 #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ 30 31 #define EFER_SCE (1<<_EFER_SCE) 32 #define EFER_LME (1<<_EFER_LME) 33 #define EFER_LMA (1<<_EFER_LMA) 34 #define EFER_NX (1<<_EFER_NX) 35 #define EFER_SVME (1<<_EFER_SVME) 36 #define EFER_LMSLE (1<<_EFER_LMSLE) 37 #define EFER_FFXSR (1<<_EFER_FFXSR) 38 #define EFER_TCE (1<<_EFER_TCE) 39 #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) 40 41 /* 42 * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc. 43 * Most MSRs support/allow only a subset of memory types, but the values 44 * themselves are common across all relevant MSRs. 45 */ 46 #define X86_MEMTYPE_UC 0ull /* Uncacheable, a.k.a. Strong Uncacheable */ 47 #define X86_MEMTYPE_WC 1ull /* Write Combining */ 48 /* RESERVED 2 */ 49 /* RESERVED 3 */ 50 #define X86_MEMTYPE_WT 4ull /* Write Through */ 51 #define X86_MEMTYPE_WP 5ull /* Write Protected */ 52 #define X86_MEMTYPE_WB 6ull /* Write Back */ 53 #define X86_MEMTYPE_UC_MINUS 7ull /* Weak Uncacheabled (PAT only) */ 54 55 /* FRED MSRs */ 56 #define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ 57 #define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ 58 #define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ 59 #define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ 60 #define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ 61 #define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ 62 #define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ 63 #define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ 64 #define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ 65 #define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ 66 67 /* Intel MSRs. Some also available on other CPUs */ 68 #define MSR_TEST_CTRL 0x00000033 69 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 70 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 71 72 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 73 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 74 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 75 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 76 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 77 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 78 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 79 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 80 #define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */ 81 #define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT) 82 83 /* A mask for bits which the kernel toggles when controlling mitigations */ 84 #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 85 | SPEC_CTRL_RRSBA_DIS_S \ 86 | SPEC_CTRL_BHI_DIS_S) 87 88 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 89 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 90 #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 91 92 #define MSR_PPIN_CTL 0x0000004e 93 #define MSR_PPIN 0x0000004f 94 95 #define MSR_IA32_PERFCTR0 0x000000c1 96 #define MSR_IA32_PERFCTR1 0x000000c2 97 #define MSR_FSB_FREQ 0x000000cd 98 #define MSR_PLATFORM_INFO 0x000000ce 99 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 100 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 101 102 #define MSR_IA32_UMWAIT_CONTROL 0xe1 103 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 104 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 105 /* 106 * The time field is bit[31:2], but representing a 32bit value with 107 * bit[1:0] zero. 108 */ 109 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 110 111 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 112 #define MSR_IA32_CORE_CAPS 0x000000cf 113 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 114 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 115 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 116 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 117 #define MSR_IA32_CORE_CAPS_BFF_RESET_BIT 9 118 #define MSR_IA32_CORE_CAPS_BFF_RESET BIT(MSR_IA32_CORE_CAPS_BFF_RESET_BIT) 119 120 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 121 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 122 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 123 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 124 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 125 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 126 127 #define MSR_MTRRcap 0x000000fe 128 129 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 130 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 131 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 132 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 133 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 134 #define ARCH_CAP_SSB_NO BIT(4) /* 135 * Not susceptible to Speculative Store Bypass 136 * attack, so no Speculative Store Bypass 137 * control required. 138 */ 139 #define ARCH_CAP_MDS_NO BIT(5) /* 140 * Not susceptible to 141 * Microarchitectural Data 142 * Sampling (MDS) vulnerabilities. 143 */ 144 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 145 * The processor is not susceptible to a 146 * machine check error due to modifying the 147 * code page size along with either the 148 * physical address or cache type 149 * without TLB invalidation. 150 */ 151 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 152 #define ARCH_CAP_TAA_NO BIT(8) /* 153 * Not susceptible to 154 * TSX Async Abort (TAA) vulnerabilities. 155 */ 156 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 157 * Not susceptible to SBDR and SSDP 158 * variants of Processor MMIO stale data 159 * vulnerabilities. 160 */ 161 #define ARCH_CAP_FBSDP_NO BIT(14) /* 162 * Not susceptible to FBSDP variant of 163 * Processor MMIO stale data 164 * vulnerabilities. 165 */ 166 #define ARCH_CAP_PSDP_NO BIT(15) /* 167 * Not susceptible to PSDP variant of 168 * Processor MMIO stale data 169 * vulnerabilities. 170 */ 171 #define ARCH_CAP_MCU_ENUM BIT(16) /* 172 * Indicates the presence of microcode update 173 * feature enumeration and status information. 174 */ 175 #define ARCH_CAP_FB_CLEAR BIT(17) /* 176 * VERW clears CPU fill buffer 177 * even on MDS_NO CPUs. 178 */ 179 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 180 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 181 * bit available to control VERW 182 * behavior. 183 */ 184 #define ARCH_CAP_RRSBA BIT(19) /* 185 * Indicates RET may use predictors 186 * other than the RSB. With eIBRS 187 * enabled predictions in kernel mode 188 * are restricted to targets in 189 * kernel. 190 */ 191 #define ARCH_CAP_BHI_NO BIT(20) /* 192 * CPU is not affected by Branch 193 * History Injection. 194 */ 195 #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 196 * IA32_XAPIC_DISABLE_STATUS MSR 197 * supported 198 */ 199 #define ARCH_CAP_PBRSB_NO BIT(24) /* 200 * Not susceptible to Post-Barrier 201 * Return Stack Buffer Predictions. 202 */ 203 #define ARCH_CAP_GDS_CTRL BIT(25) /* 204 * CPU is vulnerable to Gather 205 * Data Sampling (GDS) and 206 * has controls for mitigation. 207 */ 208 #define ARCH_CAP_GDS_NO BIT(26) /* 209 * CPU is not vulnerable to Gather 210 * Data Sampling (GDS). 211 */ 212 #define ARCH_CAP_RFDS_NO BIT(27) /* 213 * Not susceptible to Register 214 * File Data Sampling. 215 */ 216 #define ARCH_CAP_RFDS_CLEAR BIT(28) /* 217 * VERW clears CPU Register 218 * File. 219 */ 220 #define ARCH_CAP_ITS_NO BIT_ULL(62) /* 221 * Not susceptible to 222 * Indirect Target Selection. 223 * This bit is not set by 224 * HW, but is synthesized by 225 * VMMs for guests to know 226 * their affected status. 227 */ 228 229 #define MSR_IA32_FLUSH_CMD 0x0000010b 230 #define L1D_FLUSH BIT(0) /* 231 * Writeback and invalidate the 232 * L1 data cache. 233 */ 234 235 #define MSR_IA32_BBL_CR_CTL 0x00000119 236 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 237 238 #define MSR_IA32_TSX_CTRL 0x00000122 239 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 240 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 241 242 #define MSR_IA32_MCU_OPT_CTRL 0x00000123 243 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 244 #define RTM_ALLOW BIT(1) /* TSX development mode */ 245 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 246 #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ 247 #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ 248 249 #define MSR_IA32_SYSENTER_CS 0x00000174 250 #define MSR_IA32_SYSENTER_ESP 0x00000175 251 #define MSR_IA32_SYSENTER_EIP 0x00000176 252 253 #define MSR_IA32_MCG_CAP 0x00000179 254 #define MSR_IA32_MCG_STATUS 0x0000017a 255 #define MSR_IA32_MCG_CTL 0x0000017b 256 #define MSR_ERROR_CONTROL 0x0000017f 257 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 258 259 #define MSR_OFFCORE_RSP_0 0x000001a6 260 #define MSR_OFFCORE_RSP_1 0x000001a7 261 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 262 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 263 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 264 265 #define MSR_SNOOP_RSP_0 0x00001328 266 #define MSR_SNOOP_RSP_1 0x00001329 267 268 #define MSR_OMR_0 0x000003e0 269 #define MSR_OMR_1 0x000003e1 270 #define MSR_OMR_2 0x000003e2 271 #define MSR_OMR_3 0x000003e3 272 273 #define MSR_LBR_SELECT 0x000001c8 274 #define MSR_LBR_TOS 0x000001c9 275 276 #define MSR_IA32_POWER_CTL 0x000001fc 277 #define MSR_IA32_POWER_CTL_BIT_EE 19 278 279 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 280 #define MSR_INTEGRITY_CAPS 0x000002d9 281 #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 282 #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 283 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 284 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 285 #define MSR_INTEGRITY_CAPS_SBAF_BIT 8 286 #define MSR_INTEGRITY_CAPS_SBAF BIT(MSR_INTEGRITY_CAPS_SBAF_BIT) 287 #define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9) 288 289 #define MSR_LBR_NHM_FROM 0x00000680 290 #define MSR_LBR_NHM_TO 0x000006c0 291 #define MSR_LBR_CORE_FROM 0x00000040 292 #define MSR_LBR_CORE_TO 0x00000060 293 294 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 295 #define LBR_INFO_MISPRED BIT_ULL(63) 296 #define LBR_INFO_IN_TX BIT_ULL(62) 297 #define LBR_INFO_ABORT BIT_ULL(61) 298 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 299 #define LBR_INFO_CYCLES 0xffff 300 #define LBR_INFO_BR_TYPE_OFFSET 56 301 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 302 #define LBR_INFO_BR_CNTR_OFFSET 32 303 #define LBR_INFO_BR_CNTR_NUM 4 304 #define LBR_INFO_BR_CNTR_BITS 2 305 #define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0) 306 #define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0) 307 308 #define MSR_ARCH_LBR_CTL 0x000014ce 309 #define ARCH_LBR_CTL_LBREN BIT(0) 310 #define ARCH_LBR_CTL_CPL_OFFSET 1 311 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 312 #define ARCH_LBR_CTL_STACK_OFFSET 3 313 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 314 #define ARCH_LBR_CTL_FILTER_OFFSET 16 315 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 316 #define MSR_ARCH_LBR_DEPTH 0x000014cf 317 #define MSR_ARCH_LBR_FROM_0 0x00001500 318 #define MSR_ARCH_LBR_TO_0 0x00001600 319 #define MSR_ARCH_LBR_INFO_0 0x00001200 320 321 #define MSR_IA32_PEBS_ENABLE 0x000003f1 322 #define MSR_PEBS_DATA_CFG 0x000003f2 323 #define MSR_IA32_DS_AREA 0x00000600 324 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 325 #define PERF_CAP_METRICS_IDX 15 326 #define PERF_CAP_PT_IDX 16 327 328 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 329 330 #define PERF_CAP_LBR_FMT 0x3f 331 #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 332 #define PERF_CAP_ARCH_REG BIT_ULL(7) 333 #define PERF_CAP_PEBS_FORMAT 0xf00 334 #define PERF_CAP_FW_WRITES BIT_ULL(13) 335 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 336 #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) 337 #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 338 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ 339 PERF_CAP_PEBS_TIMING_INFO) 340 341 /* Arch PEBS */ 342 #define MSR_IA32_PEBS_BASE 0x000003f4 343 #define MSR_IA32_PEBS_INDEX 0x000003f5 344 #define ARCH_PEBS_OFFSET_MASK 0x7fffff 345 #define ARCH_PEBS_INDEX_WR_SHIFT 4 346 347 #define ARCH_PEBS_RELOAD 0xffffffff 348 #define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35) 349 #define ARCH_PEBS_CNTR_GP BIT_ULL(36) 350 #define ARCH_PEBS_CNTR_FIXED BIT_ULL(37) 351 #define ARCH_PEBS_CNTR_METRICS BIT_ULL(38) 352 #define ARCH_PEBS_LBR_SHIFT 40 353 #define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT) 354 #define ARCH_PEBS_VECR_XMM BIT_ULL(49) 355 #define ARCH_PEBS_VECR_YMMH BIT_ULL(50) 356 #define ARCH_PEBS_VECR_EGPRS BIT_ULL(51) 357 #define ARCH_PEBS_VECR_OPMASK BIT_ULL(53) 358 #define ARCH_PEBS_VECR_ZMMH BIT_ULL(54) 359 #define ARCH_PEBS_VECR_H16ZMM BIT_ULL(55) 360 #define ARCH_PEBS_VECR_EXT_SHIFT 49 361 #define ARCH_PEBS_VECR_EXT (0x7full << ARCH_PEBS_VECR_EXT_SHIFT) 362 #define ARCH_PEBS_GPR BIT_ULL(61) 363 #define ARCH_PEBS_AUX BIT_ULL(62) 364 #define ARCH_PEBS_EN BIT_ULL(63) 365 #define ARCH_PEBS_CNTR_MASK (ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \ 366 ARCH_PEBS_CNTR_METRICS) 367 368 #define MSR_IA32_RTIT_CTL 0x00000570 369 #define RTIT_CTL_TRACEEN BIT(0) 370 #define RTIT_CTL_CYCLEACC BIT(1) 371 #define RTIT_CTL_OS BIT(2) 372 #define RTIT_CTL_USR BIT(3) 373 #define RTIT_CTL_PWR_EVT_EN BIT(4) 374 #define RTIT_CTL_FUP_ON_PTW BIT(5) 375 #define RTIT_CTL_FABRIC_EN BIT(6) 376 #define RTIT_CTL_CR3EN BIT(7) 377 #define RTIT_CTL_TOPA BIT(8) 378 #define RTIT_CTL_MTC_EN BIT(9) 379 #define RTIT_CTL_TSC_EN BIT(10) 380 #define RTIT_CTL_DISRETC BIT(11) 381 #define RTIT_CTL_PTW_EN BIT(12) 382 #define RTIT_CTL_BRANCH_EN BIT(13) 383 #define RTIT_CTL_EVENT_EN BIT(31) 384 #define RTIT_CTL_NOTNT BIT_ULL(55) 385 #define RTIT_CTL_MTC_RANGE_OFFSET 14 386 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 387 #define RTIT_CTL_CYC_THRESH_OFFSET 19 388 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 389 #define RTIT_CTL_PSB_FREQ_OFFSET 24 390 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 391 #define RTIT_CTL_ADDR0_OFFSET 32 392 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 393 #define RTIT_CTL_ADDR1_OFFSET 36 394 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 395 #define RTIT_CTL_ADDR2_OFFSET 40 396 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 397 #define RTIT_CTL_ADDR3_OFFSET 44 398 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 399 #define MSR_IA32_RTIT_STATUS 0x00000571 400 #define RTIT_STATUS_FILTEREN BIT(0) 401 #define RTIT_STATUS_CONTEXTEN BIT(1) 402 #define RTIT_STATUS_TRIGGEREN BIT(2) 403 #define RTIT_STATUS_BUFFOVF BIT(3) 404 #define RTIT_STATUS_ERROR BIT(4) 405 #define RTIT_STATUS_STOPPED BIT(5) 406 #define RTIT_STATUS_BYTECNT_OFFSET 32 407 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 408 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 409 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 410 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 411 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 412 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 413 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 414 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 415 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 416 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 417 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 418 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 419 420 #define MSR_MTRRfix64K_00000 0x00000250 421 #define MSR_MTRRfix16K_80000 0x00000258 422 #define MSR_MTRRfix16K_A0000 0x00000259 423 #define MSR_MTRRfix4K_C0000 0x00000268 424 #define MSR_MTRRfix4K_C8000 0x00000269 425 #define MSR_MTRRfix4K_D0000 0x0000026a 426 #define MSR_MTRRfix4K_D8000 0x0000026b 427 #define MSR_MTRRfix4K_E0000 0x0000026c 428 #define MSR_MTRRfix4K_E8000 0x0000026d 429 #define MSR_MTRRfix4K_F0000 0x0000026e 430 #define MSR_MTRRfix4K_F8000 0x0000026f 431 #define MSR_MTRRdefType 0x000002ff 432 433 #define MSR_IA32_CR_PAT 0x00000277 434 435 #define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7) \ 436 ((X86_MEMTYPE_ ## p0) | (X86_MEMTYPE_ ## p1 << 8) | \ 437 (X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) | \ 438 (X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) | \ 439 (X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56)) 440 441 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 442 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 443 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 444 #define MSR_IA32_LASTINTFROMIP 0x000001dd 445 #define MSR_IA32_LASTINTTOIP 0x000001de 446 447 #define MSR_IA32_PASID 0x00000d93 448 #define MSR_IA32_PASID_VALID BIT_ULL(31) 449 450 /* DEBUGCTLMSR bits (others vary by model): */ 451 #define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */ 452 #define DEBUGCTLMSR_LBR (1UL << DEBUGCTLMSR_LBR_BIT) 453 #define DEBUGCTLMSR_BTF_SHIFT 1 454 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 455 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 456 #define DEBUGCTLMSR_TR (1UL << 6) 457 #define DEBUGCTLMSR_BTS (1UL << 7) 458 #define DEBUGCTLMSR_BTINT (1UL << 8) 459 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 460 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 461 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 462 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 463 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 464 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 465 #define DEBUGCTLMSR_RTM_DEBUG BIT(15) 466 467 #define MSR_PEBS_FRONTEND 0x000003f7 468 469 #define MSR_IA32_MC0_CTL 0x00000400 470 #define MSR_IA32_MC0_STATUS 0x00000401 471 #define MSR_IA32_MC0_ADDR 0x00000402 472 #define MSR_IA32_MC0_MISC 0x00000403 473 474 /* C-state Residency Counters */ 475 #define MSR_PKG_C3_RESIDENCY 0x000003f8 476 #define MSR_PKG_C6_RESIDENCY 0x000003f9 477 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 478 #define MSR_PKG_C7_RESIDENCY 0x000003fa 479 #define MSR_CORE_C3_RESIDENCY 0x000003fc 480 #define MSR_CORE_C6_RESIDENCY 0x000003fd 481 #define MSR_CORE_C7_RESIDENCY 0x000003fe 482 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 483 #define MSR_PKG_C2_RESIDENCY 0x0000060d 484 #define MSR_PKG_C8_RESIDENCY 0x00000630 485 #define MSR_PKG_C9_RESIDENCY 0x00000631 486 #define MSR_PKG_C10_RESIDENCY 0x00000632 487 488 /* Interrupt Response Limit */ 489 #define MSR_PKGC3_IRTL 0x0000060a 490 #define MSR_PKGC6_IRTL 0x0000060b 491 #define MSR_PKGC7_IRTL 0x0000060c 492 #define MSR_PKGC8_IRTL 0x00000633 493 #define MSR_PKGC9_IRTL 0x00000634 494 #define MSR_PKGC10_IRTL 0x00000635 495 496 /* Run Time Average Power Limiting (RAPL) Interface */ 497 498 #define MSR_VR_CURRENT_CONFIG 0x00000601 499 #define MSR_RAPL_POWER_UNIT 0x00000606 500 501 #define MSR_PKG_POWER_LIMIT 0x00000610 502 #define MSR_PKG_ENERGY_STATUS 0x00000611 503 #define MSR_PKG_PERF_STATUS 0x00000613 504 #define MSR_PKG_POWER_INFO 0x00000614 505 506 #define MSR_DRAM_POWER_LIMIT 0x00000618 507 #define MSR_DRAM_ENERGY_STATUS 0x00000619 508 #define MSR_DRAM_PERF_STATUS 0x0000061b 509 #define MSR_DRAM_POWER_INFO 0x0000061c 510 511 #define MSR_PP0_POWER_LIMIT 0x00000638 512 #define MSR_PP0_ENERGY_STATUS 0x00000639 513 #define MSR_PP0_POLICY 0x0000063a 514 #define MSR_PP0_PERF_STATUS 0x0000063b 515 516 #define MSR_PP1_POWER_LIMIT 0x00000640 517 #define MSR_PP1_ENERGY_STATUS 0x00000641 518 #define MSR_PP1_POLICY 0x00000642 519 520 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 521 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 522 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 523 524 /* Config TDP MSRs */ 525 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 526 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 527 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 528 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 529 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 530 531 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 532 #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 533 534 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 535 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 536 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 537 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 538 539 #define MSR_CORE_C1_RES 0x00000660 540 #define MSR_MODULE_C6_RES_MS 0x00000664 541 542 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 543 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 544 545 #define MSR_ATOM_CORE_RATIOS 0x0000066a 546 #define MSR_ATOM_CORE_VIDS 0x0000066b 547 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 548 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 549 550 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 551 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 552 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 553 554 /* Control-flow Enforcement Technology MSRs */ 555 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 556 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 557 #define CET_SHSTK_EN BIT_ULL(0) 558 #define CET_WRSS_EN BIT_ULL(1) 559 #define CET_ENDBR_EN BIT_ULL(2) 560 #define CET_LEG_IW_EN BIT_ULL(3) 561 #define CET_NO_TRACK_EN BIT_ULL(4) 562 #define CET_SUPPRESS_DISABLE BIT_ULL(5) 563 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 564 #define CET_SUPPRESS BIT_ULL(10) 565 #define CET_WAIT_ENDBR BIT_ULL(11) 566 567 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 568 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 569 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 570 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 571 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 572 573 /* Hardware P state interface */ 574 #define MSR_PPERF 0x0000064e 575 #define MSR_PERF_LIMIT_REASONS 0x0000064f 576 #define MSR_PM_ENABLE 0x00000770 577 #define MSR_HWP_CAPABILITIES 0x00000771 578 #define MSR_HWP_REQUEST_PKG 0x00000772 579 #define MSR_HWP_INTERRUPT 0x00000773 580 #define MSR_HWP_REQUEST 0x00000774 581 #define MSR_HWP_STATUS 0x00000777 582 583 /* CPUID.6.EAX */ 584 #define HWP_BASE_BIT (1<<7) 585 #define HWP_NOTIFICATIONS_BIT (1<<8) 586 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 587 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 588 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 589 590 /* IA32_HWP_CAPABILITIES */ 591 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 592 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 593 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 594 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 595 596 /* IA32_HWP_REQUEST */ 597 #define HWP_MIN_PERF(x) (x & 0xff) 598 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 599 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 600 #define HWP_ENERGY_PERF_PREFERENCE(x) (((u64)x & 0xff) << 24) 601 #define HWP_EPP_PERFORMANCE 0x00 602 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 603 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 604 #define HWP_EPP_POWERSAVE 0xFF 605 #define HWP_ACTIVITY_WINDOW(x) ((u64)(x & 0xff3) << 32) 606 #define HWP_PACKAGE_CONTROL(x) ((u64)(x & 0x1) << 42) 607 608 /* IA32_HWP_STATUS */ 609 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 610 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 611 612 /* IA32_HWP_INTERRUPT */ 613 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 614 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 615 616 #define MSR_AMD64_MC0_MASK 0xc0010044 617 618 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 619 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 620 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 621 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 622 623 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 624 625 /* These are consecutive and not in the normal 4er MCE bank block */ 626 #define MSR_IA32_MC0_CTL2 0x00000280 627 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 628 629 #define MSR_P6_PERFCTR0 0x000000c1 630 #define MSR_P6_PERFCTR1 0x000000c2 631 #define MSR_P6_EVNTSEL0 0x00000186 632 #define MSR_P6_EVNTSEL1 0x00000187 633 634 #define MSR_KNC_PERFCTR0 0x00000020 635 #define MSR_KNC_PERFCTR1 0x00000021 636 #define MSR_KNC_EVNTSEL0 0x00000028 637 #define MSR_KNC_EVNTSEL1 0x00000029 638 639 /* Alternative perfctr range with full access. */ 640 #define MSR_IA32_PMC0 0x000004c1 641 642 /* Auto-reload via MSR instead of DS area */ 643 #define MSR_RELOAD_PMC0 0x000014c1 644 #define MSR_RELOAD_FIXED_CTR0 0x00001309 645 646 /* V6 PMON MSR range */ 647 #define MSR_IA32_PMC_V6_GP0_CTR 0x1900 648 #define MSR_IA32_PMC_V6_GP0_CFG_A 0x1901 649 #define MSR_IA32_PMC_V6_GP0_CFG_B 0x1902 650 #define MSR_IA32_PMC_V6_GP0_CFG_C 0x1903 651 #define MSR_IA32_PMC_V6_FX0_CTR 0x1980 652 #define MSR_IA32_PMC_V6_FX0_CFG_B 0x1982 653 #define MSR_IA32_PMC_V6_FX0_CFG_C 0x1983 654 #define MSR_IA32_PMC_V6_STEP 4 655 656 /* KeyID partitioning between MKTME and TDX */ 657 #define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087 658 659 /* 660 * AMD64 MSRs. Not complete. See the architecture manual for a more 661 * complete list. 662 */ 663 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 664 #define MSR_AMD64_TSC_RATIO 0xc0000104 665 #define MSR_AMD64_NB_CFG 0xc001001f 666 #define MSR_AMD64_PATCH_LOADER 0xc0010020 667 #define MSR_AMD_PERF_CTL 0xc0010062 668 #define MSR_AMD_PERF_STATUS 0xc0010063 669 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 670 #define MSR_AMD64_GUEST_TSC_FREQ 0xc0010134 671 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 672 #define MSR_AMD64_OSVW_STATUS 0xc0010141 673 #define MSR_AMD_PPIN_CTL 0xc00102f0 674 #define MSR_AMD_PPIN 0xc00102f1 675 #define MSR_AMD64_CPUID_FN_7 0xc0011002 676 #define MSR_AMD64_CPUID_FN_1 0xc0011004 677 678 #define MSR_AMD64_CPUID_EXT_FEAT 0xc0011005 679 #define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT 54 680 #define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT) 681 682 #define MSR_AMD64_LS_CFG 0xc0011020 683 #define MSR_AMD64_DC_CFG 0xc0011022 684 #define MSR_AMD64_TW_CFG 0xc0011023 685 686 #define MSR_AMD64_FP_CFG 0xc0011028 687 #define MSR_AMD64_FP_CFG_ZEN1_DENORM_FIX_BIT 9 688 689 #define MSR_AMD64_DE_CFG 0xc0011029 690 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 691 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 692 #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 693 694 #define MSR_AMD64_BU_CFG2 0xc001102a 695 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 696 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 697 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 698 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 699 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 700 #define MSR_AMD64_IBSOPCTL 0xc0011033 701 #define MSR_AMD64_IBSOPRIP 0xc0011034 702 #define MSR_AMD64_IBSOPDATA 0xc0011035 703 #define MSR_AMD64_IBSOPDATA2 0xc0011036 704 #define MSR_AMD64_IBSOPDATA3 0xc0011037 705 #define MSR_AMD64_IBSDCLINAD 0xc0011038 706 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 707 #define MSR_AMD64_IBSOP_REG_COUNT 7 708 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 709 #define MSR_AMD64_IBSCTL 0xc001103a 710 #define MSR_AMD64_IBSBRTARGET 0xc001103b 711 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 712 #define MSR_AMD64_IBSOPDATA4 0xc001103d 713 #define MSR_AMD64_IBSOPCTL2 0xc001103e 714 #define MSR_AMD64_IBSFETCHCTL2 0xc001103f 715 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 716 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 717 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 718 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 719 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 720 #define MSR_AMD64_SEV 0xc0010131 721 #define MSR_AMD64_SEV_ENABLED_BIT 0 722 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 723 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 724 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 725 #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 726 #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 727 #define MSR_AMD64_SNP_VTOM_BIT 3 728 #define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT) 729 #define MSR_AMD64_SNP_REFLECT_VC_BIT 4 730 #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT) 731 #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5 732 #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT) 733 #define MSR_AMD64_SNP_ALT_INJ_BIT 6 734 #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT) 735 #define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7 736 #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT) 737 #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8 738 #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT) 739 #define MSR_AMD64_SNP_BTB_ISOLATION_BIT 9 740 #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT) 741 #define MSR_AMD64_SNP_VMPL_SSS_BIT 10 742 #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT) 743 #define MSR_AMD64_SNP_SECURE_TSC_BIT 11 744 #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT) 745 #define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT 12 746 #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT) 747 #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) 748 #define MSR_AMD64_SNP_IBS_VIRT_BIT 14 749 #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT) 750 #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) 751 #define MSR_AMD64_SNP_VMSA_REG_PROT_BIT 16 752 #define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT) 753 #define MSR_AMD64_SNP_SMT_PROT_BIT 17 754 #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) 755 #define MSR_AMD64_SNP_SECURE_AVIC_BIT 18 756 #define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT) 757 #define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19) 758 #define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT 23 759 #define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT) 760 #define MSR_AMD64_SNP_RESV_BIT 24 761 #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT) 762 #define MSR_AMD64_SAVIC_CONTROL 0xc0010138 763 #define MSR_AMD64_SAVIC_EN_BIT 0 764 #define MSR_AMD64_SAVIC_EN BIT_ULL(MSR_AMD64_SAVIC_EN_BIT) 765 #define MSR_AMD64_SAVIC_ALLOWEDNMI_BIT 1 766 #define MSR_AMD64_SAVIC_ALLOWEDNMI BIT_ULL(MSR_AMD64_SAVIC_ALLOWEDNMI_BIT) 767 #define MSR_AMD64_RMP_BASE 0xc0010132 768 #define MSR_AMD64_RMP_END 0xc0010133 769 #define MSR_AMD64_RMP_CFG 0xc0010136 770 #define MSR_AMD64_SEG_RMP_ENABLED_BIT 0 771 #define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT) 772 #define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8) 773 #define MSR_AMD64_RMPOPT_BASE 0xc0010139 774 #define MSR_AMD64_RMPOPT_ENABLE_BIT 0 775 #define MSR_AMD64_RMPOPT_ENABLE BIT_ULL(MSR_AMD64_RMPOPT_ENABLE_BIT) 776 777 #define MSR_SVSM_CAA 0xc001f000 778 779 /* AMD Collaborative Processor Performance Control MSRs */ 780 #define MSR_AMD_CPPC_CAP1 0xc00102b0 781 #define MSR_AMD_CPPC_ENABLE 0xc00102b1 782 #define MSR_AMD_CPPC_CAP2 0xc00102b2 783 #define MSR_AMD_CPPC_REQ 0xc00102b3 784 #define MSR_AMD_CPPC_STATUS 0xc00102b4 785 #define MSR_AMD_CPPC_REQ2 0xc00102b5 786 787 /* Masks for use with MSR_AMD_CPPC_CAP1 */ 788 #define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0) 789 #define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8) 790 #define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16) 791 #define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24) 792 #define AMD_CPPC_FLOOR_PERF_CNT_MASK GENMASK_ULL(39, 32) 793 794 /* Masks for use with MSR_AMD_CPPC_REQ */ 795 #define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) 796 #define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) 797 #define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) 798 #define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) 799 800 /* Masks for use with MSR_AMD_CPPC_REQ2 */ 801 #define AMD_CPPC_FLOOR_PERF_MASK GENMASK(7, 0) 802 803 /* AMD Performance Counter Global Status and Control MSRs */ 804 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 805 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 806 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 807 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET 0xc0000303 808 809 /* AMD Hardware Feedback Support MSRs */ 810 #define MSR_AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 811 #define MSR_AMD_WORKLOAD_CLASS_ID 0xc0000501 812 #define MSR_AMD_WORKLOAD_HRST 0xc0000502 813 814 /* AMD Last Branch Record MSRs */ 815 #define MSR_AMD64_LBR_SELECT 0xc000010e 816 817 /* Zen4 */ 818 #define MSR_ZEN4_BP_CFG 0xc001102e 819 #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4 820 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 821 #define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33 822 823 /* Fam 19h MSRs */ 824 #define MSR_F19H_UMC_PERF_CTL 0xc0010800 825 #define MSR_F19H_UMC_PERF_CTR 0xc0010801 826 827 /* Zen 2 */ 828 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 829 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT 1 830 831 /* Fam 17h MSRs */ 832 #define MSR_F17H_IRPERF 0xc00000e9 833 834 /* Fam 16h MSRs */ 835 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 836 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 837 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 838 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 839 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 840 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 841 842 /* Fam 15h MSRs */ 843 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 844 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 845 #define MSR_F15H_PERF_CTL 0xc0010200 846 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 847 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 848 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 849 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 850 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 851 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 852 853 #define MSR_F15H_PERF_CTR 0xc0010201 854 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 855 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 856 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 857 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 858 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 859 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 860 861 #define MSR_F15H_NB_PERF_CTL 0xc0010240 862 #define MSR_F15H_NB_PERF_CTR 0xc0010241 863 #define MSR_F15H_PTSC 0xc0010280 864 #define MSR_F15H_IC_CFG 0xc0011021 865 #define MSR_F15H_EX_CFG 0xc001102c 866 867 /* Fam 10h MSRs */ 868 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 869 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 870 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 871 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 872 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 873 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 874 #define MSR_FAM10H_NODE_ID 0xc001100c 875 876 /* K8 MSRs */ 877 #define MSR_K8_TOP_MEM1 0xc001001a 878 #define MSR_K8_TOP_MEM2 0xc001001d 879 #define MSR_AMD64_SYSCFG 0xc0010010 880 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 881 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 882 #define MSR_AMD64_SYSCFG_SNP_EN_BIT 24 883 #define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT) 884 #define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25 885 #define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT) 886 #define MSR_AMD64_SYSCFG_MFDM_BIT 19 887 #define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT) 888 889 #define MSR_K8_INT_PENDING_MSG 0xc0010055 890 /* C1E active bits in int pending message */ 891 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 892 #define MSR_K8_TSEG_ADDR 0xc0010112 893 #define MSR_K8_TSEG_MASK 0xc0010113 894 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 895 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 896 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 897 898 /* K7 MSRs */ 899 #define MSR_K7_EVNTSEL0 0xc0010000 900 #define MSR_K7_PERFCTR0 0xc0010004 901 #define MSR_K7_EVNTSEL1 0xc0010001 902 #define MSR_K7_PERFCTR1 0xc0010005 903 #define MSR_K7_EVNTSEL2 0xc0010002 904 #define MSR_K7_PERFCTR2 0xc0010006 905 #define MSR_K7_EVNTSEL3 0xc0010003 906 #define MSR_K7_PERFCTR3 0xc0010007 907 #define MSR_K7_CLK_CTL 0xc001001b 908 #define MSR_K7_HWCR 0xc0010015 909 #define MSR_K7_HWCR_SMMLOCK_BIT 0 910 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 911 #define MSR_K7_HWCR_IRPERF_EN_BIT 30 912 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 913 #define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35 914 #define MSR_K7_HWCR_CPUID_USER_DIS BIT_ULL(MSR_K7_HWCR_CPUID_USER_DIS_BIT) 915 #define MSR_K7_FID_VID_CTL 0xc0010041 916 #define MSR_K7_FID_VID_STATUS 0xc0010042 917 #define MSR_K7_HWCR_CPB_DIS_BIT 25 918 #define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) 919 920 /* K6 MSRs */ 921 #define MSR_K6_WHCR 0xc0000082 922 #define MSR_K6_UWCCR 0xc0000085 923 #define MSR_K6_EPMR 0xc0000086 924 #define MSR_K6_PSOR 0xc0000087 925 #define MSR_K6_PFIR 0xc0000088 926 927 /* Centaur-Hauls/IDT defined MSRs. */ 928 #define MSR_IDT_FCR1 0x00000107 929 #define MSR_IDT_FCR2 0x00000108 930 #define MSR_IDT_FCR3 0x00000109 931 #define MSR_IDT_FCR4 0x0000010a 932 933 #define MSR_IDT_MCR0 0x00000110 934 #define MSR_IDT_MCR1 0x00000111 935 #define MSR_IDT_MCR2 0x00000112 936 #define MSR_IDT_MCR3 0x00000113 937 #define MSR_IDT_MCR4 0x00000114 938 #define MSR_IDT_MCR5 0x00000115 939 #define MSR_IDT_MCR6 0x00000116 940 #define MSR_IDT_MCR7 0x00000117 941 #define MSR_IDT_MCR_CTRL 0x00000120 942 943 /* VIA Cyrix defined MSRs*/ 944 #define MSR_VIA_FCR 0x00001107 945 #define MSR_VIA_LONGHAUL 0x0000110a 946 #define MSR_VIA_RNG 0x0000110b 947 #define MSR_VIA_BCR2 0x00001147 948 949 /* Transmeta defined MSRs */ 950 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 951 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 952 #define MSR_TMTA_LRTI_READOUT 0x80868018 953 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 954 955 /* Intel defined MSRs. */ 956 #define MSR_IA32_P5_MC_ADDR 0x00000000 957 #define MSR_IA32_P5_MC_TYPE 0x00000001 958 #define MSR_IA32_TSC 0x00000010 959 #define MSR_IA32_PLATFORM_ID 0x00000017 960 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 961 #define MSR_EBC_FREQUENCY_ID 0x0000002c 962 #define MSR_SMI_COUNT 0x00000034 963 964 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 965 #define MSR_IA32_FEAT_CTL 0x0000003a 966 #define FEAT_CTL_LOCKED BIT(0) 967 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 968 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 969 #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 970 #define FEAT_CTL_SGX_ENABLED BIT(18) 971 #define FEAT_CTL_LMCE_ENABLED BIT(20) 972 973 #define MSR_IA32_TSC_ADJUST 0x0000003b 974 #define MSR_IA32_BNDCFGS 0x00000d90 975 976 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 977 978 #define MSR_IA32_XFD 0x000001c4 979 #define MSR_IA32_XFD_ERR 0x000001c5 980 #define MSR_IA32_XSS 0x00000da0 981 982 #define MSR_IA32_APICBASE 0x0000001b 983 #define MSR_IA32_APICBASE_BSP (1<<8) 984 #define MSR_IA32_APICBASE_ENABLE (1<<11) 985 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 986 987 #define MSR_IA32_UCODE_WRITE 0x00000079 988 989 #define MSR_IA32_MCU_ENUMERATION 0x0000007b 990 #define MCU_STAGING BIT(4) 991 992 #define MSR_IA32_UCODE_REV 0x0000008b 993 994 /* Intel SGX Launch Enclave Public Key Hash MSRs */ 995 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 996 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 997 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 998 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 999 1000 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 1001 #define MSR_IA32_SMBASE 0x0000009e 1002 1003 #define MSR_IA32_PERF_STATUS 0x00000198 1004 #define MSR_IA32_PERF_CTL 0x00000199 1005 #define INTEL_PERF_CTL_MASK 0xffff 1006 1007 /* AMD Branch Sampling configuration */ 1008 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 1009 #define MSR_AMD_SAMP_BR_FROM 0xc0010300 1010 1011 #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 1012 1013 #define MSR_IA32_MPERF 0x000000e7 1014 #define MSR_IA32_APERF 0x000000e8 1015 1016 #define MSR_IA32_THERM_CONTROL 0x0000019a 1017 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 1018 1019 #define THERM_INT_HIGH_ENABLE (1 << 0) 1020 #define THERM_INT_LOW_ENABLE (1 << 1) 1021 #define THERM_INT_PLN_ENABLE (1 << 24) 1022 #define THERM_INT_DPTI_ENABLE (1 << 25) 1023 1024 #define MSR_IA32_THERM_STATUS 0x0000019c 1025 1026 #define THERM_STATUS_PROCHOT (1 << 0) 1027 #define THERM_STATUS_POWER_LIMIT (1 << 10) 1028 1029 #define MSR_THERM2_CTL 0x0000019d 1030 1031 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 1032 1033 #define MSR_IA32_MISC_ENABLE 0x000001a0 1034 1035 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 1036 1037 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 1038 #define MSR_MISC_PWR_MGMT 0x000001aa 1039 1040 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 1041 #define ENERGY_PERF_BIAS_PERFORMANCE 0 1042 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 1043 #define ENERGY_PERF_BIAS_NORMAL 6 1044 #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 1045 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 1046 #define ENERGY_PERF_BIAS_POWERSAVE 15 1047 1048 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 1049 1050 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 1051 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 1052 #define PACKAGE_THERM_STATUS_DPTI_ACK (1 << 25) 1053 #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 1054 1055 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 1056 1057 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 1058 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 1059 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 1060 #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 1061 1062 /* Thermal Thresholds Support */ 1063 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 1064 #define THERM_SHIFT_THRESHOLD0 8 1065 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 1066 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 1067 #define THERM_SHIFT_THRESHOLD1 16 1068 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 1069 #define THERM_STATUS_THRESHOLD0 (1 << 6) 1070 #define THERM_LOG_THRESHOLD0 (1 << 7) 1071 #define THERM_STATUS_THRESHOLD1 (1 << 8) 1072 #define THERM_LOG_THRESHOLD1 (1 << 9) 1073 1074 /* MISC_ENABLE bits: architectural */ 1075 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 1076 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 1077 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 1078 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 1079 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 1080 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 1081 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 1082 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 1083 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 1084 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 1085 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 1086 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 1087 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 1088 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 1089 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 1090 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 1091 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 1092 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 1093 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 1094 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 1095 1096 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 1097 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 1098 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 1099 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 1100 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 1101 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 1102 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 1103 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 1104 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 1105 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 1106 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 1107 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 1108 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 1109 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 1110 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 1111 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 1112 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 1113 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 1114 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 1115 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 1116 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 1117 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 1118 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 1119 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 1120 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 1121 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 1122 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 1123 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 1124 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 1125 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 1126 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 1127 1128 /* MISC_FEATURES_ENABLES non-architectural features */ 1129 #define MSR_MISC_FEATURES_ENABLES 0x00000140 1130 1131 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 1132 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 1133 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 1134 1135 #define MSR_IA32_TSC_DEADLINE 0x000006E0 1136 1137 1138 #define MSR_TSX_FORCE_ABORT 0x0000010F 1139 1140 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 1141 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 1142 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 1143 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 1144 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 1145 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 1146 1147 /* P4/Xeon+ specific */ 1148 #define MSR_IA32_MCG_EAX 0x00000180 1149 #define MSR_IA32_MCG_EBX 0x00000181 1150 #define MSR_IA32_MCG_ECX 0x00000182 1151 #define MSR_IA32_MCG_EDX 0x00000183 1152 #define MSR_IA32_MCG_ESI 0x00000184 1153 #define MSR_IA32_MCG_EDI 0x00000185 1154 #define MSR_IA32_MCG_EBP 0x00000186 1155 #define MSR_IA32_MCG_ESP 0x00000187 1156 #define MSR_IA32_MCG_EFLAGS 0x00000188 1157 #define MSR_IA32_MCG_EIP 0x00000189 1158 #define MSR_IA32_MCG_RESERVED 0x0000018a 1159 1160 /* Pentium IV performance counter MSRs */ 1161 #define MSR_P4_BPU_PERFCTR0 0x00000300 1162 #define MSR_P4_BPU_PERFCTR1 0x00000301 1163 #define MSR_P4_BPU_PERFCTR2 0x00000302 1164 #define MSR_P4_BPU_PERFCTR3 0x00000303 1165 #define MSR_P4_MS_PERFCTR0 0x00000304 1166 #define MSR_P4_MS_PERFCTR1 0x00000305 1167 #define MSR_P4_MS_PERFCTR2 0x00000306 1168 #define MSR_P4_MS_PERFCTR3 0x00000307 1169 #define MSR_P4_FLAME_PERFCTR0 0x00000308 1170 #define MSR_P4_FLAME_PERFCTR1 0x00000309 1171 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 1172 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 1173 #define MSR_P4_IQ_PERFCTR0 0x0000030c 1174 #define MSR_P4_IQ_PERFCTR1 0x0000030d 1175 #define MSR_P4_IQ_PERFCTR2 0x0000030e 1176 #define MSR_P4_IQ_PERFCTR3 0x0000030f 1177 #define MSR_P4_IQ_PERFCTR4 0x00000310 1178 #define MSR_P4_IQ_PERFCTR5 0x00000311 1179 #define MSR_P4_BPU_CCCR0 0x00000360 1180 #define MSR_P4_BPU_CCCR1 0x00000361 1181 #define MSR_P4_BPU_CCCR2 0x00000362 1182 #define MSR_P4_BPU_CCCR3 0x00000363 1183 #define MSR_P4_MS_CCCR0 0x00000364 1184 #define MSR_P4_MS_CCCR1 0x00000365 1185 #define MSR_P4_MS_CCCR2 0x00000366 1186 #define MSR_P4_MS_CCCR3 0x00000367 1187 #define MSR_P4_FLAME_CCCR0 0x00000368 1188 #define MSR_P4_FLAME_CCCR1 0x00000369 1189 #define MSR_P4_FLAME_CCCR2 0x0000036a 1190 #define MSR_P4_FLAME_CCCR3 0x0000036b 1191 #define MSR_P4_IQ_CCCR0 0x0000036c 1192 #define MSR_P4_IQ_CCCR1 0x0000036d 1193 #define MSR_P4_IQ_CCCR2 0x0000036e 1194 #define MSR_P4_IQ_CCCR3 0x0000036f 1195 #define MSR_P4_IQ_CCCR4 0x00000370 1196 #define MSR_P4_IQ_CCCR5 0x00000371 1197 #define MSR_P4_ALF_ESCR0 0x000003ca 1198 #define MSR_P4_ALF_ESCR1 0x000003cb 1199 #define MSR_P4_BPU_ESCR0 0x000003b2 1200 #define MSR_P4_BPU_ESCR1 0x000003b3 1201 #define MSR_P4_BSU_ESCR0 0x000003a0 1202 #define MSR_P4_BSU_ESCR1 0x000003a1 1203 #define MSR_P4_CRU_ESCR0 0x000003b8 1204 #define MSR_P4_CRU_ESCR1 0x000003b9 1205 #define MSR_P4_CRU_ESCR2 0x000003cc 1206 #define MSR_P4_CRU_ESCR3 0x000003cd 1207 #define MSR_P4_CRU_ESCR4 0x000003e0 1208 #define MSR_P4_CRU_ESCR5 0x000003e1 1209 #define MSR_P4_DAC_ESCR0 0x000003a8 1210 #define MSR_P4_DAC_ESCR1 0x000003a9 1211 #define MSR_P4_FIRM_ESCR0 0x000003a4 1212 #define MSR_P4_FIRM_ESCR1 0x000003a5 1213 #define MSR_P4_FLAME_ESCR0 0x000003a6 1214 #define MSR_P4_FLAME_ESCR1 0x000003a7 1215 #define MSR_P4_FSB_ESCR0 0x000003a2 1216 #define MSR_P4_FSB_ESCR1 0x000003a3 1217 #define MSR_P4_IQ_ESCR0 0x000003ba 1218 #define MSR_P4_IQ_ESCR1 0x000003bb 1219 #define MSR_P4_IS_ESCR0 0x000003b4 1220 #define MSR_P4_IS_ESCR1 0x000003b5 1221 #define MSR_P4_ITLB_ESCR0 0x000003b6 1222 #define MSR_P4_ITLB_ESCR1 0x000003b7 1223 #define MSR_P4_IX_ESCR0 0x000003c8 1224 #define MSR_P4_IX_ESCR1 0x000003c9 1225 #define MSR_P4_MOB_ESCR0 0x000003aa 1226 #define MSR_P4_MOB_ESCR1 0x000003ab 1227 #define MSR_P4_MS_ESCR0 0x000003c0 1228 #define MSR_P4_MS_ESCR1 0x000003c1 1229 #define MSR_P4_PMH_ESCR0 0x000003ac 1230 #define MSR_P4_PMH_ESCR1 0x000003ad 1231 #define MSR_P4_RAT_ESCR0 0x000003bc 1232 #define MSR_P4_RAT_ESCR1 0x000003bd 1233 #define MSR_P4_SAAT_ESCR0 0x000003ae 1234 #define MSR_P4_SAAT_ESCR1 0x000003af 1235 #define MSR_P4_SSU_ESCR0 0x000003be 1236 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 1237 1238 #define MSR_P4_TBPU_ESCR0 0x000003c2 1239 #define MSR_P4_TBPU_ESCR1 0x000003c3 1240 #define MSR_P4_TC_ESCR0 0x000003c4 1241 #define MSR_P4_TC_ESCR1 0x000003c5 1242 #define MSR_P4_U2L_ESCR0 0x000003b0 1243 #define MSR_P4_U2L_ESCR1 0x000003b1 1244 1245 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1246 1247 /* Intel Core-based CPU performance counters */ 1248 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1249 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1250 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 1251 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1252 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1253 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1254 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1255 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1256 #define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 1257 1258 #define MSR_PERF_METRICS 0x00000329 1259 1260 /* PERF_GLOBAL_OVF_CTL bits */ 1261 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1262 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1263 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1264 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1265 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1266 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1267 1268 /* Geode defined MSRs */ 1269 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1270 1271 /* Intel VT MSRs */ 1272 #define MSR_IA32_VMX_BASIC 0x00000480 1273 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1274 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1275 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1276 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1277 #define MSR_IA32_VMX_MISC 0x00000485 1278 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1279 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1280 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1281 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1282 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1283 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1284 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1285 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1286 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1287 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1288 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1289 #define MSR_IA32_VMX_VMFUNC 0x00000491 1290 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1291 1292 #define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 1293 1294 /* Resctrl MSRs: */ 1295 /* - Intel: */ 1296 #define MSR_IA32_L3_QOS_CFG 0xc81 1297 #define MSR_IA32_L2_QOS_CFG 0xc82 1298 #define MSR_IA32_QM_EVTSEL 0xc8d 1299 #define MSR_IA32_QM_CTR 0xc8e 1300 #define MSR_IA32_PQR_ASSOC 0xc8f 1301 #define MSR_IA32_L3_CBM_BASE 0xc90 1302 #define MSR_RMID_SNC_CONFIG 0xca0 1303 #define MSR_IA32_L2_CBM_BASE 0xd10 1304 #define MSR_IA32_MBA_THRTL_BASE 0xd50 1305 1306 /* - AMD: */ 1307 #define MSR_IA32_MBA_BW_BASE 0xc0000200 1308 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 1309 #define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd 1310 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff 1311 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 1312 1313 /* AMD-V MSRs */ 1314 #define MSR_VM_CR 0xc0010114 1315 #define MSR_VM_IGNNE 0xc0010115 1316 #define MSR_VM_HSAVE_PA 0xc0010117 1317 1318 #define SVM_VM_CR_VALID_MASK 0x001fULL 1319 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 1320 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 1321 1322 /* Hardware Feedback Interface */ 1323 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1324 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1325 1326 /* x2APIC locked status */ 1327 #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1328 #define LEGACY_XAPIC_DISABLED BIT(0) /* 1329 * x2APIC mode is locked and 1330 * disabling x2APIC will cause 1331 * a #GP 1332 */ 1333 1334 #endif /* _ASM_X86_MSR_INDEX_H */ 1335