1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include "drm.h" 29 30 #if defined(__cplusplus) 31 extern "C" { 32 #endif 33 34 /* Please note that modifications to all structs defined here are 35 * subject to backwards-compatibility constraints: 36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 37 * user/kernel compatibility 38 * 2) Keep fields aligned to their size 39 * 3) Because of how drm_ioctl() works, we can add new fields at 40 * the end of an ioctl if some care is taken: drm_ioctl() will 41 * zero out the new fields at the tail of the ioctl, so a zero 42 * value should have a backwards compatible meaning. And for 43 * output params, userspace won't see the newly added output 44 * fields.. so that has to be somehow ok. 45 */ 46 47 #define MSM_PIPE_NONE 0x00 48 #define MSM_PIPE_2D0 0x01 49 #define MSM_PIPE_2D1 0x02 50 #define MSM_PIPE_3D0 0x10 51 52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 53 * the upper 16 bits (which could be extended further, if needed, maybe 54 * we extend/overload the pipe-id some day to deal with multiple rings, 55 * but even then I don't think we need the full lower 16 bits). 56 */ 57 #define MSM_PIPE_ID_MASK 0xffff 58 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 59 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 60 61 /* timeouts are specified in clock-monotonic absolute times (to simplify 62 * restarting interrupted ioctls). The following struct is logically the 63 * same as 'struct timespec' but 32/64b ABI safe. 64 */ 65 struct drm_msm_timespec { 66 __s64 tv_sec; /* seconds */ 67 __s64 tv_nsec; /* nanoseconds */ 68 }; 69 70 /* Below "RO" indicates a read-only param, "WO" indicates write-only, and 71 * "RW" indicates a param that can be both read (GET_PARAM) and written 72 * (SET_PARAM) 73 */ 74 #define MSM_PARAM_GPU_ID 0x01 /* RO */ 75 #define MSM_PARAM_GMEM_SIZE 0x02 /* RO */ 76 #define MSM_PARAM_CHIP_ID 0x03 /* RO */ 77 #define MSM_PARAM_MAX_FREQ 0x04 /* RO */ 78 #define MSM_PARAM_TIMESTAMP 0x05 /* RO */ 79 #define MSM_PARAM_GMEM_BASE 0x06 /* RO */ 80 #define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */ 81 #define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */ 82 #define MSM_PARAM_FAULTS 0x09 /* RO */ 83 #define MSM_PARAM_SUSPENDS 0x0a /* RO */ 84 #define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */ 85 #define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */ 86 #define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */ 87 #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ 88 #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ 89 #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ 90 #define MSM_PARAM_RAYTRACING 0x11 /* RO */ 91 #define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */ 92 #define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */ 93 #define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */ 94 /* PRR (Partially Resident Region) is required for sparse residency: */ 95 #define MSM_PARAM_HAS_PRR 0x15 /* RO */ 96 /* MSM_PARAM_EN_VM_BIND is set to 1 to enable VM_BIND ops. 97 * 98 * With VM_BIND enabled, userspace is required to allocate iova and use the 99 * VM_BIND ops for map/unmap ioctls. MSM_INFO_SET_IOVA and MSM_INFO_GET_IOVA 100 * will be rejected. (The latter does not have a sensible meaning when a BO 101 * can have multiple and/or partial mappings.) 102 * 103 * With VM_BIND enabled, userspace does not include a submit_bo table in the 104 * SUBMIT ioctl (this will be rejected), the resident set is determined by 105 * the the VM_BIND ops. 106 * 107 * Enabling VM_BIND will fail on devices which do not have per-process pgtables. 108 * And it is not allowed to disable VM_BIND once it has been enabled. 109 * 110 * Enabling VM_BIND should be done (attempted) prior to allocating any BOs or 111 * submitqueues of type MSM_SUBMITQUEUE_VM_BIND. 112 * 113 * Relatedly, when VM_BIND mode is enabled, the kernel will not try to recover 114 * from GPU faults or failed async VM_BIND ops, in particular because it is 115 * difficult to communicate to userspace which op failed so that userspace 116 * could rewind and try again. When the VM is marked unusable, the SUBMIT 117 * ioctl will throw -EPIPE. 118 */ 119 #define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */ 120 121 /* For backwards compat. The original support for preemption was based on 122 * a single ring per priority level so # of priority levels equals the # 123 * of rings. With drm/scheduler providing additional levels of priority, 124 * the number of priorities is greater than the # of rings. The param is 125 * renamed to better reflect this. 126 */ 127 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 128 129 struct drm_msm_param { 130 __u32 pipe; /* in, MSM_PIPE_x */ 131 __u32 param; /* in, MSM_PARAM_x */ 132 __u64 value; /* out (get_param) or in (set_param) */ 133 __u32 len; /* zero for non-pointer params */ 134 __u32 pad; /* must be zero */ 135 }; 136 137 /* 138 * GEM buffers: 139 */ 140 141 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 142 #define MSM_BO_GPU_READONLY 0x00000002 143 /* Private buffers do not need to be explicitly listed in the SUBMIT 144 * ioctl, unless referenced by a drm_msm_gem_submit_cmd. Private 145 * buffers may NOT be imported/exported or used for scanout (or any 146 * other situation where buffers can be indefinitely pinned, but 147 * cases other than scanout are all kernel owned BOs which are not 148 * visible to userspace). 149 * 150 * In exchange for those constraints, all private BOs associated with 151 * a single context (drm_file) share a single dma_resv, and if there 152 * has been no eviction since the last submit, there are no per-BO 153 * bookeeping to do, significantly cutting the SUBMIT overhead. 154 */ 155 #define MSM_BO_NO_SHARE 0x00000004 156 #define MSM_BO_CACHE_MASK 0x000f0000 157 /* cache modes */ 158 #define MSM_BO_CACHED 0x00010000 159 #define MSM_BO_WC 0x00020000 160 #define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */ 161 #define MSM_BO_CACHED_COHERENT 0x080000 162 163 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 164 MSM_BO_GPU_READONLY | \ 165 MSM_BO_NO_SHARE | \ 166 MSM_BO_CACHE_MASK) 167 168 struct drm_msm_gem_new { 169 __u64 size; /* in */ 170 __u32 flags; /* in, mask of MSM_BO_x */ 171 __u32 handle; /* out */ 172 }; 173 174 /* Get or set GEM buffer info. The requested value can be passed 175 * directly in 'value', or for data larger than 64b 'value' is a 176 * pointer to userspace buffer, with 'len' specifying the number of 177 * bytes copied into that buffer. For info returned by pointer, 178 * calling the GEM_INFO ioctl with null 'value' will return the 179 * required buffer size in 'len' 180 */ 181 #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */ 182 #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */ 183 #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */ 184 #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */ 185 #define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */ 186 #define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */ 187 #define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */ 188 #define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */ 189 190 struct drm_msm_gem_info { 191 __u32 handle; /* in */ 192 __u32 info; /* in - one of MSM_INFO_* */ 193 __u64 value; /* in or out */ 194 __u32 len; /* in or out */ 195 __u32 pad; 196 }; 197 198 #define MSM_PREP_READ 0x01 199 #define MSM_PREP_WRITE 0x02 200 #define MSM_PREP_NOSYNC 0x04 201 #define MSM_PREP_BOOST 0x08 202 203 #define MSM_PREP_FLAGS (MSM_PREP_READ | \ 204 MSM_PREP_WRITE | \ 205 MSM_PREP_NOSYNC | \ 206 MSM_PREP_BOOST | \ 207 0) 208 209 struct drm_msm_gem_cpu_prep { 210 __u32 handle; /* in */ 211 __u32 op; /* in, mask of MSM_PREP_x */ 212 struct drm_msm_timespec timeout; /* in */ 213 }; 214 215 struct drm_msm_gem_cpu_fini { 216 __u32 handle; /* in */ 217 }; 218 219 /* 220 * Cmdstream Submission: 221 */ 222 223 #define MSM_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */ 224 #define MSM_SYNCOBJ_FLAGS ( \ 225 MSM_SYNCOBJ_RESET | \ 226 0) 227 228 struct drm_msm_syncobj { 229 __u32 handle; /* in, syncobj handle. */ 230 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */ 231 __u64 point; /* in, timepoint for timeline syncobjs. */ 232 }; 233 234 /* The value written into the cmdstream is logically: 235 * 236 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 237 * 238 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 239 * with this by emit'ing two reloc entries with appropriate shift 240 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 241 * 242 * NOTE that reloc's must be sorted by order of increasing submit_offset, 243 * otherwise EINVAL. 244 */ 245 struct drm_msm_gem_submit_reloc { 246 __u32 submit_offset; /* in, offset from submit_bo */ 247 #ifdef __cplusplus 248 __u32 _or; /* in, value OR'd with result */ 249 #else 250 __u32 or; /* in, value OR'd with result */ 251 #endif 252 __s32 shift; /* in, amount of left shift (can be negative) */ 253 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 254 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 255 }; 256 257 /* submit-types: 258 * BUF - this cmd buffer is executed normally. 259 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 260 * processed normally, but the kernel does not setup an IB to 261 * this buffer in the first-level ringbuffer 262 * CTX_RESTORE_BUF - only executed if there has been a GPU context 263 * switch since the last SUBMIT ioctl 264 */ 265 #define MSM_SUBMIT_CMD_BUF 0x0001 266 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 267 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 268 struct drm_msm_gem_submit_cmd { 269 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 270 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 271 __u32 submit_offset; /* in, offset into submit_bo */ 272 __u32 size; /* in, cmdstream size */ 273 __u32 pad; 274 __u32 nr_relocs; /* in, number of submit_reloc's */ 275 union { 276 __u64 relocs; /* in, ptr to array of submit_reloc's */ 277 __u64 iova; /* cmdstream address (for VM_BIND contexts) */ 278 }; 279 }; 280 281 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 282 * cmdstream buffer(s) themselves or reloc entries) has one (and only 283 * one) entry in the submit->bos[] table. 284 * 285 * As a optimization, the current buffer (gpu virtual address) can be 286 * passed back through the 'presumed' field. If on a subsequent reloc, 287 * userspace passes back a 'presumed' address that is still valid, 288 * then patching the cmdstream for this entry is skipped. This can 289 * avoid kernel needing to map/access the cmdstream bo in the common 290 * case. 291 */ 292 #define MSM_SUBMIT_BO_READ 0x0001 293 #define MSM_SUBMIT_BO_WRITE 0x0002 294 #define MSM_SUBMIT_BO_DUMP 0x0004 295 #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008 296 297 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \ 298 MSM_SUBMIT_BO_WRITE | \ 299 MSM_SUBMIT_BO_DUMP | \ 300 MSM_SUBMIT_BO_NO_IMPLICIT) 301 302 struct drm_msm_gem_submit_bo { 303 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 304 __u32 handle; /* in, GEM handle */ 305 __u64 presumed; /* in/out, presumed buffer address */ 306 }; 307 308 /* Valid submit ioctl flags: */ 309 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 310 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 311 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 312 #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */ 313 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */ 314 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */ 315 #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */ 316 #define MSM_SUBMIT_FLAGS ( \ 317 MSM_SUBMIT_NO_IMPLICIT | \ 318 MSM_SUBMIT_FENCE_FD_IN | \ 319 MSM_SUBMIT_FENCE_FD_OUT | \ 320 MSM_SUBMIT_SUDO | \ 321 MSM_SUBMIT_SYNCOBJ_IN | \ 322 MSM_SUBMIT_SYNCOBJ_OUT | \ 323 MSM_SUBMIT_FENCE_SN_IN | \ 324 0) 325 326 /* Each cmdstream submit consists of a table of buffers involved, and 327 * one or more cmdstream buffers. This allows for conditional execution 328 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 329 */ 330 struct drm_msm_gem_submit { 331 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 332 __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */ 333 __u32 nr_bos; /* in, number of submit_bo's */ 334 __u32 nr_cmds; /* in, number of submit_cmd's */ 335 __u64 bos; /* in, ptr to array of submit_bo's */ 336 __u64 cmds; /* in, ptr to array of submit_cmd's */ 337 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 338 __u32 queueid; /* in, submitqueue id */ 339 __u64 in_syncobjs; /* in, ptr to array of drm_msm_syncobj */ 340 __u64 out_syncobjs; /* in, ptr to array of drm_msm_syncobj */ 341 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */ 342 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */ 343 __u32 syncobj_stride; /* in, stride of syncobj arrays. */ 344 __u32 pad; /*in, reserved for future use, always 0. */ 345 }; 346 347 #define MSM_VM_BIND_OP_UNMAP 0 348 #define MSM_VM_BIND_OP_MAP 1 349 #define MSM_VM_BIND_OP_MAP_NULL 2 350 351 #define MSM_VM_BIND_OP_DUMP 1 352 #define MSM_VM_BIND_OP_FLAGS ( \ 353 MSM_VM_BIND_OP_DUMP | \ 354 0) 355 356 /** 357 * struct drm_msm_vm_bind_op - bind/unbind op to run 358 */ 359 struct drm_msm_vm_bind_op { 360 /** @op: one of MSM_VM_BIND_OP_x */ 361 __u32 op; 362 /** @handle: GEM object handle, MBZ for UNMAP or MAP_NULL */ 363 __u32 handle; 364 /** @obj_offset: Offset into GEM object, MBZ for UNMAP or MAP_NULL */ 365 __u64 obj_offset; 366 /** @iova: Address to operate on */ 367 __u64 iova; 368 /** @range: Number of bites to to map/unmap */ 369 __u64 range; 370 /** @flags: Bitmask of MSM_VM_BIND_OP_FLAG_x */ 371 __u32 flags; 372 /** @pad: MBZ */ 373 __u32 pad; 374 }; 375 376 #define MSM_VM_BIND_FENCE_FD_IN 0x00000001 377 #define MSM_VM_BIND_FENCE_FD_OUT 0x00000002 378 #define MSM_VM_BIND_FLAGS ( \ 379 MSM_VM_BIND_FENCE_FD_IN | \ 380 MSM_VM_BIND_FENCE_FD_OUT | \ 381 0) 382 383 /** 384 * struct drm_msm_vm_bind - Input of &DRM_IOCTL_MSM_VM_BIND 385 */ 386 struct drm_msm_vm_bind { 387 /** @flags: in, bitmask of MSM_VM_BIND_x */ 388 __u32 flags; 389 /** @nr_ops: the number of bind ops in this ioctl */ 390 __u32 nr_ops; 391 /** @fence_fd: in/out fence fd (see MSM_VM_BIND_FENCE_FD_IN/OUT) */ 392 __s32 fence_fd; 393 /** @queue_id: in, submitqueue id */ 394 __u32 queue_id; 395 /** @in_syncobjs: in, ptr to array of drm_msm_gem_syncobj */ 396 __u64 in_syncobjs; 397 /** @out_syncobjs: in, ptr to array of drm_msm_gem_syncobj */ 398 __u64 out_syncobjs; 399 /** @nr_in_syncobjs: in, number of entries in in_syncobj */ 400 __u32 nr_in_syncobjs; 401 /** @nr_out_syncobjs: in, number of entries in out_syncobj */ 402 __u32 nr_out_syncobjs; 403 /** @syncobj_stride: in, stride of syncobj arrays */ 404 __u32 syncobj_stride; 405 /** @op_stride: sizeof each struct drm_msm_vm_bind_op in @ops */ 406 __u32 op_stride; 407 union { 408 /** @op: used if num_ops == 1 */ 409 struct drm_msm_vm_bind_op op; 410 /** @ops: userptr to array of drm_msm_vm_bind_op if num_ops > 1 */ 411 __u64 ops; 412 }; 413 }; 414 415 #define MSM_WAIT_FENCE_BOOST 0x00000001 416 #define MSM_WAIT_FENCE_FLAGS ( \ 417 MSM_WAIT_FENCE_BOOST | \ 418 0) 419 420 /* The normal way to synchronize with the GPU is just to CPU_PREP on 421 * a buffer if you need to access it from the CPU (other cmdstream 422 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 423 * handle the required synchronization under the hood). This ioctl 424 * mainly just exists as a way to implement the gallium pipe_fence 425 * APIs without requiring a dummy bo to synchronize on. 426 */ 427 struct drm_msm_wait_fence { 428 __u32 fence; /* in */ 429 __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ 430 struct drm_msm_timespec timeout; /* in */ 431 __u32 queueid; /* in, submitqueue id */ 432 }; 433 434 /* madvise provides a way to tell the kernel in case a buffers contents 435 * can be discarded under memory pressure, which is useful for userspace 436 * bo cache where we want to optimistically hold on to buffer allocate 437 * and potential mmap, but allow the pages to be discarded under memory 438 * pressure. 439 * 440 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 441 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 442 * In the WILLNEED case, 'retained' indicates to userspace whether the 443 * backing pages still exist. 444 */ 445 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 446 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 447 #define __MSM_MADV_PURGED 2 /* internal state */ 448 449 struct drm_msm_gem_madvise { 450 __u32 handle; /* in, GEM handle */ 451 __u32 madv; /* in, MSM_MADV_x */ 452 __u32 retained; /* out, whether backing store still exists */ 453 }; 454 455 /* 456 * Draw queues allow the user to set specific submission parameter. Command 457 * submissions specify a specific submitqueue to use. ID 0 is reserved for 458 * backwards compatibility as a "default" submitqueue. 459 * 460 * Because VM_BIND async updates happen on the CPU, they must run on a 461 * virtual queue created with the flag MSM_SUBMITQUEUE_VM_BIND. If we had 462 * a way to do pgtable updates on the GPU, we could drop this restriction. 463 */ 464 465 #define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 466 #define MSM_SUBMITQUEUE_VM_BIND 0x00000002 /* virtual queue for VM_BIND ops */ 467 468 #define MSM_SUBMITQUEUE_FLAGS ( \ 469 MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ 470 MSM_SUBMITQUEUE_VM_BIND | \ 471 0) 472 473 /* 474 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, 475 * a lower numeric value is higher priority. 476 */ 477 struct drm_msm_submitqueue { 478 __u32 flags; /* in, MSM_SUBMITQUEUE_x */ 479 __u32 prio; /* in, Priority level */ 480 __u32 id; /* out, identifier */ 481 }; 482 483 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 484 485 struct drm_msm_submitqueue_query { 486 __u64 data; 487 __u32 id; 488 __u32 param; 489 __u32 len; 490 __u32 pad; 491 }; 492 493 #define DRM_MSM_GET_PARAM 0x00 494 #define DRM_MSM_SET_PARAM 0x01 495 #define DRM_MSM_GEM_NEW 0x02 496 #define DRM_MSM_GEM_INFO 0x03 497 #define DRM_MSM_GEM_CPU_PREP 0x04 498 #define DRM_MSM_GEM_CPU_FINI 0x05 499 #define DRM_MSM_GEM_SUBMIT 0x06 500 #define DRM_MSM_WAIT_FENCE 0x07 501 #define DRM_MSM_GEM_MADVISE 0x08 502 /* placeholder: 503 #define DRM_MSM_GEM_SVM_NEW 0x09 504 */ 505 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 506 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 507 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 508 #define DRM_MSM_VM_BIND 0x0D 509 510 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 511 #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) 512 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 513 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 514 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 515 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 516 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 517 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 518 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 519 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 520 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 521 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 522 #define DRM_IOCTL_MSM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind) 523 524 #if defined(__cplusplus) 525 } 526 #endif 527 528 #endif /* __MSM_DRM_H__ */ 529