1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/pm.h> 9 #include <linux/types.h> 10 11 #include <linux/pinctrl/pinctrl.h> 12 13 struct platform_device; 14 15 struct pinctrl_pin_desc; 16 17 #define APQ_PIN_FUNCTION(fname) \ 18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 19 fname##_groups, \ 20 ARRAY_SIZE(fname##_groups)) 21 22 #define IPQ_PIN_FUNCTION(fname) \ 23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 24 fname##_groups, \ 25 ARRAY_SIZE(fname##_groups)) 26 27 #define MSM_PIN_FUNCTION(fname) \ 28 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 29 fname##_groups, \ 30 ARRAY_SIZE(fname##_groups)) 31 32 #define MSM_GPIO_PIN_FUNCTION(fname) \ 33 [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 34 fname##_groups, \ 35 ARRAY_SIZE(fname##_groups)) 36 37 #define QCA_PIN_FUNCTION(fname) \ 38 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 39 fname##_groups, \ 40 ARRAY_SIZE(fname##_groups)) 41 42 #define QCA_GPIO_PIN_FUNCTION(fname) \ 43 [qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 44 fname##_groups, \ 45 ARRAY_SIZE(fname##_groups)) 46 47 /** 48 * struct msm_pingroup - Qualcomm pingroup definition 49 * @grp: Generic data of the pin group (name and pins) 50 * @funcs: A list of pinmux functions that can be selected for 51 * this group. The index of the selected function is used 52 * for programming the function selector. 53 * Entries should be indices into the groups list of the 54 * struct msm_pinctrl_soc_data. 55 * @ctl_reg: Offset of the register holding control bits for this group. 56 * @io_reg: Offset of the register holding input/output bits for this group. 57 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 58 * @intr_status_reg: Offset of the register holding the status bits for this group. 59 * @intr_target_reg: Offset of the register specifying routing of the interrupts 60 * from this group. On most SoCs this register is the same as 61 * @intr_cfg_reg; leaving this field as zero causes the driver 62 * to fall back to @intr_cfg_reg automatically. Only set this 63 * explicitly on older SoCs where the interrupt target routing 64 * lives in a separate register (e.g. APQ8064, MSM8960). 65 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 66 * @pull_bit: Offset in @ctl_reg for the bias configuration. 67 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 68 * @od_bit: Offset in @ctl_reg for controlling open drain. 69 * @oe_bit: Offset in @ctl_reg for controlling output enable. 70 * @in_bit: Offset in @io_reg for the input bit value. 71 * @out_bit: Offset in @io_reg for the output bit value. 72 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 73 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 74 * status. 75 * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate 76 * wakeup events. 77 * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO. 78 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 79 * @intr_target_width: Number of bits used for specifying interrupt routing target. 80 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 81 * this gpio should get routed to the KPSS processor. 82 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 83 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 84 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 85 * @intr_detection_width: Number of bits used for specifying interrupt type, 86 * Should be 2 for SoCs that can detect both edges in hardware, 87 * otherwise 1. 88 */ 89 struct msm_pingroup { 90 struct pingroup grp; 91 92 unsigned *funcs; 93 unsigned nfuncs; 94 95 u32 ctl_reg; 96 u32 io_reg; 97 u32 intr_cfg_reg; 98 u32 intr_status_reg; 99 u32 intr_target_reg; 100 101 unsigned int tile:2; 102 103 unsigned mux_bit:5; 104 105 unsigned pull_bit:5; 106 unsigned drv_bit:5; 107 unsigned i2c_pull_bit:5; 108 109 unsigned od_bit:5; 110 unsigned egpio_enable:5; 111 unsigned egpio_present:5; 112 unsigned oe_bit:5; 113 unsigned in_bit:5; 114 unsigned out_bit:5; 115 116 unsigned intr_enable_bit:5; 117 unsigned intr_status_bit:5; 118 unsigned intr_ack_high:1; 119 120 unsigned intr_wakeup_present_bit:5; 121 unsigned intr_wakeup_enable_bit:5; 122 unsigned intr_target_bit:5; 123 unsigned intr_target_width:5; 124 unsigned intr_target_kpss_val:5; 125 unsigned intr_raw_status_bit:5; 126 unsigned intr_polarity_bit:5; 127 unsigned intr_detection_bit:5; 128 unsigned intr_detection_width:5; 129 }; 130 131 /** 132 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 133 * @gpio: The GPIOs that are wakeup capable 134 * @wakeirq: The interrupt at the always-on interrupt controller 135 */ 136 struct msm_gpio_wakeirq_map { 137 unsigned int gpio; 138 unsigned int wakeirq; 139 }; 140 141 /** 142 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 143 * @pins: An array describing all pins the pin controller affects. 144 * @npins: The number of entries in @pins. 145 * @functions: An array describing all mux functions the SoC supports. 146 * @nfunctions: The number of entries in @functions. 147 * @groups: An array describing all pin groups the pin SoC supports. 148 * @ngroups: The numbmer of entries in @groups. 149 * @ngpio: The number of pingroups the driver should expose as GPIOs. 150 * @pull_no_keeper: The SoC does not support keeper bias. 151 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 152 * @nwakeirq_map: The number of entries in @wakeirq_map 153 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 154 * to be aware that their parent can't handle dual 155 * edge interrupts. 156 * @gpio_func: Which function number is GPIO (usually 0). 157 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 158 * hardware this is a mux 1-level above the TLMM, we'll treat 159 * it as if this is just another mux state of the TLMM. Since 160 * it doesn't really map to hardware, we'll allocate a virtual 161 * function number for eGPIO and any time we see that function 162 * number used we'll treat it as a request to mux away from 163 * our TLMM towards another owner. 164 */ 165 struct msm_pinctrl_soc_data { 166 const struct pinctrl_pin_desc *pins; 167 unsigned npins; 168 const struct pinfunction *functions; 169 unsigned nfunctions; 170 const struct msm_pingroup *groups; 171 unsigned ngroups; 172 unsigned ngpios; 173 bool pull_no_keeper; 174 const char *const *tiles; 175 unsigned int ntiles; 176 const int *reserved_gpios; 177 const struct msm_gpio_wakeirq_map *wakeirq_map; 178 unsigned int nwakeirq_map; 179 bool wakeirq_dual_edge_errata; 180 unsigned int gpio_func; 181 unsigned int egpio_func; 182 }; 183 184 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 185 186 int msm_pinctrl_probe(struct platform_device *pdev, 187 const struct msm_pinctrl_soc_data *soc_data); 188 189 #endif 190