1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2012-2013 Renesas Solutions Corp.
4 * Copyright (C) 2013 Magnus Damm
5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 */
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/pinctrl/pinconf-generic.h>
10
11 #include "sh_pfc.h"
12
13 #define CPU_ALL_PORT(fn, pfx, sfx) \
14 /* Port0 - Port30 */ \
15 PORT_10(0, fn, pfx, sfx), \
16 PORT_10(10, fn, pfx##1, sfx), \
17 PORT_10(20, fn, pfx##2, sfx), \
18 PORT_1(30, fn, pfx##30, sfx), \
19 /* Port32 - Port40 */ \
20 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
21 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
22 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
23 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
24 PORT_1(40, fn, pfx##40, sfx), \
25 /* Port64 - Port85 */ \
26 PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
27 PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
28 PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
29 PORT_10(70, fn, pfx##7, sfx), \
30 PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
31 PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
32 PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
33 /* Port96 - Port126 */ \
34 PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
35 PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
36 PORT_10(100, fn, pfx##10, sfx), \
37 PORT_10(110, fn, pfx##11, sfx), \
38 PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
39 PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
40 PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
41 PORT_1(126, fn, pfx##126, sfx), \
42 /* Port128 - Port134 */ \
43 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
44 PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
45 PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
46 PORT_1(134, fn, pfx##134, sfx), \
47 /* Port160 - Port178 */ \
48 PORT_10(160, fn, pfx##16, sfx), \
49 PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
50 PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
51 PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
52 PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
53 PORT_1(178, fn, pfx##178, sfx), \
54 /* Port192 - Port222 */ \
55 PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
56 PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
57 PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
58 PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
59 PORT_10(200, fn, pfx##20, sfx), \
60 PORT_10(210, fn, pfx##21, sfx), \
61 PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
62 PORT_1(222, fn, pfx##222, sfx), \
63 /* Port224 - Port250 */ \
64 PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
65 PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
66 PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
67 PORT_10(230, fn, pfx##23, sfx), \
68 PORT_10(240, fn, pfx##24, sfx), \
69 PORT_1(250, fn, pfx##250, sfx), \
70 /* Port256 - Port283 */ \
71 PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
72 PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
73 PORT_10(260, fn, pfx##26, sfx), \
74 PORT_10(270, fn, pfx##27, sfx), \
75 PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
76 PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
77 /* Port288 - Port308 */ \
78 PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
79 PORT_10(290, fn, pfx##29, sfx), \
80 PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
81 PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
82 PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
83 PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
84 PORT_1(308, fn, pfx##308, sfx), \
85 /* Port320 - Port329 */ \
86 PORT_10(320, fn, pfx##32, sfx)
87
88
89 enum {
90 PINMUX_RESERVED = 0,
91
92 /* PORT0_DATA -> PORT329_DATA */
93 PINMUX_DATA_BEGIN,
94 PORT_ALL(DATA),
95 PINMUX_DATA_END,
96
97 /* PORT0_IN -> PORT329_IN */
98 PINMUX_INPUT_BEGIN,
99 PORT_ALL(IN),
100 PINMUX_INPUT_END,
101
102 /* PORT0_OUT -> PORT329_OUT */
103 PINMUX_OUTPUT_BEGIN,
104 PORT_ALL(OUT),
105 PINMUX_OUTPUT_END,
106
107 PINMUX_FUNCTION_BEGIN,
108 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
109 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
110 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
111 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
112 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
113 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
114 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
115 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
116 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
117 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
118
119 MSEL1CR_31_0, MSEL1CR_31_1,
120 MSEL1CR_27_0, MSEL1CR_27_1,
121 MSEL1CR_25_0, MSEL1CR_25_1,
122 MSEL1CR_24_0, MSEL1CR_24_1,
123 MSEL1CR_22_0, MSEL1CR_22_1,
124 MSEL1CR_21_0, MSEL1CR_21_1,
125 MSEL1CR_20_0, MSEL1CR_20_1,
126 MSEL1CR_19_0, MSEL1CR_19_1,
127 MSEL1CR_18_0, MSEL1CR_18_1,
128 MSEL1CR_17_0, MSEL1CR_17_1,
129 MSEL1CR_16_0, MSEL1CR_16_1,
130 MSEL1CR_15_0, MSEL1CR_15_1,
131 MSEL1CR_14_0, MSEL1CR_14_1,
132 MSEL1CR_13_0, MSEL1CR_13_1,
133 MSEL1CR_12_0, MSEL1CR_12_1,
134 MSEL1CR_11_0, MSEL1CR_11_1,
135 MSEL1CR_10_0, MSEL1CR_10_1,
136 MSEL1CR_09_0, MSEL1CR_09_1,
137 MSEL1CR_08_0, MSEL1CR_08_1,
138 MSEL1CR_07_0, MSEL1CR_07_1,
139 MSEL1CR_06_0, MSEL1CR_06_1,
140 MSEL1CR_05_0, MSEL1CR_05_1,
141 MSEL1CR_04_0, MSEL1CR_04_1,
142 MSEL1CR_03_0, MSEL1CR_03_1,
143 MSEL1CR_02_0, MSEL1CR_02_1,
144 MSEL1CR_01_0, MSEL1CR_01_1,
145 MSEL1CR_00_0, MSEL1CR_00_1,
146
147 MSEL3CR_31_0, MSEL3CR_31_1,
148 MSEL3CR_28_0, MSEL3CR_28_1,
149 MSEL3CR_27_0, MSEL3CR_27_1,
150 MSEL3CR_26_0, MSEL3CR_26_1,
151 MSEL3CR_23_0, MSEL3CR_23_1,
152 MSEL3CR_22_0, MSEL3CR_22_1,
153 MSEL3CR_21_0, MSEL3CR_21_1,
154 MSEL3CR_20_0, MSEL3CR_20_1,
155 MSEL3CR_19_0, MSEL3CR_19_1,
156 MSEL3CR_18_0, MSEL3CR_18_1,
157 MSEL3CR_17_0, MSEL3CR_17_1,
158 MSEL3CR_16_0, MSEL3CR_16_1,
159 MSEL3CR_15_0, MSEL3CR_15_1,
160 MSEL3CR_12_0, MSEL3CR_12_1,
161 MSEL3CR_11_0, MSEL3CR_11_1,
162 MSEL3CR_10_0, MSEL3CR_10_1,
163 MSEL3CR_09_0, MSEL3CR_09_1,
164 MSEL3CR_06_0, MSEL3CR_06_1,
165 MSEL3CR_03_0, MSEL3CR_03_1,
166 MSEL3CR_01_0, MSEL3CR_01_1,
167 MSEL3CR_00_0, MSEL3CR_00_1,
168
169 MSEL4CR_30_0, MSEL4CR_30_1,
170 MSEL4CR_29_0, MSEL4CR_29_1,
171 MSEL4CR_28_0, MSEL4CR_28_1,
172 MSEL4CR_27_0, MSEL4CR_27_1,
173 MSEL4CR_26_0, MSEL4CR_26_1,
174 MSEL4CR_25_0, MSEL4CR_25_1,
175 MSEL4CR_24_0, MSEL4CR_24_1,
176 MSEL4CR_23_0, MSEL4CR_23_1,
177 MSEL4CR_22_0, MSEL4CR_22_1,
178 MSEL4CR_21_0, MSEL4CR_21_1,
179 MSEL4CR_20_0, MSEL4CR_20_1,
180 MSEL4CR_19_0, MSEL4CR_19_1,
181 MSEL4CR_18_0, MSEL4CR_18_1,
182 MSEL4CR_17_0, MSEL4CR_17_1,
183 MSEL4CR_16_0, MSEL4CR_16_1,
184 MSEL4CR_15_0, MSEL4CR_15_1,
185 MSEL4CR_14_0, MSEL4CR_14_1,
186 MSEL4CR_13_0, MSEL4CR_13_1,
187 MSEL4CR_12_0, MSEL4CR_12_1,
188 MSEL4CR_11_0, MSEL4CR_11_1,
189 MSEL4CR_10_0, MSEL4CR_10_1,
190 MSEL4CR_09_0, MSEL4CR_09_1,
191 MSEL4CR_07_0, MSEL4CR_07_1,
192 MSEL4CR_04_0, MSEL4CR_04_1,
193 MSEL4CR_01_0, MSEL4CR_01_1,
194
195 MSEL5CR_31_0, MSEL5CR_31_1,
196 MSEL5CR_30_0, MSEL5CR_30_1,
197 MSEL5CR_29_0, MSEL5CR_29_1,
198 MSEL5CR_28_0, MSEL5CR_28_1,
199 MSEL5CR_27_0, MSEL5CR_27_1,
200 MSEL5CR_26_0, MSEL5CR_26_1,
201 MSEL5CR_25_0, MSEL5CR_25_1,
202 MSEL5CR_24_0, MSEL5CR_24_1,
203 MSEL5CR_23_0, MSEL5CR_23_1,
204 MSEL5CR_22_0, MSEL5CR_22_1,
205 MSEL5CR_21_0, MSEL5CR_21_1,
206 MSEL5CR_20_0, MSEL5CR_20_1,
207 MSEL5CR_19_0, MSEL5CR_19_1,
208 MSEL5CR_18_0, MSEL5CR_18_1,
209 MSEL5CR_17_0, MSEL5CR_17_1,
210 MSEL5CR_16_0, MSEL5CR_16_1,
211 MSEL5CR_15_0, MSEL5CR_15_1,
212 MSEL5CR_14_0, MSEL5CR_14_1,
213 MSEL5CR_13_0, MSEL5CR_13_1,
214 MSEL5CR_12_0, MSEL5CR_12_1,
215 MSEL5CR_11_0, MSEL5CR_11_1,
216 MSEL5CR_10_0, MSEL5CR_10_1,
217 MSEL5CR_09_0, MSEL5CR_09_1,
218 MSEL5CR_08_0, MSEL5CR_08_1,
219 MSEL5CR_07_0, MSEL5CR_07_1,
220 MSEL5CR_06_0, MSEL5CR_06_1,
221
222 MSEL8CR_16_0, MSEL8CR_16_1,
223 MSEL8CR_01_0, MSEL8CR_01_1,
224 MSEL8CR_00_0, MSEL8CR_00_1,
225
226 PINMUX_FUNCTION_END,
227
228 PINMUX_MARK_BEGIN,
229
230
231 #define F1(a) a##_MARK
232 #define F2(a) a##_MARK
233 #define F3(a) a##_MARK
234 #define F4(a) a##_MARK
235 #define F5(a) a##_MARK
236 #define F6(a) a##_MARK
237 #define F7(a) a##_MARK
238 #define IRQ(a) IRQ##a##_MARK
239
240 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
241 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
242 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
243 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
244 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
245 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
246 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
247 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
248 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
249 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
250 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
251 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
252 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
253 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
254 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
255 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
256 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
257 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
258 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
259 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
260 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
261 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
262 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
263 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
264 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
265 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
266 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
267 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
268 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
269 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
270 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
271 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
272
273 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
274 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
275 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
276 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
277 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
278 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
279 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
280 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
281 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
282 F7(CHSCIF0_HSCK), /* Port40 */
283
284 F1(PDM0_DATA), /* Port64 */
285 F1(PDM1_DATA),
286 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
287 IRQ(40),
288 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
289 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
290 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
291 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
292 F7(CHSCIF1_HRTS), /* Port70 */
293 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
294 F7(CHSCIF1_HCTS),
295 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
296 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
297 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
298 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
299 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
300
301 F1(KEYIN0), /* Port96 */
302 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
303 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
304 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
305 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
306 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
307 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
308 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
309 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
310 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
311 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
312 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
313 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
314 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
315 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
316 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
317 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
318 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
319 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
320 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
321 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
322 F5(SIM0_VOLTSEL1), /* Port130 */
323 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
324 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
325 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
326 IRQ(20), /* Port160 */
327 IRQ(21), IRQ(22), IRQ(23),
328 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
329 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
330 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
331 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
332 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
333 F1(A9), F2(MMCD1_6), IRQ(32),
334 F1(A8), F2(MMCD1_5), IRQ(33),
335 F1(A7), F2(MMCD1_4), IRQ(34),
336 F1(A6), F2(MMCD1_3), IRQ(35),
337 F1(A5), F2(MMCD1_2), IRQ(36),
338 F1(A4), F2(MMCD1_1), IRQ(37),
339 F1(A3), F2(MMCD1_0), IRQ(38),
340 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
341 F1(A1),
342 F1(A0), F2(BS),
343 F1(CKO), F2(MMCCLK1),
344 F1(CS0_N), F5(SIM0_GPO1),
345 F1(CS2_N), F5(SIM0_GPO2),
346 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
347 F1(D15), F5(GIO_OUT15),
348 F1(D14), F5(GIO_OUT14),
349 F1(D13), F5(GIO_OUT13),
350 F1(D12), F5(GIO_OUT12), /* Port210 */
351 F1(D11), F5(WGM_TXP2),
352 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
353 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
354 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
355 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
356 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
357 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
358 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
359 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
360 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
361 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
362 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
363 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
364 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
365 F1(WE0_N), F2(RDWR_227),
366 F1(WE1_N), F5(SIM0_GPO0),
367 F1(PWMO), F2(VIO_CKO1_229),
368 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
369 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
370 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
371 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
372 F1(FSIAISLD), F2(PDM3_DATA_235),
373 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
374 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
375 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
376 F1(FSIBISLD), /* Port240 */
377 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
378 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
379 F1(FSIBCK), F3(ISP_SHUTTER0_245),
380 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
381 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
382 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
383 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
384 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
385 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
386 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
387 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
388 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
389 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
390 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
391 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
392 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
393 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
394 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
395 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
396 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
397 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
398 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
399 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
400 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
401 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
402 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
403 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
404 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
405 F4(MSIOF6_SS1), /* Port300 */
406 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
407 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
408 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
409 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
410 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
411 IRQ(55), IRQ(56), IRQ(57),
412 PINMUX_MARK_END,
413 };
414
415 static const u16 pinmux_data[] = {
416 /* specify valid pin states for each pin in GPIO mode */
417 PINMUX_DATA_ALL(),
418
419 /* Port0 */
420 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
421 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
422 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
423 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
424
425 /* Port1 */
426 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
427 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
428 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
429 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
430
431 /* Port2 */
432 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
433 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
434 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
435 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
436
437 /* Port3 */
438 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
439 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
440 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
441 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
442
443 /* Port4 */
444 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
445 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
446 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
447 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
448
449 /* Port5 */
450 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
451 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
452 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
453 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
454
455 /* Port6 */
456 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
457 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
458 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
459 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
460
461 /* Port7 */
462 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
463 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
464 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
465 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
466
467 /* Port8 */
468 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
469 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
470 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
471 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
472
473 /* Port9 */
474 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
475 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
476 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
477 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
478
479 /* Port10 */
480 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
481 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
482 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
483 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
484
485 /* Port11 */
486 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
487 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
488 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
489 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
490
491 /* Port12 */
492 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
493 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
494 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
495 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
496
497 /* Port13 */
498 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
499 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
500 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
501 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
502 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
503
504 /* Port14 */
505 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
506 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
507 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
508 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
509 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
510
511 /* Port15 */
512 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
513 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
514 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
515 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
516
517 /* Port16 */
518 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
519 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
520 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
521
522 /* Port17 */
523 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
524 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
525 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
526
527 /* Port18 */
528 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
529 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
530 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
531
532 /* Port19 */
533 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
534 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
535 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
536
537 /* Port20 */
538 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
539 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
540 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
541
542 /* Port21 */
543 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
544 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
545 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
546
547 /* Port22 */
548 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
549 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
550 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
551
552 /* Port23 */
553 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
554 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
555 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
556
557 /* Port24 */
558 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
559 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
560 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
561 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
562
563 /* Port25 */
564 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
565 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
566 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
567
568 /* Port26 */
569 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
570 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
571 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
572 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
573
574 /* Port27 */
575 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
576 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
577 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
578 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
579
580 /* Port28 */
581 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
582 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
583 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
584
585 /* Port29 */
586 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
587 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
588 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
589
590 /* Port30 */
591 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
592 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
593 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
594
595 /* Port32 */
596 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
597 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
598 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
599
600 /* Port33 */
601 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
602 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
603 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
604
605 /* Port34 */
606 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
607 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
608 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
609
610 /* Port35 */
611 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
612 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
613
614 /* Port36 */
615 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
616 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
617
618 /* Port37 */
619 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
620 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
621
622 /* Port38 */
623 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
624 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
625 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
626 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
627
628 /* Port39 */
629 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
630 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
631 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
632 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
633
634 /* Port40 */
635 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
636 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
637 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
638 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
639
640 /* Port64 */
641 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
642
643 /* Port65 */
644 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
645
646 /* Port66 */
647 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
648 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
649 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
650 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
651 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
652
653 /* Port67 */
654 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
655 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
656 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
657 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
658
659 /* Port68 */
660 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
661 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
662 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
663 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
664
665 /* Port69 */
666 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
667 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
668 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
669 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
670
671 /* Port70 */
672 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
673 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
674 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
675 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
676 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
677
678 /* Port71 */
679 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
680 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
681 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
682 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
683 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
684
685 /* Port72 */
686 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
687 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
688 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
689 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
690
691 /* Port73 */
692 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
693 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
694 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
695 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
696
697 /* Port74 - Port85 */
698 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
699 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
700 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
701 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
702 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
703 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
704 PINMUX_DATA(TXP_MARK, PORT80_FN1),
705 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
706 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
707 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
708 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
709 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
710
711 /* Port96 - Port101 */
712 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
713 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
714 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
715 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
716 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
717 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
718
719 /* Port102 */
720 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
721 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
722
723 /* Port103 */
724 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
725 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
726
727 /* Port104 - Port108 */
728 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
729 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
730 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
731 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
732 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
733
734 /* Port109 */
735 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
736 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
737
738 /* Port110 */
739 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
740 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
741
742 /* Port111 */
743 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
744 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
745 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
746
747 /* Port112 */
748 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
749 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
750 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
751 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
752
753 /* Port113 */
754 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
755 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
756 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
757 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
758
759 /* Port114 */
760 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
761 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
762 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
763 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
764
765 /* Port115 */
766 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
767 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
768 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
769 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
770
771 /* Port116 */
772 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
773 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
774
775 /* Port117 */
776 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
777 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
778
779 /* Port118 */
780 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
781 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
782
783 /* Port119 */
784 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
785 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
786
787 /* Port120 */
788 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
789 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
790 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
791
792 /* Port121 */
793 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
794 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
795
796 /* Port122 */
797 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
798 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
799
800 /* Port123 */
801 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
802 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
803
804 /* Port124 */
805 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
806
807 /* Port125 */
808 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
809 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
810 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
811 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
812
813 /* Port126 */
814 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
815 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
816 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
817
818 /* Port128 */
819 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
820 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
821 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
822 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
823
824 /* Port129 */
825 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
826 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
827 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
828
829 /* Port130 */
830 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
831 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
832 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
833 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
834
835 /* Port131 */
836 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
837 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
838
839 /* Port132 */
840 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
841 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
842 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
843
844 /* Port133 */
845 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
846 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
847 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
848 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
849
850 /* Port134 */
851 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
852 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
853 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
854
855 /* Port160 - Port178 */
856 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
857 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
858 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
859 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
860 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
861 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
862 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
863 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
864 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
865 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
866 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
867 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
868 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
869 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
870 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
871 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
872 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
873 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
874 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
875
876 /* Port192 - Port200 FN1 */
877 PINMUX_DATA(A10_MARK, PORT192_FN1),
878 PINMUX_DATA(A9_MARK, PORT193_FN1),
879 PINMUX_DATA(A8_MARK, PORT194_FN1),
880 PINMUX_DATA(A7_MARK, PORT195_FN1),
881 PINMUX_DATA(A6_MARK, PORT196_FN1),
882 PINMUX_DATA(A5_MARK, PORT197_FN1),
883 PINMUX_DATA(A4_MARK, PORT198_FN1),
884 PINMUX_DATA(A3_MARK, PORT199_FN1),
885 PINMUX_DATA(A2_MARK, PORT200_FN1),
886
887 /* Port192 - Port200 FN2 */
888 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
889 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
890 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
891 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
892 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
893 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
894 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
895 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
896 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
897
898 /* Port192 - Port200 IRQ */
899 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
900 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
901 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
902 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
903 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
904 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
905 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
906 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
907 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
908
909 /* Port201 */
910 PINMUX_DATA(A1_MARK, PORT201_FN1),
911
912 /* Port202 */
913 PINMUX_DATA(A0_MARK, PORT202_FN1),
914 PINMUX_DATA(BS_MARK, PORT202_FN2),
915
916 /* Port203 */
917 PINMUX_DATA(CKO_MARK, PORT203_FN1),
918 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
919
920 /* Port204 */
921 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
922 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
923
924 /* Port205 */
925 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
926 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
927
928 /* Port206 */
929 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
930 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
931 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
932
933 /* Port207 - Port212 FN1 */
934 PINMUX_DATA(D15_MARK, PORT207_FN1),
935 PINMUX_DATA(D14_MARK, PORT208_FN1),
936 PINMUX_DATA(D13_MARK, PORT209_FN1),
937 PINMUX_DATA(D12_MARK, PORT210_FN1),
938 PINMUX_DATA(D11_MARK, PORT211_FN1),
939 PINMUX_DATA(D10_MARK, PORT212_FN1),
940
941 /* Port207 - Port212 FN5 */
942 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
943 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
944 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
945 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
946 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
947 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
948
949 /* Port213 - Port222 FN1 */
950 PINMUX_DATA(D9_MARK, PORT213_FN1),
951 PINMUX_DATA(D8_MARK, PORT214_FN1),
952 PINMUX_DATA(D7_MARK, PORT215_FN1),
953 PINMUX_DATA(D6_MARK, PORT216_FN1),
954 PINMUX_DATA(D5_MARK, PORT217_FN1),
955 PINMUX_DATA(D4_MARK, PORT218_FN1),
956 PINMUX_DATA(D3_MARK, PORT219_FN1),
957 PINMUX_DATA(D2_MARK, PORT220_FN1),
958 PINMUX_DATA(D1_MARK, PORT221_FN1),
959 PINMUX_DATA(D0_MARK, PORT222_FN1),
960
961 /* Port213 - Port222 FN2 */
962 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
963 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
964 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
965 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
966 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
967 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
968 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
969 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
970 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
971 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
972
973 /* Port213 - Port222 FN5 */
974 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
975 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
976 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
977 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
978 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
979 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
980 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
981 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
982 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
983 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
984
985 /* Port224 */
986 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
987 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
988 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
989
990 /* Port225 */
991 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
992
993 /* Port226 */
994 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
995 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
996 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
997
998 /* Port227 */
999 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1000 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1001
1002 /* Port228 */
1003 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1004 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1005
1006 /* Port229 */
1007 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1008 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1009
1010 /* Port230 */
1011 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1012 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1013
1014 /* Port231 */
1015 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1016 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1017
1018 /* Port232 */
1019 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1020 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1021
1022 /* Port233 */
1023 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1024 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1025
1026 /* Port234 */
1027 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1028 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1029 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1030
1031 /* Port235 */
1032 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1033 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1034
1035 /* Port236 */
1036 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1037 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1038 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1039
1040 /* Port237 */
1041 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1042 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1043
1044 /* Port238 */
1045 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1046 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1047
1048 /* Port239 */
1049 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1050 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1051
1052 /* Port240 */
1053 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1054
1055 /* Port241 */
1056 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1057 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1058
1059 /* Port242 */
1060 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1061 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1062
1063 /* Port243 */
1064 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1065 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1066
1067 /* Port244 */
1068 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1069 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1070
1071 /* Port245 */
1072 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1073 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1074
1075 /* Port246 - Port250 FN1 */
1076 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1077 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1078 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1079 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1080 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1081
1082 /* Port256 - Port258 */
1083 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1084 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1085 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1086
1087 /* Port259 */
1088 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1089 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1090
1091 /* Port260 */
1092 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1093
1094 /* Port261 */
1095 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1096 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1097
1098 /* Port262 */
1099 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1100
1101 /* Port263 - Port266 FN1 */
1102 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1103 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1104 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1105 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1106
1107 /* Port263 - Port266 FN4 */
1108 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1109 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1110 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1111 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1112
1113 /* Port267 */
1114 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1115
1116 /* Port268 */
1117 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1118 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1119
1120 /* Port269 */
1121 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1122 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1123
1124 /* Port270 - Port273 FN1 */
1125 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1126 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1127 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1128 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1129
1130 /* Port270 - Port273 FN3 */
1131 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1132 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1133 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1134 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1135
1136 /* Port274 */
1137 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1138 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1139
1140 /* Port275 - Port280 */
1141 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1142 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1143 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1144 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1145 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1146 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1147
1148 /* Port281 */
1149 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1150 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1151
1152 /* Port282 */
1153 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1154 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1155
1156 /* Port283 */
1157 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1158
1159 /* Port289 */
1160 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1161 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1162
1163 /* Port290 */
1164 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1165 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1166 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1167
1168 /* Port291 - Port294 FN1 */
1169 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1170 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1171 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1172 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1173
1174 /* Port291 - Port294 FN3 */
1175 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1176 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1177 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1178 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1179
1180 /* Port295 */
1181 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1182 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1183 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1184 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1185
1186 /* Port296 */
1187 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1188 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1189 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1190
1191 /* Port297 - Port300 FN1 */
1192 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1193 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1194 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1195 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1196
1197 /* Port297 - Port300 FN2 */
1198 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1199 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1200 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1201 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1202
1203 /* Port297 - Port300 FN3 */
1204 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1205 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1206 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1207 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1208
1209 /* Port297 - Port300 FN4 */
1210 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1211 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1212 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1213 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1214
1215 /* Port301 */
1216 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1217 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1218
1219 /* Port302 - Port306 FN1 */
1220 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1221 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1222 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1223 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1224 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1225
1226 /* Port302 - Port306 FN3 */
1227 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1228 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1229 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1230 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1231 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1232
1233 /* Port307 */
1234 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1235
1236 /* Port308 */
1237 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1238 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1239
1240 /* Port320 - Port329 */
1241 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1242 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1243 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1244 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1245 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1246 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1247 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1248 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1249 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1250 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1251 };
1252
1253 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1254 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1255 #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
1256
1257 #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1258 #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1259
1260 static const struct sh_pfc_pin pinmux_pins[] = {
1261 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1262 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1263 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1264 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1265 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1266 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1267 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1268 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1269 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1270 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1271 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1272 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1273 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1274 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1275 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1276 R8A73A4_PIN_IO_PU_PD(30),
1277 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1278 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1279 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1280 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1281 R8A73A4_PIN_IO_PU_PD(40),
1282 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1283 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1284 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1285 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1286 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1287 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1288 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1289 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1290 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1291 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1292 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1293 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1294 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1295 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1296 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1297 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1298 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1299 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1300 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1301 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1302 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1303 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1304 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1305 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1306 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1307 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1308 R8A73A4_PIN_IO_PU_PD(126),
1309 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1310 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1311 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1312 R8A73A4_PIN_IO_PU_PD(134),
1313 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1314 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1315 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1316 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1317 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1318 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1319 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1320 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1321 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1322 R8A73A4_PIN_IO_PU_PD(178),
1323 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1324 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1325 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1326 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1327 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1328 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1329 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1330 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1331 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1332 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1333 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1334 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1335 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1336 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1337 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1338 R8A73A4_PIN_IO_PU_PD(222),
1339 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1340 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1341 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1342 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1343 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1344 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1345 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1346 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1347 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1348 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1349 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1350 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1351 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1352 R8A73A4_PIN_IO_PU_PD(250),
1353 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1354 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1355 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1356 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1357 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1358 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1359 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1360 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1361 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1362 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1363 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1364 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1365 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1366 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1367 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1368 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1369 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1370 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1371 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1372 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1373 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1374 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1375 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1376 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1377 R8A73A4_PIN_IO_PU_PD(308),
1378 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1379 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1380 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1381 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1382 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1383 };
1384
1385 /* - IRQC ------------------------------------------------------------------- */
1386 #define IRQC_PINS_MUX(pin, irq_mark) \
1387 static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1388 pin, \
1389 }; \
1390 static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1391 IRQ##irq_mark##_MARK, \
1392 }
1393 IRQC_PINS_MUX(0, 0);
1394 IRQC_PINS_MUX(1, 1);
1395 IRQC_PINS_MUX(2, 2);
1396 IRQC_PINS_MUX(3, 3);
1397 IRQC_PINS_MUX(4, 4);
1398 IRQC_PINS_MUX(5, 5);
1399 IRQC_PINS_MUX(6, 6);
1400 IRQC_PINS_MUX(7, 7);
1401 IRQC_PINS_MUX(8, 8);
1402 IRQC_PINS_MUX(9, 9);
1403 IRQC_PINS_MUX(10, 10);
1404 IRQC_PINS_MUX(11, 11);
1405 IRQC_PINS_MUX(12, 12);
1406 IRQC_PINS_MUX(13, 13);
1407 IRQC_PINS_MUX(14, 14);
1408 IRQC_PINS_MUX(15, 15);
1409 IRQC_PINS_MUX(66, 40);
1410 IRQC_PINS_MUX(84, 19);
1411 IRQC_PINS_MUX(85, 18);
1412 IRQC_PINS_MUX(102, 41);
1413 IRQC_PINS_MUX(103, 42);
1414 IRQC_PINS_MUX(109, 43);
1415 IRQC_PINS_MUX(110, 44);
1416 IRQC_PINS_MUX(111, 45);
1417 IRQC_PINS_MUX(112, 46);
1418 IRQC_PINS_MUX(113, 47);
1419 IRQC_PINS_MUX(114, 48);
1420 IRQC_PINS_MUX(115, 49);
1421 IRQC_PINS_MUX(160, 20);
1422 IRQC_PINS_MUX(161, 21);
1423 IRQC_PINS_MUX(162, 22);
1424 IRQC_PINS_MUX(163, 23);
1425 IRQC_PINS_MUX(175, 24);
1426 IRQC_PINS_MUX(176, 25);
1427 IRQC_PINS_MUX(177, 26);
1428 IRQC_PINS_MUX(178, 27);
1429 IRQC_PINS_MUX(192, 31);
1430 IRQC_PINS_MUX(193, 32);
1431 IRQC_PINS_MUX(194, 33);
1432 IRQC_PINS_MUX(195, 34);
1433 IRQC_PINS_MUX(196, 35);
1434 IRQC_PINS_MUX(197, 36);
1435 IRQC_PINS_MUX(198, 37);
1436 IRQC_PINS_MUX(199, 38);
1437 IRQC_PINS_MUX(200, 39);
1438 IRQC_PINS_MUX(290, 51);
1439 IRQC_PINS_MUX(296, 52);
1440 IRQC_PINS_MUX(301, 50);
1441 IRQC_PINS_MUX(320, 16);
1442 IRQC_PINS_MUX(321, 17);
1443 IRQC_PINS_MUX(322, 28);
1444 IRQC_PINS_MUX(323, 29);
1445 IRQC_PINS_MUX(324, 30);
1446 IRQC_PINS_MUX(325, 53);
1447 IRQC_PINS_MUX(326, 54);
1448 IRQC_PINS_MUX(327, 55);
1449 IRQC_PINS_MUX(328, 56);
1450 IRQC_PINS_MUX(329, 57);
1451 /* - MMCIF0 ----------------------------------------------------------------- */
1452 static const unsigned int mmc0_data_pins[] = {
1453 /* D[0:7] */
1454 164, 165, 166, 167, 168, 169, 170, 171,
1455 };
1456 static const unsigned int mmc0_data_mux[] = {
1457 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1458 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1459 };
1460 static const unsigned int mmc0_ctrl_pins[] = {
1461 /* CMD, CLK */
1462 172, 173,
1463 };
1464 static const unsigned int mmc0_ctrl_mux[] = {
1465 MMCCMD0_MARK, MMCCLK0_MARK,
1466 };
1467 /* - MMCIF1 ----------------------------------------------------------------- */
1468 static const unsigned int mmc1_data_pins[] = {
1469 /* D[0:7] */
1470 199, 198, 197, 196, 195, 194, 193, 192,
1471 };
1472 static const unsigned int mmc1_data_mux[] = {
1473 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1474 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1475 };
1476 static const unsigned int mmc1_ctrl_pins[] = {
1477 /* CMD, CLK */
1478 200, 203,
1479 };
1480 static const unsigned int mmc1_ctrl_mux[] = {
1481 MMCCMD1_MARK, MMCCLK1_MARK,
1482 };
1483 /* - SCIFA0 ----------------------------------------------------------------- */
1484 static const unsigned int scifa0_data_pins[] = {
1485 /* SCIFA0_RXD, SCIFA0_TXD */
1486 117, 116,
1487 };
1488 static const unsigned int scifa0_data_mux[] = {
1489 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1490 };
1491 static const unsigned int scifa0_clk_pins[] = {
1492 /* SCIFA0_SCK */
1493 34,
1494 };
1495 static const unsigned int scifa0_clk_mux[] = {
1496 SCIFA0_SCK_MARK,
1497 };
1498 static const unsigned int scifa0_ctrl_pins[] = {
1499 /* SCIFA0_RTS, SCIFA0_CTS */
1500 32, 33,
1501 };
1502 static const unsigned int scifa0_ctrl_mux[] = {
1503 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1504 };
1505 /* - SCIFA1 ----------------------------------------------------------------- */
1506 static const unsigned int scifa1_data_pins[] = {
1507 /* SCIFA1_RXD, SCIFA1_TXD */
1508 119, 118,
1509 };
1510 static const unsigned int scifa1_data_mux[] = {
1511 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1512 };
1513 static const unsigned int scifa1_clk_pins[] = {
1514 /* SCIFA1_SCK */
1515 37,
1516 };
1517 static const unsigned int scifa1_clk_mux[] = {
1518 SCIFA1_SCK_MARK,
1519 };
1520 static const unsigned int scifa1_ctrl_pins[] = {
1521 /* SCIFA1_RTS, SCIFA1_CTS */
1522 35, 36,
1523 };
1524 static const unsigned int scifa1_ctrl_mux[] = {
1525 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1526 };
1527 /* - SCIFB0 ----------------------------------------------------------------- */
1528 static const unsigned int scifb0_data_pins[] = {
1529 /* SCIFB0_RXD, SCIFB0_TXD */
1530 123, 122,
1531 };
1532 static const unsigned int scifb0_data_mux[] = {
1533 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1534 };
1535 static const unsigned int scifb0_clk_pins[] = {
1536 /* SCIFB0_SCK */
1537 40,
1538 };
1539 static const unsigned int scifb0_clk_mux[] = {
1540 SCIFB0_SCK_MARK,
1541 };
1542 static const unsigned int scifb0_ctrl_pins[] = {
1543 /* SCIFB0_RTS, SCIFB0_CTS */
1544 38, 39,
1545 };
1546 static const unsigned int scifb0_ctrl_mux[] = {
1547 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1548 };
1549 /* - SCIFB1 ----------------------------------------------------------------- */
1550 static const unsigned int scifb1_data_pins[] = {
1551 /* SCIFB1_RXD, SCIFB1_TXD */
1552 27, 26,
1553 };
1554 static const unsigned int scifb1_data_mux[] = {
1555 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1556 };
1557 static const unsigned int scifb1_clk_pins[] = {
1558 /* SCIFB1_SCK */
1559 28,
1560 };
1561 static const unsigned int scifb1_clk_mux[] = {
1562 SCIFB1_SCK_28_MARK,
1563 };
1564 static const unsigned int scifb1_ctrl_pins[] = {
1565 /* SCIFB1_RTS, SCIFB1_CTS */
1566 24, 25,
1567 };
1568 static const unsigned int scifb1_ctrl_mux[] = {
1569 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1570 };
1571 static const unsigned int scifb1_data_b_pins[] = {
1572 /* SCIFB1_RXD, SCIFB1_TXD */
1573 72, 67,
1574 };
1575 static const unsigned int scifb1_data_b_mux[] = {
1576 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1577 };
1578 static const unsigned int scifb1_clk_b_pins[] = {
1579 /* SCIFB1_SCK */
1580 261,
1581 };
1582 static const unsigned int scifb1_clk_b_mux[] = {
1583 SCIFB1_SCK_261_MARK,
1584 };
1585 static const unsigned int scifb1_ctrl_b_pins[] = {
1586 /* SCIFB1_RTS, SCIFB1_CTS */
1587 70, 71,
1588 };
1589 static const unsigned int scifb1_ctrl_b_mux[] = {
1590 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1591 };
1592 /* - SCIFB2 ----------------------------------------------------------------- */
1593 static const unsigned int scifb2_data_pins[] = {
1594 /* SCIFB2_RXD, SCIFB2_TXD */
1595 69, 68,
1596 };
1597 static const unsigned int scifb2_data_mux[] = {
1598 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1599 };
1600 static const unsigned int scifb2_clk_pins[] = {
1601 /* SCIFB2_SCK */
1602 262,
1603 };
1604 static const unsigned int scifb2_clk_mux[] = {
1605 SCIFB2_SCK_262_MARK,
1606 };
1607 static const unsigned int scifb2_ctrl_pins[] = {
1608 /* SCIFB2_RTS, SCIFB2_CTS */
1609 73, 66,
1610 };
1611 static const unsigned int scifb2_ctrl_mux[] = {
1612 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1613 };
1614 static const unsigned int scifb2_data_b_pins[] = {
1615 /* SCIFB2_RXD, SCIFB2_TXD */
1616 297, 295,
1617 };
1618 static const unsigned int scifb2_data_b_mux[] = {
1619 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1620 };
1621 static const unsigned int scifb2_clk_b_pins[] = {
1622 /* SCIFB2_SCK */
1623 299,
1624 };
1625 static const unsigned int scifb2_clk_b_mux[] = {
1626 SCIFB2_SCK_299_MARK,
1627 };
1628 static const unsigned int scifb2_ctrl_b_pins[] = {
1629 /* SCIFB2_RTS, SCIFB2_CTS */
1630 300, 298,
1631 };
1632 static const unsigned int scifb2_ctrl_b_mux[] = {
1633 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1634 };
1635 /* - SCIFB3 ----------------------------------------------------------------- */
1636 static const unsigned int scifb3_data_pins[] = {
1637 /* SCIFB3_RXD, SCIFB3_TXD */
1638 22, 21,
1639 };
1640 static const unsigned int scifb3_data_mux[] = {
1641 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1642 };
1643 static const unsigned int scifb3_clk_pins[] = {
1644 /* SCIFB3_SCK */
1645 23,
1646 };
1647 static const unsigned int scifb3_clk_mux[] = {
1648 SCIFB3_SCK_23_MARK,
1649 };
1650 static const unsigned int scifb3_ctrl_pins[] = {
1651 /* SCIFB3_RTS, SCIFB3_CTS */
1652 19, 20,
1653 };
1654 static const unsigned int scifb3_ctrl_mux[] = {
1655 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1656 };
1657 static const unsigned int scifb3_data_b_pins[] = {
1658 /* SCIFB3_RXD, SCIFB3_TXD */
1659 120, 121,
1660 };
1661 static const unsigned int scifb3_data_b_mux[] = {
1662 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1663 };
1664 static const unsigned int scifb3_clk_b_pins[] = {
1665 /* SCIFB3_SCK */
1666 40,
1667 };
1668 static const unsigned int scifb3_clk_b_mux[] = {
1669 SCIFB3_SCK_40_MARK,
1670 };
1671 static const unsigned int scifb3_ctrl_b_pins[] = {
1672 /* SCIFB3_RTS, SCIFB3_CTS */
1673 38, 39,
1674 };
1675 static const unsigned int scifb3_ctrl_b_mux[] = {
1676 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1677 };
1678 /* - SDHI0 ------------------------------------------------------------------ */
1679 static const unsigned int sdhi0_data_pins[] = {
1680 /* D[0:3] */
1681 302, 303, 304, 305,
1682 };
1683 static const unsigned int sdhi0_data_mux[] = {
1684 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1685 };
1686 static const unsigned int sdhi0_ctrl_pins[] = {
1687 /* CLK, CMD */
1688 308, 306,
1689 };
1690 static const unsigned int sdhi0_ctrl_mux[] = {
1691 SDHICLK0_MARK, SDHICMD0_MARK,
1692 };
1693 static const unsigned int sdhi0_cd_pins[] = {
1694 /* CD */
1695 301,
1696 };
1697 static const unsigned int sdhi0_cd_mux[] = {
1698 SDHICD0_MARK,
1699 };
1700 static const unsigned int sdhi0_wp_pins[] = {
1701 /* WP */
1702 307,
1703 };
1704 static const unsigned int sdhi0_wp_mux[] = {
1705 SDHIWP0_MARK,
1706 };
1707 /* - SDHI1 ------------------------------------------------------------------ */
1708 static const unsigned int sdhi1_data_pins[] = {
1709 /* D[0:3] */
1710 289, 290, 291, 292,
1711 };
1712 static const unsigned int sdhi1_data_mux[] = {
1713 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1714 };
1715 static const unsigned int sdhi1_ctrl_pins[] = {
1716 /* CLK, CMD */
1717 293, 294,
1718 };
1719 static const unsigned int sdhi1_ctrl_mux[] = {
1720 SDHICLK1_MARK, SDHICMD1_MARK,
1721 };
1722 /* - SDHI2 ------------------------------------------------------------------ */
1723 static const unsigned int sdhi2_data_pins[] = {
1724 /* D[0:3] */
1725 295, 296, 297, 298,
1726 };
1727 static const unsigned int sdhi2_data_mux[] = {
1728 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1729 };
1730 static const unsigned int sdhi2_ctrl_pins[] = {
1731 /* CLK, CMD */
1732 299, 300,
1733 };
1734 static const unsigned int sdhi2_ctrl_mux[] = {
1735 SDHICLK2_MARK, SDHICMD2_MARK,
1736 };
1737
1738 static const struct sh_pfc_pin_group pinmux_groups[] = {
1739 SH_PFC_PIN_GROUP(irqc_irq0),
1740 SH_PFC_PIN_GROUP(irqc_irq1),
1741 SH_PFC_PIN_GROUP(irqc_irq2),
1742 SH_PFC_PIN_GROUP(irqc_irq3),
1743 SH_PFC_PIN_GROUP(irqc_irq4),
1744 SH_PFC_PIN_GROUP(irqc_irq5),
1745 SH_PFC_PIN_GROUP(irqc_irq6),
1746 SH_PFC_PIN_GROUP(irqc_irq7),
1747 SH_PFC_PIN_GROUP(irqc_irq8),
1748 SH_PFC_PIN_GROUP(irqc_irq9),
1749 SH_PFC_PIN_GROUP(irqc_irq10),
1750 SH_PFC_PIN_GROUP(irqc_irq11),
1751 SH_PFC_PIN_GROUP(irqc_irq12),
1752 SH_PFC_PIN_GROUP(irqc_irq13),
1753 SH_PFC_PIN_GROUP(irqc_irq14),
1754 SH_PFC_PIN_GROUP(irqc_irq15),
1755 SH_PFC_PIN_GROUP(irqc_irq16),
1756 SH_PFC_PIN_GROUP(irqc_irq17),
1757 SH_PFC_PIN_GROUP(irqc_irq18),
1758 SH_PFC_PIN_GROUP(irqc_irq19),
1759 SH_PFC_PIN_GROUP(irqc_irq20),
1760 SH_PFC_PIN_GROUP(irqc_irq21),
1761 SH_PFC_PIN_GROUP(irqc_irq22),
1762 SH_PFC_PIN_GROUP(irqc_irq23),
1763 SH_PFC_PIN_GROUP(irqc_irq24),
1764 SH_PFC_PIN_GROUP(irqc_irq25),
1765 SH_PFC_PIN_GROUP(irqc_irq26),
1766 SH_PFC_PIN_GROUP(irqc_irq27),
1767 SH_PFC_PIN_GROUP(irqc_irq28),
1768 SH_PFC_PIN_GROUP(irqc_irq29),
1769 SH_PFC_PIN_GROUP(irqc_irq30),
1770 SH_PFC_PIN_GROUP(irqc_irq31),
1771 SH_PFC_PIN_GROUP(irqc_irq32),
1772 SH_PFC_PIN_GROUP(irqc_irq33),
1773 SH_PFC_PIN_GROUP(irqc_irq34),
1774 SH_PFC_PIN_GROUP(irqc_irq35),
1775 SH_PFC_PIN_GROUP(irqc_irq36),
1776 SH_PFC_PIN_GROUP(irqc_irq37),
1777 SH_PFC_PIN_GROUP(irqc_irq38),
1778 SH_PFC_PIN_GROUP(irqc_irq39),
1779 SH_PFC_PIN_GROUP(irqc_irq40),
1780 SH_PFC_PIN_GROUP(irqc_irq41),
1781 SH_PFC_PIN_GROUP(irqc_irq42),
1782 SH_PFC_PIN_GROUP(irqc_irq43),
1783 SH_PFC_PIN_GROUP(irqc_irq44),
1784 SH_PFC_PIN_GROUP(irqc_irq45),
1785 SH_PFC_PIN_GROUP(irqc_irq46),
1786 SH_PFC_PIN_GROUP(irqc_irq47),
1787 SH_PFC_PIN_GROUP(irqc_irq48),
1788 SH_PFC_PIN_GROUP(irqc_irq49),
1789 SH_PFC_PIN_GROUP(irqc_irq50),
1790 SH_PFC_PIN_GROUP(irqc_irq51),
1791 SH_PFC_PIN_GROUP(irqc_irq52),
1792 SH_PFC_PIN_GROUP(irqc_irq53),
1793 SH_PFC_PIN_GROUP(irqc_irq54),
1794 SH_PFC_PIN_GROUP(irqc_irq55),
1795 SH_PFC_PIN_GROUP(irqc_irq56),
1796 SH_PFC_PIN_GROUP(irqc_irq57),
1797 BUS_DATA_PIN_GROUP(mmc0_data, 1),
1798 BUS_DATA_PIN_GROUP(mmc0_data, 4),
1799 BUS_DATA_PIN_GROUP(mmc0_data, 8),
1800 SH_PFC_PIN_GROUP(mmc0_ctrl),
1801 BUS_DATA_PIN_GROUP(mmc1_data, 1),
1802 BUS_DATA_PIN_GROUP(mmc1_data, 4),
1803 BUS_DATA_PIN_GROUP(mmc1_data, 8),
1804 SH_PFC_PIN_GROUP(mmc1_ctrl),
1805 SH_PFC_PIN_GROUP(scifa0_data),
1806 SH_PFC_PIN_GROUP(scifa0_clk),
1807 SH_PFC_PIN_GROUP(scifa0_ctrl),
1808 SH_PFC_PIN_GROUP(scifa1_data),
1809 SH_PFC_PIN_GROUP(scifa1_clk),
1810 SH_PFC_PIN_GROUP(scifa1_ctrl),
1811 SH_PFC_PIN_GROUP(scifb0_data),
1812 SH_PFC_PIN_GROUP(scifb0_clk),
1813 SH_PFC_PIN_GROUP(scifb0_ctrl),
1814 SH_PFC_PIN_GROUP(scifb1_data),
1815 SH_PFC_PIN_GROUP(scifb1_clk),
1816 SH_PFC_PIN_GROUP(scifb1_ctrl),
1817 SH_PFC_PIN_GROUP(scifb1_data_b),
1818 SH_PFC_PIN_GROUP(scifb1_clk_b),
1819 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1820 SH_PFC_PIN_GROUP(scifb2_data),
1821 SH_PFC_PIN_GROUP(scifb2_clk),
1822 SH_PFC_PIN_GROUP(scifb2_ctrl),
1823 SH_PFC_PIN_GROUP(scifb2_data_b),
1824 SH_PFC_PIN_GROUP(scifb2_clk_b),
1825 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1826 SH_PFC_PIN_GROUP(scifb3_data),
1827 SH_PFC_PIN_GROUP(scifb3_clk),
1828 SH_PFC_PIN_GROUP(scifb3_ctrl),
1829 SH_PFC_PIN_GROUP(scifb3_data_b),
1830 SH_PFC_PIN_GROUP(scifb3_clk_b),
1831 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1832 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1833 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
1834 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1835 SH_PFC_PIN_GROUP(sdhi0_cd),
1836 SH_PFC_PIN_GROUP(sdhi0_wp),
1837 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
1838 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
1839 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1840 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
1841 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
1842 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1843 };
1844
1845 static const char * const irqc_groups[] = {
1846 "irqc_irq0",
1847 "irqc_irq1",
1848 "irqc_irq2",
1849 "irqc_irq3",
1850 "irqc_irq4",
1851 "irqc_irq5",
1852 "irqc_irq6",
1853 "irqc_irq7",
1854 "irqc_irq8",
1855 "irqc_irq9",
1856 "irqc_irq10",
1857 "irqc_irq11",
1858 "irqc_irq12",
1859 "irqc_irq13",
1860 "irqc_irq14",
1861 "irqc_irq15",
1862 "irqc_irq16",
1863 "irqc_irq17",
1864 "irqc_irq18",
1865 "irqc_irq19",
1866 "irqc_irq20",
1867 "irqc_irq21",
1868 "irqc_irq22",
1869 "irqc_irq23",
1870 "irqc_irq24",
1871 "irqc_irq25",
1872 "irqc_irq26",
1873 "irqc_irq27",
1874 "irqc_irq28",
1875 "irqc_irq29",
1876 "irqc_irq30",
1877 "irqc_irq31",
1878 "irqc_irq32",
1879 "irqc_irq33",
1880 "irqc_irq34",
1881 "irqc_irq35",
1882 "irqc_irq36",
1883 "irqc_irq37",
1884 "irqc_irq38",
1885 "irqc_irq39",
1886 "irqc_irq40",
1887 "irqc_irq41",
1888 "irqc_irq42",
1889 "irqc_irq43",
1890 "irqc_irq44",
1891 "irqc_irq45",
1892 "irqc_irq46",
1893 "irqc_irq47",
1894 "irqc_irq48",
1895 "irqc_irq49",
1896 "irqc_irq50",
1897 "irqc_irq51",
1898 "irqc_irq52",
1899 "irqc_irq53",
1900 "irqc_irq54",
1901 "irqc_irq55",
1902 "irqc_irq56",
1903 "irqc_irq57",
1904 };
1905
1906 static const char * const mmc0_groups[] = {
1907 "mmc0_data1",
1908 "mmc0_data4",
1909 "mmc0_data8",
1910 "mmc0_ctrl",
1911 };
1912
1913 static const char * const mmc1_groups[] = {
1914 "mmc1_data1",
1915 "mmc1_data4",
1916 "mmc1_data8",
1917 "mmc1_ctrl",
1918 };
1919
1920 static const char * const scifa0_groups[] = {
1921 "scifa0_data",
1922 "scifa0_clk",
1923 "scifa0_ctrl",
1924 };
1925
1926 static const char * const scifa1_groups[] = {
1927 "scifa1_data",
1928 "scifa1_clk",
1929 "scifa1_ctrl",
1930 };
1931
1932 static const char * const scifb0_groups[] = {
1933 "scifb0_data",
1934 "scifb0_clk",
1935 "scifb0_ctrl",
1936 };
1937
1938 static const char * const scifb1_groups[] = {
1939 "scifb1_data",
1940 "scifb1_clk",
1941 "scifb1_ctrl",
1942 "scifb1_data_b",
1943 "scifb1_clk_b",
1944 "scifb1_ctrl_b",
1945 };
1946
1947 static const char * const scifb2_groups[] = {
1948 "scifb2_data",
1949 "scifb2_clk",
1950 "scifb2_ctrl",
1951 "scifb2_data_b",
1952 "scifb2_clk_b",
1953 "scifb2_ctrl_b",
1954 };
1955
1956 static const char * const scifb3_groups[] = {
1957 "scifb3_data",
1958 "scifb3_clk",
1959 "scifb3_ctrl",
1960 "scifb3_data_b",
1961 "scifb3_clk_b",
1962 "scifb3_ctrl_b",
1963 };
1964
1965 static const char * const sdhi0_groups[] = {
1966 "sdhi0_data1",
1967 "sdhi0_data4",
1968 "sdhi0_ctrl",
1969 "sdhi0_cd",
1970 "sdhi0_wp",
1971 };
1972
1973 static const char * const sdhi1_groups[] = {
1974 "sdhi1_data1",
1975 "sdhi1_data4",
1976 "sdhi1_ctrl",
1977 };
1978
1979 static const char * const sdhi2_groups[] = {
1980 "sdhi2_data1",
1981 "sdhi2_data4",
1982 "sdhi2_ctrl",
1983 };
1984
1985 static const struct sh_pfc_function pinmux_functions[] = {
1986 SH_PFC_FUNCTION(irqc),
1987 SH_PFC_FUNCTION(mmc0),
1988 SH_PFC_FUNCTION(mmc1),
1989 SH_PFC_FUNCTION(scifa0),
1990 SH_PFC_FUNCTION(scifa1),
1991 SH_PFC_FUNCTION(scifb0),
1992 SH_PFC_FUNCTION(scifb1),
1993 SH_PFC_FUNCTION(scifb2),
1994 SH_PFC_FUNCTION(scifb3),
1995 SH_PFC_FUNCTION(sdhi0),
1996 SH_PFC_FUNCTION(sdhi1),
1997 SH_PFC_FUNCTION(sdhi2),
1998 };
1999
2000 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2001 PORTCR(0, 0xe6050000),
2002 PORTCR(1, 0xe6050001),
2003 PORTCR(2, 0xe6050002),
2004 PORTCR(3, 0xe6050003),
2005 PORTCR(4, 0xe6050004),
2006 PORTCR(5, 0xe6050005),
2007 PORTCR(6, 0xe6050006),
2008 PORTCR(7, 0xe6050007),
2009 PORTCR(8, 0xe6050008),
2010 PORTCR(9, 0xe6050009),
2011 PORTCR(10, 0xe605000A),
2012 PORTCR(11, 0xe605000B),
2013 PORTCR(12, 0xe605000C),
2014 PORTCR(13, 0xe605000D),
2015 PORTCR(14, 0xe605000E),
2016 PORTCR(15, 0xe605000F),
2017 PORTCR(16, 0xe6050010),
2018 PORTCR(17, 0xe6050011),
2019 PORTCR(18, 0xe6050012),
2020 PORTCR(19, 0xe6050013),
2021 PORTCR(20, 0xe6050014),
2022 PORTCR(21, 0xe6050015),
2023 PORTCR(22, 0xe6050016),
2024 PORTCR(23, 0xe6050017),
2025 PORTCR(24, 0xe6050018),
2026 PORTCR(25, 0xe6050019),
2027 PORTCR(26, 0xe605001A),
2028 PORTCR(27, 0xe605001B),
2029 PORTCR(28, 0xe605001C),
2030 PORTCR(29, 0xe605001D),
2031 PORTCR(30, 0xe605001E),
2032 PORTCR(32, 0xe6051020),
2033 PORTCR(33, 0xe6051021),
2034 PORTCR(34, 0xe6051022),
2035 PORTCR(35, 0xe6051023),
2036 PORTCR(36, 0xe6051024),
2037 PORTCR(37, 0xe6051025),
2038 PORTCR(38, 0xe6051026),
2039 PORTCR(39, 0xe6051027),
2040 PORTCR(40, 0xe6051028),
2041 PORTCR(64, 0xe6050040),
2042 PORTCR(65, 0xe6050041),
2043 PORTCR(66, 0xe6050042),
2044 PORTCR(67, 0xe6050043),
2045 PORTCR(68, 0xe6050044),
2046 PORTCR(69, 0xe6050045),
2047 PORTCR(70, 0xe6050046),
2048 PORTCR(71, 0xe6050047),
2049 PORTCR(72, 0xe6050048),
2050 PORTCR(73, 0xe6050049),
2051 PORTCR(74, 0xe605004A),
2052 PORTCR(75, 0xe605004B),
2053 PORTCR(76, 0xe605004C),
2054 PORTCR(77, 0xe605004D),
2055 PORTCR(78, 0xe605004E),
2056 PORTCR(79, 0xe605004F),
2057 PORTCR(80, 0xe6050050),
2058 PORTCR(81, 0xe6050051),
2059 PORTCR(82, 0xe6050052),
2060 PORTCR(83, 0xe6050053),
2061 PORTCR(84, 0xe6050054),
2062 PORTCR(85, 0xe6050055),
2063 PORTCR(96, 0xe6051060),
2064 PORTCR(97, 0xe6051061),
2065 PORTCR(98, 0xe6051062),
2066 PORTCR(99, 0xe6051063),
2067 PORTCR(100, 0xe6051064),
2068 PORTCR(101, 0xe6051065),
2069 PORTCR(102, 0xe6051066),
2070 PORTCR(103, 0xe6051067),
2071 PORTCR(104, 0xe6051068),
2072 PORTCR(105, 0xe6051069),
2073 PORTCR(106, 0xe605106A),
2074 PORTCR(107, 0xe605106B),
2075 PORTCR(108, 0xe605106C),
2076 PORTCR(109, 0xe605106D),
2077 PORTCR(110, 0xe605106E),
2078 PORTCR(111, 0xe605106F),
2079 PORTCR(112, 0xe6051070),
2080 PORTCR(113, 0xe6051071),
2081 PORTCR(114, 0xe6051072),
2082 PORTCR(115, 0xe6051073),
2083 PORTCR(116, 0xe6051074),
2084 PORTCR(117, 0xe6051075),
2085 PORTCR(118, 0xe6051076),
2086 PORTCR(119, 0xe6051077),
2087 PORTCR(120, 0xe6051078),
2088 PORTCR(121, 0xe6051079),
2089 PORTCR(122, 0xe605107A),
2090 PORTCR(123, 0xe605107B),
2091 PORTCR(124, 0xe605107C),
2092 PORTCR(125, 0xe605107D),
2093 PORTCR(126, 0xe605107E),
2094 PORTCR(128, 0xe6051080),
2095 PORTCR(129, 0xe6051081),
2096 PORTCR(130, 0xe6051082),
2097 PORTCR(131, 0xe6051083),
2098 PORTCR(132, 0xe6051084),
2099 PORTCR(133, 0xe6051085),
2100 PORTCR(134, 0xe6051086),
2101 PORTCR(160, 0xe60520A0),
2102 PORTCR(161, 0xe60520A1),
2103 PORTCR(162, 0xe60520A2),
2104 PORTCR(163, 0xe60520A3),
2105 PORTCR(164, 0xe60520A4),
2106 PORTCR(165, 0xe60520A5),
2107 PORTCR(166, 0xe60520A6),
2108 PORTCR(167, 0xe60520A7),
2109 PORTCR(168, 0xe60520A8),
2110 PORTCR(169, 0xe60520A9),
2111 PORTCR(170, 0xe60520AA),
2112 PORTCR(171, 0xe60520AB),
2113 PORTCR(172, 0xe60520AC),
2114 PORTCR(173, 0xe60520AD),
2115 PORTCR(174, 0xe60520AE),
2116 PORTCR(175, 0xe60520AF),
2117 PORTCR(176, 0xe60520B0),
2118 PORTCR(177, 0xe60520B1),
2119 PORTCR(178, 0xe60520B2),
2120 PORTCR(192, 0xe60520C0),
2121 PORTCR(193, 0xe60520C1),
2122 PORTCR(194, 0xe60520C2),
2123 PORTCR(195, 0xe60520C3),
2124 PORTCR(196, 0xe60520C4),
2125 PORTCR(197, 0xe60520C5),
2126 PORTCR(198, 0xe60520C6),
2127 PORTCR(199, 0xe60520C7),
2128 PORTCR(200, 0xe60520C8),
2129 PORTCR(201, 0xe60520C9),
2130 PORTCR(202, 0xe60520CA),
2131 PORTCR(203, 0xe60520CB),
2132 PORTCR(204, 0xe60520CC),
2133 PORTCR(205, 0xe60520CD),
2134 PORTCR(206, 0xe60520CE),
2135 PORTCR(207, 0xe60520CF),
2136 PORTCR(208, 0xe60520D0),
2137 PORTCR(209, 0xe60520D1),
2138 PORTCR(210, 0xe60520D2),
2139 PORTCR(211, 0xe60520D3),
2140 PORTCR(212, 0xe60520D4),
2141 PORTCR(213, 0xe60520D5),
2142 PORTCR(214, 0xe60520D6),
2143 PORTCR(215, 0xe60520D7),
2144 PORTCR(216, 0xe60520D8),
2145 PORTCR(217, 0xe60520D9),
2146 PORTCR(218, 0xe60520DA),
2147 PORTCR(219, 0xe60520DB),
2148 PORTCR(220, 0xe60520DC),
2149 PORTCR(221, 0xe60520DD),
2150 PORTCR(222, 0xe60520DE),
2151 PORTCR(224, 0xe60520E0),
2152 PORTCR(225, 0xe60520E1),
2153 PORTCR(226, 0xe60520E2),
2154 PORTCR(227, 0xe60520E3),
2155 PORTCR(228, 0xe60520E4),
2156 PORTCR(229, 0xe60520E5),
2157 PORTCR(230, 0xe60520e6),
2158 PORTCR(231, 0xe60520E7),
2159 PORTCR(232, 0xe60520E8),
2160 PORTCR(233, 0xe60520E9),
2161 PORTCR(234, 0xe60520EA),
2162 PORTCR(235, 0xe60520EB),
2163 PORTCR(236, 0xe60520EC),
2164 PORTCR(237, 0xe60520ED),
2165 PORTCR(238, 0xe60520EE),
2166 PORTCR(239, 0xe60520EF),
2167 PORTCR(240, 0xe60520F0),
2168 PORTCR(241, 0xe60520F1),
2169 PORTCR(242, 0xe60520F2),
2170 PORTCR(243, 0xe60520F3),
2171 PORTCR(244, 0xe60520F4),
2172 PORTCR(245, 0xe60520F5),
2173 PORTCR(246, 0xe60520F6),
2174 PORTCR(247, 0xe60520F7),
2175 PORTCR(248, 0xe60520F8),
2176 PORTCR(249, 0xe60520F9),
2177 PORTCR(250, 0xe60520FA),
2178 PORTCR(256, 0xe6052100),
2179 PORTCR(257, 0xe6052101),
2180 PORTCR(258, 0xe6052102),
2181 PORTCR(259, 0xe6052103),
2182 PORTCR(260, 0xe6052104),
2183 PORTCR(261, 0xe6052105),
2184 PORTCR(262, 0xe6052106),
2185 PORTCR(263, 0xe6052107),
2186 PORTCR(264, 0xe6052108),
2187 PORTCR(265, 0xe6052109),
2188 PORTCR(266, 0xe605210A),
2189 PORTCR(267, 0xe605210B),
2190 PORTCR(268, 0xe605210C),
2191 PORTCR(269, 0xe605210D),
2192 PORTCR(270, 0xe605210E),
2193 PORTCR(271, 0xe605210F),
2194 PORTCR(272, 0xe6052110),
2195 PORTCR(273, 0xe6052111),
2196 PORTCR(274, 0xe6052112),
2197 PORTCR(275, 0xe6052113),
2198 PORTCR(276, 0xe6052114),
2199 PORTCR(277, 0xe6052115),
2200 PORTCR(278, 0xe6052116),
2201 PORTCR(279, 0xe6052117),
2202 PORTCR(280, 0xe6052118),
2203 PORTCR(281, 0xe6052119),
2204 PORTCR(282, 0xe605211A),
2205 PORTCR(283, 0xe605211B),
2206 PORTCR(288, 0xe6053120),
2207 PORTCR(289, 0xe6053121),
2208 PORTCR(290, 0xe6053122),
2209 PORTCR(291, 0xe6053123),
2210 PORTCR(292, 0xe6053124),
2211 PORTCR(293, 0xe6053125),
2212 PORTCR(294, 0xe6053126),
2213 PORTCR(295, 0xe6053127),
2214 PORTCR(296, 0xe6053128),
2215 PORTCR(297, 0xe6053129),
2216 PORTCR(298, 0xe605312A),
2217 PORTCR(299, 0xe605312B),
2218 PORTCR(300, 0xe605312C),
2219 PORTCR(301, 0xe605312D),
2220 PORTCR(302, 0xe605312E),
2221 PORTCR(303, 0xe605312F),
2222 PORTCR(304, 0xe6053130),
2223 PORTCR(305, 0xe6053131),
2224 PORTCR(306, 0xe6053132),
2225 PORTCR(307, 0xe6053133),
2226 PORTCR(308, 0xe6053134),
2227 PORTCR(320, 0xe6053140),
2228 PORTCR(321, 0xe6053141),
2229 PORTCR(322, 0xe6053142),
2230 PORTCR(323, 0xe6053143),
2231 PORTCR(324, 0xe6053144),
2232 PORTCR(325, 0xe6053145),
2233 PORTCR(326, 0xe6053146),
2234 PORTCR(327, 0xe6053147),
2235 PORTCR(328, 0xe6053148),
2236 PORTCR(329, 0xe6053149),
2237
2238 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
2239 MSEL1CR_31_0, MSEL1CR_31_1,
2240 0, 0,
2241 0, 0,
2242 0, 0,
2243 MSEL1CR_27_0, MSEL1CR_27_1,
2244 0, 0,
2245 MSEL1CR_25_0, MSEL1CR_25_1,
2246 MSEL1CR_24_0, MSEL1CR_24_1,
2247 0, 0,
2248 MSEL1CR_22_0, MSEL1CR_22_1,
2249 MSEL1CR_21_0, MSEL1CR_21_1,
2250 MSEL1CR_20_0, MSEL1CR_20_1,
2251 MSEL1CR_19_0, MSEL1CR_19_1,
2252 MSEL1CR_18_0, MSEL1CR_18_1,
2253 MSEL1CR_17_0, MSEL1CR_17_1,
2254 MSEL1CR_16_0, MSEL1CR_16_1,
2255 MSEL1CR_15_0, MSEL1CR_15_1,
2256 MSEL1CR_14_0, MSEL1CR_14_1,
2257 MSEL1CR_13_0, MSEL1CR_13_1,
2258 MSEL1CR_12_0, MSEL1CR_12_1,
2259 MSEL1CR_11_0, MSEL1CR_11_1,
2260 MSEL1CR_10_0, MSEL1CR_10_1,
2261 MSEL1CR_09_0, MSEL1CR_09_1,
2262 MSEL1CR_08_0, MSEL1CR_08_1,
2263 MSEL1CR_07_0, MSEL1CR_07_1,
2264 MSEL1CR_06_0, MSEL1CR_06_1,
2265 MSEL1CR_05_0, MSEL1CR_05_1,
2266 MSEL1CR_04_0, MSEL1CR_04_1,
2267 MSEL1CR_03_0, MSEL1CR_03_1,
2268 MSEL1CR_02_0, MSEL1CR_02_1,
2269 MSEL1CR_01_0, MSEL1CR_01_1,
2270 MSEL1CR_00_0, MSEL1CR_00_1,
2271 ))
2272 },
2273 { PINMUX_CFG_REG_VAR("MSEL3CR", 0xe6058020, 32,
2274 GROUP(1, -2, 1, 1, 1, -2, 1, 1, 1, 1, 1, 1,
2275 1, 1, 1, -2, 1, 1, 1, 1, -2, 1, -2, 1,
2276 -1, 1, 1),
2277 GROUP(
2278 MSEL3CR_31_0, MSEL3CR_31_1,
2279 /* RESERVED [2] */
2280 MSEL3CR_28_0, MSEL3CR_28_1,
2281 MSEL3CR_27_0, MSEL3CR_27_1,
2282 MSEL3CR_26_0, MSEL3CR_26_1,
2283 /* RESERVED [2] */
2284 MSEL3CR_23_0, MSEL3CR_23_1,
2285 MSEL3CR_22_0, MSEL3CR_22_1,
2286 MSEL3CR_21_0, MSEL3CR_21_1,
2287 MSEL3CR_20_0, MSEL3CR_20_1,
2288 MSEL3CR_19_0, MSEL3CR_19_1,
2289 MSEL3CR_18_0, MSEL3CR_18_1,
2290 MSEL3CR_17_0, MSEL3CR_17_1,
2291 MSEL3CR_16_0, MSEL3CR_16_1,
2292 MSEL3CR_15_0, MSEL3CR_15_1,
2293 /* RESERVED [2] */
2294 MSEL3CR_12_0, MSEL3CR_12_1,
2295 MSEL3CR_11_0, MSEL3CR_11_1,
2296 MSEL3CR_10_0, MSEL3CR_10_1,
2297 MSEL3CR_09_0, MSEL3CR_09_1,
2298 /* RESERVED [2] */
2299 MSEL3CR_06_0, MSEL3CR_06_1,
2300 /* RESERVED [2] */
2301 MSEL3CR_03_0, MSEL3CR_03_1,
2302 /* RESERVED [1] */
2303 MSEL3CR_01_0, MSEL3CR_01_1,
2304 MSEL3CR_00_0, MSEL3CR_00_1,
2305 ))
2306 },
2307 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
2308 0, 0,
2309 MSEL4CR_30_0, MSEL4CR_30_1,
2310 MSEL4CR_29_0, MSEL4CR_29_1,
2311 MSEL4CR_28_0, MSEL4CR_28_1,
2312 MSEL4CR_27_0, MSEL4CR_27_1,
2313 MSEL4CR_26_0, MSEL4CR_26_1,
2314 MSEL4CR_25_0, MSEL4CR_25_1,
2315 MSEL4CR_24_0, MSEL4CR_24_1,
2316 MSEL4CR_23_0, MSEL4CR_23_1,
2317 MSEL4CR_22_0, MSEL4CR_22_1,
2318 MSEL4CR_21_0, MSEL4CR_21_1,
2319 MSEL4CR_20_0, MSEL4CR_20_1,
2320 MSEL4CR_19_0, MSEL4CR_19_1,
2321 MSEL4CR_18_0, MSEL4CR_18_1,
2322 MSEL4CR_17_0, MSEL4CR_17_1,
2323 MSEL4CR_16_0, MSEL4CR_16_1,
2324 MSEL4CR_15_0, MSEL4CR_15_1,
2325 MSEL4CR_14_0, MSEL4CR_14_1,
2326 MSEL4CR_13_0, MSEL4CR_13_1,
2327 MSEL4CR_12_0, MSEL4CR_12_1,
2328 MSEL4CR_11_0, MSEL4CR_11_1,
2329 MSEL4CR_10_0, MSEL4CR_10_1,
2330 MSEL4CR_09_0, MSEL4CR_09_1,
2331 0, 0,
2332 MSEL4CR_07_0, MSEL4CR_07_1,
2333 0, 0,
2334 0, 0,
2335 MSEL4CR_04_0, MSEL4CR_04_1,
2336 0, 0,
2337 0, 0,
2338 MSEL4CR_01_0, MSEL4CR_01_1,
2339 0, 0,
2340 ))
2341 },
2342 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
2343 MSEL5CR_31_0, MSEL5CR_31_1,
2344 MSEL5CR_30_0, MSEL5CR_30_1,
2345 MSEL5CR_29_0, MSEL5CR_29_1,
2346 MSEL5CR_28_0, MSEL5CR_28_1,
2347 MSEL5CR_27_0, MSEL5CR_27_1,
2348 MSEL5CR_26_0, MSEL5CR_26_1,
2349 MSEL5CR_25_0, MSEL5CR_25_1,
2350 MSEL5CR_24_0, MSEL5CR_24_1,
2351 MSEL5CR_23_0, MSEL5CR_23_1,
2352 MSEL5CR_22_0, MSEL5CR_22_1,
2353 MSEL5CR_21_0, MSEL5CR_21_1,
2354 MSEL5CR_20_0, MSEL5CR_20_1,
2355 MSEL5CR_19_0, MSEL5CR_19_1,
2356 MSEL5CR_18_0, MSEL5CR_18_1,
2357 MSEL5CR_17_0, MSEL5CR_17_1,
2358 MSEL5CR_16_0, MSEL5CR_16_1,
2359 MSEL5CR_15_0, MSEL5CR_15_1,
2360 MSEL5CR_14_0, MSEL5CR_14_1,
2361 MSEL5CR_13_0, MSEL5CR_13_1,
2362 MSEL5CR_12_0, MSEL5CR_12_1,
2363 MSEL5CR_11_0, MSEL5CR_11_1,
2364 MSEL5CR_10_0, MSEL5CR_10_1,
2365 MSEL5CR_09_0, MSEL5CR_09_1,
2366 MSEL5CR_08_0, MSEL5CR_08_1,
2367 MSEL5CR_07_0, MSEL5CR_07_1,
2368 MSEL5CR_06_0, MSEL5CR_06_1,
2369 0, 0,
2370 0, 0,
2371 0, 0,
2372 0, 0,
2373 0, 0,
2374 0, 0,
2375 ))
2376 },
2377 { PINMUX_CFG_REG_VAR("MSEL8CR", 0xe6058034, 32,
2378 GROUP(-15, 1, -14, 1, 1),
2379 GROUP(
2380 /* RESERVED [15] */
2381 MSEL8CR_16_0, MSEL8CR_16_1,
2382 /* RESERVED [14] */
2383 MSEL8CR_01_0, MSEL8CR_01_1,
2384 MSEL8CR_00_0, MSEL8CR_00_1,
2385 ))
2386 },
2387 { /* sentinel */ }
2388 };
2389
2390 static const struct pinmux_data_reg pinmux_data_regs[] = {
2391
2392 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
2393 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2394 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2395 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2396 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2397 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2398 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2399 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2400 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2401 ))
2402 },
2403 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
2404 0, 0, 0, 0,
2405 0, 0, 0, 0,
2406 0, 0, 0, 0,
2407 0, 0, 0, 0,
2408 0, 0, 0, 0,
2409 0, 0, 0, PORT40_DATA,
2410 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2411 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2412 ))
2413 },
2414 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
2415 0, 0, 0, 0,
2416 0, 0, 0, 0,
2417 0, 0, PORT85_DATA, PORT84_DATA,
2418 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2419 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2420 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2421 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2422 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2423 ))
2424 },
2425 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
2426 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2427 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2428 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2429 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2430 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2431 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2432 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2433 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2434 ))
2435 },
2436 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
2437 0, 0, 0, 0,
2438 0, 0, 0, 0,
2439 0, 0, 0, 0,
2440 0, 0, 0, 0,
2441 0, 0, 0, 0,
2442 0, 0, 0, 0,
2443 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2444 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2445 ))
2446 },
2447 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
2448 0, 0, 0, 0,
2449 0, 0, 0, 0,
2450 0, 0, 0, 0,
2451 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2452 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2453 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2454 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2455 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2456 ))
2457 },
2458 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
2459 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2460 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2461 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2462 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2463 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2464 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2465 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2466 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2467 ))
2468 },
2469 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
2470 0, 0, 0, 0,
2471 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2472 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2473 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2474 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2475 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2476 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2477 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2478 ))
2479 },
2480 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
2481 0, 0, 0, 0,
2482 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2483 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2484 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2485 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2486 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2487 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2488 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2489 ))
2490 },
2491 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
2492 0, 0, 0, 0,
2493 0, 0, 0, 0,
2494 0, 0, 0, PORT308_DATA,
2495 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2496 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2497 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2498 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2499 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2500 ))
2501 },
2502 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
2503 0, 0, 0, 0,
2504 0, 0, 0, 0,
2505 0, 0, 0, 0,
2506 0, 0, 0, 0,
2507 0, 0, 0, 0,
2508 0, 0, PORT329_DATA, PORT328_DATA,
2509 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2510 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2511 ))
2512 },
2513 { /* sentinel */ }
2514 };
2515
2516 static const struct pinmux_irq pinmux_irqs[] = {
2517 PINMUX_IRQ(0), /* IRQ0 */
2518 PINMUX_IRQ(1), /* IRQ1 */
2519 PINMUX_IRQ(2), /* IRQ2 */
2520 PINMUX_IRQ(3), /* IRQ3 */
2521 PINMUX_IRQ(4), /* IRQ4 */
2522 PINMUX_IRQ(5), /* IRQ5 */
2523 PINMUX_IRQ(6), /* IRQ6 */
2524 PINMUX_IRQ(7), /* IRQ7 */
2525 PINMUX_IRQ(8), /* IRQ8 */
2526 PINMUX_IRQ(9), /* IRQ9 */
2527 PINMUX_IRQ(10), /* IRQ10 */
2528 PINMUX_IRQ(11), /* IRQ11 */
2529 PINMUX_IRQ(12), /* IRQ12 */
2530 PINMUX_IRQ(13), /* IRQ13 */
2531 PINMUX_IRQ(14), /* IRQ14 */
2532 PINMUX_IRQ(15), /* IRQ15 */
2533 PINMUX_IRQ(320), /* IRQ16 */
2534 PINMUX_IRQ(321), /* IRQ17 */
2535 PINMUX_IRQ(85), /* IRQ18 */
2536 PINMUX_IRQ(84), /* IRQ19 */
2537 PINMUX_IRQ(160), /* IRQ20 */
2538 PINMUX_IRQ(161), /* IRQ21 */
2539 PINMUX_IRQ(162), /* IRQ22 */
2540 PINMUX_IRQ(163), /* IRQ23 */
2541 PINMUX_IRQ(175), /* IRQ24 */
2542 PINMUX_IRQ(176), /* IRQ25 */
2543 PINMUX_IRQ(177), /* IRQ26 */
2544 PINMUX_IRQ(178), /* IRQ27 */
2545 PINMUX_IRQ(322), /* IRQ28 */
2546 PINMUX_IRQ(323), /* IRQ29 */
2547 PINMUX_IRQ(324), /* IRQ30 */
2548 PINMUX_IRQ(192), /* IRQ31 */
2549 PINMUX_IRQ(193), /* IRQ32 */
2550 PINMUX_IRQ(194), /* IRQ33 */
2551 PINMUX_IRQ(195), /* IRQ34 */
2552 PINMUX_IRQ(196), /* IRQ35 */
2553 PINMUX_IRQ(197), /* IRQ36 */
2554 PINMUX_IRQ(198), /* IRQ37 */
2555 PINMUX_IRQ(199), /* IRQ38 */
2556 PINMUX_IRQ(200), /* IRQ39 */
2557 PINMUX_IRQ(66), /* IRQ40 */
2558 PINMUX_IRQ(102), /* IRQ41 */
2559 PINMUX_IRQ(103), /* IRQ42 */
2560 PINMUX_IRQ(109), /* IRQ43 */
2561 PINMUX_IRQ(110), /* IRQ44 */
2562 PINMUX_IRQ(111), /* IRQ45 */
2563 PINMUX_IRQ(112), /* IRQ46 */
2564 PINMUX_IRQ(113), /* IRQ47 */
2565 PINMUX_IRQ(114), /* IRQ48 */
2566 PINMUX_IRQ(115), /* IRQ49 */
2567 PINMUX_IRQ(301), /* IRQ50 */
2568 PINMUX_IRQ(290), /* IRQ51 */
2569 PINMUX_IRQ(296), /* IRQ52 */
2570 PINMUX_IRQ(325), /* IRQ53 */
2571 PINMUX_IRQ(326), /* IRQ54 */
2572 PINMUX_IRQ(327), /* IRQ55 */
2573 PINMUX_IRQ(328), /* IRQ56 */
2574 PINMUX_IRQ(329), /* IRQ57 */
2575 };
2576
2577 static const unsigned int r8a73a4_portcr_offsets[] = {
2578 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2579 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2580 0x00002000, 0x00003000, 0x00003000,
2581 };
2582
r8a73a4_pin_to_portcr(unsigned int pin)2583 static int r8a73a4_pin_to_portcr(unsigned int pin)
2584 {
2585 return r8a73a4_portcr_offsets[pin >> 5] + pin;
2586 }
2587
2588 static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2589 .get_bias = rmobile_pinmux_get_bias,
2590 .set_bias = rmobile_pinmux_set_bias,
2591 .pin_to_portcr = r8a73a4_pin_to_portcr,
2592 };
2593
2594 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2595 .name = "r8a73a4_pfc",
2596 .ops = &r8a73a4_pfc_ops,
2597
2598 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2599 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2600 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2601
2602 .pins = pinmux_pins,
2603 .nr_pins = ARRAY_SIZE(pinmux_pins),
2604
2605 .groups = pinmux_groups,
2606 .nr_groups = ARRAY_SIZE(pinmux_groups),
2607 .functions = pinmux_functions,
2608 .nr_functions = ARRAY_SIZE(pinmux_functions),
2609
2610 .cfg_regs = pinmux_config_regs,
2611 .data_regs = pinmux_data_regs,
2612
2613 .pinmux_data = pinmux_data,
2614 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2615
2616 .gpio_irq = pinmux_irqs,
2617 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2618 };
2619