1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* SpacemiT clock and reset driver definitions for the K3 SoC */ 4 5 #ifndef __SOC_K3_SYSCON_H__ 6 #define __SOC_K3_SYSCON_H__ 7 8 #include "ccu.h" 9 10 /* APBS register offset */ 11 #define APBS_PLL1_SWCR1 0x100 12 #define APBS_PLL1_SWCR2 0x104 13 #define APBS_PLL1_SWCR3 0x108 14 #define APBS_PLL2_SWCR1 0x118 15 #define APBS_PLL2_SWCR2 0x11c 16 #define APBS_PLL2_SWCR3 0x120 17 #define APBS_PLL3_SWCR1 0x124 18 #define APBS_PLL3_SWCR2 0x128 19 #define APBS_PLL3_SWCR3 0x12c 20 #define APBS_PLL4_SWCR1 0x130 21 #define APBS_PLL4_SWCR2 0x134 22 #define APBS_PLL4_SWCR3 0x138 23 #define APBS_PLL5_SWCR1 0x13c 24 #define APBS_PLL5_SWCR2 0x140 25 #define APBS_PLL5_SWCR3 0x144 26 #define APBS_PLL6_SWCR1 0x148 27 #define APBS_PLL6_SWCR2 0x14c 28 #define APBS_PLL6_SWCR3 0x150 29 #define APBS_PLL7_SWCR1 0x158 30 #define APBS_PLL7_SWCR2 0x15c 31 #define APBS_PLL7_SWCR3 0x160 32 #define APBS_PLL8_SWCR1 0x180 33 #define APBS_PLL8_SWCR2 0x184 34 #define APBS_PLL8_SWCR3 0x188 35 36 /* MPMU register offset */ 37 #define MPMU_FCCR 0x0008 38 #define MPMU_POSR 0x0010 39 #define POSR_PLL1_LOCK BIT(24) 40 #define POSR_PLL2_LOCK BIT(25) 41 #define POSR_PLL3_LOCK BIT(26) 42 #define POSR_PLL4_LOCK BIT(27) 43 #define POSR_PLL5_LOCK BIT(28) 44 #define POSR_PLL6_LOCK BIT(29) 45 #define POSR_PLL7_LOCK BIT(30) 46 #define POSR_PLL8_LOCK BIT(31) 47 #define MPMU_SUCCR 0x0014 48 #define MPMU_ISCCR0 0x0040 49 #define MPMU_ISCCR1 0x0044 50 #define MPMU_WDTPCR 0x0200 51 #define MPMU_RIPCCR 0x0210 52 #define MPMU_ACGR 0x1024 53 #define MPMU_APBCSCR 0x1050 54 #define MPMU_SUCCR_1 0x10b0 55 56 #define MPMU_I2S0_SYSCLK 0x1100 57 #define MPMU_I2S2_SYSCLK 0x1104 58 #define MPMU_I2S3_SYSCLK 0x1108 59 #define MPMU_I2S4_SYSCLK 0x110c 60 #define MPMU_I2S5_SYSCLK 0x1110 61 #define MPMU_I2S_SYSCLK_CTRL 0x1114 62 63 /* APBC register offset */ 64 #define APBC_UART0_CLK_RST 0x00 65 #define APBC_UART2_CLK_RST 0x04 66 #define APBC_GPIO_CLK_RST 0x08 67 #define APBC_PWM0_CLK_RST 0x0c 68 #define APBC_PWM1_CLK_RST 0x10 69 #define APBC_PWM2_CLK_RST 0x14 70 #define APBC_PWM3_CLK_RST 0x18 71 #define APBC_TWSI8_CLK_RST 0x20 72 #define APBC_UART3_CLK_RST 0x24 73 #define APBC_RTC_CLK_RST 0x28 74 #define APBC_TWSI0_CLK_RST 0x2c 75 #define APBC_TWSI1_CLK_RST 0x30 76 #define APBC_TIMERS0_CLK_RST 0x34 77 #define APBC_TWSI2_CLK_RST 0x38 78 #define APBC_AIB_CLK_RST 0x3c 79 #define APBC_TWSI4_CLK_RST 0x40 80 #define APBC_TIMERS1_CLK_RST 0x44 81 #define APBC_ONEWIRE_CLK_RST 0x48 82 #define APBC_TWSI5_CLK_RST 0x4c 83 #define APBC_DRO_CLK_RST 0x58 84 #define APBC_IR0_CLK_RST 0x5c 85 #define APBC_IR1_CLK_RST 0x1c 86 #define APBC_TWSI6_CLK_RST 0x60 87 #define APBC_COUNTER_CLK_SEL 0x64 88 #define APBC_TSEN_CLK_RST 0x6c 89 #define APBC_UART4_CLK_RST 0x70 90 #define APBC_UART5_CLK_RST 0x74 91 #define APBC_UART6_CLK_RST 0x78 92 #define APBC_SSP3_CLK_RST 0x7c 93 #define APBC_SSPA0_CLK_RST 0x80 94 #define APBC_SSPA1_CLK_RST 0x84 95 #define APBC_SSPA2_CLK_RST 0x88 96 #define APBC_SSPA3_CLK_RST 0x8c 97 #define APBC_IPC_AP2AUD_CLK_RST 0x90 98 #define APBC_UART7_CLK_RST 0x94 99 #define APBC_UART8_CLK_RST 0x98 100 #define APBC_UART9_CLK_RST 0x9c 101 #define APBC_CAN0_CLK_RST 0xa0 102 #define APBC_CAN1_CLK_RST 0xa4 103 #define APBC_PWM4_CLK_RST 0xa8 104 #define APBC_PWM5_CLK_RST 0xac 105 #define APBC_PWM6_CLK_RST 0xb0 106 #define APBC_PWM7_CLK_RST 0xb4 107 #define APBC_PWM8_CLK_RST 0xb8 108 #define APBC_PWM9_CLK_RST 0xbc 109 #define APBC_PWM10_CLK_RST 0xc0 110 #define APBC_PWM11_CLK_RST 0xc4 111 #define APBC_PWM12_CLK_RST 0xc8 112 #define APBC_PWM13_CLK_RST 0xcc 113 #define APBC_PWM14_CLK_RST 0xd0 114 #define APBC_PWM15_CLK_RST 0xd4 115 #define APBC_PWM16_CLK_RST 0xd8 116 #define APBC_PWM17_CLK_RST 0xdc 117 #define APBC_PWM18_CLK_RST 0xe0 118 #define APBC_PWM19_CLK_RST 0xe4 119 #define APBC_TIMERS2_CLK_RST 0x11c 120 #define APBC_TIMERS3_CLK_RST 0x120 121 #define APBC_TIMERS4_CLK_RST 0x124 122 #define APBC_TIMERS5_CLK_RST 0x128 123 #define APBC_TIMERS6_CLK_RST 0x12c 124 #define APBC_TIMERS7_CLK_RST 0x130 125 126 #define APBC_CAN2_CLK_RST 0x148 127 #define APBC_CAN3_CLK_RST 0x14c 128 #define APBC_CAN4_CLK_RST 0x150 129 #define APBC_UART10_CLK_RST 0x154 130 #define APBC_SSP0_CLK_RST 0x158 131 #define APBC_SSP1_CLK_RST 0x15c 132 #define APBC_SSPA4_CLK_RST 0x160 133 #define APBC_SSPA5_CLK_RST 0x164 134 135 /* APMU register offset */ 136 #define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 137 #define APMU_ISP_CLK_RES_CTRL 0x038 138 #define APMU_PMU_CLK_GATE_CTRL 0x040 139 #define APMU_LCD_CLK_RES_CTRL1 0x044 140 #define APMU_LCD_SPI_CLK_RES_CTRL 0x048 141 #define APMU_LCD_CLK_RES_CTRL2 0x04c 142 #define APMU_CCIC_CLK_RES_CTRL 0x050 143 #define APMU_SDH0_CLK_RES_CTRL 0x054 144 #define APMU_SDH1_CLK_RES_CTRL 0x058 145 #define APMU_USB_CLK_RES_CTRL 0x05c 146 #define APMU_QSPI_CLK_RES_CTRL 0x060 147 #define APMU_DMA_CLK_RES_CTRL 0x064 148 #define APMU_AES_CLK_RES_CTRL 0x068 149 #define APMU_MCB_CLK_RES_CTRL 0x06c 150 #define APMU_VPU_CLK_RES_CTRL 0x0a4 151 #define APMU_DTC_CLK_RES_CTRL 0x0ac 152 #define APMU_GPU_CLK_RES_CTRL 0x0cc 153 #define APMU_SDH2_CLK_RES_CTRL 0x0e0 154 #define APMU_PMUA_MC_CTRL 0x0e8 155 #define APMU_PMU_CC2_AP 0x100 156 #define APMU_PMUA_EM_CLK_RES_CTRL 0x104 157 #define APMU_UCIE_CTRL 0x11c 158 #define APMU_RCPU_CLK_RES_CTRL 0x14c 159 #define APMU_TOP_DCLK_CTRL 0x158 160 #define APMU_LCD_EDP_CTRL 0x23c 161 #define APMU_UFS_CLK_RES_CTRL 0x268 162 #define APMU_LCD_CLK_RES_CTRL3 0x26c 163 #define APMU_LCD_CLK_RES_CTRL4 0x270 164 #define APMU_LCD_CLK_RES_CTRL5 0x274 165 #define APMU_CCI550_CLK_CTRL 0x300 166 #define APMU_ACLK_CLK_CTRL 0x388 167 #define APMU_CPU_C0_CLK_CTRL 0x38C 168 #define APMU_CPU_C1_CLK_CTRL 0x390 169 #define APMU_CPU_C2_CLK_CTRL 0x394 170 #define APMU_CPU_C3_CLK_CTRL 0x208 171 #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 172 #define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 173 #define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 174 #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 175 #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 176 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 177 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec 178 #define APMU_EMAC2_CLK_RES_CTRL 0x248 179 #define APMU_ESPI_CLK_RES_CTRL 0x240 180 #define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 181 182 /* DCIU register offsets */ 183 #define DCIU_DMASYS_CLK_EN 0x234 184 #define DCIU_DMASYS_SDMA_CLK_EN 0x238 185 #define DCIU_C2_TCM_PIPE_CLK 0x244 186 #define DCIU_C3_TCM_PIPE_CLK 0x248 187 188 #define DCIU_DMASYS_S0_RSTN 0x204 189 #define DCIU_DMASYS_S1_RSTN 0x208 190 #define DCIU_DMASYS_A0_RSTN 0x20C 191 #define DCIU_DMASYS_A1_RSTN 0x210 192 #define DCIU_DMASYS_A2_RSTN 0x214 193 #define DCIU_DMASYS_A3_RSTN 0x218 194 #define DCIU_DMASYS_A4_RSTN 0x21C 195 #define DCIU_DMASYS_A5_RSTN 0x220 196 #define DCIU_DMASYS_A6_RSTN 0x224 197 #define DCIU_DMASYS_A7_RSTN 0x228 198 #define DCIU_DMASYS_RSTN 0x22C 199 #define DCIU_DMASYS_SDMA_RSTN 0x230 200 201 /* RCPU SYSCTRL register offsets */ 202 #define RCPU_CAN_CLK_RST 0x4c 203 #define RCPU_CAN1_CLK_RST 0xF0 204 #define RCPU_CAN2_CLK_RST 0xF4 205 #define RCPU_CAN3_CLK_RST 0xF8 206 #define RCPU_CAN4_CLK_RST 0xFC 207 #define RCPU_IRC_CLK_RST 0x48 208 #define RCPU_IRC1_CLK_RST 0xEC 209 #define RCPU_GMAC_CLK_RST 0xE4 210 #define RCPU_ESPI_CLK_RST 0xDC 211 #define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 212 #define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 213 214 /* RCPU UARTCTRL register offsets */ 215 #define RCPU1_UART0_CLK_RST 0x00 216 #define RCPU1_UART1_CLK_RST 0x04 217 #define RCPU1_UART2_CLK_RST 0x08 218 #define RCPU1_UART3_CLK_RST 0x0c 219 #define RCPU1_UART4_CLK_RST 0x10 220 #define RCPU1_UART5_CLK_RST 0x14 221 222 /* RCPU I2SCTRL register offsets */ 223 #define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 224 #define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 225 #define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 226 #define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C 227 228 #define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 229 #define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 230 231 /* RCPU SPICTRL register offsets */ 232 #define RCPU3_SSP0_CLK_RST 0x00 233 #define RCPU3_SSP1_CLK_RST 0x04 234 #define RCPU3_PWR_SSP_CLK_RST 0x08 235 236 /* RCPU I2CCTRL register offsets */ 237 #define RCPU4_I2C0_CLK_RST 0x00 238 #define RCPU4_I2C1_CLK_RST 0x04 239 #define RCPU4_PWR_I2C_CLK_RST 0x08 240 241 /* RPMU register offsets */ 242 #define RCPU5_AON_PER_CLK_RST_CTRL 0x2C 243 #define RCPU5_TIMER1_CLK_RST 0x4C 244 #define RCPU5_TIMER2_CLK_RST 0x70 245 #define RCPU5_TIMER3_CLK_RST 0x78 246 #define RCPU5_TIMER4_CLK_RST 0x7C 247 #define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 248 #define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 249 #define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 250 #define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 251 #define RCPU5_RT24_CORE0_SW_RESET 0xCC 252 #define RCPU5_RT24_CORE1_SW_RESET 0xD0 253 254 /* RCPU PWMCTRL register offsets */ 255 #define RCPU6_PWM0_CLK_RST 0x00 256 #define RCPU6_PWM1_CLK_RST 0x04 257 #define RCPU6_PWM2_CLK_RST 0x08 258 #define RCPU6_PWM3_CLK_RST 0x0c 259 #define RCPU6_PWM4_CLK_RST 0x10 260 #define RCPU6_PWM5_CLK_RST 0x14 261 #define RCPU6_PWM6_CLK_RST 0x18 262 #define RCPU6_PWM7_CLK_RST 0x1c 263 #define RCPU6_PWM8_CLK_RST 0x20 264 #define RCPU6_PWM9_CLK_RST 0x24 265 266 /* APBC2 SEC register offsets */ 267 #define APBC2_UART1_CLK_RST 0x00 268 #define APBC2_SSP2_CLK_RST 0x04 269 #define APBC2_TWSI3_CLK_RST 0x08 270 #define APBC2_RTC_CLK_RST 0x0c 271 #define APBC2_TIMERS_CLK_RST 0x10 272 #define APBC2_GPIO_CLK_RST 0x1c 273 274 #endif /* __SOC_K3_SYSCON_H__ */ 275