1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2023 Broadcom Inc. All rights reserved. 4 */ 5 #ifndef MPI30_IOC_H 6 #define MPI30_IOC_H 1 7 struct mpi3_ioc_init_request { 8 __le16 host_tag; 9 u8 ioc_use_only02; 10 u8 function; 11 __le16 ioc_use_only04; 12 u8 ioc_use_only06; 13 u8 msg_flags; 14 __le16 change_count; 15 __le16 reserved0a; 16 union mpi3_version_union mpi_version; 17 __le64 time_stamp; 18 u8 reserved18; 19 u8 who_init; 20 __le16 reserved1a; 21 __le16 reply_free_queue_depth; 22 __le16 reserved1e; 23 __le64 reply_free_queue_address; 24 __le32 reserved28; 25 __le16 sense_buffer_free_queue_depth; 26 __le16 sense_buffer_length; 27 __le64 sense_buffer_free_queue_address; 28 __le64 driver_information_address; 29 }; 30 #define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08) 31 #define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) 32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) 33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0) 34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) 35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) 36 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) 37 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) 38 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 39 #define MPI3_WHOINIT_ROM_BIOS (0x02) 40 #define MPI3_WHOINIT_HOST_DRIVER (0x03) 41 #define MPI3_WHOINIT_MANUFACTURER (0x04) 42 43 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003) 44 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0) 45 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000) 46 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001) 47 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002) 48 #define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003) 49 50 struct mpi3_ioc_facts_request { 51 __le16 host_tag; 52 u8 ioc_use_only02; 53 u8 function; 54 __le16 ioc_use_only04; 55 u8 ioc_use_only06; 56 u8 msg_flags; 57 __le16 change_count; 58 __le16 reserved0a; 59 __le32 reserved0c; 60 union mpi3_sge_union sgl; 61 }; 62 63 struct mpi3_ioc_facts_data { 64 __le16 ioc_facts_data_length; 65 __le16 reserved02; 66 union mpi3_version_union mpi_version; 67 struct mpi3_comp_image_version fw_version; 68 __le32 ioc_capabilities; 69 u8 ioc_number; 70 u8 who_init; 71 __le16 max_msix_vectors; 72 __le16 max_outstanding_requests; 73 __le16 product_id; 74 __le16 ioc_request_frame_size; 75 __le16 reply_frame_size; 76 __le16 ioc_exceptions; 77 __le16 max_persistent_id; 78 u8 sge_modifier_mask; 79 u8 sge_modifier_value; 80 u8 sge_modifier_shift; 81 u8 protocol_flags; 82 __le16 max_sas_initiators; 83 __le16 max_data_length; 84 __le16 max_sas_expanders; 85 __le16 max_enclosures; 86 __le16 min_dev_handle; 87 __le16 max_dev_handle; 88 __le16 max_pcie_switches; 89 __le16 max_nvme; 90 __le16 reserved38; 91 __le16 max_vds; 92 __le16 max_host_pds; 93 __le16 max_adv_host_pds; 94 __le16 max_raid_pds; 95 __le16 max_posted_cmd_buffers; 96 __le32 flags; 97 __le16 max_operational_request_queues; 98 __le16 max_operational_reply_queues; 99 __le16 shutdown_timeout; 100 __le16 reserved4e; 101 __le32 diag_trace_size; 102 __le32 diag_fw_size; 103 __le32 diag_driver_size; 104 u8 max_host_pd_ns_count; 105 u8 max_adv_host_pd_ns_count; 106 u8 max_raidpd_ns_count; 107 u8 max_devices_per_throttle_group; 108 __le16 io_throttle_data_length; 109 __le16 max_io_throttle_group; 110 __le16 io_throttle_low; 111 __le16 io_throttle_high; 112 __le32 diag_fdl_size; 113 __le32 diag_tty_size; 114 }; 115 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) 116 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31) 117 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) 118 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) 119 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) 120 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9) 121 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) 122 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) 123 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100) 124 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080) 125 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040) 126 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020) 127 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010) 128 #define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008) 129 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002) 130 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) 131 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 132 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 133 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 134 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 135 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 136 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 137 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) 138 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) 139 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 140 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 141 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8) 142 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 143 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) 144 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) 145 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) 146 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) 147 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) 148 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) 149 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 150 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 151 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 152 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 153 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 154 #define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004) 155 #define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002) 156 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 157 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0) 158 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 159 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 160 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 161 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 162 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 163 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 164 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 165 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) 166 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 167 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 168 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 169 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 170 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4) 171 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 172 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 173 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 174 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 175 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0) 176 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 177 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 178 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) 179 #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) 180 #define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000) 181 #define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000) 182 struct mpi3_mgmt_passthrough_request { 183 __le16 host_tag; 184 u8 ioc_use_only02; 185 u8 function; 186 __le16 ioc_use_only04; 187 u8 ioc_use_only06; 188 u8 msg_flags; 189 __le16 change_count; 190 __le16 reserved0a; 191 __le32 reserved0c[5]; 192 union mpi3_sge_union command_sgl; 193 union mpi3_sge_union response_sgl; 194 }; 195 196 struct mpi3_create_request_queue_request { 197 __le16 host_tag; 198 u8 ioc_use_only02; 199 u8 function; 200 __le16 ioc_use_only04; 201 u8 ioc_use_only06; 202 u8 msg_flags; 203 __le16 change_count; 204 u8 flags; 205 u8 burst; 206 __le16 size; 207 __le16 queue_id; 208 __le16 reply_queue_id; 209 __le16 reserved12; 210 __le32 reserved14; 211 __le64 base_address; 212 }; 213 214 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 215 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7) 216 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 217 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 218 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) 219 struct mpi3_delete_request_queue_request { 220 __le16 host_tag; 221 u8 ioc_use_only02; 222 u8 function; 223 __le16 ioc_use_only04; 224 u8 ioc_use_only06; 225 u8 msg_flags; 226 __le16 change_count; 227 __le16 queue_id; 228 }; 229 230 struct mpi3_create_reply_queue_request { 231 __le16 host_tag; 232 u8 ioc_use_only02; 233 u8 function; 234 __le16 ioc_use_only04; 235 u8 ioc_use_only06; 236 u8 msg_flags; 237 __le16 change_count; 238 u8 flags; 239 u8 reserved0b; 240 __le16 size; 241 __le16 queue_id; 242 __le16 msix_index; 243 __le16 reserved12; 244 __le32 reserved14; 245 __le64 base_address; 246 }; 247 248 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 249 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7) 250 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 251 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 252 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) 253 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 254 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0) 255 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 256 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 257 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) 258 struct mpi3_delete_reply_queue_request { 259 __le16 host_tag; 260 u8 ioc_use_only02; 261 u8 function; 262 __le16 ioc_use_only04; 263 u8 ioc_use_only06; 264 u8 msg_flags; 265 __le16 change_count; 266 __le16 queue_id; 267 }; 268 269 struct mpi3_port_enable_request { 270 __le16 host_tag; 271 u8 ioc_use_only02; 272 u8 function; 273 __le16 ioc_use_only04; 274 u8 ioc_use_only06; 275 u8 msg_flags; 276 __le16 change_count; 277 __le16 reserved0a; 278 }; 279 280 #define MPI3_EVENT_LOG_DATA (0x01) 281 #define MPI3_EVENT_CHANGE (0x02) 282 #define MPI3_EVENT_GPIO_INTERRUPT (0x04) 283 #define MPI3_EVENT_CABLE_MGMT (0x06) 284 #define MPI3_EVENT_DEVICE_ADDED (0x07) 285 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 286 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 287 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 288 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 289 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 290 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 291 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 292 #define MPI3_EVENT_SAS_DISCOVERY (0x11) 293 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 294 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 295 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 296 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 297 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 298 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 299 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 300 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 301 #define MPI3_EVENT_PCIE_ENUMERATION (0x22) 302 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) 303 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 304 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) 305 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 306 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 307 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 308 struct mpi3_event_notification_request { 309 __le16 host_tag; 310 u8 ioc_use_only02; 311 u8 function; 312 __le16 ioc_use_only04; 313 u8 ioc_use_only06; 314 u8 msg_flags; 315 __le16 change_count; 316 __le16 reserved0a; 317 __le16 sas_broadcast_primitive_masks; 318 __le16 sas_notify_primitive_masks; 319 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 320 }; 321 322 struct mpi3_event_notification_reply { 323 __le16 host_tag; 324 u8 ioc_use_only02; 325 u8 function; 326 __le16 ioc_use_only04; 327 u8 ioc_use_only06; 328 u8 msg_flags; 329 __le16 ioc_use_only08; 330 __le16 ioc_status; 331 __le32 ioc_log_info; 332 u8 event_data_length; 333 u8 event; 334 __le16 ioc_change_count; 335 __le32 event_context; 336 __le32 event_data[1]; 337 }; 338 339 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 340 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0) 341 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 342 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 343 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 344 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1) 345 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 346 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 347 struct mpi3_event_data_gpio_interrupt { 348 u8 gpio_num; 349 u8 reserved01[3]; 350 }; 351 struct mpi3_event_data_cable_management { 352 __le32 active_cable_power_requirement; 353 u8 status; 354 u8 receptacle_id; 355 __le16 reserved06; 356 }; 357 358 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 359 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 360 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 361 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 362 struct mpi3_event_ack_request { 363 __le16 host_tag; 364 u8 ioc_use_only02; 365 u8 function; 366 __le16 ioc_use_only04; 367 u8 ioc_use_only06; 368 u8 msg_flags; 369 __le16 change_count; 370 __le16 reserved0a; 371 u8 event; 372 u8 reserved0d[3]; 373 __le32 event_context; 374 }; 375 376 struct mpi3_event_data_prepare_for_reset { 377 u8 reason_code; 378 u8 reserved01; 379 __le16 reserved02; 380 }; 381 382 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 383 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 384 struct mpi3_event_data_comp_image_activation { 385 __le32 reserved00; 386 }; 387 388 struct mpi3_event_data_device_status_change { 389 __le16 task_tag; 390 u8 reason_code; 391 u8 io_unit_port; 392 __le16 parent_dev_handle; 393 __le16 dev_handle; 394 __le64 wwid; 395 u8 lun[8]; 396 }; 397 398 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 399 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 400 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 401 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 402 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 403 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 404 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 405 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 406 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 407 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 408 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 409 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 410 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 411 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 412 struct mpi3_event_data_energy_pack_change { 413 __le32 reserved00; 414 __le16 shutdown_timeout; 415 __le16 reserved06; 416 }; 417 418 struct mpi3_event_data_sas_discovery { 419 u8 flags; 420 u8 reason_code; 421 u8 io_unit_port; 422 u8 reserved03; 423 __le32 discovery_status; 424 }; 425 426 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 427 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 428 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 429 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 430 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 431 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 432 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 433 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 434 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) 435 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) 436 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 437 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) 438 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 439 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 440 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 441 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 442 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 443 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 444 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 445 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 446 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 447 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 448 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 449 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 450 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 451 struct mpi3_event_data_sas_broadcast_primitive { 452 u8 phy_num; 453 u8 io_unit_port; 454 u8 port_width; 455 u8 primitive; 456 }; 457 458 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 459 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 460 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 461 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 462 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 463 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 464 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 465 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 466 struct mpi3_event_data_sas_notify_primitive { 467 u8 phy_num; 468 u8 io_unit_port; 469 u8 reserved02; 470 u8 primitive; 471 }; 472 473 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 474 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 475 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 476 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 477 struct mpi3_event_sas_topo_phy_entry { 478 __le16 attached_dev_handle; 479 u8 link_rate; 480 u8 status; 481 }; 482 483 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 484 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 485 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 486 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 487 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 488 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 489 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 490 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 491 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 492 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 493 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 494 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 495 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 496 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 497 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 498 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 499 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 500 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 501 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 502 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 503 #define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0) 504 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 505 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 506 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 507 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 508 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 509 struct mpi3_event_data_sas_topology_change_list { 510 __le16 enclosure_handle; 511 __le16 expander_dev_handle; 512 u8 num_phys; 513 u8 reserved05[3]; 514 u8 num_entries; 515 u8 start_phy_num; 516 u8 exp_status; 517 u8 io_unit_port; 518 struct mpi3_event_sas_topo_phy_entry phy_entry[] __counted_by(num_entries); 519 }; 520 521 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 522 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 523 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 524 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 525 struct mpi3_event_data_sas_phy_counter { 526 __le64 time_stamp; 527 __le32 reserved08; 528 u8 phy_event_code; 529 u8 phy_num; 530 __le16 reserved0e; 531 __le32 phy_event_info; 532 u8 counter_type; 533 u8 threshold_window; 534 u8 time_units; 535 u8 reserved17; 536 __le32 event_threshold; 537 __le16 threshold_flags; 538 __le16 reserved1e; 539 }; 540 541 struct mpi3_event_data_sas_device_disc_err { 542 __le16 dev_handle; 543 u8 reason_code; 544 u8 io_unit_port; 545 __le32 reserved04; 546 __le64 sas_address; 547 }; 548 549 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 550 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 551 struct mpi3_event_data_pcie_enumeration { 552 u8 flags; 553 u8 reason_code; 554 u8 io_unit_port; 555 u8 reserved03; 556 __le32 enumeration_status; 557 }; 558 559 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 560 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 561 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 562 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 563 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 564 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 565 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 566 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 567 struct mpi3_event_pcie_topo_port_entry { 568 __le16 attached_dev_handle; 569 u8 port_status; 570 u8 reserved03; 571 u8 current_port_info; 572 u8 reserved05; 573 u8 previous_port_info; 574 u8 reserved07; 575 }; 576 577 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 578 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 579 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 580 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 581 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 582 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 583 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4) 584 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 585 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 586 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 587 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 588 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 589 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 590 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 591 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0) 592 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 593 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 594 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 595 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 596 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 597 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 598 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 599 struct mpi3_event_data_pcie_topology_change_list { 600 __le16 enclosure_handle; 601 __le16 switch_dev_handle; 602 u8 num_ports; 603 u8 reserved05[3]; 604 u8 num_entries; 605 u8 start_port_num; 606 u8 switch_status; 607 u8 io_unit_port; 608 __le32 reserved0c; 609 struct mpi3_event_pcie_topo_port_entry port_entry[] __counted_by(num_entries); 610 }; 611 612 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 613 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 614 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 615 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 616 struct mpi3_event_data_pcie_error_threshold { 617 __le64 timestamp; 618 u8 reason_code; 619 u8 port; 620 __le16 switch_dev_handle; 621 u8 error; 622 u8 action; 623 __le16 threshold_count; 624 __le16 attached_dev_handle; 625 __le16 reserved12; 626 __le32 reserved14; 627 }; 628 629 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) 630 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) 631 struct mpi3_event_data_sas_init_dev_status_change { 632 u8 reason_code; 633 u8 io_unit_port; 634 __le16 dev_handle; 635 __le32 reserved04; 636 __le64 sas_address; 637 }; 638 639 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 640 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 641 struct mpi3_event_data_sas_init_table_overflow { 642 __le16 max_init; 643 __le16 current_init; 644 __le32 reserved04; 645 __le64 sas_address; 646 }; 647 648 struct mpi3_event_data_hard_reset_received { 649 u8 reserved00; 650 u8 io_unit_port; 651 __le16 reserved02; 652 }; 653 654 struct mpi3_event_data_diag_buffer_status_change { 655 u8 type; 656 u8 reason_code; 657 __le16 reserved02; 658 __le32 reserved04; 659 }; 660 661 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) 662 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) 663 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) 664 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 665 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 666 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 667 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 668 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 669 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 670 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 671 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 672 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 673 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 674 #define MPI3_PEL_CLASS_DEBUG (0x00) 675 #define MPI3_PEL_CLASS_PROGRESS (0x01) 676 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 677 #define MPI3_PEL_CLASS_WARNING (0x03) 678 #define MPI3_PEL_CLASS_CRITICAL (0x04) 679 #define MPI3_PEL_CLASS_FATAL (0x05) 680 #define MPI3_PEL_CLASS_FAULT (0x06) 681 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 682 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 683 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 684 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 685 #define MPI3_PEL_ACTION_GET_LOG (0x03) 686 #define MPI3_PEL_ACTION_GET_COUNT (0x04) 687 #define MPI3_PEL_ACTION_WAIT (0x05) 688 #define MPI3_PEL_ACTION_ABORT (0x06) 689 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 690 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 691 #define MPI3_PEL_STATUS_SUCCESS (0x00) 692 #define MPI3_PEL_STATUS_NOT_FOUND (0x01) 693 #define MPI3_PEL_STATUS_ABORTED (0x02) 694 #define MPI3_PEL_STATUS_NOT_READY (0x03) 695 struct mpi3_pel_seq { 696 __le32 newest; 697 __le32 oldest; 698 __le32 clear; 699 __le32 shutdown; 700 __le32 boot; 701 __le32 last_acknowledged; 702 }; 703 704 struct mpi3_pel_entry { 705 __le64 time_stamp; 706 __le32 sequence_number; 707 __le16 log_code; 708 __le16 arg_type; 709 __le16 locale; 710 u8 class; 711 u8 flags; 712 u8 ext_num; 713 u8 num_exts; 714 u8 arg_data_size; 715 u8 fixed_format_strings_size; 716 __le32 reserved18[2]; 717 __le32 pel_info[24]; 718 }; 719 720 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) 721 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) 722 struct mpi3_pel_list { 723 __le32 log_count; 724 __le32 reserved04; 725 struct mpi3_pel_entry entry[1]; 726 }; 727 728 struct mpi3_pel_arg_map { 729 u8 arg_type; 730 u8 length; 731 __le16 start_location; 732 }; 733 734 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 735 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 736 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 737 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 738 struct mpi3_pel_print_string { 739 __le16 log_code; 740 __le16 string_length; 741 u8 num_arg_map; 742 u8 reserved05[3]; 743 struct mpi3_pel_arg_map arg_map[1]; 744 }; 745 746 struct mpi3_pel_print_string_list { 747 __le32 num_print_strings; 748 __le32 residual_bytes_remain; 749 __le32 reserved08[2]; 750 struct mpi3_pel_print_string print_string[1]; 751 }; 752 753 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 754 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 755 #endif 756 struct mpi3_pel_request { 757 __le16 host_tag; 758 u8 ioc_use_only02; 759 u8 function; 760 __le16 ioc_use_only04; 761 u8 ioc_use_only06; 762 u8 msg_flags; 763 __le16 change_count; 764 u8 action; 765 u8 reserved0b; 766 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 767 }; 768 769 struct mpi3_pel_req_action_get_sequence_numbers { 770 __le16 host_tag; 771 u8 ioc_use_only02; 772 u8 function; 773 __le16 ioc_use_only04; 774 u8 ioc_use_only06; 775 u8 msg_flags; 776 __le16 change_count; 777 u8 action; 778 u8 reserved0b; 779 __le32 reserved0c[5]; 780 union mpi3_sge_union sgl; 781 }; 782 783 struct mpi3_pel_req_action_clear_log_marker { 784 __le16 host_tag; 785 u8 ioc_use_only02; 786 u8 function; 787 __le16 ioc_use_only04; 788 u8 ioc_use_only06; 789 u8 msg_flags; 790 __le16 change_count; 791 u8 action; 792 u8 reserved0b; 793 u8 clear_type; 794 u8 reserved0d[3]; 795 }; 796 797 struct mpi3_pel_req_action_get_log { 798 __le16 host_tag; 799 u8 ioc_use_only02; 800 u8 function; 801 __le16 ioc_use_only04; 802 u8 ioc_use_only06; 803 u8 msg_flags; 804 __le16 change_count; 805 u8 action; 806 u8 reserved0b; 807 __le32 starting_sequence_number; 808 __le16 locale; 809 u8 class; 810 u8 reserved13; 811 __le32 reserved14[3]; 812 union mpi3_sge_union sgl; 813 }; 814 815 struct mpi3_pel_req_action_get_count { 816 __le16 host_tag; 817 u8 ioc_use_only02; 818 u8 function; 819 __le16 ioc_use_only04; 820 u8 ioc_use_only06; 821 u8 msg_flags; 822 __le16 change_count; 823 u8 action; 824 u8 reserved0b; 825 __le32 starting_sequence_number; 826 __le16 locale; 827 u8 class; 828 u8 reserved13; 829 __le32 reserved14[3]; 830 union mpi3_sge_union sgl; 831 }; 832 833 struct mpi3_pel_req_action_wait { 834 __le16 host_tag; 835 u8 ioc_use_only02; 836 u8 function; 837 __le16 ioc_use_only04; 838 u8 ioc_use_only06; 839 u8 msg_flags; 840 __le16 change_count; 841 u8 action; 842 u8 reserved0b; 843 __le32 starting_sequence_number; 844 __le16 locale; 845 u8 class; 846 u8 reserved13; 847 __le16 wait_time; 848 __le16 reserved16; 849 __le32 reserved18[2]; 850 }; 851 852 struct mpi3_pel_req_action_abort { 853 __le16 host_tag; 854 u8 ioc_use_only02; 855 u8 function; 856 __le16 ioc_use_only04; 857 u8 ioc_use_only06; 858 u8 msg_flags; 859 __le16 change_count; 860 u8 action; 861 u8 reserved0b; 862 __le32 reserved0c; 863 __le16 abort_host_tag; 864 __le16 reserved12; 865 __le32 reserved14; 866 }; 867 868 struct mpi3_pel_req_action_get_print_strings { 869 __le16 host_tag; 870 u8 ioc_use_only02; 871 u8 function; 872 __le16 ioc_use_only04; 873 u8 ioc_use_only06; 874 u8 msg_flags; 875 __le16 change_count; 876 u8 action; 877 u8 reserved0b; 878 __le32 reserved0c; 879 __le16 start_log_code; 880 __le16 reserved12; 881 __le32 reserved14[3]; 882 union mpi3_sge_union sgl; 883 }; 884 885 struct mpi3_pel_req_action_acknowledge { 886 __le16 host_tag; 887 u8 ioc_use_only02; 888 u8 function; 889 __le16 ioc_use_only04; 890 u8 ioc_use_only06; 891 u8 msg_flags; 892 __le16 change_count; 893 u8 action; 894 u8 reserved0b; 895 __le32 sequence_number; 896 __le32 reserved10; 897 }; 898 899 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) 900 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0) 901 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) 902 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) 903 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) 904 struct mpi3_pel_reply { 905 __le16 host_tag; 906 u8 ioc_use_only02; 907 u8 function; 908 __le16 ioc_use_only04; 909 u8 ioc_use_only06; 910 u8 msg_flags; 911 __le16 ioc_use_only08; 912 __le16 ioc_status; 913 __le32 ioc_log_info; 914 u8 action; 915 u8 reserved11; 916 __le16 reserved12; 917 __le16 pe_log_status; 918 __le16 reserved16; 919 __le32 transfer_length; 920 }; 921 922 struct mpi3_ci_download_request { 923 __le16 host_tag; 924 u8 ioc_use_only02; 925 u8 function; 926 __le16 ioc_use_only04; 927 u8 ioc_use_only06; 928 u8 msg_flags; 929 __le16 change_count; 930 u8 action; 931 u8 reserved0b; 932 __le32 signature1; 933 __le32 total_image_size; 934 __le32 image_offset; 935 __le32 segment_size; 936 __le32 reserved1c; 937 union mpi3_sge_union sgl; 938 }; 939 940 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 941 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 942 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 943 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 944 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0) 945 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 946 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 947 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 948 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 949 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 950 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 951 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 952 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) 953 struct mpi3_ci_download_reply { 954 __le16 host_tag; 955 u8 ioc_use_only02; 956 u8 function; 957 __le16 ioc_use_only04; 958 u8 ioc_use_only06; 959 u8 msg_flags; 960 __le16 ioc_use_only08; 961 __le16 ioc_status; 962 __le32 ioc_log_info; 963 u8 flags; 964 u8 cache_dirty; 965 u8 pending_count; 966 u8 reserved13; 967 }; 968 969 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 970 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40) 971 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) 972 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 973 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 974 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1) 975 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 976 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 977 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 978 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 979 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 980 struct mpi3_ci_upload_request { 981 __le16 host_tag; 982 u8 ioc_use_only02; 983 u8 function; 984 __le16 ioc_use_only04; 985 u8 ioc_use_only06; 986 u8 msg_flags; 987 __le16 change_count; 988 __le16 reserved0a; 989 __le32 signature1; 990 __le32 reserved10; 991 __le32 image_offset; 992 __le32 segment_size; 993 __le32 reserved1c; 994 union mpi3_sge_union sgl; 995 }; 996 997 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 998 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0) 999 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 1000 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 1001 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 1002 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1) 1003 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 1004 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 1005 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 1006 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 1007 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 1008 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 1009 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06) 1010 #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07) 1011 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 1012 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 1013 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 1014 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) 1015 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20) 1016 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) 1017 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) 1018 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) 1019 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) 1020 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 1021 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 1022 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00) 1023 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 1024 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 1025 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 1026 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) 1027 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00) 1028 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 1029 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 1030 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) 1031 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) 1032 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1033 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1034 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) 1035 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) 1036 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) 1037 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1038 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1039 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1040 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 1041 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 1042 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 1043 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 1044 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 1045 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 1046 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 1047 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 1048 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 1049 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 1050 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 1051 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0) 1052 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) 1053 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 1054 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 1055 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 1056 #define MPI3_CTRL_ACTION_NOP (0x00) 1057 #define MPI3_CTRL_ACTION_LINK_RESET (0x01) 1058 #define MPI3_CTRL_ACTION_HARD_RESET (0x02) 1059 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) 1060 struct mpi3_iounit_control_request { 1061 __le16 host_tag; 1062 u8 ioc_use_only02; 1063 u8 function; 1064 __le16 ioc_use_only04; 1065 u8 ioc_use_only06; 1066 u8 msg_flags; 1067 __le16 change_count; 1068 u8 reserved0a; 1069 u8 operation; 1070 __le32 reserved0c; 1071 __le64 param64[2]; 1072 __le32 param32[4]; 1073 __le16 param16[4]; 1074 u8 param8[8]; 1075 }; 1076 1077 struct mpi3_iounit_control_reply { 1078 __le16 host_tag; 1079 u8 ioc_use_only02; 1080 u8 function; 1081 __le16 ioc_use_only04; 1082 u8 ioc_use_only06; 1083 u8 msg_flags; 1084 __le16 ioc_use_only08; 1085 __le16 ioc_status; 1086 __le32 ioc_log_info; 1087 __le64 value64[2]; 1088 __le32 value32[4]; 1089 __le16 value16[4]; 1090 u8 value8[8]; 1091 }; 1092 #endif 1093