1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #ifndef MPI3MR_H_INCLUDED
11 #define MPI3MR_H_INCLUDED
12
13 #include <linux/blkdev.h>
14 #include <linux/blk-mq.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/delay.h>
17 #include <linux/dmapool.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/miscdevice.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/aer.h>
27 #include <linux/poll.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/types.h>
31 #include <linux/uaccess.h>
32 #include <linux/utsname.h>
33 #include <linux/workqueue.h>
34 #include <linux/unaligned.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_dbg.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_tcq.h>
41 #include <uapi/scsi/scsi_bsg_mpi3mr.h>
42 #include <scsi/scsi_transport_sas.h>
43
44 #include "mpi/mpi30_transport.h"
45 #include "mpi/mpi30_cnfg.h"
46 #include "mpi/mpi30_image.h"
47 #include "mpi/mpi30_init.h"
48 #include "mpi/mpi30_ioc.h"
49 #include "mpi/mpi30_sas.h"
50 #include "mpi/mpi30_pci.h"
51 #include "mpi/mpi30_tool.h"
52 #include "mpi3mr_debug.h"
53
54 /* Global list and lock for storing multiple adapters managed by the driver */
55 extern spinlock_t mrioc_list_lock;
56 extern struct list_head mrioc_list;
57 extern int prot_mask;
58 extern atomic64_t event_counter;
59
60 #define MPI3MR_DRIVER_VERSION "8.12.0.3.50"
61 #define MPI3MR_DRIVER_RELDATE "11-November-2024"
62
63 #define MPI3MR_DRIVER_NAME "mpi3mr"
64 #define MPI3MR_DRIVER_LICENSE "GPL"
65 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
66 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
67
68 #define MPI3MR_NAME_LENGTH 64
69 #define IOCNAME "%s: "
70
71 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)
72
73 /* Definitions for internal SGL and Chain SGL buffers */
74 #define MPI3MR_PAGE_SIZE_4K 4096
75 #define MPI3MR_DEFAULT_SGL_ENTRIES 256
76 #define MPI3MR_MAX_SGL_ENTRIES 2048
77
78 /* Definitions for MAX values for shost */
79 #define MPI3MR_MAX_CMDS_LUN 128
80 #define MPI3MR_MAX_CDB_LENGTH 32
81
82 /* Admin queue management definitions */
83 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
84 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
85 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128
86 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
87
88 /* Operational queue management definitions */
89 #define MPI3MR_OP_REQ_Q_QD 512
90 #define MPI3MR_OP_REP_Q_QD 1024
91 #define MPI3MR_OP_REP_Q_QD4K 4096
92 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
93 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096
94 #define MPI3MR_MAX_SEG_LIST_SIZE 4096
95
96 /* Reserved Host Tag definitions */
97 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
98 #define MPI3MR_HOSTTAG_INITCMDS 1
99 #define MPI3MR_HOSTTAG_BSG_CMDS 2
100 #define MPI3MR_HOSTTAG_PEL_ABORT 3
101 #define MPI3MR_HOSTTAG_PEL_WAIT 4
102 #define MPI3MR_HOSTTAG_BLK_TMS 5
103 #define MPI3MR_HOSTTAG_CFG_CMDS 6
104 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7
105
106 #define MPI3MR_NUM_DEVRMCMD 16
107 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)
108 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
109 MPI3MR_NUM_DEVRMCMD - 1)
110
111 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
112 #define MPI3MR_NUM_EVTACKCMD 4
113 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
114 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
115 MPI3MR_NUM_EVTACKCMD - 1)
116
117 /* Reduced resource count definition for crash kernel */
118 #define MPI3MR_HOST_IOS_KDUMP 128
119
120 /* command/controller interaction timeout definitions in seconds */
121 #define MPI3MR_INTADMCMD_TIMEOUT 60
122 #define MPI3MR_PORTENABLE_TIMEOUT 300
123 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5
124 #define MPI3MR_ABORTTM_TIMEOUT 60
125 #define MPI3MR_RESETTM_TIMEOUT 60
126 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
127 #define MPI3MR_TSUPDATE_INTERVAL 900
128 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
129 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
130 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
131 #define MPI3MR_RESET_ACK_TIMEOUT 30
132 #define MPI3MR_MUR_TIMEOUT 120
133 #define MPI3MR_RESET_TIMEOUT 510
134
135 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
136
137 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10
138
139 #define MPI3MR_SCMD_TIMEOUT (60 * HZ)
140 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
141
142 /* Internal admin command state definitions*/
143 #define MPI3MR_CMD_NOTUSED 0x8000
144 #define MPI3MR_CMD_COMPLETE 0x0001
145 #define MPI3MR_CMD_PENDING 0x0002
146 #define MPI3MR_CMD_REPLY_VALID 0x0004
147 #define MPI3MR_CMD_RESET 0x0008
148
149 /* Definitions for Event replies and sense buffer allocated per controller */
150 #define MPI3MR_NUM_EVT_REPLIES 64
151 #define MPI3MR_SENSE_BUF_SZ 256
152 #define MPI3MR_SENSEBUF_FACTOR 3
153 #define MPI3MR_CHAINBUF_FACTOR 3
154 #define MPI3MR_CHAINBUFDIX_FACTOR 2
155
156 /* Invalid target device handle */
157 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
158
159 /* Controller Reset related definitions */
160 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
161 #define MPI3MR_MAX_RESET_RETRY_COUNT 3
162
163 /* ResponseCode definitions */
164 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
165 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
166 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
167
168 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
169 #define MPI3MR_DEFAULT_PGSZEXP (12)
170
171 /* Command retry count definitions */
172 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
173 #define MPI3MR_PEL_RETRY_COUNT 3
174
175 /* Default target device queue depth */
176 #define MPI3MR_DEFAULT_SDEV_QD 32
177
178 /* Definitions for Threaded IRQ poll*/
179 #define MPI3MR_IRQ_POLL_SLEEP 20
180 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
181
182 /* Definitions for the controller security status*/
183 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
184 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
185
186 #define MPI3MR_INVALID_DEVICE 0x00
187 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
188 #define MPI3MR_HARD_SECURE_DEVICE 0x08
189 #define MPI3MR_TAMPERED_DEVICE 0x0C
190
191 #define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024)
192 #define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024)
193 #define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024)
194 #define MPI3MR_MAX_NUM_HDB 2
195
196 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0
197 #define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1
198 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2
199 #define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3
200 #define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4
201 #define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5
202
203 #define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0
204 #define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1
205 #define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2
206 #define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3
207
208 #define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024)
209 #define MPI3MR_MAX_NUM_HDB 2
210
211 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0
212 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1
213
214 #define MPI3MR_THRESHOLD_REPLY_COUNT 100
215
216 /* SGE Flag definition */
217 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
218 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
219 MPI3_SGE_FLAGS_END_OF_LIST)
220
221 /* MSI Index from Reply Queue Index */
222 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
223
224 /*
225 * Maximum data transfer size definitions for management
226 * application commands
227 */
228 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
229 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512
230 /*
231 * 2048 sectors are for data buffers and additional 512 sectors for
232 * other buffers
233 */
234 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
235
236 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256
237 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048
238
239 #define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD)
240
241 /**
242 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
243 * Encapsulated commands.
244 *
245 * @base_addr: Physical address
246 * @length: SGE length
247 * @rsvd: Reserved
248 * @rsvd1: Reserved
249 * @sub_type: sgl sub type
250 * @type: sgl type
251 */
252 struct mpi3mr_nvme_pt_sge {
253 __le64 base_addr;
254 __le32 length;
255 u16 rsvd;
256 u8 rsvd1;
257 u8 sub_type:4;
258 u8 type:4;
259 };
260
261 /**
262 * struct mpi3mr_buf_map - local structure to
263 * track kernel and user buffers associated with an BSG
264 * structure.
265 *
266 * @bsg_buf: BSG buffer virtual address
267 * @bsg_buf_len: BSG buffer length
268 * @kern_buf: Kernel buffer virtual address
269 * @kern_buf_len: Kernel buffer length
270 * @kern_buf_dma: Kernel buffer DMA address
271 * @data_dir: Data direction.
272 */
273 struct mpi3mr_buf_map {
274 void *bsg_buf;
275 u32 bsg_buf_len;
276 void *kern_buf;
277 u32 kern_buf_len;
278 dma_addr_t kern_buf_dma;
279 u8 data_dir;
280 u16 num_dma_desc;
281 struct dma_memory_desc *dma_desc;
282 };
283
284 /* IOC State definitions */
285 enum mpi3mr_iocstate {
286 MRIOC_STATE_READY = 1,
287 MRIOC_STATE_RESET,
288 MRIOC_STATE_FAULT,
289 MRIOC_STATE_BECOMING_READY,
290 MRIOC_STATE_RESET_REQUESTED,
291 MRIOC_STATE_UNRECOVERABLE,
292 };
293
294 /* Reset reason code definitions*/
295 enum mpi3mr_reset_reason {
296 MPI3MR_RESET_FROM_BRINGUP = 1,
297 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
298 MPI3MR_RESET_FROM_APP = 3,
299 MPI3MR_RESET_FROM_EH_HOS = 4,
300 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
301 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
302 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
303 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
304 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
305 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
306 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
307 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
308 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
309 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
310 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
311 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
312 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
313 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
314 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
315 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
316 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
317 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
318 MPI3MR_RESET_FROM_SYSFS = 23,
319 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
320 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
321 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26,
322 MPI3MR_RESET_FROM_FIRMWARE = 27,
323 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
324 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
325 MPI3MR_RESET_FROM_TRIGGER = 31,
326 };
327
328 #define MPI3MR_RESET_REASON_OSTYPE_LINUX 1
329 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28
330 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20
331
332 /* Queue type definitions */
333 enum queue_type {
334 MPI3MR_DEFAULT_QUEUE = 0,
335 MPI3MR_POLL_QUEUE,
336 };
337
338 /**
339 * struct mpi3mr_compimg_ver - replica of component image
340 * version defined in mpi30_image.h in host endianness
341 *
342 */
343 struct mpi3mr_compimg_ver {
344 u16 build_num;
345 u16 cust_id;
346 u8 ph_minor;
347 u8 ph_major;
348 u8 gen_minor;
349 u8 gen_major;
350 };
351
352 /**
353 * struct mpi3mr_ioc_facs - replica of component image version
354 * defined in mpi30_ioc.h in host endianness
355 *
356 */
357 struct mpi3mr_ioc_facts {
358 u32 ioc_capabilities;
359 struct mpi3mr_compimg_ver fw_ver;
360 u32 mpi_version;
361 u32 diag_trace_sz;
362 u32 diag_fw_sz;
363 u32 diag_drvr_sz;
364 u16 max_reqs;
365 u16 product_id;
366 u16 op_req_sz;
367 u16 reply_sz;
368 u16 exceptions;
369 u16 max_perids;
370 u16 max_pds;
371 u16 max_sasexpanders;
372 u32 max_data_length;
373 u16 max_sasinitiators;
374 u16 max_enclosures;
375 u16 max_pcie_switches;
376 u16 max_nvme;
377 u16 max_vds;
378 u16 max_hpds;
379 u16 max_advhpds;
380 u16 max_raid_pds;
381 u16 min_devhandle;
382 u16 max_devhandle;
383 u16 max_op_req_q;
384 u16 max_op_reply_q;
385 u16 shutdown_timeout;
386 u8 ioc_num;
387 u8 who_init;
388 u16 max_msix_vectors;
389 u8 personality;
390 u8 dma_mask;
391 u8 protocol_flags;
392 u8 sge_mod_mask;
393 u8 sge_mod_value;
394 u8 sge_mod_shift;
395 u8 max_dev_per_tg;
396 u16 max_io_throttle_group;
397 u16 io_throttle_data_length;
398 u16 io_throttle_low;
399 u16 io_throttle_high;
400
401 };
402
403 /**
404 * struct segments - memory descriptor structure to store
405 * virtual and dma addresses for operational queue segments.
406 *
407 * @segment: virtual address
408 * @segment_dma: dma address
409 */
410 struct segments {
411 void *segment;
412 dma_addr_t segment_dma;
413 };
414
415 /**
416 * struct op_req_qinfo - Operational Request Queue Information
417 *
418 * @ci: consumer index
419 * @pi: producer index
420 * @num_request: Maximum number of entries in the queue
421 * @qid: Queue Id starting from 1
422 * @reply_qid: Associated reply queue Id
423 * @num_segments: Number of discontiguous memory segments
424 * @segment_qd: Depth of each segments
425 * @q_lock: Concurrent queue access lock
426 * @q_segments: Segment descriptor pointer
427 * @q_segment_list: Segment list base virtual address
428 * @q_segment_list_dma: Segment list base DMA address
429 */
430 struct op_req_qinfo {
431 u16 ci;
432 u16 pi;
433 u16 num_requests;
434 u16 qid;
435 u16 reply_qid;
436 u16 num_segments;
437 u16 segment_qd;
438 spinlock_t q_lock;
439 struct segments *q_segments;
440 void *q_segment_list;
441 dma_addr_t q_segment_list_dma;
442 };
443
444 /**
445 * struct op_reply_qinfo - Operational Reply Queue Information
446 *
447 * @ci: consumer index
448 * @qid: Queue Id starting from 1
449 * @num_replies: Maximum number of entries in the queue
450 * @num_segments: Number of discontiguous memory segments
451 * @segment_qd: Depth of each segments
452 * @q_segments: Segment descriptor pointer
453 * @q_segment_list: Segment list base virtual address
454 * @q_segment_list_dma: Segment list base DMA address
455 * @ephase: Expected phased identifier for the reply queue
456 * @pend_ios: Number of IOs pending in HW for this queue
457 * @enable_irq_poll: Flag to indicate polling is enabled
458 * @in_use: Queue is handled by poll/ISR
459 * @qtype: Type of queue (types defined in enum queue_type)
460 */
461 struct op_reply_qinfo {
462 u16 ci;
463 u16 qid;
464 u16 num_replies;
465 u16 num_segments;
466 u16 segment_qd;
467 struct segments *q_segments;
468 void *q_segment_list;
469 dma_addr_t q_segment_list_dma;
470 u8 ephase;
471 atomic_t pend_ios;
472 bool enable_irq_poll;
473 atomic_t in_use;
474 enum queue_type qtype;
475 };
476
477 /**
478 * struct mpi3mr_intr_info - Interrupt cookie information
479 *
480 * @mrioc: Adapter instance reference
481 * @os_irq: irq number
482 * @msix_index: MSIx index
483 * @op_reply_q: Associated operational reply queue
484 * @name: Dev name for the irq claiming device
485 */
486 struct mpi3mr_intr_info {
487 struct mpi3mr_ioc *mrioc;
488 int os_irq;
489 u16 msix_index;
490 struct op_reply_qinfo *op_reply_q;
491 char name[MPI3MR_NAME_LENGTH];
492 };
493
494 /**
495 * struct mpi3mr_throttle_group_info - Throttle group info
496 *
497 * @io_divert: Flag indicates io divert is on or off for the TG
498 * @need_qd_reduction: Flag to indicate QD reduction is needed
499 * @qd_reduction: Queue Depth reduction in units of 10%
500 * @fw_qd: QueueDepth value reported by the firmware
501 * @modified_qd: Modified QueueDepth value due to throttling
502 * @id: Throttle Group ID.
503 * @high: High limit to turn on throttling in 512 byte blocks
504 * @low: Low limit to turn off throttling in 512 byte blocks
505 * @pend_large_data_sz: Counter to track pending large data
506 */
507 struct mpi3mr_throttle_group_info {
508 u8 io_divert;
509 u8 need_qd_reduction;
510 u8 qd_reduction;
511 u16 fw_qd;
512 u16 modified_qd;
513 u16 id;
514 u32 high;
515 u32 low;
516 atomic_t pend_large_data_sz;
517 };
518
519 /* HBA port flags */
520 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01
521 #define MPI3MR_HBA_PORT_FLAG_NEW 0x02
522
523 /* IOCTL data transfer sge*/
524 #define MPI3MR_NUM_IOCTL_SGE 256
525 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
526
527 /**
528 * struct mpi3mr_hba_port - HBA's port information
529 * @port_id: Port number
530 * @flags: HBA port flags
531 */
532 struct mpi3mr_hba_port {
533 struct list_head list;
534 u8 port_id;
535 u8 flags;
536 };
537
538 /**
539 * struct mpi3mr_sas_port - Internal SAS port information
540 * @port_list: List of ports belonging to a SAS node
541 * @num_phys: Number of phys associated with port
542 * @marked_responding: used while refresing the sas ports
543 * @lowest_phy: lowest phy ID of current sas port, valid for controller port
544 * @phy_mask: phy_mask of current sas port, valid for controller port
545 * @hba_port: HBA port entry
546 * @remote_identify: Attached device identification
547 * @rphy: SAS transport layer rphy object
548 * @port: SAS transport layer port object
549 * @phy_list: mpi3mr_sas_phy objects belonging to this port
550 */
551 struct mpi3mr_sas_port {
552 struct list_head port_list;
553 u8 num_phys;
554 u8 marked_responding;
555 int lowest_phy;
556 u64 phy_mask;
557 struct mpi3mr_hba_port *hba_port;
558 struct sas_identify remote_identify;
559 struct sas_rphy *rphy;
560 struct sas_port *port;
561 struct list_head phy_list;
562 };
563
564 /**
565 * struct mpi3mr_sas_phy - Internal SAS Phy information
566 * @port_siblings: List of phys belonging to a port
567 * @identify: Phy identification
568 * @remote_identify: Attached device identification
569 * @phy: SAS transport layer Phy object
570 * @phy_id: Unique phy id within a port
571 * @handle: Firmware device handle for this phy
572 * @attached_handle: Firmware device handle for attached device
573 * @phy_belongs_to_port: Flag to indicate phy belongs to port
574 @hba_port: HBA port entry
575 */
576 struct mpi3mr_sas_phy {
577 struct list_head port_siblings;
578 struct sas_identify identify;
579 struct sas_identify remote_identify;
580 struct sas_phy *phy;
581 u8 phy_id;
582 u16 handle;
583 u16 attached_handle;
584 u8 phy_belongs_to_port;
585 struct mpi3mr_hba_port *hba_port;
586 };
587
588 /**
589 * struct mpi3mr_sas_node - SAS host/expander information
590 * @list: List of sas nodes in a controller
591 * @parent_dev: Parent device class
592 * @num_phys: Number phys belonging to sas_node
593 * @sas_address: SAS address of sas_node
594 * @handle: Firmware device handle for this sas_host/expander
595 * @sas_address_parent: SAS address of parent expander or host
596 * @enclosure_handle: Firmware handle of enclosure of this node
597 * @device_info: Capabilities of this sas_host/expander
598 * @non_responding: used to refresh the expander devices during reset
599 * @host_node: Flag to indicate this is a host_node
600 * @hba_port: HBA port entry
601 * @phy: A list of phys that make up this sas_host/expander
602 * @sas_port_list: List of internal ports of this node
603 * @rphy: sas_rphy object of this expander node
604 */
605 struct mpi3mr_sas_node {
606 struct list_head list;
607 struct device *parent_dev;
608 u8 num_phys;
609 u64 sas_address;
610 u16 handle;
611 u64 sas_address_parent;
612 u16 enclosure_handle;
613 u64 enclosure_logical_id;
614 u8 non_responding;
615 u8 host_node;
616 struct mpi3mr_hba_port *hba_port;
617 struct mpi3mr_sas_phy *phy;
618 struct list_head sas_port_list;
619 struct sas_rphy *rphy;
620 };
621
622 /**
623 * struct mpi3mr_enclosure_node - enclosure information
624 * @list: List of enclosures
625 * @pg0: Enclosure page 0;
626 */
627 struct mpi3mr_enclosure_node {
628 struct list_head list;
629 struct mpi3_enclosure_page0 pg0;
630 };
631
632 /**
633 * struct tgt_dev_sas_sata - SAS/SATA device specific
634 * information cached from firmware given data
635 *
636 * @sas_address: World wide unique SAS address
637 * @sas_address_parent: Sas address of parent expander or host
638 * @dev_info: Device information bits
639 * @phy_id: Phy identifier provided in device page 0
640 * @attached_phy_id: Attached phy identifier provided in device page 0
641 * @sas_transport_attached: Is this device exposed to transport
642 * @pend_sas_rphy_add: Flag to check device is in process of add
643 * @hba_port: HBA port entry
644 * @rphy: SAS transport layer rphy object
645 */
646 struct tgt_dev_sas_sata {
647 u64 sas_address;
648 u64 sas_address_parent;
649 u16 dev_info;
650 u8 phy_id;
651 u8 attached_phy_id;
652 u8 sas_transport_attached;
653 u8 pend_sas_rphy_add;
654 struct mpi3mr_hba_port *hba_port;
655 struct sas_rphy *rphy;
656 };
657
658 /**
659 * struct tgt_dev_pcie - PCIe device specific information cached
660 * from firmware given data
661 *
662 * @mdts: Maximum data transfer size
663 * @capb: Device capabilities
664 * @pgsz: Device page size
665 * @abort_to: Timeout for abort TM
666 * @reset_to: Timeout for Target/LUN reset TM
667 * @dev_info: Device information bits
668 */
669 struct tgt_dev_pcie {
670 u32 mdts;
671 u16 capb;
672 u8 pgsz;
673 u8 abort_to;
674 u8 reset_to;
675 u16 dev_info;
676 };
677
678 /**
679 * struct tgt_dev_vd - virtual device specific information
680 * cached from firmware given data
681 *
682 * @state: State of the VD
683 * @tg_qd_reduction: Queue Depth reduction in units of 10%
684 * @tg_id: VDs throttle group ID
685 * @high: High limit to turn on throttling in 512 byte blocks
686 * @low: Low limit to turn off throttling in 512 byte blocks
687 * @tg: Pointer to throttle group info
688 */
689 struct tgt_dev_vd {
690 u8 state;
691 u8 tg_qd_reduction;
692 u16 tg_id;
693 u32 tg_high;
694 u32 tg_low;
695 struct mpi3mr_throttle_group_info *tg;
696 };
697
698
699 /**
700 * union _form_spec_inf - union of device specific information
701 */
702 union _form_spec_inf {
703 struct tgt_dev_sas_sata sas_sata_inf;
704 struct tgt_dev_pcie pcie_inf;
705 struct tgt_dev_vd vd_inf;
706 };
707
708 enum mpi3mr_dev_state {
709 MPI3MR_DEV_CREATED = 1,
710 MPI3MR_DEV_REMOVE_HS_STARTED = 2,
711 MPI3MR_DEV_DELETED = 3,
712 };
713
714 /**
715 * struct mpi3mr_tgt_dev - target device data structure
716 *
717 * @list: List pointer
718 * @starget: Scsi_target pointer
719 * @dev_handle: FW device handle
720 * @parent_handle: FW parent device handle
721 * @slot: Slot number
722 * @encl_handle: FW enclosure handle
723 * @perst_id: FW assigned Persistent ID
724 * @devpg0_flag: Device Page0 flag
725 * @dev_type: SAS/SATA/PCIE device type
726 * @is_hidden: Should be exposed to upper layers or not
727 * @host_exposed: Already exposed to host or not
728 * @io_unit_port: IO Unit port ID
729 * @non_stl: Is this device not to be attached with SAS TL
730 * @io_throttle_enabled: I/O throttling needed or not
731 * @wslen: Write same max length
732 * @q_depth: Device specific Queue Depth
733 * @wwid: World wide ID
734 * @enclosure_logical_id: Enclosure logical identifier
735 * @dev_spec: Device type specific information
736 * @ref_count: Reference count
737 * @state: device state
738 */
739 struct mpi3mr_tgt_dev {
740 struct list_head list;
741 struct scsi_target *starget;
742 u16 dev_handle;
743 u16 parent_handle;
744 u16 slot;
745 u16 encl_handle;
746 u16 perst_id;
747 u16 devpg0_flag;
748 u8 dev_type;
749 u8 is_hidden;
750 u8 host_exposed;
751 u8 io_unit_port;
752 u8 non_stl;
753 u8 io_throttle_enabled;
754 u16 wslen;
755 u16 q_depth;
756 u64 wwid;
757 u64 enclosure_logical_id;
758 union _form_spec_inf dev_spec;
759 struct kref ref_count;
760 enum mpi3mr_dev_state state;
761 };
762
763 /**
764 * mpi3mr_tgtdev_get - k reference incrementor
765 * @s: Target device reference
766 *
767 * Increment target device reference count.
768 */
mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev * s)769 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
770 {
771 kref_get(&s->ref_count);
772 }
773
774 /**
775 * mpi3mr_free_tgtdev - target device memory dealloctor
776 * @r: k reference pointer of the target device
777 *
778 * Free target device memory when no reference.
779 */
mpi3mr_free_tgtdev(struct kref * r)780 static inline void mpi3mr_free_tgtdev(struct kref *r)
781 {
782 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
783 }
784
785 /**
786 * mpi3mr_tgtdev_put - k reference decrementor
787 * @s: Target device reference
788 *
789 * Decrement target device reference count.
790 */
mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev * s)791 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
792 {
793 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
794 }
795
796
797 /**
798 * struct mpi3mr_stgt_priv_data - SCSI target private structure
799 *
800 * @starget: Scsi_target pointer
801 * @dev_handle: FW device handle
802 * @perst_id: FW assigned Persistent ID
803 * @num_luns: Number of Logical Units
804 * @block_io: I/O blocked to the device or not
805 * @dev_removed: Device removed in the Firmware
806 * @dev_removedelay: Device is waiting to be removed in FW
807 * @dev_type: Device type
808 * @dev_nvme_dif: Device is NVMe DIF enabled
809 * @wslen: Write same max length
810 * @io_throttle_enabled: I/O throttling needed or not
811 * @io_divert: Flag indicates io divert is on or off for the dev
812 * @throttle_group: Pointer to throttle group info
813 * @tgt_dev: Internal target device pointer
814 * @pend_count: Counter to track pending I/Os during error
815 * handling
816 */
817 struct mpi3mr_stgt_priv_data {
818 struct scsi_target *starget;
819 u16 dev_handle;
820 u16 perst_id;
821 u32 num_luns;
822 atomic_t block_io;
823 u8 dev_removed;
824 u8 dev_removedelay;
825 u8 dev_type;
826 u8 dev_nvme_dif;
827 u16 wslen;
828 u8 io_throttle_enabled;
829 u8 io_divert;
830 struct mpi3mr_throttle_group_info *throttle_group;
831 struct mpi3mr_tgt_dev *tgt_dev;
832 u32 pend_count;
833 };
834
835 /**
836 * struct mpi3mr_stgt_priv_data - SCSI device private structure
837 *
838 * @tgt_priv_data: Scsi_target private data pointer
839 * @lun_id: LUN ID of the device
840 * @ncq_prio_enable: NCQ priority enable for SATA device
841 * @pend_count: Counter to track pending I/Os during error
842 * handling
843 * @wslen: Write same max length
844 */
845 struct mpi3mr_sdev_priv_data {
846 struct mpi3mr_stgt_priv_data *tgt_priv_data;
847 u32 lun_id;
848 u8 ncq_prio_enable;
849 u32 pend_count;
850 u16 wslen;
851 };
852
853 /**
854 * struct mpi3mr_drv_cmd - Internal command tracker
855 *
856 * @mutex: Command mutex
857 * @done: Completeor for wakeup
858 * @reply: Firmware reply for internal commands
859 * @sensebuf: Sensebuf for SCSI IO commands
860 * @iou_rc: IO Unit control reason code
861 * @state: Command State
862 * @dev_handle: Firmware handle for device specific commands
863 * @ioc_status: IOC status from the firmware
864 * @ioc_loginfo:IOC log info from the firmware
865 * @is_waiting: Is the command issued in block mode
866 * @is_sense: Is Sense data present
867 * @retry_count: Retry count for retriable commands
868 * @host_tag: Host tag used by the command
869 * @callback: Callback for non blocking commands
870 */
871 struct mpi3mr_drv_cmd {
872 struct mutex mutex;
873 struct completion done;
874 void *reply;
875 u8 *sensebuf;
876 u8 iou_rc;
877 u16 state;
878 u16 dev_handle;
879 u16 ioc_status;
880 u32 ioc_loginfo;
881 u8 is_waiting;
882 u8 is_sense;
883 u8 retry_count;
884 u16 host_tag;
885
886 void (*callback)(struct mpi3mr_ioc *mrioc,
887 struct mpi3mr_drv_cmd *drv_cmd);
888 };
889
890 /**
891 * union mpi3mr_trigger_data - Trigger data information
892 * @fault: Fault code
893 * @global: Global trigger data
894 * @element: element trigger data
895 */
896 union mpi3mr_trigger_data {
897 u16 fault;
898 u64 global;
899 union mpi3_driver2_trigger_element element;
900 };
901
902 /**
903 * struct trigger_event_data - store trigger related
904 * information.
905 *
906 * @trace_hdb: Trace diag buffer descriptor reference
907 * @fw_hdb: FW diag buffer descriptor reference
908 * @trigger_type: Trigger type
909 * @trigger_specific_data: Trigger specific data
910 * @snapdump: Snapdump enable or disable flag
911 */
912 struct trigger_event_data {
913 struct diag_buffer_desc *trace_hdb;
914 struct diag_buffer_desc *fw_hdb;
915 u8 trigger_type;
916 union mpi3mr_trigger_data trigger_specific_data;
917 bool snapdump;
918 };
919
920 /**
921 * struct diag_buffer_desc - memory descriptor structure to
922 * store virtual, dma addresses, size, buffer status for host
923 * diagnostic buffers.
924 *
925 * @type: Buffer type
926 * @trigger_data: Trigger data
927 * @trigger_type: Trigger type
928 * @status: Buffer status
929 * @size: Buffer size
930 * @addr: Virtual address
931 * @dma_addr: Buffer DMA address
932 */
933 struct diag_buffer_desc {
934 u8 type;
935 union mpi3mr_trigger_data trigger_data;
936 u8 trigger_type;
937 u8 status;
938 u32 size;
939 void *addr;
940 dma_addr_t dma_addr;
941 };
942
943 /**
944 * struct dma_memory_desc - memory descriptor structure to store
945 * virtual address, dma address and size for any generic dma
946 * memory allocations in the driver.
947 *
948 * @size: buffer size
949 * @addr: virtual address
950 * @dma_addr: dma address
951 */
952 struct dma_memory_desc {
953 u32 size;
954 void *addr;
955 dma_addr_t dma_addr;
956 };
957
958
959 /**
960 * struct chain_element - memory descriptor structure to store
961 * virtual and dma addresses for chain elements.
962 *
963 * @addr: virtual address
964 * @dma_addr: dma address
965 */
966 struct chain_element {
967 void *addr;
968 dma_addr_t dma_addr;
969 };
970
971 /**
972 * struct scmd_priv - SCSI command private data
973 *
974 * @host_tag: Host tag specific to operational queue
975 * @in_lld_scope: Command in LLD scope or not
976 * @meta_sg_valid: DIX command with meta data SGL or not
977 * @scmd: SCSI Command pointer
978 * @req_q_idx: Operational request queue index
979 * @chain_idx: Chain frame index
980 * @meta_chain_idx: Chain frame index of meta data SGL
981 * @mpi3mr_scsiio_req: MPI SCSI IO request
982 */
983 struct scmd_priv {
984 u16 host_tag;
985 u8 in_lld_scope;
986 u8 meta_sg_valid;
987 struct scsi_cmnd *scmd;
988 u16 req_q_idx;
989 int chain_idx;
990 int meta_chain_idx;
991 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
992 };
993
994 /**
995 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
996 * private data
997 *
998 * @list: List pointer
999 * @pdev: PCI device pointer
1000 * @shost: Scsi_Host pointer
1001 * @id: Controller ID
1002 * @cpu_count: Number of online CPUs
1003 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
1004 * @name: Controller ASCII name
1005 * @driver_name: Driver ASCII name
1006 * @sysif_regs: System interface registers virtual address
1007 * @sysif_regs_phys: System interface registers physical address
1008 * @bars: PCI BARS
1009 * @dma_mask: DMA mask
1010 * @msix_count: Number of MSIX vectors used
1011 * @intr_enabled: Is interrupts enabled
1012 * @num_admin_req: Number of admin requests
1013 * @admin_req_q_sz: Admin request queue size
1014 * @admin_req_pi: Admin request queue producer index
1015 * @admin_req_ci: Admin request queue consumer index
1016 * @admin_req_base: Admin request queue base virtual address
1017 * @admin_req_dma: Admin request queue base dma address
1018 * @admin_req_lock: Admin queue access lock
1019 * @num_admin_replies: Number of admin replies
1020 * @admin_reply_q_sz: Admin reply queue size
1021 * @admin_reply_ci: Admin reply queue consumer index
1022 * @admin_reply_ephase:Admin reply queue expected phase
1023 * @admin_reply_base: Admin reply queue base virtual address
1024 * @admin_reply_dma: Admin reply queue base dma address
1025 * @admin_reply_q_in_use: Queue is handled by poll/ISR
1026 * @ready_timeout: Controller ready timeout
1027 * @intr_info: Interrupt cookie pointer
1028 * @intr_info_count: Number of interrupt cookies
1029 * @is_intr_info_set: Flag to indicate intr info is setup
1030 * @num_queues: Number of operational queues
1031 * @num_op_req_q: Number of operational request queues
1032 * @req_qinfo: Operational request queue info pointer
1033 * @num_op_reply_q: Number of operational reply queues
1034 * @op_reply_qinfo: Operational reply queue info pointer
1035 * @init_cmds: Command tracker for initialization commands
1036 * @cfg_cmds: Command tracker for configuration requests
1037 * @facts: Cached IOC facts data
1038 * @op_reply_desc_sz: Operational reply descriptor size
1039 * @num_reply_bufs: Number of reply buffers allocated
1040 * @reply_buf_pool: Reply buffer pool
1041 * @reply_buf: Reply buffer base virtual address
1042 * @reply_buf_dma: Reply buffer DMA address
1043 * @reply_buf_dma_max_address: Reply DMA address max limit
1044 * @reply_free_qsz: Reply free queue size
1045 * @reply_free_q_pool: Reply free queue pool
1046 * @reply_free_q: Reply free queue base virtual address
1047 * @reply_free_q_dma: Reply free queue base DMA address
1048 * @reply_free_queue_lock: Reply free queue lock
1049 * @reply_free_queue_host_index: Reply free queue host index
1050 * @num_sense_bufs: Number of sense buffers
1051 * @sense_buf_pool: Sense buffer pool
1052 * @sense_buf: Sense buffer base virtual address
1053 * @sense_buf_dma: Sense buffer base DMA address
1054 * @sense_buf_q_sz: Sense buffer queue size
1055 * @sense_buf_q_pool: Sense buffer queue pool
1056 * @sense_buf_q: Sense buffer queue virtual address
1057 * @sense_buf_q_dma: Sense buffer queue DMA address
1058 * @sbq_lock: Sense buffer queue lock
1059 * @sbq_host_index: Sense buffer queuehost index
1060 * @event_masks: Event mask bitmap
1061 * @fwevt_worker_thread: Firmware event worker thread
1062 * @fwevt_lock: Firmware event lock
1063 * @fwevt_list: Firmware event list
1064 * @watchdog_work_q_name: Fault watchdog worker thread name
1065 * @watchdog_work_q: Fault watchdog worker thread
1066 * @watchdog_work: Fault watchdog work
1067 * @watchdog_lock: Fault watchdog lock
1068 * @is_driver_loading: Is driver still loading
1069 * @scan_started: Async scan started
1070 * @scan_failed: Asycn scan failed
1071 * @stop_drv_processing: Stop all command processing
1072 * @device_refresh_on: Don't process the events until devices are refreshed
1073 * @max_host_ios: Maximum host I/O count
1074 * @max_sgl_entries: Max SGL entries per I/O
1075 * @chain_buf_count: Chain buffer count
1076 * @chain_buf_pool: Chain buffer pool
1077 * @chain_sgl_list: Chain SGL list
1078 * @chain_bitmap: Chain buffer allocator bitmap
1079 * @chain_buf_lock: Chain buffer list lock
1080 * @bsg_cmds: Command tracker for BSG command
1081 * @host_tm_cmds: Command tracker for task management commands
1082 * @dev_rmhs_cmds: Command tracker for device removal commands
1083 * @evtack_cmds: Command tracker for event ack commands
1084 * @devrem_bitmap: Device removal bitmap
1085 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap
1086 * @removepend_bitmap: Remove pending bitmap
1087 * @delayed_rmhs_list: Delayed device removal list
1088 * @evtack_cmds_bitmap: Event Ack bitmap
1089 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
1090 * @ts_update_counter: Timestamp update counter
1091 * @ts_update_interval: Timestamp update interval
1092 * @reset_in_progress: Reset in progress flag
1093 * @unrecoverable: Controller unrecoverable flag
1094 * @prev_reset_result: Result of previous reset
1095 * @reset_mutex: Controller reset mutex
1096 * @reset_waitq: Controller reset wait queue
1097 * @prepare_for_reset: Prepare for reset event received
1098 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
1099 * @prp_list_virt: NVMe encapsulated PRP list virtual base
1100 * @prp_list_dma: NVMe encapsulated PRP list DMA
1101 * @prp_sz: NVME encapsulated PRP list size
1102 * @diagsave_timeout: Diagnostic information save timeout
1103 * @logging_level: Controller debug logging level
1104 * @flush_io_count: I/O count to flush after reset
1105 * @current_event: Firmware event currently in process
1106 * @driver_info: Driver, Kernel, OS information to firmware
1107 * @change_count: Topology change count
1108 * @pel_enabled: Persistent Event Log(PEL) enabled or not
1109 * @pel_abort_requested: PEL abort is requested or not
1110 * @pel_class: PEL Class identifier
1111 * @pel_locale: PEL Locale identifier
1112 * @pel_cmds: Command tracker for PEL wait command
1113 * @pel_abort_cmd: Command tracker for PEL abort command
1114 * @pel_newest_seqnum: Newest PEL sequenece number
1115 * @pel_seqnum_virt: PEL sequence number virtual address
1116 * @pel_seqnum_dma: PEL sequence number DMA address
1117 * @pel_seqnum_sz: PEL sequenece number size
1118 * @op_reply_q_offset: Operational reply queue offset with MSIx
1119 * @default_qcount: Total Default queues
1120 * @active_poll_qcount: Currently active poll queue count
1121 * @requested_poll_qcount: User requested poll queue count
1122 * @bsg_dev: BSG device structure
1123 * @bsg_queue: Request queue for BSG device
1124 * @stop_bsgs: Stop BSG request flag
1125 * @logdata_buf: Circular buffer to store log data entries
1126 * @logdata_buf_idx: Index of entry in buffer to store
1127 * @logdata_entry_sz: log data entry size
1128 * @pend_large_data_sz: Counter to track pending large data
1129 * @io_throttle_data_length: I/O size to track in 512b blocks
1130 * @io_throttle_high: I/O size to start throttle in 512b blocks
1131 * @io_throttle_low: I/O size to stop throttle in 512b blocks
1132 * @num_io_throttle_group: Maximum number of throttle groups
1133 * @throttle_groups: Pointer to throttle group info structures
1134 * @sas_transport_enabled: SAS transport enabled or not
1135 * @scsi_device_channel: Channel ID for SCSI devices
1136 * @transport_cmds: Command tracker for SAS transport commands
1137 * @sas_hba: SAS node for the controller
1138 * @sas_expander_list: SAS node list of expanders
1139 * @sas_node_lock: Lock to protect SAS node list
1140 * @hba_port_table_list: List of HBA Ports
1141 * @enclosure_list: List of Enclosure objects
1142 * @diag_buffers: Host diagnostic buffers
1143 * @driver_pg2: Driver page 2 pointer
1144 * @reply_trigger_present: Reply trigger present flag
1145 * @event_trigger_present: Event trigger present flag
1146 * @scsisense_trigger_present: Scsi sense trigger present flag
1147 * @ioctl_dma_pool: DMA pool for IOCTL data buffers
1148 * @ioctl_sge: DMA buffer descriptors for IOCTL data
1149 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain
1150 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response
1151 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not
1152 * @trace_release_trigger_active: Trace trigger active flag
1153 * @fw_release_trigger_active: Fw release trigger active flag
1154 * @snapdump_trigger_active: Snapdump trigger active flag
1155 * @pci_err_recovery: PCI error recovery in progress
1156 * @block_on_pci_err: Block IO during PCI error recovery
1157 */
1158 struct mpi3mr_ioc {
1159 struct list_head list;
1160 struct pci_dev *pdev;
1161 struct Scsi_Host *shost;
1162 u8 id;
1163 int cpu_count;
1164 bool enable_segqueue;
1165 u32 irqpoll_sleep;
1166
1167 char name[MPI3MR_NAME_LENGTH];
1168 char driver_name[MPI3MR_NAME_LENGTH];
1169
1170 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
1171 resource_size_t sysif_regs_phys;
1172 int bars;
1173 u64 dma_mask;
1174
1175 u16 msix_count;
1176 u8 intr_enabled;
1177
1178 u16 num_admin_req;
1179 u32 admin_req_q_sz;
1180 u16 admin_req_pi;
1181 u16 admin_req_ci;
1182 void *admin_req_base;
1183 dma_addr_t admin_req_dma;
1184 spinlock_t admin_req_lock;
1185
1186 u16 num_admin_replies;
1187 u32 admin_reply_q_sz;
1188 u16 admin_reply_ci;
1189 u8 admin_reply_ephase;
1190 void *admin_reply_base;
1191 dma_addr_t admin_reply_dma;
1192 atomic_t admin_reply_q_in_use;
1193
1194 u32 ready_timeout;
1195
1196 struct mpi3mr_intr_info *intr_info;
1197 u16 intr_info_count;
1198 bool is_intr_info_set;
1199
1200 u16 num_queues;
1201 u16 num_op_req_q;
1202 struct op_req_qinfo *req_qinfo;
1203
1204 u16 num_op_reply_q;
1205 struct op_reply_qinfo *op_reply_qinfo;
1206
1207 struct mpi3mr_drv_cmd init_cmds;
1208 struct mpi3mr_drv_cmd cfg_cmds;
1209 struct mpi3mr_ioc_facts facts;
1210 u16 op_reply_desc_sz;
1211
1212 u32 num_reply_bufs;
1213 struct dma_pool *reply_buf_pool;
1214 u8 *reply_buf;
1215 dma_addr_t reply_buf_dma;
1216 dma_addr_t reply_buf_dma_max_address;
1217
1218 u16 reply_free_qsz;
1219 u16 reply_sz;
1220 struct dma_pool *reply_free_q_pool;
1221 __le64 *reply_free_q;
1222 dma_addr_t reply_free_q_dma;
1223 spinlock_t reply_free_queue_lock;
1224 u32 reply_free_queue_host_index;
1225
1226 u32 num_sense_bufs;
1227 struct dma_pool *sense_buf_pool;
1228 u8 *sense_buf;
1229 dma_addr_t sense_buf_dma;
1230
1231 u16 sense_buf_q_sz;
1232 struct dma_pool *sense_buf_q_pool;
1233 __le64 *sense_buf_q;
1234 dma_addr_t sense_buf_q_dma;
1235 spinlock_t sbq_lock;
1236 u32 sbq_host_index;
1237 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
1238
1239 struct workqueue_struct *fwevt_worker_thread;
1240 spinlock_t fwevt_lock;
1241 struct list_head fwevt_list;
1242
1243 char watchdog_work_q_name[50];
1244 struct workqueue_struct *watchdog_work_q;
1245 struct delayed_work watchdog_work;
1246 spinlock_t watchdog_lock;
1247
1248 u8 is_driver_loading;
1249 u8 scan_started;
1250 u16 scan_failed;
1251 u8 stop_drv_processing;
1252 u8 device_refresh_on;
1253
1254 u16 max_host_ios;
1255 spinlock_t tgtdev_lock;
1256 struct list_head tgtdev_list;
1257 u16 max_sgl_entries;
1258
1259 u32 chain_buf_count;
1260 struct dma_pool *chain_buf_pool;
1261 struct chain_element *chain_sgl_list;
1262 unsigned long *chain_bitmap;
1263 spinlock_t chain_buf_lock;
1264
1265 struct mpi3mr_drv_cmd bsg_cmds;
1266 struct mpi3mr_drv_cmd host_tm_cmds;
1267 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1268 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1269 unsigned long *devrem_bitmap;
1270 u16 dev_handle_bitmap_bits;
1271 unsigned long *removepend_bitmap;
1272 struct list_head delayed_rmhs_list;
1273 unsigned long *evtack_cmds_bitmap;
1274 struct list_head delayed_evtack_cmds_list;
1275
1276 u16 ts_update_counter;
1277 u16 ts_update_interval;
1278 u8 reset_in_progress;
1279 u8 unrecoverable;
1280 int prev_reset_result;
1281 struct mutex reset_mutex;
1282 wait_queue_head_t reset_waitq;
1283
1284 u8 prepare_for_reset;
1285 u16 prepare_for_reset_timeout_counter;
1286
1287 void *prp_list_virt;
1288 dma_addr_t prp_list_dma;
1289 u32 prp_sz;
1290
1291 u16 diagsave_timeout;
1292 int logging_level;
1293 u16 flush_io_count;
1294
1295 struct mpi3mr_fwevt *current_event;
1296 struct mpi3_driver_info_layout driver_info;
1297 u16 change_count;
1298
1299 u8 pel_enabled;
1300 u8 pel_abort_requested;
1301 u8 pel_class;
1302 u16 pel_locale;
1303 struct mpi3mr_drv_cmd pel_cmds;
1304 struct mpi3mr_drv_cmd pel_abort_cmd;
1305
1306 u32 pel_newest_seqnum;
1307 void *pel_seqnum_virt;
1308 dma_addr_t pel_seqnum_dma;
1309 u32 pel_seqnum_sz;
1310
1311 u16 op_reply_q_offset;
1312 u16 default_qcount;
1313 u16 active_poll_qcount;
1314 u16 requested_poll_qcount;
1315
1316 struct device bsg_dev;
1317 struct request_queue *bsg_queue;
1318 u8 stop_bsgs;
1319 u8 *logdata_buf;
1320 u16 logdata_buf_idx;
1321 u16 logdata_entry_sz;
1322
1323 atomic_t pend_large_data_sz;
1324 u32 io_throttle_data_length;
1325 u32 io_throttle_high;
1326 u32 io_throttle_low;
1327 u16 num_io_throttle_group;
1328 struct mpi3mr_throttle_group_info *throttle_groups;
1329
1330 u8 sas_transport_enabled;
1331 u8 scsi_device_channel;
1332 struct mpi3mr_drv_cmd transport_cmds;
1333 struct mpi3mr_sas_node sas_hba;
1334 struct list_head sas_expander_list;
1335 spinlock_t sas_node_lock;
1336 struct list_head hba_port_table_list;
1337 struct list_head enclosure_list;
1338
1339 struct dma_pool *ioctl_dma_pool;
1340 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
1341 struct dma_memory_desc ioctl_chain_sge;
1342 struct dma_memory_desc ioctl_resp_sge;
1343 bool ioctl_sges_allocated;
1344 bool reply_trigger_present;
1345 bool event_trigger_present;
1346 bool scsisense_trigger_present;
1347 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB];
1348 struct mpi3_driver_page2 *driver_pg2;
1349 spinlock_t trigger_lock;
1350 bool snapdump_trigger_active;
1351 bool trace_release_trigger_active;
1352 bool fw_release_trigger_active;
1353 bool pci_err_recovery;
1354 bool block_on_pci_err;
1355 };
1356
1357 /**
1358 * struct mpi3mr_fwevt - Firmware event structure.
1359 *
1360 * @list: list head
1361 * @work: Work structure
1362 * @mrioc: Adapter instance reference
1363 * @event_id: MPI3 firmware event ID
1364 * @send_ack: Event acknowledgment required or not
1365 * @process_evt: Bottomhalf processing required or not
1366 * @evt_ctx: Event context to send in Ack
1367 * @event_data_size: size of the event data in bytes
1368 * @pending_at_sml: waiting for device add/remove API to complete
1369 * @discard: discard this event
1370 * @ref_count: kref count
1371 * @event_data: Actual MPI3 event data
1372 */
1373 struct mpi3mr_fwevt {
1374 struct list_head list;
1375 struct work_struct work;
1376 struct mpi3mr_ioc *mrioc;
1377 u16 event_id;
1378 bool send_ack;
1379 bool process_evt;
1380 u32 evt_ctx;
1381 u16 event_data_size;
1382 bool pending_at_sml;
1383 bool discard;
1384 struct kref ref_count;
1385 char event_data[] __aligned(4);
1386 };
1387
1388
1389 /**
1390 * struct delayed_dev_rmhs_node - Delayed device removal node
1391 *
1392 * @list: list head
1393 * @handle: Device handle
1394 * @iou_rc: IO Unit Control Reason Code
1395 */
1396 struct delayed_dev_rmhs_node {
1397 struct list_head list;
1398 u16 handle;
1399 u8 iou_rc;
1400 };
1401
1402 /**
1403 * struct delayed_evt_ack_node - Delayed event ack node
1404 * @list: list head
1405 * @event: MPI3 event ID
1406 * @event_ctx: event context
1407 */
1408 struct delayed_evt_ack_node {
1409 struct list_head list;
1410 u8 event;
1411 u32 event_ctx;
1412 };
1413
1414 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1415 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1416 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1417 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1418 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1419 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1420 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1421 u16 admin_req_sz, u8 ignore_reset);
1422 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1423 struct op_req_qinfo *opreqq, u8 *req);
1424 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1425 dma_addr_t dma_addr);
1426 void mpi3mr_build_zero_len_sge(void *paddr);
1427 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1428 dma_addr_t phys_addr);
1429 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1430 dma_addr_t phys_addr);
1431 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1432 u64 sense_buf_dma);
1433
1434 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1435 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1436 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1437 struct mpi3_event_notification_reply *event_reply);
1438 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1439 struct mpi3_default_reply_descriptor *reply_desc,
1440 u64 *reply_dma, u16 qidx);
1441 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1442 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1443
1444 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1445 u16 reset_reason, u8 snapdump);
1446 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1447 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1448
1449 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1450 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1451 u32 event_ctx);
1452
1453 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1454 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1455 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1456 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1457 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1458 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1459 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1460 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1461 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1462 struct op_reply_qinfo *op_reply_q);
1463 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1464 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1465 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1466 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1467 u16 handle, uint lun, u16 htag, ulong timeout,
1468 struct mpi3mr_drv_cmd *drv_cmd,
1469 u8 *resp_code, struct scsi_cmnd *scmd);
1470 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1471 struct mpi3mr_ioc *mrioc, u16 handle);
1472 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1473 struct mpi3mr_drv_cmd *drv_cmd);
1474 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1475 struct mpi3mr_drv_cmd *drv_cmd);
1476 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1477 u16 event_data_size);
1478 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1479 struct mpi3mr_ioc *mrioc, u16 handle);
1480 extern const struct attribute_group *mpi3mr_host_groups[];
1481 extern const struct attribute_group *mpi3mr_dev_groups[];
1482
1483 extern struct sas_function_template mpi3mr_transport_functions;
1484 extern struct scsi_transport_template *mpi3mr_transport_template;
1485
1486 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1487 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1488 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1489 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1490 u32 form_spec);
1491 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1492 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1493 u32 form_spec);
1494 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1495 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1496 u32 form_spec);
1497 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1498 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1499 u32 form_spec);
1500 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1501 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1502 u32 form_spec);
1503 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1504 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1505 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1506 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1507 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1508 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1509 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1510 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1511 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
1512 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type);
1513
1514 u8 mpi3mr_is_expander_device(u16 device_info);
1515 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);
1516 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,
1517 struct mpi3mr_hba_port *hba_port);
1518 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc
1519 *mrioc, u16 handle);
1520 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,
1521 u8 port_id);
1522 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);
1523 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);
1524 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,
1525 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,
1526 struct mpi3mr_hba_port *hba_port);
1527 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
1528 struct mpi3mr_tgt_dev *tgtdev);
1529 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
1530 struct mpi3mr_tgt_dev *tgtdev);
1531 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,
1532 struct mpi3mr_tgt_dev *tgtdev);
1533 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(
1534 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);
1535 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
1536 bool device_add);
1537 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);
1538 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);
1539 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);
1540 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);
1541 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);
1542 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);
1543 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc);
1544 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc,
1545 struct mpi3mr_sas_node *sas_expander);
1546 void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc);
1547 int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc);
1548 int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc,
1549 struct diag_buffer_desc *diag_buffer);
1550 void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action);
1551 void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb,
1552 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1553 int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type);
1554 struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc,
1555 u8 buf_type);
1556 int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc,
1557 struct diag_buffer_desc *diag_buffer);
1558 void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc,
1559 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1560 void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus,
1561 u32 iocloginfo);
1562 void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc,
1563 struct trigger_event_data *event_data);
1564 void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc,
1565 u8 ascq);
1566 void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event);
1567 void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data);
1568 void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc,
1569 struct mpi3_event_notification_reply *event_reply);
1570 #endif /*MPI3MR_H_INCLUDED*/
1571