xref: /linux/arch/m68k/include/asm/mcfmmu.h (revision 664b0bae0b87f69bc9deb098f5e0158b9cf18e04)
1 /*
2  *	mcfmmu.h -- definitions for the ColdFire v4e MMU
3  *
4  *	(C) Copyright 2011,  Greg Ungerer <gerg@uclinux.org>
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file COPYING in the main directory of this archive
8  * for more details.
9  */
10 
11 #ifndef	MCFMMU_H
12 #define	MCFMMU_H
13 
14 /*
15  *	The MMU support registers are mapped into the address space using
16  *	the processor MMUBASE register. We used a fixed address for mapping,
17  *	there doesn't seem any need to make this configurable yet.
18  */
19 #define	MMUBASE		0xfe000000
20 
21 /*
22  *	The support registers of the MMU. Names are the sames as those
23  *	used in the Freescale v4e documentation.
24  */
25 #define	MMUCR		(MMUBASE + 0x00)	/* Control register */
26 #define	MMUOR		(MMUBASE + 0x04)	/* Operation register */
27 #define	MMUSR		(MMUBASE + 0x08)	/* Status register */
28 #define	MMUAR		(MMUBASE + 0x10)	/* TLB Address register */
29 #define	MMUTR		(MMUBASE + 0x14)	/* TLB Tag register */
30 #define	MMUDR		(MMUBASE + 0x18)	/* TLB Data register */
31 
32 /*
33  *	MMU Control register bit flags
34  */
35 #define	MMUCR_EN	0x00000001		/* Virtual mode enable */
36 #define	MMUCR_ASM	0x00000002		/* Address space mode */
37 
38 /*
39  *	MMU Operation register.
40  */
41 #define	MMUOR_UAA	0x00000001		/* Update allocation address */
42 #define	MMUOR_ACC	0x00000002		/* TLB access */
43 #define	MMUOR_RD	0x00000004		/* TLB access read */
44 #define	MMUOR_WR	0x00000000		/* TLB access write */
45 #define	MMUOR_ADR	0x00000008		/* TLB address select */
46 #define	MMUOR_ITLB	0x00000010		/* ITLB operation */
47 #define	MMUOR_CAS	0x00000020		/* Clear non-locked ASID TLBs */
48 #define	MMUOR_CNL	0x00000040		/* Clear non-locked TLBs */
49 #define	MMUOR_CA	0x00000080		/* Clear all TLBs */
50 #define	MMUOR_STLB	0x00000100		/* Search TLBs */
51 #define	MMUOR_AAN	16			/* TLB allocation address */
52 #define	MMUOR_AAMASK	0xffff0000		/* AA mask */
53 
54 /*
55  *	MMU Status register.
56  */
57 #define	MMUSR_HIT	0x00000002		/* Search TLB hit */
58 #define	MMUSR_WF	0x00000008		/* Write access fault */
59 #define	MMUSR_RF	0x00000010		/* Read access fault */
60 #define	MMUSR_SPF	0x00000020		/* Supervisor protect fault */
61 
62 /*
63  *	MMU Read/Write Tag register.
64  */
65 #define	MMUTR_V		0x00000001		/* Valid */
66 #define	MMUTR_SG	0x00000002		/* Shared global */
67 #define	MMUTR_IDN	2			/* Address Space ID */
68 #define	MMUTR_IDMASK	0x000003fc		/* ASID mask */
69 #define	MMUTR_VAN	10			/* Virtual Address */
70 #define	MMUTR_VAMASK	0xfffffc00		/* VA mask */
71 
72 /*
73  *	MMU Read/Write Data register.
74  */
75 #define	MMUDR_LK	0x00000002		/* Lock entry */
76 #define	MMUDR_X		0x00000004		/* Execute access enable */
77 #define	MMUDR_W		0x00000008		/* Write access enable */
78 #define	MMUDR_R		0x00000010		/* Read access enable */
79 #define	MMUDR_SP	0x00000020		/* Supervisor access enable */
80 #define	MMUDR_CM_CWT	0x00000000		/* Cachable write thru */
81 #define	MMUDR_CM_CCB	0x00000040		/* Cachable copy back */
82 #define	MMUDR_CM_NCP	0x00000080		/* Non-cachable precise */
83 #define	MMUDR_CM_NCI	0x000000c0		/* Non-cachable imprecise */
84 #define	MMUDR_SZ_1MB	0x00000000		/* 1MB page size */
85 #define	MMUDR_SZ_4KB	0x00000100		/* 4kB page size */
86 #define	MMUDR_SZ_8KB	0x00000200		/* 8kB page size */
87 #define	MMUDR_SZ_1KB	0x00000300		/* 1kB page size */
88 #define	MMUDR_PAN	10			/* Physical address */
89 #define	MMUDR_PAMASK	0xfffffc00		/* PA mask */
90 
91 #ifndef __ASSEMBLY__
92 
93 /*
94  *	Simple access functions for the MMU registers. Nothing fancy
95  *	currently required, just simple 32bit access.
96  */
mmu_read(u32 a)97 static inline u32 mmu_read(u32 a)
98 {
99 	return *((volatile u32 *) a);
100 }
101 
mmu_write(u32 a,u32 v)102 static inline void mmu_write(u32 a, u32 v)
103 {
104 	*((volatile u32 *) a) = v;
105 	__asm__ __volatile__ ("nop");
106 }
107 
108 void cf_bootmem_alloc(void);
109 void cf_mmu_context_init(void);
110 int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
111 
112 #endif
113 
114 #endif	/* MCFMMU_H */
115