xref: /linux/include/dt-bindings/clock/qcom,mmcc-sdm660.h (revision d0034a7a4ac7fae708146ac0059b9c47a1543f0d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H
7 #define _DT_BINDINGS_CLK_MSM_MMCC_660_H
8 
9 #define AHB_CLK_SRC							0
10 #define BYTE0_CLK_SRC						1
11 #define BYTE1_CLK_SRC						2
12 #define CAMSS_GP0_CLK_SRC					3
13 #define CAMSS_GP1_CLK_SRC					4
14 #define CCI_CLK_SRC							5
15 #define CPP_CLK_SRC							6
16 #define CSI0_CLK_SRC						7
17 #define CSI0PHYTIMER_CLK_SRC				8
18 #define CSI1_CLK_SRC						9
19 #define CSI1PHYTIMER_CLK_SRC				10
20 #define CSI2_CLK_SRC						11
21 #define CSI2PHYTIMER_CLK_SRC				12
22 #define CSI3_CLK_SRC						13
23 #define CSIPHY_CLK_SRC						14
24 #define DP_AUX_CLK_SRC						15
25 #define DP_CRYPTO_CLK_SRC					16
26 #define DP_GTC_CLK_SRC						17
27 #define DP_LINK_CLK_SRC						18
28 #define DP_PIXEL_CLK_SRC					19
29 #define ESC0_CLK_SRC						20
30 #define ESC1_CLK_SRC						21
31 #define JPEG0_CLK_SRC						22
32 #define MCLK0_CLK_SRC						23
33 #define MCLK1_CLK_SRC						24
34 #define MCLK2_CLK_SRC						25
35 #define MCLK3_CLK_SRC						26
36 #define MDP_CLK_SRC							27
37 #define MMPLL0_PLL							28
38 #define MMPLL10_PLL							29
39 #define MMPLL1_PLL							30
40 #define MMPLL3_PLL							31
41 #define MMPLL4_PLL							32
42 #define MMPLL5_PLL							33
43 #define MMPLL6_PLL							34
44 #define MMPLL7_PLL							35
45 #define MMPLL8_PLL							36
46 #define BIMC_SMMU_AHB_CLK					37
47 #define BIMC_SMMU_AXI_CLK					38
48 #define CAMSS_AHB_CLK						39
49 #define CAMSS_CCI_AHB_CLK					40
50 #define CAMSS_CCI_CLK						41
51 #define CAMSS_CPHY_CSID0_CLK				42
52 #define CAMSS_CPHY_CSID1_CLK				43
53 #define CAMSS_CPHY_CSID2_CLK				44
54 #define CAMSS_CPHY_CSID3_CLK				45
55 #define CAMSS_CPP_AHB_CLK					46
56 #define CAMSS_CPP_AXI_CLK					47
57 #define CAMSS_CPP_CLK						48
58 #define CAMSS_CPP_VBIF_AHB_CLK				49
59 #define CAMSS_CSI0_AHB_CLK					50
60 #define CAMSS_CSI0_CLK						51
61 #define CAMSS_CSI0PHYTIMER_CLK				52
62 #define CAMSS_CSI0PIX_CLK					53
63 #define CAMSS_CSI0RDI_CLK					54
64 #define CAMSS_CSI1_AHB_CLK					55
65 #define CAMSS_CSI1_CLK						56
66 #define CAMSS_CSI1PHYTIMER_CLK				57
67 #define CAMSS_CSI1PIX_CLK					58
68 #define CAMSS_CSI1RDI_CLK					59
69 #define CAMSS_CSI2_AHB_CLK					60
70 #define CAMSS_CSI2_CLK						61
71 #define CAMSS_CSI2PHYTIMER_CLK				62
72 #define CAMSS_CSI2PIX_CLK					63
73 #define CAMSS_CSI2RDI_CLK					64
74 #define CAMSS_CSI3_AHB_CLK					65
75 #define CAMSS_CSI3_CLK						66
76 #define CAMSS_CSI3PIX_CLK					67
77 #define CAMSS_CSI3RDI_CLK					68
78 #define CAMSS_CSI_VFE0_CLK					69
79 #define CAMSS_CSI_VFE1_CLK					70
80 #define CAMSS_CSIPHY0_CLK					71
81 #define CAMSS_CSIPHY1_CLK					72
82 #define CAMSS_CSIPHY2_CLK					73
83 #define CAMSS_GP0_CLK						74
84 #define CAMSS_GP1_CLK						75
85 #define CAMSS_ISPIF_AHB_CLK					76
86 #define CAMSS_JPEG0_CLK						77
87 #define CAMSS_JPEG_AHB_CLK					78
88 #define CAMSS_JPEG_AXI_CLK					79
89 #define CAMSS_MCLK0_CLK						80
90 #define CAMSS_MCLK1_CLK						81
91 #define CAMSS_MCLK2_CLK						82
92 #define CAMSS_MCLK3_CLK						83
93 #define CAMSS_MICRO_AHB_CLK					84
94 #define CAMSS_TOP_AHB_CLK					85
95 #define CAMSS_VFE0_AHB_CLK					86
96 #define CAMSS_VFE0_CLK						87
97 #define CAMSS_VFE0_STREAM_CLK				88
98 #define CAMSS_VFE1_AHB_CLK					89
99 #define CAMSS_VFE1_CLK						90
100 #define CAMSS_VFE1_STREAM_CLK				91
101 #define CAMSS_VFE_VBIF_AHB_CLK				92
102 #define CAMSS_VFE_VBIF_AXI_CLK				93
103 #define CSIPHY_AHB2CRIF_CLK					94
104 #define CXO_CLK								95
105 #define MDSS_AHB_CLK						96
106 #define MDSS_AXI_CLK						97
107 #define MDSS_BYTE0_CLK						98
108 #define MDSS_BYTE0_INTF_CLK					99
109 #define MDSS_BYTE0_INTF_DIV_CLK				100
110 #define MDSS_BYTE1_CLK						101
111 #define MDSS_BYTE1_INTF_CLK					102
112 #define MDSS_DP_AUX_CLK						103
113 #define MDSS_DP_CRYPTO_CLK					104
114 #define MDSS_DP_GTC_CLK						105
115 #define MDSS_DP_LINK_CLK					106
116 #define MDSS_DP_LINK_INTF_CLK				107
117 #define MDSS_DP_PIXEL_CLK					108
118 #define MDSS_ESC0_CLK						109
119 #define MDSS_ESC1_CLK						110
120 #define MDSS_HDMI_DP_AHB_CLK				111
121 #define MDSS_MDP_CLK						112
122 #define MDSS_PCLK0_CLK						113
123 #define MDSS_PCLK1_CLK						114
124 #define MDSS_ROT_CLK						115
125 #define MDSS_VSYNC_CLK						116
126 #define MISC_AHB_CLK						117
127 #define MISC_CXO_CLK						118
128 #define MNOC_AHB_CLK						119
129 #define SNOC_DVM_AXI_CLK					120
130 #define THROTTLE_CAMSS_AHB_CLK				121
131 #define THROTTLE_CAMSS_AXI_CLK				122
132 #define THROTTLE_MDSS_AHB_CLK				123
133 #define THROTTLE_MDSS_AXI_CLK				124
134 #define THROTTLE_VIDEO_AHB_CLK				125
135 #define THROTTLE_VIDEO_AXI_CLK				126
136 #define VIDEO_AHB_CLK						127
137 #define VIDEO_AXI_CLK						128
138 #define VIDEO_CORE_CLK						129
139 #define VIDEO_SUBCORE0_CLK					130
140 #define PCLK0_CLK_SRC						131
141 #define PCLK1_CLK_SRC						132
142 #define ROT_CLK_SRC							133
143 #define VFE0_CLK_SRC						134
144 #define VFE1_CLK_SRC						135
145 #define VIDEO_CORE_CLK_SRC					136
146 #define VSYNC_CLK_SRC						137
147 #define MDSS_BYTE1_INTF_DIV_CLK				138
148 #define AXI_CLK_SRC							139
149 
150 #define VENUS_GDSC								0
151 #define VENUS_CORE0_GDSC						1
152 #define MDSS_GDSC								2
153 #define CAMSS_TOP_GDSC							3
154 #define CAMSS_VFE0_GDSC							4
155 #define CAMSS_VFE1_GDSC							5
156 #define CAMSS_CPP_GDSC							6
157 #define BIMC_SMMU_GDSC							7
158 
159 #define CAMSS_MICRO_BCR				 0
160 
161 #endif
162 
163