1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H 9 #define _ASM_X86_AMD_IOMMU_TYPES_H 10 11 #include <linux/bitfield.h> 12 #include <linux/iommu.h> 13 #include <linux/types.h> 14 #include <linux/mmu_notifier.h> 15 #include <linux/mutex.h> 16 #include <linux/msi.h> 17 #include <linux/list.h> 18 #include <linux/sizes.h> 19 #include <linux/spinlock.h> 20 #include <linux/pci.h> 21 #include <linux/iommufd.h> 22 #include <linux/irqreturn.h> 23 #include <linux/generic_pt/iommu.h> 24 25 #include <uapi/linux/iommufd.h> 26 27 /* 28 * Maximum number of IOMMUs supported 29 */ 30 #define MAX_IOMMUS 32 31 32 /* 33 * some size calculation constants 34 */ 35 #define DEV_TABLE_ENTRY_SIZE 32 36 37 /* Capability offsets used by the driver */ 38 #define MMIO_CAP_HDR_OFFSET 0x00 39 #define MMIO_RANGE_OFFSET 0x0c 40 #define MMIO_MISC_OFFSET 0x10 41 42 /* Masks, shifts and macros to parse the device range capability */ 43 #define MMIO_RANGE_LD_MASK 0xff000000 44 #define MMIO_RANGE_FD_MASK 0x00ff0000 45 #define MMIO_RANGE_BUS_MASK 0x0000ff00 46 #define MMIO_RANGE_LD_SHIFT 24 47 #define MMIO_RANGE_FD_SHIFT 16 48 #define MMIO_RANGE_BUS_SHIFT 8 49 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) 50 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) 51 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) 52 #define MMIO_MSI_NUM(x) ((x) & 0x1f) 53 54 /* Used offsets into the MMIO space */ 55 #define MMIO_DEV_TABLE_OFFSET 0x0000 56 #define MMIO_CMD_BUF_OFFSET 0x0008 57 #define MMIO_EVT_BUF_OFFSET 0x0010 58 #define MMIO_CONTROL_OFFSET 0x0018 59 #define MMIO_EXCL_BASE_OFFSET 0x0020 60 #define MMIO_EXCL_LIMIT_OFFSET 0x0028 61 #define MMIO_EXT_FEATURES 0x0030 62 #define MMIO_PPR_LOG_OFFSET 0x0038 63 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 64 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 65 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C 66 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 67 #define MMIO_MSI_DATA_OFFSET 0x0164 68 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 69 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 70 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 71 #define MMIO_EXT_FEATURES2 0x01A0 72 #define MMIO_CMD_HEAD_OFFSET 0x2000 73 #define MMIO_CMD_TAIL_OFFSET 0x2008 74 #define MMIO_EVT_HEAD_OFFSET 0x2010 75 #define MMIO_EVT_TAIL_OFFSET 0x2018 76 #define MMIO_STATUS_OFFSET 0x2020 77 #define MMIO_PPR_HEAD_OFFSET 0x2030 78 #define MMIO_PPR_TAIL_OFFSET 0x2038 79 #define MMIO_GA_HEAD_OFFSET 0x2040 80 #define MMIO_GA_TAIL_OFFSET 0x2048 81 #define MMIO_CNTR_CONF_OFFSET 0x4000 82 #define MMIO_CNTR_REG_OFFSET 0x40000 83 #define MMIO_REG_END_OFFSET 0x80000 84 85 86 87 /* Extended Feature Bits */ 88 #define FEATURE_PREFETCH BIT_ULL(0) 89 #define FEATURE_PPR BIT_ULL(1) 90 #define FEATURE_X2APIC BIT_ULL(2) 91 #define FEATURE_NX BIT_ULL(3) 92 #define FEATURE_GT BIT_ULL(4) 93 #define FEATURE_IA BIT_ULL(6) 94 #define FEATURE_GA BIT_ULL(7) 95 #define FEATURE_HE BIT_ULL(8) 96 #define FEATURE_PC BIT_ULL(9) 97 #define FEATURE_HATS GENMASK_ULL(11, 10) 98 #define FEATURE_GATS GENMASK_ULL(13, 12) 99 #define FEATURE_GLX GENMASK_ULL(15, 14) 100 #define FEATURE_GAM_VAPIC BIT_ULL(21) 101 #define FEATURE_PASMAX GENMASK_ULL(36, 32) 102 #define FEATURE_GIOSUP BIT_ULL(48) 103 #define FEATURE_HASUP BIT_ULL(49) 104 #define FEATURE_EPHSUP BIT_ULL(50) 105 #define FEATURE_HDSUP BIT_ULL(52) 106 #define FEATURE_SNP BIT_ULL(63) 107 108 109 /* Extended Feature 2 Bits */ 110 #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) 111 #define FEATURE_GCR3TRPMODE BIT_ULL(3) 112 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) 113 #define FEATURE_SNPAVICSUP_GAM(x) \ 114 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) 115 #define FEATURE_HT_RANGE_IGNORE BIT_ULL(11) 116 117 #define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8) 118 #define FEATURE_NUM_INT_REMAP_SUP_2K(x) \ 119 (FIELD_GET(FEATURE_NUM_INT_REMAP_SUP, x) == 0x1) 120 121 /* Note: 122 * The current driver only support 16-bit PASID. 123 * Currently, hardware only implement upto 16-bit PASID 124 * even though the spec says it could have upto 20 bits. 125 */ 126 #define PASID_MASK 0x0000ffff 127 128 /* MMIO status bits */ 129 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0) 130 #define MMIO_STATUS_EVT_INT_MASK BIT(1) 131 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2) 132 #define MMIO_STATUS_EVT_RUN_MASK BIT(3) 133 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5) 134 #define MMIO_STATUS_PPR_INT_MASK BIT(6) 135 #define MMIO_STATUS_PPR_RUN_MASK BIT(7) 136 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8) 137 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9) 138 #define MMIO_STATUS_GALOG_INT_MASK BIT(10) 139 140 /* event logging constants */ 141 #define EVENT_TYPE_SHIFT 28 142 #define EVENT_TYPE_MASK 0xf 143 #define EVENT_TYPE_ILL_DEV 0x1 144 #define EVENT_TYPE_IO_FAULT 0x2 145 #define EVENT_TYPE_DEV_TAB_ERR 0x3 146 #define EVENT_TYPE_PAGE_TAB_ERR 0x4 147 #define EVENT_TYPE_ILL_CMD 0x5 148 #define EVENT_TYPE_CMD_HARD_ERR 0x6 149 #define EVENT_TYPE_IOTLB_INV_TO 0x7 150 #define EVENT_TYPE_INV_DEV_REQ 0x8 151 #define EVENT_TYPE_INV_PPR_REQ 0x9 152 #define EVENT_TYPE_RMP_FAULT 0xd 153 #define EVENT_TYPE_RMP_HW_ERR 0xe 154 #define EVENT_DEVID_MASK 0xffff 155 #define EVENT_DEVID_SHIFT 0 156 #define EVENT_DOMID_MASK_LO 0xffff 157 #define EVENT_DOMID_MASK_HI 0xf0000 158 #define EVENT_FLAGS_MASK 0xfff 159 #define EVENT_FLAGS_SHIFT 0x10 160 #define EVENT_FLAG_RW 0x020 161 #define EVENT_FLAG_I 0x008 162 163 /* feature control bits */ 164 #define CONTROL_IOMMU_EN 0 165 #define CONTROL_HT_TUN_EN 1 166 #define CONTROL_EVT_LOG_EN 2 167 #define CONTROL_EVT_INT_EN 3 168 #define CONTROL_COMWAIT_EN 4 169 #define CONTROL_INV_TIMEOUT 5 170 #define CONTROL_PASSPW_EN 8 171 #define CONTROL_RESPASSPW_EN 9 172 #define CONTROL_COHERENT_EN 10 173 #define CONTROL_ISOC_EN 11 174 #define CONTROL_CMDBUF_EN 12 175 #define CONTROL_PPRLOG_EN 13 176 #define CONTROL_PPRINT_EN 14 177 #define CONTROL_PPR_EN 15 178 #define CONTROL_GT_EN 16 179 #define CONTROL_GA_EN 17 180 #define CONTROL_GAM_EN 25 181 #define CONTROL_GALOG_EN 28 182 #define CONTROL_GAINT_EN 29 183 #define CONTROL_NUM_INT_REMAP_MODE 43 184 #define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03 185 #define CONTROL_NUM_INT_REMAP_MODE_2K 0x01 186 #define CONTROL_EPH_EN 45 187 #define CONTROL_XT_EN 50 188 #define CONTROL_INTCAPXT_EN 51 189 #define CONTROL_GCR3TRPMODE 58 190 #define CONTROL_IRTCACHEDIS 59 191 #define CONTROL_SNPAVIC_EN 61 192 193 #define CTRL_INV_TO_MASK 7 194 #define CTRL_INV_TO_NONE 0 195 #define CTRL_INV_TO_1MS 1 196 #define CTRL_INV_TO_10MS 2 197 #define CTRL_INV_TO_100MS 3 198 #define CTRL_INV_TO_1S 4 199 #define CTRL_INV_TO_10S 5 200 #define CTRL_INV_TO_100S 6 201 202 /* command specific defines */ 203 #define CMD_COMPL_WAIT 0x01 204 #define CMD_INV_DEV_ENTRY 0x02 205 #define CMD_INV_IOMMU_PAGES 0x03 206 #define CMD_INV_IOTLB_PAGES 0x04 207 #define CMD_INV_IRT 0x05 208 #define CMD_COMPLETE_PPR 0x07 209 #define CMD_INV_ALL 0x08 210 211 #define CMD_COMPL_WAIT_STORE_MASK 0x01 212 #define CMD_COMPL_WAIT_INT_MASK 0x02 213 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 214 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 215 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 216 217 #define PPR_STATUS_MASK 0xf 218 #define PPR_STATUS_SHIFT 12 219 220 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7ffffffffffff000ULL 221 222 /* macros and definitions for device table entries */ 223 #define DEV_ENTRY_VALID 0x00 224 #define DEV_ENTRY_TRANSLATION 0x01 225 #define DEV_ENTRY_HAD 0x07 226 #define DEV_ENTRY_PPR 0x34 227 #define DEV_ENTRY_IR 0x3d 228 #define DEV_ENTRY_IW 0x3e 229 #define DEV_ENTRY_NO_PAGE_FAULT 0x62 230 #define DEV_ENTRY_SYSMGT1 0x68 231 #define DEV_ENTRY_SYSMGT2 0x69 232 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40) 233 234 #define DEV_ENTRY_IRQ_TBL_EN 0x80 235 #define DEV_ENTRY_INIT_PASS 0xb8 236 #define DEV_ENTRY_EINT_PASS 0xb9 237 #define DEV_ENTRY_NMI_PASS 0xba 238 #define DEV_ENTRY_LINT0_PASS 0xbe 239 #define DEV_ENTRY_LINT1_PASS 0xbf 240 #define DEV_ENTRY_MODE_MASK 0x07 241 #define DEV_ENTRY_MODE_SHIFT 0x09 242 243 #define MAX_DEV_TABLE_ENTRIES 0xffff 244 245 /* constants to configure the command buffer */ 246 #define CMD_BUFFER_SIZE 8192 247 #define CMD_BUFFER_UNINITIALIZED 1 248 #define CMD_BUFFER_ENTRIES 512 249 #define MMIO_CMD_SIZE_SHIFT 56 250 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) 251 #define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */ 252 #define MMIO_CMD_BUFFER_HEAD(x) FIELD_GET(MMIO_CMD_HEAD_MASK, (x)) 253 #define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */ 254 #define MMIO_CMD_BUFFER_TAIL(x) FIELD_GET(MMIO_CMD_TAIL_MASK, (x)) 255 256 /* constants for event buffer handling */ 257 #define EVTLOG_ENTRY_SIZE 0x10 258 #define EVTLOG_SIZE_SHIFT 56 259 #define EVTLOG_SIZE_DEF SZ_8K /* 512 entries */ 260 #define EVTLOG_LEN_MASK_DEF (0x9ULL << EVTLOG_SIZE_SHIFT) 261 #define EVTLOG_SIZE_MAX SZ_512K /* 32K entries */ 262 #define EVTLOG_LEN_MASK_MAX (0xFULL << EVTLOG_SIZE_SHIFT) 263 264 /* Constants for PPR Log handling */ 265 #define PPRLOG_ENTRY_SIZE 0x10 266 #define PPRLOG_SIZE_SHIFT 56 267 #define PPRLOG_SIZE_DEF SZ_8K /* 512 entries */ 268 #define PPRLOG_LEN_MASK_DEF (0x9ULL << PPRLOG_SIZE_SHIFT) 269 #define PPRLOG_SIZE_MAX SZ_512K /* 32K entries */ 270 #define PPRLOG_LEN_MASK_MAX (0xFULL << PPRLOG_SIZE_SHIFT) 271 272 /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */ 273 #define PPR_FLAG_EXEC 0x002 /* Execute permission requested */ 274 #define PPR_FLAG_READ 0x004 /* Read permission requested */ 275 #define PPR_FLAG_WRITE 0x020 /* Write permission requested */ 276 #define PPR_FLAG_US 0x040 /* 1: User, 0: Supervisor */ 277 #define PPR_FLAG_RVSD 0x080 /* Reserved bit not zero */ 278 #define PPR_FLAG_GN 0x100 /* GVA and PASID is valid */ 279 280 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 281 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) 282 #define PPR_DEVID(x) ((x) & 0xffffULL) 283 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) 284 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) 285 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) 286 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) 287 288 #define PPR_REQ_FAULT 0x01 289 290 /* Constants for GA Log handling */ 291 #define GA_LOG_ENTRIES 512 292 #define GA_LOG_SIZE_SHIFT 56 293 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) 294 #define GA_ENTRY_SIZE 8 295 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) 296 297 #define GA_TAG(x) (u32)(x & 0xffffffffULL) 298 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) 299 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 300 301 #define GA_GUEST_NR 0x1 302 303 /* 304 * This bitmap is used to advertise the page sizes our hardware support 305 * to the IOMMU core, which will then use this information to split 306 * physically contiguous memory regions it is mapping into page sizes 307 * that we support. 308 * 309 * 512GB Pages are not supported due to a hardware bug 310 * Page sizes >= the 52 bit max physical address of the CPU are not supported. 311 */ 312 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G) 313 314 /* Special mode where page-sizes are limited to 4 KiB */ 315 #define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE) 316 317 /* 4K, 2MB, 1G page sizes are supported */ 318 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30)) 319 320 /* Bit value definition for dte irq remapping fields*/ 321 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6) 322 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) 323 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) 324 #define DTE_IRQ_REMAP_ENABLE 1ULL 325 326 #define DTE_INTTAB_ALIGNMENT 128 327 #define DTE_INTTABLEN_MASK (0xfULL << 1) 328 #define DTE_INTTABLEN_VALUE_512 9ULL 329 #define DTE_INTTABLEN_512 (DTE_INTTABLEN_VALUE_512 << 1) 330 #define MAX_IRQS_PER_TABLE_512 BIT(DTE_INTTABLEN_VALUE_512) 331 #define DTE_INTTABLEN_VALUE_2K 11ULL 332 #define DTE_INTTABLEN_2K (DTE_INTTABLEN_VALUE_2K << 1) 333 #define MAX_IRQS_PER_TABLE_2K BIT(DTE_INTTABLEN_VALUE_2K) 334 335 #define PAGE_MODE_NONE 0x00 336 #define PAGE_MODE_1_LEVEL 0x01 337 #define PAGE_MODE_2_LEVEL 0x02 338 #define PAGE_MODE_3_LEVEL 0x03 339 #define PAGE_MODE_4_LEVEL 0x04 340 #define PAGE_MODE_5_LEVEL 0x05 341 #define PAGE_MODE_6_LEVEL 0x06 342 #define PAGE_MODE_7_LEVEL 0x07 343 344 #define GUEST_PGTABLE_4_LEVEL 0x00 345 #define GUEST_PGTABLE_5_LEVEL 0x01 346 347 #define PM_ADDR_MASK 0x000ffffffffff000ULL 348 349 /* 350 * Bit value definition for DTE fields 351 */ 352 #define DTE_FLAG_V BIT_ULL(0) 353 #define DTE_FLAG_TV BIT_ULL(1) 354 #define DTE_FLAG_HAD (3ULL << 7) 355 #define DTE_MODE_MASK GENMASK_ULL(11, 9) 356 #define DTE_HOST_TRP GENMASK_ULL(51, 12) 357 #define DTE_FLAG_PPR BIT_ULL(52) 358 #define DTE_FLAG_GIOV BIT_ULL(54) 359 #define DTE_FLAG_GV BIT_ULL(55) 360 #define DTE_GLX GENMASK_ULL(57, 56) 361 #define DTE_FLAG_IR BIT_ULL(61) 362 #define DTE_FLAG_IW BIT_ULL(62) 363 364 #define DTE_FLAG_IOTLB BIT_ULL(32) 365 #define DTE_FLAG_MASK (0x3ffULL << 32) 366 #define DTE_DOMID_MASK GENMASK_ULL(15, 0) 367 368 #define DTE_GCR3_14_12 GENMASK_ULL(60, 58) 369 #define DTE_GCR3_30_15 GENMASK_ULL(31, 16) 370 #define DTE_GCR3_51_31 GENMASK_ULL(63, 43) 371 372 #define DTE_GPT_LEVEL_SHIFT 54 373 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54) 374 375 #define GCR3_VALID 0x01ULL 376 377 /* DTE[128:179] | DTE[184:191] */ 378 #define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52) 379 380 #define IOMMU_PROT_MASK 0x03 381 #define IOMMU_PROT_IR 0x01 382 #define IOMMU_PROT_IW 0x02 383 384 /* IOMMU capabilities */ 385 #define IOMMU_CAP_IOTLB 24 386 #define IOMMU_CAP_NPCACHE 26 387 #define IOMMU_CAP_EFR 27 388 389 /* IOMMU IVINFO */ 390 #define IOMMU_IVINFO_OFFSET 36 391 #define IOMMU_IVINFO_EFRSUP BIT(0) 392 #define IOMMU_IVINFO_DMA_REMAP BIT(1) 393 #define IOMMU_IVINFO_VASIZE GENMASK_ULL(21, 15) 394 395 /* IOMMU Feature Reporting Field (for IVHD type 10h */ 396 #define IOMMU_FEAT_GASUP_SHIFT 6 397 398 /* IOMMU HATDIS for IVHD type 11h and 40h */ 399 #define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0 400 401 /* IOMMU Extended Feature Register (EFR) */ 402 #define IOMMU_EFR_XTSUP_SHIFT 2 403 #define IOMMU_EFR_GASUP_SHIFT 7 404 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 405 406 #define MAX_DOMAIN_ID 65536 407 408 /* Timeout stuff */ 409 #define LOOP_TIMEOUT 100000 410 #define MMIO_STATUS_TIMEOUT 2000000 411 412 extern bool amd_iommu_dump; 413 #define DUMP_printk(format, arg...) \ 414 do { \ 415 if (amd_iommu_dump) \ 416 pr_info(format, ## arg); \ 417 } while(0); 418 419 /* global flag if IOMMUs cache non-present entries */ 420 extern bool amd_iommu_np_cache; 421 /* Only true if all IOMMUs support device IOTLBs */ 422 extern bool amd_iommu_iotlb_sup; 423 424 struct irq_remap_table { 425 raw_spinlock_t lock; 426 unsigned min_index; 427 u32 *table; 428 }; 429 430 /* Interrupt remapping feature used? */ 431 extern bool amd_iommu_irq_remap; 432 433 extern const struct iommu_ops amd_iommu_ops; 434 435 /* IVRS indicates that pre-boot remapping was enabled */ 436 extern bool amdr_ivrs_remap_support; 437 438 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff) 439 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff) 440 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \ 441 ((devid) & 0xffff)) 442 443 /* Make iterating over all pci segment easier */ 444 #define for_each_pci_segment(pci_seg) \ 445 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list) 446 #define for_each_pci_segment_safe(pci_seg, next) \ 447 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list) 448 /* 449 * Make iterating over all IOMMUs easier 450 */ 451 #define for_each_iommu(iommu) \ 452 list_for_each_entry((iommu), &amd_iommu_list, list) 453 #define for_each_iommu_safe(iommu, next) \ 454 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) 455 /* Making iterating over protection_domain->dev_data_list easier */ 456 #define for_each_pdom_dev_data(pdom_dev_data, pdom) \ 457 list_for_each_entry(pdom_dev_data, &pdom->dev_data_list, list) 458 #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) \ 459 list_for_each_entry_safe((pdom_dev_data), (next), &pdom->dev_data_list, list) 460 461 #define for_each_ivhd_dte_flags(entry) \ 462 list_for_each_entry((entry), &amd_ivhd_dev_flags_list, list) 463 464 struct amd_iommu; 465 struct iommu_domain; 466 struct irq_domain; 467 struct amd_irte_ops; 468 469 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) 470 471 struct gcr3_tbl_info { 472 u64 *gcr3_tbl; /* Guest CR3 table */ 473 int glx; /* Number of levels for GCR3 table */ 474 u32 pasid_cnt; /* Track attached PASIDs */ 475 u16 domid; /* Per device domain ID */ 476 }; 477 478 enum protection_domain_mode { 479 PD_MODE_NONE, 480 PD_MODE_V1, 481 PD_MODE_V2, 482 }; 483 484 /* Track dev_data/PASID list for the protection domain */ 485 struct pdom_dev_data { 486 /* Points to attached device data */ 487 struct iommu_dev_data *dev_data; 488 /* PASID attached to the protection domain */ 489 ioasid_t pasid; 490 /* For protection_domain->dev_data_list */ 491 struct list_head list; 492 }; 493 494 /* Keeps track of the IOMMUs attached to protection domain */ 495 struct pdom_iommu_info { 496 struct amd_iommu *iommu; /* IOMMUs attach to protection domain */ 497 u32 refcnt; /* Count of attached dev/pasid per domain/IOMMU */ 498 }; 499 500 struct amd_iommu_viommu { 501 struct iommufd_viommu core; 502 struct protection_domain *parent; /* nest parent domain for this viommu */ 503 struct list_head pdom_list; /* For protection_domain->viommu_list */ 504 505 /* 506 * Per-vIOMMU guest domain ID to host domain ID mapping. 507 * Indexed by guest domain ID. 508 */ 509 struct xarray gdomid_array; 510 }; 511 512 /* 513 * Contains guest domain ID mapping info, 514 * which is stored in the struct xarray gdomid_array. 515 */ 516 struct guest_domain_mapping_info { 517 refcount_t users; 518 u32 hdom_id; /* Host domain ID */ 519 }; 520 521 /* 522 * Nested domain is specifically used for nested translation 523 */ 524 struct nested_domain { 525 struct iommu_domain domain; /* generic domain handle used by iommu core code */ 526 u16 gdom_id; /* domain ID from gDTE */ 527 struct guest_domain_mapping_info *gdom_info; 528 struct iommu_hwpt_amd_guest gdte; /* Guest vIOMMU DTE */ 529 struct amd_iommu_viommu *viommu; /* AMD hw-viommu this nested domain belong to */ 530 }; 531 532 /* 533 * This structure contains generic data for IOMMU protection domains 534 * independent of their use. 535 */ 536 struct protection_domain { 537 union { 538 struct iommu_domain domain; 539 struct pt_iommu iommu; 540 struct pt_iommu_amdv1 amdv1; 541 struct pt_iommu_x86_64 amdv2; 542 }; 543 struct list_head dev_list; /* List of all devices in this domain */ 544 spinlock_t lock; /* mostly used to lock the page table*/ 545 u16 id; /* the domain id written to the device table */ 546 enum protection_domain_mode pd_mode; /* Track page table type */ 547 bool dirty_tracking; /* dirty tracking is enabled in the domain */ 548 struct xarray iommu_array; /* per-IOMMU reference count */ 549 550 struct mmu_notifier mn; /* mmu notifier for the SVA domain */ 551 struct list_head dev_data_list; /* List of pdom_dev_data */ 552 553 /* 554 * Store reference to list of vIOMMUs, which use this protection domain. 555 * This will be used to look up host domain ID when flushing this domain. 556 */ 557 struct list_head viommu_list; 558 }; 559 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain); 560 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain); 561 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain); 562 563 /* 564 * This structure contains information about one PCI segment in the system. 565 */ 566 struct amd_iommu_pci_seg { 567 /* List with all PCI segments in the system */ 568 struct list_head list; 569 570 /* List of all available dev_data structures */ 571 struct llist_head dev_data_list; 572 573 /* PCI segment number */ 574 u16 id; 575 576 /* Largest PCI device id we expect translation requests for */ 577 u16 last_bdf; 578 579 /* Size of the device table */ 580 u32 dev_table_size; 581 582 /* 583 * device table virtual address 584 * 585 * Pointer to the per PCI segment device table. 586 * It is indexed by the PCI device id or the HT unit id and contains 587 * information about the domain the device belongs to as well as the 588 * page table root pointer. 589 */ 590 struct dev_table_entry *dev_table; 591 592 /* 593 * The rlookup iommu table is used to find the IOMMU which is 594 * responsible for a specific device. It is indexed by the PCI 595 * device id. 596 */ 597 struct amd_iommu **rlookup_table; 598 599 /* 600 * This table is used to find the irq remapping table for a given 601 * device id quickly. 602 */ 603 struct irq_remap_table **irq_lookup_table; 604 605 /* 606 * Pointer to a device table which the content of old device table 607 * will be copied to. It's only be used in kdump kernel. 608 */ 609 struct dev_table_entry *old_dev_tbl_cpy; 610 611 /* 612 * The alias table is a driver specific data structure which contains the 613 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 614 * More than one device can share the same requestor id. 615 */ 616 u16 *alias_table; 617 618 /* 619 * A list of required unity mappings we find in ACPI. It is not locked 620 * because as runtime it is only read. It is created at ACPI table 621 * parsing time. 622 */ 623 struct list_head unity_map; 624 }; 625 626 /* 627 * Structure where we save information about one hardware AMD IOMMU in the 628 * system. 629 */ 630 struct amd_iommu { 631 struct list_head list; 632 633 /* Index within the IOMMU array */ 634 int index; 635 636 /* locks the accesses to the hardware */ 637 raw_spinlock_t lock; 638 639 /* Pointer to PCI device of this IOMMU */ 640 struct pci_dev *dev; 641 642 /* Cache pdev to root device for resume quirks */ 643 struct pci_dev *root_pdev; 644 645 /* physical address of MMIO space */ 646 u64 mmio_phys; 647 648 /* physical end address of MMIO space */ 649 u64 mmio_phys_end; 650 651 /* virtual address of MMIO space */ 652 u8 __iomem *mmio_base; 653 654 /* capabilities of that IOMMU read from ACPI */ 655 u32 cap; 656 657 /* flags read from acpi table */ 658 u8 acpi_flags; 659 660 /* Extended features */ 661 u64 features; 662 663 /* Extended features 2 */ 664 u64 features2; 665 666 /* PCI device id of the IOMMU device */ 667 u16 devid; 668 669 /* 670 * Capability pointer. There could be more than one IOMMU per PCI 671 * device function if there are more than one AMD IOMMU capability 672 * pointers. 673 */ 674 u16 cap_ptr; 675 676 /* pci domain of this IOMMU */ 677 struct amd_iommu_pci_seg *pci_seg; 678 679 /* command buffer virtual address */ 680 u8 *cmd_buf; 681 u32 cmd_buf_head; 682 u32 cmd_buf_tail; 683 684 /* event buffer virtual address */ 685 u8 *evt_buf; 686 687 /* Name for event log interrupt */ 688 unsigned char evt_irq_name[16]; 689 690 /* Base of the PPR log, if present */ 691 u8 *ppr_log; 692 693 /* Name for PPR log interrupt */ 694 unsigned char ppr_irq_name[16]; 695 696 /* Base of the GA log, if present */ 697 u8 *ga_log; 698 699 /* Name for GA log interrupt */ 700 unsigned char ga_irq_name[16]; 701 702 /* Tail of the GA log, if present */ 703 u8 *ga_log_tail; 704 705 /* true if interrupts for this IOMMU are already enabled */ 706 bool int_enabled; 707 708 /* if one, we need to send a completion wait command */ 709 bool need_sync; 710 711 /* true if disable irte caching */ 712 bool irtcachedis_enabled; 713 714 /* Handle for IOMMU core code */ 715 struct iommu_device iommu; 716 717 /* 718 * We can't rely on the BIOS to restore all values on reinit, so we 719 * need to stash them 720 */ 721 722 /* The iommu BAR */ 723 u32 stored_addr_lo; 724 u32 stored_addr_hi; 725 726 /* 727 * Each iommu has 6 l1s, each of which is documented as having 0x12 728 * registers 729 */ 730 u32 stored_l1[6][0x12]; 731 732 /* The l2 indirect registers */ 733 u32 stored_l2[0x83]; 734 735 /* The maximum PC banks and counters/bank (PCSup=1) */ 736 u8 max_banks; 737 u8 max_counters; 738 #ifdef CONFIG_IRQ_REMAP 739 struct irq_domain *ir_domain; 740 741 struct amd_irte_ops *irte_ops; 742 #endif 743 744 u32 flags; 745 volatile u64 *cmd_sem; 746 u64 cmd_sem_val; 747 /* 748 * Track physical address to directly use it in build_completion_wait() 749 * and avoid adding any special checks and handling for kdump. 750 */ 751 u64 cmd_sem_paddr; 752 753 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 754 /* DebugFS Info */ 755 struct dentry *debugfs; 756 int dbg_mmio_offset; 757 int dbg_cap_offset; 758 #endif 759 760 /* IOPF support */ 761 struct iopf_queue *iopf_queue; 762 unsigned char iopfq_name[32]; 763 }; 764 765 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) 766 { 767 struct iommu_device *iommu = dev_to_iommu_device(dev); 768 769 return container_of(iommu, struct amd_iommu, iommu); 770 } 771 772 #define ACPIHID_UID_LEN 256 773 #define ACPIHID_HID_LEN 9 774 775 struct acpihid_map_entry { 776 struct list_head list; 777 u8 uid[ACPIHID_UID_LEN]; 778 u8 hid[ACPIHID_HID_LEN]; 779 u32 devid; 780 u32 root_devid; 781 bool cmd_line; 782 struct iommu_group *group; 783 }; 784 785 struct devid_map { 786 struct list_head list; 787 u8 id; 788 u32 devid; 789 bool cmd_line; 790 }; 791 792 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */ 793 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */ 794 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */ 795 /* Device may request execution on memory pages */ 796 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 797 /* Device may request super-user privileges */ 798 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 799 800 /* 801 * This struct contains device specific data for the IOMMU 802 */ 803 struct iommu_dev_data { 804 /*Protect against attach/detach races */ 805 struct mutex mutex; 806 spinlock_t dte_lock; /* DTE lock for 256-bit access */ 807 808 struct list_head list; /* For domain->dev_list */ 809 struct llist_node dev_data_list; /* For global dev_data_list */ 810 struct protection_domain *domain; /* Domain the device is bound to */ 811 struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */ 812 struct device *dev; 813 u16 devid; /* PCI Device ID */ 814 815 unsigned int max_irqs; /* Maximum IRQs supported by device */ 816 u32 max_pasids; /* Max supported PASIDs */ 817 u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */ 818 int ats_qdep; 819 u8 ats_enabled :1; /* ATS state */ 820 u8 pri_enabled :1; /* PRI state */ 821 u8 pasid_enabled:1; /* PASID state */ 822 u8 pri_tlp :1; /* PASID TLB required for 823 PPR completions */ 824 u8 ppr :1; /* Enable device PPR support */ 825 bool use_vapic; /* Enable device to use vapic mode */ 826 bool defer_attach; 827 828 struct ratelimit_state rs; /* Ratelimit IOPF messages */ 829 }; 830 831 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ 832 extern struct list_head ioapic_map; 833 extern struct list_head hpet_map; 834 extern struct list_head acpihid_map; 835 836 /* 837 * List with all PCI segments in the system. This list is not locked because 838 * it is only written at driver initialization time 839 */ 840 extern struct list_head amd_iommu_pci_seg_list; 841 842 /* 843 * List with all IOMMUs in the system. This list is not locked because it is 844 * only written and read at driver initialization or suspend time 845 */ 846 extern struct list_head amd_iommu_list; 847 848 /* 849 * Structure defining one entry in the device table 850 */ 851 struct dev_table_entry { 852 union { 853 u64 data[4]; 854 u128 data128[2]; 855 }; 856 }; 857 858 /* 859 * Structure defining one entry in the command buffer 860 */ 861 struct iommu_cmd { 862 u32 data[4]; 863 }; 864 865 /* 866 * Structure to sture persistent DTE flags from IVHD 867 */ 868 struct ivhd_dte_flags { 869 struct list_head list; 870 u16 segid; 871 u16 devid_first; 872 u16 devid_last; 873 struct dev_table_entry dte; 874 }; 875 876 /* 877 * One entry for unity mappings parsed out of the ACPI table. 878 */ 879 struct unity_map_entry { 880 struct list_head list; 881 882 /* starting device id this entry is used for (including) */ 883 u16 devid_start; 884 /* end device id this entry is used for (including) */ 885 u16 devid_end; 886 887 /* start address to unity map (including) */ 888 u64 address_start; 889 /* end address to unity map (including) */ 890 u64 address_end; 891 892 /* required protection */ 893 int prot; 894 }; 895 896 /* 897 * Data structures for device handling 898 */ 899 900 extern bool amd_iommu_force_isolation; 901 902 /* Max levels of glxval supported */ 903 extern int amd_iommu_max_glx_val; 904 905 /* IDA to track protection domain IDs */ 906 extern struct ida pdom_ids; 907 908 /* Global EFR and EFR2 registers */ 909 extern u64 amd_iommu_efr; 910 extern u64 amd_iommu_efr2; 911 912 static inline int get_ioapic_devid(int id) 913 { 914 struct devid_map *entry; 915 916 list_for_each_entry(entry, &ioapic_map, list) { 917 if (entry->id == id) 918 return entry->devid; 919 } 920 921 return -EINVAL; 922 } 923 924 static inline int get_hpet_devid(int id) 925 { 926 struct devid_map *entry; 927 928 list_for_each_entry(entry, &hpet_map, list) { 929 if (entry->id == id) 930 return entry->devid; 931 } 932 933 return -EINVAL; 934 } 935 936 enum amd_iommu_intr_mode_type { 937 /* 938 * The legacy format mode is not visible to users to prevent the user 939 * from crashing x2APIC systems, which for all intents and purposes 940 * require 128-bit IRTEs. The legacy format will be forced as needed 941 * when hardware doesn't support 128-bit IRTEs. 942 */ 943 AMD_IOMMU_GUEST_IR_LEGACY, 944 AMD_IOMMU_GUEST_IR_LEGACY_GA, 945 AMD_IOMMU_GUEST_IR_VAPIC, 946 }; 947 948 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ 949 x == AMD_IOMMU_GUEST_IR_LEGACY_GA) 950 951 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) 952 953 union irte { 954 u32 val; 955 struct { 956 u32 valid : 1, 957 no_fault : 1, 958 int_type : 3, 959 rq_eoi : 1, 960 dm : 1, 961 rsvd_1 : 1, 962 destination : 8, 963 vector : 8, 964 rsvd_2 : 8; 965 } fields; 966 }; 967 968 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff) 969 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff) 970 971 union irte_ga_lo { 972 u64 val; 973 974 /* For int remapping */ 975 struct { 976 u64 valid : 1, 977 no_fault : 1, 978 /* ------ */ 979 int_type : 3, 980 rq_eoi : 1, 981 dm : 1, 982 /* ------ */ 983 guest_mode : 1, 984 destination : 24, 985 ga_tag : 32; 986 } fields_remap; 987 988 /* For guest vAPIC */ 989 struct { 990 u64 valid : 1, 991 no_fault : 1, 992 /* ------ */ 993 ga_log_intr : 1, 994 rsvd1 : 3, 995 is_run : 1, 996 /* ------ */ 997 guest_mode : 1, 998 destination : 24, 999 ga_tag : 32; 1000 } fields_vapic; 1001 }; 1002 1003 union irte_ga_hi { 1004 u64 val; 1005 struct { 1006 u64 vector : 8, 1007 rsvd_1 : 4, 1008 ga_root_ptr : 40, 1009 rsvd_2 : 4, 1010 destination : 8; 1011 } fields; 1012 }; 1013 1014 struct irte_ga { 1015 union { 1016 struct { 1017 union irte_ga_lo lo; 1018 union irte_ga_hi hi; 1019 }; 1020 u128 irte; 1021 }; 1022 }; 1023 1024 struct irq_2_irte { 1025 u16 devid; /* Device ID for IRTE table */ 1026 u16 index; /* Index into IRTE table*/ 1027 }; 1028 1029 struct amd_ir_data { 1030 struct amd_iommu *iommu; 1031 struct irq_2_irte irq_2_irte; 1032 struct msi_msg msi_entry; 1033 void *entry; /* Pointer to union irte or struct irte_ga */ 1034 1035 /** 1036 * Store information for activate/de-activate 1037 * Guest virtual APIC mode during runtime. 1038 */ 1039 struct irq_cfg *cfg; 1040 int ga_vector; 1041 u64 ga_root_ptr; 1042 u32 ga_tag; 1043 }; 1044 1045 struct amd_irte_ops { 1046 void (*prepare)(void *, u32, bool, u8, u32, int); 1047 void (*activate)(struct amd_iommu *iommu, void *, u16, u16); 1048 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16); 1049 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32); 1050 void *(*get)(struct irq_remap_table *, int); 1051 void (*set_allocated)(struct irq_remap_table *, int); 1052 bool (*is_allocated)(struct irq_remap_table *, int); 1053 void (*clear_allocated)(struct irq_remap_table *, int); 1054 }; 1055 1056 #ifdef CONFIG_IRQ_REMAP 1057 extern struct amd_irte_ops irte_32_ops; 1058 extern struct amd_irte_ops irte_128_ops; 1059 #endif 1060 1061 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ 1062