xref: /linux/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_PCI_HW_H
5 #define _MLXSW_PCI_HW_H
6 
7 #include <linux/bitops.h>
8 
9 #include "item.h"
10 
11 #define MLXSW_PCI_BAR0_SIZE		(1024 * 1024) /* 1MB */
12 #define MLXSW_PCI_PAGE_SIZE		4096
13 
14 #define MLXSW_PCI_CIR_BASE			0x71000
15 #define MLXSW_PCI_CIR_IN_PARAM_HI		MLXSW_PCI_CIR_BASE
16 #define MLXSW_PCI_CIR_IN_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER		(MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI		(MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN			(MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL			(MLXSW_PCI_CIR_BASE + 0x18)
22 #define MLXSW_PCI_CIR_CTRL_GO_BIT		BIT(23)
23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT		BIT(22)
24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT	12
25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT		24
26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS		1000
27 
28 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	900000
29 #define MLXSW_PCI_SW_RESET_WAIT_MSECS		400
30 #define MLXSW_PCI_FW_READY			0xA1844
31 #define MLXSW_PCI_FW_READY_MASK			0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC		0x5E
33 
34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET		0x000
35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET		0x200
36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET		0x400
37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET		0x600
38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET	0x800
39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET	0xA00
40 
41 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)	\
42 	((offset) + (type_offset) + (num) * 4)
43 
44 #define MLXSW_PCI_CQS_MAX	96
45 #define MLXSW_PCI_EQS_MAX	2
46 #define MLXSW_PCI_EQS_COUNT	1
47 #define MLXSW_PCI_EQ_COMP_NUM	1
48 
49 #define MLXSW_PCI_SDQS_MIN	2 /* EMAD and control traffic */
50 #define MLXSW_PCI_SDQ_EMAD_INDEX	0
51 #define MLXSW_PCI_SDQ_EMAD_TC	0
52 #define MLXSW_PCI_SDQ_CTL_TC	3
53 
54 #define MLXSW_PCI_AQ_PAGES	8
55 #define MLXSW_PCI_AQ_SIZE	(MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
56 #define MLXSW_PCI_WQE_SIZE	32 /* 32 bytes per element */
57 #define MLXSW_PCI_CQE01_SIZE	16 /* 16 bytes per element */
58 #define MLXSW_PCI_CQE2_SIZE	32 /* 32 bytes per element */
59 #define MLXSW_PCI_CQE_SIZE_MAX	MLXSW_PCI_CQE2_SIZE
60 #define MLXSW_PCI_EQE_SIZE	16 /* 16 bytes per element */
61 #define MLXSW_PCI_WQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
62 #define MLXSW_PCI_CQE01_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
63 #define MLXSW_PCI_CQE2_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
64 #define MLXSW_PCI_EQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
65 #define MLXSW_PCI_EQE_UPDATE_COUNT	0x80
66 
67 #define MLXSW_PCI_WQE_SG_ENTRIES	3
68 #define MLXSW_PCI_WQE_TYPE_ETHERNET	0xA
69 
70 /* pci_wqe_c
71  * If set it indicates that a completion should be reported upon
72  * execution of this descriptor.
73  */
74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
75 
76 /* pci_wqe_lp
77  * Local Processing, set if packet should be processed by the local
78  * switch hardware:
79  * For Ethernet EMAD (Direct Route and non Direct Route) -
80  * must be set if packet destination is local device
81  * For InfiniBand CTL - must be set if packet destination is local device
82  * Otherwise it must be clear
83  * Local Process packets must not exceed the size of 2K (including payload
84  * and headers).
85  */
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
87 
88 /* pci_wqe_type
89  * Packet type.
90  */
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
92 
93 /* pci_wqe_ipcs
94  * Calculate IPv4 and TCP / UDP checksums.
95  */
96 MLXSW_ITEM32(pci, wqe, ipcs, 0x00, 14, 1);
97 
98 /* pci_wqe_byte_count
99  * Size of i-th scatter/gather entry, 0 if entry is unused.
100  */
101 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
102 
103 /* pci_wqe_address
104  * Physical address of i-th scatter/gather entry.
105  * Gather Entries must be 2Byte aligned.
106  */
107 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
108 
109 enum mlxsw_pci_cqe_v {
110 	MLXSW_PCI_CQE_V0,
111 	MLXSW_PCI_CQE_V1,
112 	MLXSW_PCI_CQE_V2,
113 };
114 
115 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)				\
116 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe)	\
117 {										\
118 	switch (v) {								\
119 	default:								\
120 	case MLXSW_PCI_CQE_V0:							\
121 		return mlxsw_pci_cqe##v0##_##name##_get(cqe);			\
122 	case MLXSW_PCI_CQE_V1:							\
123 		return mlxsw_pci_cqe##v1##_##name##_get(cqe);			\
124 	case MLXSW_PCI_CQE_V2:							\
125 		return mlxsw_pci_cqe##v2##_##name##_get(cqe);			\
126 	}									\
127 }										\
128 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v,		\
129 					      char *cqe, u32 val)		\
130 {										\
131 	switch (v) {								\
132 	default:								\
133 	case MLXSW_PCI_CQE_V0:							\
134 		mlxsw_pci_cqe##v0##_##name##_set(cqe, val);			\
135 		break;								\
136 	case MLXSW_PCI_CQE_V1:							\
137 		mlxsw_pci_cqe##v1##_##name##_set(cqe, val);			\
138 		break;								\
139 	case MLXSW_PCI_CQE_V2:							\
140 		mlxsw_pci_cqe##v2##_##name##_set(cqe, val);			\
141 		break;								\
142 	}									\
143 }
144 
145 /* pci_cqe_lag
146  * Packet arrives from a port which is a LAG
147  */
148 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
149 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
150 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
151 
152 /* pci_cqe_system_port/lag_id
153  * When lag=0: System port on which the packet was received
154  * When lag=1:
155  * bits [15:4] LAG ID on which the packet was received
156  * bits [3:0] sub_port on which the packet was received
157  */
158 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
159 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
160 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
161 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
162 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
163 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
164 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
165 
166 /* pci_cqe_wqe_counter
167  * WQE count of the WQEs completed on the associated dqn
168  */
169 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
170 
171 /* pci_cqe_byte_count
172  * Byte count of received packets including additional two
173  * Reserved Bytes that are append to the end of the frame.
174  * Reserved for Send CQE.
175  */
176 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
177 
178 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID	0xFFFF
179 
180 /* pci_cqe_mirror_cong_high
181  * Congestion level in units of 8KB of the egress traffic class of the original
182  * packet that does mirroring to the CPU. Value of 0xFFFF means that the
183  * congestion level is invalid.
184  */
185 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
186 
187 /* pci_cqe_trap_id
188  * Trap ID that captured the packet.
189  */
190 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
191 
192 /* pci_cqe_crc
193  * Length include CRC. Indicates the length field includes
194  * the packet's CRC.
195  */
196 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
197 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
198 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
199 
200 /* pci_cqe_e
201  * CQE with Error.
202  */
203 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
204 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
205 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
206 
207 /* pci_cqe_sr
208  * 1 - Send Queue
209  * 0 - Receive Queue
210  */
211 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
212 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
213 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
214 
215 /* pci_cqe_dqn
216  * Descriptor Queue (DQ) Number.
217  */
218 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
219 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
220 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
221 
222 /* pci_cqe_time_stamp_low
223  * Time stamp of the CQE
224  * Format according to time_stamp_type:
225  * 0: uSec - 1.024uSec (default for devices which do not support
226  * time_stamp_type). Only bits 15:0 are valid
227  * 1: FRC - Free Running Clock - units of 1nSec
228  * 2: UTC - time_stamp[37:30] = Sec
229  *	  - time_stamp[29:0] = nSec
230  * 3: Mirror_UTC. UTC time stamp of the original packet that has
231  * MIRROR_SESSION traps
232  *   - time_stamp[37:30] = Sec
233  *   - time_stamp[29:0] = nSec
234  *   Formats 0..2 are configured by
235  *   CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
236  *   Format 3 is used for MIRROR_SESSION traps
237  *   Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
238  */
239 MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
240 
241 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID	0x1F
242 
243 /* pci_cqe_mirror_tclass
244  * The egress traffic class of the original packet that does mirroring to the
245  * CPU. Value of 0x1F means that the traffic class is invalid.
246  */
247 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
248 
249 /* pci_cqe_tx_lag
250  * The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.
251  */
252 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
253 
254 /* pci_cqe_tx_lag_subport
255  * The port index within the LAG of a packet that is mirrored / sampled to the
256  * CPU. Reserved when tx_lag is 0.
257  */
258 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
259 
260 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT	0xFFFE
261 #define MLXSW_PCI_CQE2_TX_PORT_INVALID		0xFFFF
262 
263 /* pci_cqe_tx_lag_id
264  * The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.
265  * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
266  * is invalid. Reserved when tx_lag is 0.
267  */
268 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
269 
270 /* pci_cqe_tx_system_port
271  * The Tx port of the original packet that is mirrored / sampled to the CPU.
272  * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
273  * invalid. Reserved when tx_lag is 1.
274  */
275 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
276 
277 /* pci_cqe_mirror_cong_low
278  * Congestion level in units of 8KB of the egress traffic class of the original
279  * packet that does mirroring to the CPU. Value of 0xFFFF means that the
280  * congestion level is invalid.
281  */
282 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
283 
284 #define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT	13	/* Units of 8KB. */
285 
mlxsw_pci_cqe2_mirror_cong_get(const char * cqe)286 static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)
287 {
288 	u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);
289 	u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);
290 
291 	return cong_high << 12 | cong_low;
292 }
293 
294 /* pci_cqe_user_def_val_orig_pkt_len
295  * When trap_id is an ACL: User defined value from policy engine action.
296  */
297 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
298 
299 /* pci_cqe_mirror_reason
300  * Mirror reason.
301  */
302 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
303 
304 enum mlxsw_pci_cqe_time_stamp_type {
305 	MLXSW_PCI_CQE_TIME_STAMP_TYPE_USEC,
306 	MLXSW_PCI_CQE_TIME_STAMP_TYPE_FRC,
307 	MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC,
308 	MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC,
309 };
310 
311 /* pci_cqe_time_stamp_type
312  * Time stamp type:
313  * 0: uSec - 1.024uSec (default for devices which do not support
314  * time_stamp_type)
315  * 1: FRC - Free Running Clock - units of 1nSec
316  * 2: UTC
317  * 3: Mirror_UTC. UTC time stamp of the original packet that has
318  * MIRROR_SESSION traps
319  */
320 MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
321 
322 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID	0xFFFFFF
323 
324 /* pci_cqe_time_stamp_high
325  * Time stamp of the CQE
326  * Format according to time_stamp_type:
327  * 0: uSec - 1.024uSec (default for devices which do not support
328  * time_stamp_type). Only bits 15:0 are valid
329  * 1: FRC - Free Running Clock - units of 1nSec
330  * 2: UTC - time_stamp[37:30] = Sec
331  *	  - time_stamp[29:0] = nSec
332  * 3: Mirror_UTC. UTC time stamp of the original packet that has
333  * MIRROR_SESSION traps
334  *   - time_stamp[37:30] = Sec
335  *   - time_stamp[29:0] = nSec
336  *   Formats 0..2 are configured by
337  *   CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
338  *   Format 3 is used for MIRROR_SESSION traps
339  *   Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
340  */
341 MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
342 
mlxsw_pci_cqe2_time_stamp_get(const char * cqe)343 static inline u64 mlxsw_pci_cqe2_time_stamp_get(const char *cqe)
344 {
345 	u64 ts_high = mlxsw_pci_cqe2_time_stamp_high_get(cqe);
346 	u64 ts_low = mlxsw_pci_cqe2_time_stamp_low_get(cqe);
347 
348 	return ts_high << 16 | ts_low;
349 }
350 
mlxsw_pci_cqe2_time_stamp_sec_get(const char * cqe)351 static inline u8 mlxsw_pci_cqe2_time_stamp_sec_get(const char *cqe)
352 {
353 	u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
354 
355 	return full_ts >> 30 & 0xFF;
356 }
357 
mlxsw_pci_cqe2_time_stamp_nsec_get(const char * cqe)358 static inline u32 mlxsw_pci_cqe2_time_stamp_nsec_get(const char *cqe)
359 {
360 	u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
361 
362 	return full_ts & 0x3FFFFFFF;
363 }
364 
365 /* pci_cqe_mirror_latency
366  * End-to-end latency of the original packet that does mirroring to the CPU.
367  * Value of 0xFFFFFF means that the latency is invalid. Units are according to
368  * MOGCR.mirror_latency_units.
369  */
370 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
371 
372 /* pci_cqe_owner
373  * Ownership bit.
374  */
375 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
376 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
377 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
378 
379 /* pci_eqe_event_type
380  * Event type.
381  */
382 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
383 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP	0x00
384 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD	0x0A
385 
386 /* pci_eqe_event_sub_type
387  * Event type.
388  */
389 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
390 
391 /* pci_eqe_cqn
392  * Completion Queue that triggered this EQE.
393  */
394 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
395 
396 /* pci_eqe_owner
397  * Ownership bit.
398  */
399 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
400 
401 /* pci_eqe_cmd_token
402  * Command completion event - token
403  */
404 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
405 
406 /* pci_eqe_cmd_status
407  * Command completion event - status
408  */
409 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
410 
411 /* pci_eqe_cmd_out_param_h
412  * Command completion event - output parameter - higher part
413  */
414 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
415 
416 /* pci_eqe_cmd_out_param_l
417  * Command completion event - output parameter - lower part
418  */
419 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
420 
421 #endif
422