xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
193 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
194 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
195 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
196 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
197 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
198 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
199 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
200 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
202 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
203 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
205 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
206 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
207 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
208 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
209 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
210 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
211 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
212 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
213 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
214 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
215 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
216 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
217 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
218 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
219 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
220 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
221 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
222 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
223 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
224 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
225 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
226 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
227 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
228 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
229 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
230 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
231 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
232 	MLX5_CMD_OP_NOP                           = 0x80d,
233 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
234 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
235 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
236 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
237 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
238 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
239 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
240 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
241 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
242 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
243 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
244 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
245 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
246 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
247 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
248 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
249 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
250 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
251 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
252 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
253 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
254 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
255 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
256 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
257 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
258 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
259 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
260 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
261 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
262 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
263 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
264 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
265 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
266 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
267 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
268 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
269 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
270 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
271 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
272 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
273 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
274 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
275 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
276 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
277 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
278 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
279 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
280 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
281 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
282 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
283 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
284 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
285 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
286 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
287 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
288 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
289 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
290 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
291 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
292 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
293 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
294 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
295 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
296 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
297 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
298 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
299 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
300 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
301 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
302 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
303 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
304 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
305 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
306 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
307 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
308 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
309 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
310 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
311 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
312 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
313 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
314 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
315 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
316 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
317 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
318 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
319 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
320 	MLX5_CMD_OP_MAX
321 };
322 
323 /* Valid range for general commands that don't work over an object */
324 enum {
325 	MLX5_CMD_OP_GENERAL_START = 0xb00,
326 	MLX5_CMD_OP_GENERAL_END = 0xd00,
327 };
328 
329 enum {
330 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
332 };
333 
334 enum {
335 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
336 };
337 
338 struct mlx5_ifc_flow_table_fields_supported_bits {
339 	u8         outer_dmac[0x1];
340 	u8         outer_smac[0x1];
341 	u8         outer_ether_type[0x1];
342 	u8         outer_ip_version[0x1];
343 	u8         outer_first_prio[0x1];
344 	u8         outer_first_cfi[0x1];
345 	u8         outer_first_vid[0x1];
346 	u8         outer_ipv4_ttl[0x1];
347 	u8         outer_second_prio[0x1];
348 	u8         outer_second_cfi[0x1];
349 	u8         outer_second_vid[0x1];
350 	u8         reserved_at_b[0x1];
351 	u8         outer_sip[0x1];
352 	u8         outer_dip[0x1];
353 	u8         outer_frag[0x1];
354 	u8         outer_ip_protocol[0x1];
355 	u8         outer_ip_ecn[0x1];
356 	u8         outer_ip_dscp[0x1];
357 	u8         outer_udp_sport[0x1];
358 	u8         outer_udp_dport[0x1];
359 	u8         outer_tcp_sport[0x1];
360 	u8         outer_tcp_dport[0x1];
361 	u8         outer_tcp_flags[0x1];
362 	u8         outer_gre_protocol[0x1];
363 	u8         outer_gre_key[0x1];
364 	u8         outer_vxlan_vni[0x1];
365 	u8         outer_geneve_vni[0x1];
366 	u8         outer_geneve_oam[0x1];
367 	u8         outer_geneve_protocol_type[0x1];
368 	u8         outer_geneve_opt_len[0x1];
369 	u8         source_vhca_port[0x1];
370 	u8         source_eswitch_port[0x1];
371 
372 	u8         inner_dmac[0x1];
373 	u8         inner_smac[0x1];
374 	u8         inner_ether_type[0x1];
375 	u8         inner_ip_version[0x1];
376 	u8         inner_first_prio[0x1];
377 	u8         inner_first_cfi[0x1];
378 	u8         inner_first_vid[0x1];
379 	u8         reserved_at_27[0x1];
380 	u8         inner_second_prio[0x1];
381 	u8         inner_second_cfi[0x1];
382 	u8         inner_second_vid[0x1];
383 	u8         reserved_at_2b[0x1];
384 	u8         inner_sip[0x1];
385 	u8         inner_dip[0x1];
386 	u8         inner_frag[0x1];
387 	u8         inner_ip_protocol[0x1];
388 	u8         inner_ip_ecn[0x1];
389 	u8         inner_ip_dscp[0x1];
390 	u8         inner_udp_sport[0x1];
391 	u8         inner_udp_dport[0x1];
392 	u8         inner_tcp_sport[0x1];
393 	u8         inner_tcp_dport[0x1];
394 	u8         inner_tcp_flags[0x1];
395 	u8         reserved_at_37[0x9];
396 
397 	u8         geneve_tlv_option_0_data[0x1];
398 	u8         geneve_tlv_option_0_exist[0x1];
399 	u8         reserved_at_42[0x3];
400 	u8         outer_first_mpls_over_udp[0x4];
401 	u8         outer_first_mpls_over_gre[0x4];
402 	u8         inner_first_mpls[0x4];
403 	u8         outer_first_mpls[0x4];
404 	u8         reserved_at_55[0x2];
405 	u8	   outer_esp_spi[0x1];
406 	u8         reserved_at_58[0x2];
407 	u8         bth_dst_qp[0x1];
408 	u8         reserved_at_5b[0x5];
409 
410 	u8         reserved_at_60[0x18];
411 	u8         metadata_reg_c_7[0x1];
412 	u8         metadata_reg_c_6[0x1];
413 	u8         metadata_reg_c_5[0x1];
414 	u8         metadata_reg_c_4[0x1];
415 	u8         metadata_reg_c_3[0x1];
416 	u8         metadata_reg_c_2[0x1];
417 	u8         metadata_reg_c_1[0x1];
418 	u8         metadata_reg_c_0[0x1];
419 };
420 
421 /* Table 2170 - Flow Table Fields Supported 2 Format */
422 struct mlx5_ifc_flow_table_fields_supported_2_bits {
423 	u8         reserved_at_0[0x2];
424 	u8         inner_l4_type[0x1];
425 	u8         outer_l4_type[0x1];
426 	u8         reserved_at_4[0xa];
427 	u8         bth_opcode[0x1];
428 	u8         reserved_at_f[0x1];
429 	u8         tunnel_header_0_1[0x1];
430 	u8         reserved_at_11[0xf];
431 
432 	u8         reserved_at_20[0x60];
433 };
434 
435 struct mlx5_ifc_flow_table_prop_layout_bits {
436 	u8         ft_support[0x1];
437 	u8         reserved_at_1[0x1];
438 	u8         flow_counter[0x1];
439 	u8	   flow_modify_en[0x1];
440 	u8         modify_root[0x1];
441 	u8         identified_miss_table_mode[0x1];
442 	u8         flow_table_modify[0x1];
443 	u8         reformat[0x1];
444 	u8         decap[0x1];
445 	u8         reset_root_to_default[0x1];
446 	u8         pop_vlan[0x1];
447 	u8         push_vlan[0x1];
448 	u8         reserved_at_c[0x1];
449 	u8         pop_vlan_2[0x1];
450 	u8         push_vlan_2[0x1];
451 	u8	   reformat_and_vlan_action[0x1];
452 	u8	   reserved_at_10[0x1];
453 	u8         sw_owner[0x1];
454 	u8	   reformat_l3_tunnel_to_l2[0x1];
455 	u8	   reformat_l2_to_l3_tunnel[0x1];
456 	u8	   reformat_and_modify_action[0x1];
457 	u8	   ignore_flow_level[0x1];
458 	u8         reserved_at_16[0x1];
459 	u8	   table_miss_action_domain[0x1];
460 	u8         termination_table[0x1];
461 	u8         reformat_and_fwd_to_table[0x1];
462 	u8         reserved_at_1a[0x2];
463 	u8         ipsec_encrypt[0x1];
464 	u8         ipsec_decrypt[0x1];
465 	u8         sw_owner_v2[0x1];
466 	u8         reserved_at_1f[0x1];
467 
468 	u8         termination_table_raw_traffic[0x1];
469 	u8         reserved_at_21[0x1];
470 	u8         log_max_ft_size[0x6];
471 	u8         log_max_modify_header_context[0x8];
472 	u8         max_modify_header_actions[0x8];
473 	u8         max_ft_level[0x8];
474 
475 	u8         reformat_add_esp_trasport[0x1];
476 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
477 	u8         reformat_add_esp_transport_over_udp[0x1];
478 	u8         reformat_del_esp_trasport[0x1];
479 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
480 	u8         reformat_del_esp_transport_over_udp[0x1];
481 	u8         execute_aso[0x1];
482 	u8         reserved_at_47[0x19];
483 
484 	u8         reserved_at_60[0x2];
485 	u8         reformat_insert[0x1];
486 	u8         reformat_remove[0x1];
487 	u8         macsec_encrypt[0x1];
488 	u8         macsec_decrypt[0x1];
489 	u8         reserved_at_66[0x2];
490 	u8         reformat_add_macsec[0x1];
491 	u8         reformat_remove_macsec[0x1];
492 	u8         reparse[0x1];
493 	u8         reserved_at_6b[0x1];
494 	u8         cross_vhca_object[0x1];
495 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
496 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
497 	u8         ignore_flow_level_rtc_valid[0x1];
498 	u8         reserved_at_70[0x8];
499 	u8         log_max_ft_num[0x8];
500 
501 	u8         reserved_at_80[0x10];
502 	u8         log_max_flow_counter[0x8];
503 	u8         log_max_destination[0x8];
504 
505 	u8         reserved_at_a0[0x18];
506 	u8         log_max_flow[0x8];
507 
508 	u8         reserved_at_c0[0x40];
509 
510 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
511 
512 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
513 };
514 
515 struct mlx5_ifc_odp_per_transport_service_cap_bits {
516 	u8         send[0x1];
517 	u8         receive[0x1];
518 	u8         write[0x1];
519 	u8         read[0x1];
520 	u8         atomic[0x1];
521 	u8         srq_receive[0x1];
522 	u8         reserved_at_6[0x1a];
523 };
524 
525 struct mlx5_ifc_ipv4_layout_bits {
526 	u8         reserved_at_0[0x60];
527 
528 	u8         ipv4[0x20];
529 };
530 
531 struct mlx5_ifc_ipv6_layout_bits {
532 	u8         ipv6[16][0x8];
533 };
534 
535 struct mlx5_ifc_ipv6_simple_layout_bits {
536 	u8         ipv6_127_96[0x20];
537 	u8         ipv6_95_64[0x20];
538 	u8         ipv6_63_32[0x20];
539 	u8         ipv6_31_0[0x20];
540 };
541 
542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
543 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
544 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
545 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
546 	u8         reserved_at_0[0x80];
547 };
548 
549 enum {
550 	MLX5_PACKET_L4_TYPE_NONE,
551 	MLX5_PACKET_L4_TYPE_TCP,
552 	MLX5_PACKET_L4_TYPE_UDP,
553 };
554 
555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
556 	u8         smac_47_16[0x20];
557 
558 	u8         smac_15_0[0x10];
559 	u8         ethertype[0x10];
560 
561 	u8         dmac_47_16[0x20];
562 
563 	u8         dmac_15_0[0x10];
564 	u8         first_prio[0x3];
565 	u8         first_cfi[0x1];
566 	u8         first_vid[0xc];
567 
568 	u8         ip_protocol[0x8];
569 	u8         ip_dscp[0x6];
570 	u8         ip_ecn[0x2];
571 	u8         cvlan_tag[0x1];
572 	u8         svlan_tag[0x1];
573 	u8         frag[0x1];
574 	u8         ip_version[0x4];
575 	u8         tcp_flags[0x9];
576 
577 	u8         tcp_sport[0x10];
578 	u8         tcp_dport[0x10];
579 
580 	u8         l4_type[0x2];
581 	u8         reserved_at_c2[0xe];
582 	u8         ipv4_ihl[0x4];
583 	u8         reserved_at_c4[0x4];
584 
585 	u8         ttl_hoplimit[0x8];
586 
587 	u8         udp_sport[0x10];
588 	u8         udp_dport[0x10];
589 
590 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
591 
592 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
593 };
594 
595 struct mlx5_ifc_nvgre_key_bits {
596 	u8 hi[0x18];
597 	u8 lo[0x8];
598 };
599 
600 union mlx5_ifc_gre_key_bits {
601 	struct mlx5_ifc_nvgre_key_bits nvgre;
602 	u8 key[0x20];
603 };
604 
605 struct mlx5_ifc_fte_match_set_misc_bits {
606 	u8         gre_c_present[0x1];
607 	u8         reserved_at_1[0x1];
608 	u8         gre_k_present[0x1];
609 	u8         gre_s_present[0x1];
610 	u8         source_vhca_port[0x4];
611 	u8         source_sqn[0x18];
612 
613 	u8         source_eswitch_owner_vhca_id[0x10];
614 	u8         source_port[0x10];
615 
616 	u8         outer_second_prio[0x3];
617 	u8         outer_second_cfi[0x1];
618 	u8         outer_second_vid[0xc];
619 	u8         inner_second_prio[0x3];
620 	u8         inner_second_cfi[0x1];
621 	u8         inner_second_vid[0xc];
622 
623 	u8         outer_second_cvlan_tag[0x1];
624 	u8         inner_second_cvlan_tag[0x1];
625 	u8         outer_second_svlan_tag[0x1];
626 	u8         inner_second_svlan_tag[0x1];
627 	u8         reserved_at_64[0xc];
628 	u8         gre_protocol[0x10];
629 
630 	union mlx5_ifc_gre_key_bits gre_key;
631 
632 	u8         vxlan_vni[0x18];
633 	u8         bth_opcode[0x8];
634 
635 	u8         geneve_vni[0x18];
636 	u8         reserved_at_d8[0x6];
637 	u8         geneve_tlv_option_0_exist[0x1];
638 	u8         geneve_oam[0x1];
639 
640 	u8         reserved_at_e0[0xc];
641 	u8         outer_ipv6_flow_label[0x14];
642 
643 	u8         reserved_at_100[0xc];
644 	u8         inner_ipv6_flow_label[0x14];
645 
646 	u8         reserved_at_120[0xa];
647 	u8         geneve_opt_len[0x6];
648 	u8         geneve_protocol_type[0x10];
649 
650 	u8         reserved_at_140[0x8];
651 	u8         bth_dst_qp[0x18];
652 	u8	   inner_esp_spi[0x20];
653 	u8	   outer_esp_spi[0x20];
654 	u8         reserved_at_1a0[0x60];
655 };
656 
657 struct mlx5_ifc_fte_match_mpls_bits {
658 	u8         mpls_label[0x14];
659 	u8         mpls_exp[0x3];
660 	u8         mpls_s_bos[0x1];
661 	u8         mpls_ttl[0x8];
662 };
663 
664 struct mlx5_ifc_fte_match_set_misc2_bits {
665 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
666 
667 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
668 
669 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
670 
671 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
672 
673 	u8         metadata_reg_c_7[0x20];
674 
675 	u8         metadata_reg_c_6[0x20];
676 
677 	u8         metadata_reg_c_5[0x20];
678 
679 	u8         metadata_reg_c_4[0x20];
680 
681 	u8         metadata_reg_c_3[0x20];
682 
683 	u8         metadata_reg_c_2[0x20];
684 
685 	u8         metadata_reg_c_1[0x20];
686 
687 	u8         metadata_reg_c_0[0x20];
688 
689 	u8         metadata_reg_a[0x20];
690 
691 	u8         reserved_at_1a0[0x8];
692 
693 	u8         macsec_syndrome[0x8];
694 	u8         ipsec_syndrome[0x8];
695 	u8         reserved_at_1b8[0x8];
696 
697 	u8         reserved_at_1c0[0x40];
698 };
699 
700 struct mlx5_ifc_fte_match_set_misc3_bits {
701 	u8         inner_tcp_seq_num[0x20];
702 
703 	u8         outer_tcp_seq_num[0x20];
704 
705 	u8         inner_tcp_ack_num[0x20];
706 
707 	u8         outer_tcp_ack_num[0x20];
708 
709 	u8	   reserved_at_80[0x8];
710 	u8         outer_vxlan_gpe_vni[0x18];
711 
712 	u8         outer_vxlan_gpe_next_protocol[0x8];
713 	u8         outer_vxlan_gpe_flags[0x8];
714 	u8	   reserved_at_b0[0x10];
715 
716 	u8	   icmp_header_data[0x20];
717 
718 	u8	   icmpv6_header_data[0x20];
719 
720 	u8	   icmp_type[0x8];
721 	u8	   icmp_code[0x8];
722 	u8	   icmpv6_type[0x8];
723 	u8	   icmpv6_code[0x8];
724 
725 	u8         geneve_tlv_option_0_data[0x20];
726 
727 	u8	   gtpu_teid[0x20];
728 
729 	u8	   gtpu_msg_type[0x8];
730 	u8	   gtpu_msg_flags[0x8];
731 	u8	   reserved_at_170[0x10];
732 
733 	u8	   gtpu_dw_2[0x20];
734 
735 	u8	   gtpu_first_ext_dw_0[0x20];
736 
737 	u8	   gtpu_dw_0[0x20];
738 
739 	u8	   reserved_at_1e0[0x20];
740 };
741 
742 struct mlx5_ifc_fte_match_set_misc4_bits {
743 	u8         prog_sample_field_value_0[0x20];
744 
745 	u8         prog_sample_field_id_0[0x20];
746 
747 	u8         prog_sample_field_value_1[0x20];
748 
749 	u8         prog_sample_field_id_1[0x20];
750 
751 	u8         prog_sample_field_value_2[0x20];
752 
753 	u8         prog_sample_field_id_2[0x20];
754 
755 	u8         prog_sample_field_value_3[0x20];
756 
757 	u8         prog_sample_field_id_3[0x20];
758 
759 	u8         reserved_at_100[0x100];
760 };
761 
762 struct mlx5_ifc_fte_match_set_misc5_bits {
763 	u8         macsec_tag_0[0x20];
764 
765 	u8         macsec_tag_1[0x20];
766 
767 	u8         macsec_tag_2[0x20];
768 
769 	u8         macsec_tag_3[0x20];
770 
771 	u8         tunnel_header_0[0x20];
772 
773 	u8         tunnel_header_1[0x20];
774 
775 	u8         tunnel_header_2[0x20];
776 
777 	u8         tunnel_header_3[0x20];
778 
779 	u8         reserved_at_100[0x100];
780 };
781 
782 struct mlx5_ifc_cmd_pas_bits {
783 	u8         pa_h[0x20];
784 
785 	u8         pa_l[0x14];
786 	u8         reserved_at_34[0xc];
787 };
788 
789 struct mlx5_ifc_uint64_bits {
790 	u8         hi[0x20];
791 
792 	u8         lo[0x20];
793 };
794 
795 enum {
796 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
797 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
798 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
799 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
800 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
801 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
802 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
803 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
804 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
805 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
806 };
807 
808 struct mlx5_ifc_ads_bits {
809 	u8         fl[0x1];
810 	u8         free_ar[0x1];
811 	u8         reserved_at_2[0xe];
812 	u8         pkey_index[0x10];
813 
814 	u8         plane_index[0x8];
815 	u8         grh[0x1];
816 	u8         mlid[0x7];
817 	u8         rlid[0x10];
818 
819 	u8         ack_timeout[0x5];
820 	u8         reserved_at_45[0x3];
821 	u8         src_addr_index[0x8];
822 	u8         reserved_at_50[0x4];
823 	u8         stat_rate[0x4];
824 	u8         hop_limit[0x8];
825 
826 	u8         reserved_at_60[0x4];
827 	u8         tclass[0x8];
828 	u8         flow_label[0x14];
829 
830 	u8         rgid_rip[16][0x8];
831 
832 	u8         reserved_at_100[0x4];
833 	u8         f_dscp[0x1];
834 	u8         f_ecn[0x1];
835 	u8         reserved_at_106[0x1];
836 	u8         f_eth_prio[0x1];
837 	u8         ecn[0x2];
838 	u8         dscp[0x6];
839 	u8         udp_sport[0x10];
840 
841 	u8         dei_cfi[0x1];
842 	u8         eth_prio[0x3];
843 	u8         sl[0x4];
844 	u8         vhca_port_num[0x8];
845 	u8         rmac_47_32[0x10];
846 
847 	u8         rmac_31_0[0x20];
848 };
849 
850 struct mlx5_ifc_flow_table_nic_cap_bits {
851 	u8         nic_rx_multi_path_tirs[0x1];
852 	u8         nic_rx_multi_path_tirs_fts[0x1];
853 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
854 	u8	   reserved_at_3[0x4];
855 	u8	   sw_owner_reformat_supported[0x1];
856 	u8	   reserved_at_8[0x18];
857 
858 	u8	   encap_general_header[0x1];
859 	u8	   reserved_at_21[0xa];
860 	u8	   log_max_packet_reformat_context[0x5];
861 	u8	   reserved_at_30[0x6];
862 	u8	   max_encap_header_size[0xa];
863 	u8	   reserved_at_40[0x1c0];
864 
865 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
866 
867 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
868 
869 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
870 
871 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
872 
873 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
874 
875 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
876 
877 	u8         reserved_at_e00[0x600];
878 
879 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
880 
881 	u8         reserved_at_1480[0x80];
882 
883 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
884 
885 	u8         reserved_at_1580[0x280];
886 
887 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
888 
889 	u8         reserved_at_1880[0x780];
890 
891 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
892 
893 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
894 
895 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
896 
897 	u8         reserved_at_20c0[0x5f40];
898 };
899 
900 struct mlx5_ifc_port_selection_cap_bits {
901 	u8         reserved_at_0[0x10];
902 	u8         port_select_flow_table[0x1];
903 	u8         reserved_at_11[0x1];
904 	u8         port_select_flow_table_bypass[0x1];
905 	u8         reserved_at_13[0xd];
906 
907 	u8         reserved_at_20[0x1e0];
908 
909 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
910 
911 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
912 
913 	u8         reserved_at_480[0x7b80];
914 };
915 
916 enum {
917 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
918 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
919 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
920 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
921 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
922 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
923 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
924 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
925 };
926 
927 struct mlx5_ifc_flow_table_eswitch_cap_bits {
928 	u8      fdb_to_vport_reg_c_id[0x8];
929 	u8      reserved_at_8[0x5];
930 	u8      fdb_uplink_hairpin[0x1];
931 	u8      fdb_multi_path_any_table_limit_regc[0x1];
932 	u8      reserved_at_f[0x1];
933 	u8      fdb_dynamic_tunnel[0x1];
934 	u8      reserved_at_11[0x1];
935 	u8      fdb_multi_path_any_table[0x1];
936 	u8      reserved_at_13[0x2];
937 	u8      fdb_modify_header_fwd_to_table[0x1];
938 	u8      fdb_ipv4_ttl_modify[0x1];
939 	u8      flow_source[0x1];
940 	u8      reserved_at_18[0x2];
941 	u8      multi_fdb_encap[0x1];
942 	u8      egress_acl_forward_to_vport[0x1];
943 	u8      fdb_multi_path_to_table[0x1];
944 	u8      reserved_at_1d[0x3];
945 
946 	u8      reserved_at_20[0x1e0];
947 
948 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
949 
950 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
951 
952 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
953 
954 	u8      reserved_at_800[0xC00];
955 
956 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
957 
958 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
959 
960 	u8      reserved_at_1500[0x300];
961 
962 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
963 
964 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
965 
966 	u8      sw_steering_uplink_icm_address_rx[0x40];
967 
968 	u8      sw_steering_uplink_icm_address_tx[0x40];
969 
970 	u8      reserved_at_1900[0x6700];
971 };
972 
973 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
974 	u8         reserved_at_0[0x3];
975 	u8         log_max_num_ste[0x5];
976 	u8         reserved_at_8[0x3];
977 	u8         log_max_num_stc[0x5];
978 	u8         reserved_at_10[0x3];
979 	u8         log_max_num_rtc[0x5];
980 	u8         reserved_at_18[0x3];
981 	u8         log_max_num_header_modify_pattern[0x5];
982 
983 	u8         rtc_hash_split_table[0x1];
984 	u8         rtc_linear_lookup_table[0x1];
985 	u8         reserved_at_22[0x1];
986 	u8         stc_alloc_log_granularity[0x5];
987 	u8         reserved_at_28[0x3];
988 	u8         stc_alloc_log_max[0x5];
989 	u8         reserved_at_30[0x3];
990 	u8         ste_alloc_log_granularity[0x5];
991 	u8         reserved_at_38[0x3];
992 	u8         ste_alloc_log_max[0x5];
993 
994 	u8         reserved_at_40[0xb];
995 	u8         rtc_reparse_mode[0x5];
996 	u8         reserved_at_50[0x3];
997 	u8         rtc_index_mode[0x5];
998 	u8         reserved_at_58[0x3];
999 	u8         rtc_log_depth_max[0x5];
1000 
1001 	u8         reserved_at_60[0x10];
1002 	u8         ste_format[0x10];
1003 
1004 	u8         stc_action_type[0x80];
1005 
1006 	u8         header_insert_type[0x10];
1007 	u8         header_remove_type[0x10];
1008 
1009 	u8         trivial_match_definer[0x20];
1010 
1011 	u8         reserved_at_140[0x1b];
1012 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1013 
1014 	u8         reserved_at_160[0x18];
1015 	u8         access_index_mode[0x8];
1016 
1017 	u8         reserved_at_180[0x10];
1018 	u8         ste_format_gen_wqe[0x10];
1019 
1020 	u8         linear_match_definer_reg_c3[0x20];
1021 
1022 	u8         fdb_jump_to_tir_stc[0x1];
1023 	u8         reserved_at_1c1[0x1f];
1024 };
1025 
1026 struct mlx5_ifc_esw_cap_bits {
1027 	u8         reserved_at_0[0x1d];
1028 	u8         merged_eswitch[0x1];
1029 	u8         reserved_at_1e[0x2];
1030 
1031 	u8         reserved_at_20[0x40];
1032 
1033 	u8         esw_manager_vport_number_valid[0x1];
1034 	u8         reserved_at_61[0xf];
1035 	u8         esw_manager_vport_number[0x10];
1036 
1037 	u8         reserved_at_80[0x780];
1038 };
1039 
1040 enum {
1041 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1042 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1043 };
1044 
1045 struct mlx5_ifc_e_switch_cap_bits {
1046 	u8         vport_svlan_strip[0x1];
1047 	u8         vport_cvlan_strip[0x1];
1048 	u8         vport_svlan_insert[0x1];
1049 	u8         vport_cvlan_insert_if_not_exist[0x1];
1050 	u8         vport_cvlan_insert_overwrite[0x1];
1051 	u8         reserved_at_5[0x1];
1052 	u8         vport_cvlan_insert_always[0x1];
1053 	u8         esw_shared_ingress_acl[0x1];
1054 	u8         esw_uplink_ingress_acl[0x1];
1055 	u8         root_ft_on_other_esw[0x1];
1056 	u8         reserved_at_a[0xf];
1057 	u8         esw_functions_changed[0x1];
1058 	u8         reserved_at_1a[0x1];
1059 	u8         ecpf_vport_exists[0x1];
1060 	u8         counter_eswitch_affinity[0x1];
1061 	u8         merged_eswitch[0x1];
1062 	u8         nic_vport_node_guid_modify[0x1];
1063 	u8         nic_vport_port_guid_modify[0x1];
1064 
1065 	u8         vxlan_encap_decap[0x1];
1066 	u8         nvgre_encap_decap[0x1];
1067 	u8         reserved_at_22[0x1];
1068 	u8         log_max_fdb_encap_uplink[0x5];
1069 	u8         reserved_at_21[0x3];
1070 	u8         log_max_packet_reformat_context[0x5];
1071 	u8         reserved_2b[0x6];
1072 	u8         max_encap_header_size[0xa];
1073 
1074 	u8         reserved_at_40[0xb];
1075 	u8         log_max_esw_sf[0x5];
1076 	u8         esw_sf_base_id[0x10];
1077 
1078 	u8         reserved_at_60[0x7a0];
1079 
1080 };
1081 
1082 struct mlx5_ifc_qos_cap_bits {
1083 	u8         packet_pacing[0x1];
1084 	u8         esw_scheduling[0x1];
1085 	u8         esw_bw_share[0x1];
1086 	u8         esw_rate_limit[0x1];
1087 	u8         reserved_at_4[0x1];
1088 	u8         packet_pacing_burst_bound[0x1];
1089 	u8         packet_pacing_typical_size[0x1];
1090 	u8         reserved_at_7[0x1];
1091 	u8         nic_sq_scheduling[0x1];
1092 	u8         nic_bw_share[0x1];
1093 	u8         nic_rate_limit[0x1];
1094 	u8         packet_pacing_uid[0x1];
1095 	u8         log_esw_max_sched_depth[0x4];
1096 	u8         reserved_at_10[0x10];
1097 
1098 	u8         reserved_at_20[0x9];
1099 	u8         esw_cross_esw_sched[0x1];
1100 	u8         reserved_at_2a[0x1];
1101 	u8         log_max_qos_nic_queue_group[0x5];
1102 	u8         reserved_at_30[0x10];
1103 
1104 	u8         packet_pacing_max_rate[0x20];
1105 
1106 	u8         packet_pacing_min_rate[0x20];
1107 
1108 	u8         reserved_at_80[0xb];
1109 	u8         log_esw_max_rate_limit[0x5];
1110 	u8         packet_pacing_rate_table_size[0x10];
1111 
1112 	u8         esw_element_type[0x10];
1113 	u8         esw_tsar_type[0x10];
1114 
1115 	u8         reserved_at_c0[0x10];
1116 	u8         max_qos_para_vport[0x10];
1117 
1118 	u8         max_tsar_bw_share[0x20];
1119 
1120 	u8         nic_element_type[0x10];
1121 	u8         nic_tsar_type[0x10];
1122 
1123 	u8         reserved_at_120[0x3];
1124 	u8         log_meter_aso_granularity[0x5];
1125 	u8         reserved_at_128[0x3];
1126 	u8         log_meter_aso_max_alloc[0x5];
1127 	u8         reserved_at_130[0x3];
1128 	u8         log_max_num_meter_aso[0x5];
1129 	u8         reserved_at_138[0x8];
1130 
1131 	u8         reserved_at_140[0x6c0];
1132 };
1133 
1134 struct mlx5_ifc_debug_cap_bits {
1135 	u8         core_dump_general[0x1];
1136 	u8         core_dump_qp[0x1];
1137 	u8         reserved_at_2[0x7];
1138 	u8         resource_dump[0x1];
1139 	u8         reserved_at_a[0x16];
1140 
1141 	u8         reserved_at_20[0x2];
1142 	u8         stall_detect[0x1];
1143 	u8         reserved_at_23[0x1d];
1144 
1145 	u8         reserved_at_40[0x7c0];
1146 };
1147 
1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1149 	u8         csum_cap[0x1];
1150 	u8         vlan_cap[0x1];
1151 	u8         lro_cap[0x1];
1152 	u8         lro_psh_flag[0x1];
1153 	u8         lro_time_stamp[0x1];
1154 	u8         reserved_at_5[0x2];
1155 	u8         wqe_vlan_insert[0x1];
1156 	u8         self_lb_en_modifiable[0x1];
1157 	u8         reserved_at_9[0x2];
1158 	u8         max_lso_cap[0x5];
1159 	u8         multi_pkt_send_wqe[0x2];
1160 	u8	   wqe_inline_mode[0x2];
1161 	u8         rss_ind_tbl_cap[0x4];
1162 	u8         reg_umr_sq[0x1];
1163 	u8         scatter_fcs[0x1];
1164 	u8         enhanced_multi_pkt_send_wqe[0x1];
1165 	u8         tunnel_lso_const_out_ip_id[0x1];
1166 	u8         tunnel_lro_gre[0x1];
1167 	u8         tunnel_lro_vxlan[0x1];
1168 	u8         tunnel_stateless_gre[0x1];
1169 	u8         tunnel_stateless_vxlan[0x1];
1170 
1171 	u8         swp[0x1];
1172 	u8         swp_csum[0x1];
1173 	u8         swp_lso[0x1];
1174 	u8         cqe_checksum_full[0x1];
1175 	u8         tunnel_stateless_geneve_tx[0x1];
1176 	u8         tunnel_stateless_mpls_over_udp[0x1];
1177 	u8         tunnel_stateless_mpls_over_gre[0x1];
1178 	u8         tunnel_stateless_vxlan_gpe[0x1];
1179 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1180 	u8         tunnel_stateless_ip_over_ip[0x1];
1181 	u8         insert_trailer[0x1];
1182 	u8         reserved_at_2b[0x1];
1183 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1184 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1185 	u8         reserved_at_2e[0x2];
1186 	u8         max_vxlan_udp_ports[0x8];
1187 	u8         swp_csum_l4_partial[0x1];
1188 	u8         reserved_at_39[0x5];
1189 	u8         max_geneve_opt_len[0x1];
1190 	u8         tunnel_stateless_geneve_rx[0x1];
1191 
1192 	u8         reserved_at_40[0x10];
1193 	u8         lro_min_mss_size[0x10];
1194 
1195 	u8         reserved_at_60[0x120];
1196 
1197 	u8         lro_timer_supported_periods[4][0x20];
1198 
1199 	u8         reserved_at_200[0x600];
1200 };
1201 
1202 enum {
1203 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1204 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1205 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1206 };
1207 
1208 struct mlx5_ifc_roce_cap_bits {
1209 	u8         roce_apm[0x1];
1210 	u8         reserved_at_1[0x3];
1211 	u8         sw_r_roce_src_udp_port[0x1];
1212 	u8         fl_rc_qp_when_roce_disabled[0x1];
1213 	u8         fl_rc_qp_when_roce_enabled[0x1];
1214 	u8         roce_cc_general[0x1];
1215 	u8	   qp_ooo_transmit_default[0x1];
1216 	u8         reserved_at_9[0x15];
1217 	u8	   qp_ts_format[0x2];
1218 
1219 	u8         reserved_at_20[0x60];
1220 
1221 	u8         reserved_at_80[0xc];
1222 	u8         l3_type[0x4];
1223 	u8         reserved_at_90[0x8];
1224 	u8         roce_version[0x8];
1225 
1226 	u8         reserved_at_a0[0x10];
1227 	u8         r_roce_dest_udp_port[0x10];
1228 
1229 	u8         r_roce_max_src_udp_port[0x10];
1230 	u8         r_roce_min_src_udp_port[0x10];
1231 
1232 	u8         reserved_at_e0[0x10];
1233 	u8         roce_address_table_size[0x10];
1234 
1235 	u8         reserved_at_100[0x700];
1236 };
1237 
1238 struct mlx5_ifc_sync_steering_in_bits {
1239 	u8         opcode[0x10];
1240 	u8         uid[0x10];
1241 
1242 	u8         reserved_at_20[0x10];
1243 	u8         op_mod[0x10];
1244 
1245 	u8         reserved_at_40[0xc0];
1246 };
1247 
1248 struct mlx5_ifc_sync_steering_out_bits {
1249 	u8         status[0x8];
1250 	u8         reserved_at_8[0x18];
1251 
1252 	u8         syndrome[0x20];
1253 
1254 	u8         reserved_at_40[0x40];
1255 };
1256 
1257 struct mlx5_ifc_sync_crypto_in_bits {
1258 	u8         opcode[0x10];
1259 	u8         uid[0x10];
1260 
1261 	u8         reserved_at_20[0x10];
1262 	u8         op_mod[0x10];
1263 
1264 	u8         reserved_at_40[0x20];
1265 
1266 	u8         reserved_at_60[0x10];
1267 	u8         crypto_type[0x10];
1268 
1269 	u8         reserved_at_80[0x80];
1270 };
1271 
1272 struct mlx5_ifc_sync_crypto_out_bits {
1273 	u8         status[0x8];
1274 	u8         reserved_at_8[0x18];
1275 
1276 	u8         syndrome[0x20];
1277 
1278 	u8         reserved_at_40[0x40];
1279 };
1280 
1281 struct mlx5_ifc_device_mem_cap_bits {
1282 	u8         memic[0x1];
1283 	u8         reserved_at_1[0x1f];
1284 
1285 	u8         reserved_at_20[0xb];
1286 	u8         log_min_memic_alloc_size[0x5];
1287 	u8         reserved_at_30[0x8];
1288 	u8	   log_max_memic_addr_alignment[0x8];
1289 
1290 	u8         memic_bar_start_addr[0x40];
1291 
1292 	u8         memic_bar_size[0x20];
1293 
1294 	u8         max_memic_size[0x20];
1295 
1296 	u8         steering_sw_icm_start_address[0x40];
1297 
1298 	u8         reserved_at_100[0x8];
1299 	u8         log_header_modify_sw_icm_size[0x8];
1300 	u8         reserved_at_110[0x2];
1301 	u8         log_sw_icm_alloc_granularity[0x6];
1302 	u8         log_steering_sw_icm_size[0x8];
1303 
1304 	u8         log_indirect_encap_sw_icm_size[0x8];
1305 	u8         reserved_at_128[0x10];
1306 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1307 
1308 	u8         header_modify_sw_icm_start_address[0x40];
1309 
1310 	u8         reserved_at_180[0x40];
1311 
1312 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1313 
1314 	u8         memic_operations[0x20];
1315 
1316 	u8         reserved_at_220[0x20];
1317 
1318 	u8         indirect_encap_sw_icm_start_address[0x40];
1319 
1320 	u8         reserved_at_280[0x580];
1321 };
1322 
1323 struct mlx5_ifc_device_event_cap_bits {
1324 	u8         user_affiliated_events[4][0x40];
1325 
1326 	u8         user_unaffiliated_events[4][0x40];
1327 };
1328 
1329 struct mlx5_ifc_virtio_emulation_cap_bits {
1330 	u8         desc_tunnel_offload_type[0x1];
1331 	u8         eth_frame_offload_type[0x1];
1332 	u8         virtio_version_1_0[0x1];
1333 	u8         device_features_bits_mask[0xd];
1334 	u8         event_mode[0x8];
1335 	u8         virtio_queue_type[0x8];
1336 
1337 	u8         max_tunnel_desc[0x10];
1338 	u8         reserved_at_30[0x3];
1339 	u8         log_doorbell_stride[0x5];
1340 	u8         reserved_at_38[0x3];
1341 	u8         log_doorbell_bar_size[0x5];
1342 
1343 	u8         doorbell_bar_offset[0x40];
1344 
1345 	u8         max_emulated_devices[0x8];
1346 	u8         max_num_virtio_queues[0x18];
1347 
1348 	u8         reserved_at_a0[0x20];
1349 
1350 	u8	   reserved_at_c0[0x13];
1351 	u8         desc_group_mkey_supported[0x1];
1352 	u8         freeze_to_rdy_supported[0x1];
1353 	u8         reserved_at_d5[0xb];
1354 
1355 	u8         reserved_at_e0[0x20];
1356 
1357 	u8         umem_1_buffer_param_a[0x20];
1358 
1359 	u8         umem_1_buffer_param_b[0x20];
1360 
1361 	u8         umem_2_buffer_param_a[0x20];
1362 
1363 	u8         umem_2_buffer_param_b[0x20];
1364 
1365 	u8         umem_3_buffer_param_a[0x20];
1366 
1367 	u8         umem_3_buffer_param_b[0x20];
1368 
1369 	u8         reserved_at_1c0[0x640];
1370 };
1371 
1372 enum {
1373 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1374 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1375 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1376 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1377 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1378 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1379 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1380 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1381 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1382 };
1383 
1384 enum {
1385 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1386 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1387 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1388 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1389 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1390 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1391 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1392 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1393 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1394 };
1395 
1396 struct mlx5_ifc_atomic_caps_bits {
1397 	u8         reserved_at_0[0x40];
1398 
1399 	u8         atomic_req_8B_endianness_mode[0x2];
1400 	u8         reserved_at_42[0x4];
1401 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1402 
1403 	u8         reserved_at_47[0x19];
1404 
1405 	u8         reserved_at_60[0x20];
1406 
1407 	u8         reserved_at_80[0x10];
1408 	u8         atomic_operations[0x10];
1409 
1410 	u8         reserved_at_a0[0x10];
1411 	u8         atomic_size_qp[0x10];
1412 
1413 	u8         reserved_at_c0[0x10];
1414 	u8         atomic_size_dc[0x10];
1415 
1416 	u8         reserved_at_e0[0x720];
1417 };
1418 
1419 struct mlx5_ifc_odp_scheme_cap_bits {
1420 	u8         reserved_at_0[0x40];
1421 
1422 	u8         sig[0x1];
1423 	u8         reserved_at_41[0x4];
1424 	u8         page_prefetch[0x1];
1425 	u8         reserved_at_46[0x1a];
1426 
1427 	u8         reserved_at_60[0x20];
1428 
1429 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1430 
1431 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1432 
1433 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1434 
1435 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1436 
1437 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1438 
1439 	u8         reserved_at_120[0xe0];
1440 };
1441 
1442 struct mlx5_ifc_odp_cap_bits {
1443 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1444 
1445 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1446 
1447 	u8         reserved_at_400[0x200];
1448 
1449 	u8         mem_page_fault[0x1];
1450 	u8         reserved_at_601[0x1f];
1451 
1452 	u8         reserved_at_620[0x1e0];
1453 };
1454 
1455 struct mlx5_ifc_tls_cap_bits {
1456 	u8         tls_1_2_aes_gcm_128[0x1];
1457 	u8         tls_1_3_aes_gcm_128[0x1];
1458 	u8         tls_1_2_aes_gcm_256[0x1];
1459 	u8         tls_1_3_aes_gcm_256[0x1];
1460 	u8         reserved_at_4[0x1c];
1461 
1462 	u8         reserved_at_20[0x7e0];
1463 };
1464 
1465 struct mlx5_ifc_ipsec_cap_bits {
1466 	u8         ipsec_full_offload[0x1];
1467 	u8         ipsec_crypto_offload[0x1];
1468 	u8         ipsec_esn[0x1];
1469 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1470 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1471 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1472 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1473 	u8         reserved_at_7[0x4];
1474 	u8         log_max_ipsec_offload[0x5];
1475 	u8         reserved_at_10[0x10];
1476 
1477 	u8         min_log_ipsec_full_replay_window[0x8];
1478 	u8         max_log_ipsec_full_replay_window[0x8];
1479 	u8         reserved_at_30[0x7d0];
1480 };
1481 
1482 struct mlx5_ifc_macsec_cap_bits {
1483 	u8    macsec_epn[0x1];
1484 	u8    reserved_at_1[0x2];
1485 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1486 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1487 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1488 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1489 	u8    reserved_at_7[0x4];
1490 	u8    log_max_macsec_offload[0x5];
1491 	u8    reserved_at_10[0x10];
1492 
1493 	u8    min_log_macsec_full_replay_window[0x8];
1494 	u8    max_log_macsec_full_replay_window[0x8];
1495 	u8    reserved_at_30[0x10];
1496 
1497 	u8    reserved_at_40[0x7c0];
1498 };
1499 
1500 enum {
1501 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1502 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1503 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1504 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1505 };
1506 
1507 enum {
1508 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1509 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1510 };
1511 
1512 enum {
1513 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1514 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1515 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1516 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1517 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1518 };
1519 
1520 enum {
1521 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1522 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1523 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1524 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1525 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1526 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1527 };
1528 
1529 enum {
1530 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1531 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1532 };
1533 
1534 enum {
1535 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1536 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1537 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1538 };
1539 
1540 enum {
1541 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1542 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1543 };
1544 
1545 enum {
1546 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1547 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1548 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1549 };
1550 
1551 enum {
1552 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1553 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1554 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1555 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1556 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1557 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1558 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1559 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1560 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1561 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1562 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1563 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1564 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1565 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1566 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1567 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1568 };
1569 
1570 enum {
1571 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1572 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1573 	MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1574 	MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1575 };
1576 
1577 #define MLX5_FC_BULK_SIZE_FACTOR 128
1578 
1579 enum mlx5_fc_bulk_alloc_bitmask {
1580 	MLX5_FC_BULK_128   = (1 << 0),
1581 	MLX5_FC_BULK_256   = (1 << 1),
1582 	MLX5_FC_BULK_512   = (1 << 2),
1583 	MLX5_FC_BULK_1024  = (1 << 3),
1584 	MLX5_FC_BULK_2048  = (1 << 4),
1585 	MLX5_FC_BULK_4096  = (1 << 5),
1586 	MLX5_FC_BULK_8192  = (1 << 6),
1587 	MLX5_FC_BULK_16384 = (1 << 7),
1588 };
1589 
1590 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1591 
1592 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1593 
1594 enum {
1595 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1596 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1597 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1598 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1599 };
1600 
1601 struct mlx5_ifc_cmd_hca_cap_bits {
1602 	u8         reserved_at_0[0x6];
1603 	u8         page_request_disable[0x1];
1604 	u8         abs_native_port_num[0x1];
1605 	u8         reserved_at_8[0x8];
1606 	u8         shared_object_to_user_object_allowed[0x1];
1607 	u8         reserved_at_13[0xe];
1608 	u8         vhca_resource_manager[0x1];
1609 
1610 	u8         hca_cap_2[0x1];
1611 	u8         create_lag_when_not_master_up[0x1];
1612 	u8         dtor[0x1];
1613 	u8         event_on_vhca_state_teardown_request[0x1];
1614 	u8         event_on_vhca_state_in_use[0x1];
1615 	u8         event_on_vhca_state_active[0x1];
1616 	u8         event_on_vhca_state_allocated[0x1];
1617 	u8         event_on_vhca_state_invalid[0x1];
1618 	u8         reserved_at_28[0x8];
1619 	u8         vhca_id[0x10];
1620 
1621 	u8         reserved_at_40[0x40];
1622 
1623 	u8         log_max_srq_sz[0x8];
1624 	u8         log_max_qp_sz[0x8];
1625 	u8         event_cap[0x1];
1626 	u8         reserved_at_91[0x2];
1627 	u8         isolate_vl_tc_new[0x1];
1628 	u8         reserved_at_94[0x4];
1629 	u8         prio_tag_required[0x1];
1630 	u8         reserved_at_99[0x2];
1631 	u8         log_max_qp[0x5];
1632 
1633 	u8         reserved_at_a0[0x3];
1634 	u8	   ece_support[0x1];
1635 	u8	   reserved_at_a4[0x5];
1636 	u8         reg_c_preserve[0x1];
1637 	u8         reserved_at_aa[0x1];
1638 	u8         log_max_srq[0x5];
1639 	u8         reserved_at_b0[0x1];
1640 	u8         uplink_follow[0x1];
1641 	u8         ts_cqe_to_dest_cqn[0x1];
1642 	u8         reserved_at_b3[0x6];
1643 	u8         go_back_n[0x1];
1644 	u8         reserved_at_ba[0x6];
1645 
1646 	u8         max_sgl_for_optimized_performance[0x8];
1647 	u8         log_max_cq_sz[0x8];
1648 	u8         relaxed_ordering_write_umr[0x1];
1649 	u8         relaxed_ordering_read_umr[0x1];
1650 	u8         reserved_at_d2[0x7];
1651 	u8         virtio_net_device_emualtion_manager[0x1];
1652 	u8         virtio_blk_device_emualtion_manager[0x1];
1653 	u8         log_max_cq[0x5];
1654 
1655 	u8         log_max_eq_sz[0x8];
1656 	u8         relaxed_ordering_write[0x1];
1657 	u8         relaxed_ordering_read_pci_enabled[0x1];
1658 	u8         log_max_mkey[0x6];
1659 	u8         reserved_at_f0[0x6];
1660 	u8	   terminate_scatter_list_mkey[0x1];
1661 	u8	   repeated_mkey[0x1];
1662 	u8         dump_fill_mkey[0x1];
1663 	u8         reserved_at_f9[0x2];
1664 	u8         fast_teardown[0x1];
1665 	u8         log_max_eq[0x4];
1666 
1667 	u8         max_indirection[0x8];
1668 	u8         fixed_buffer_size[0x1];
1669 	u8         log_max_mrw_sz[0x7];
1670 	u8         force_teardown[0x1];
1671 	u8         reserved_at_111[0x1];
1672 	u8         log_max_bsf_list_size[0x6];
1673 	u8         umr_extended_translation_offset[0x1];
1674 	u8         null_mkey[0x1];
1675 	u8         log_max_klm_list_size[0x6];
1676 
1677 	u8         reserved_at_120[0x2];
1678 	u8	   qpc_extension[0x1];
1679 	u8	   reserved_at_123[0x7];
1680 	u8         log_max_ra_req_dc[0x6];
1681 	u8         reserved_at_130[0x2];
1682 	u8         eth_wqe_too_small[0x1];
1683 	u8         reserved_at_133[0x6];
1684 	u8         vnic_env_cq_overrun[0x1];
1685 	u8         log_max_ra_res_dc[0x6];
1686 
1687 	u8         reserved_at_140[0x5];
1688 	u8         release_all_pages[0x1];
1689 	u8         must_not_use[0x1];
1690 	u8         reserved_at_147[0x2];
1691 	u8         roce_accl[0x1];
1692 	u8         log_max_ra_req_qp[0x6];
1693 	u8         reserved_at_150[0xa];
1694 	u8         log_max_ra_res_qp[0x6];
1695 
1696 	u8         end_pad[0x1];
1697 	u8         cc_query_allowed[0x1];
1698 	u8         cc_modify_allowed[0x1];
1699 	u8         start_pad[0x1];
1700 	u8         cache_line_128byte[0x1];
1701 	u8         reserved_at_165[0x4];
1702 	u8         rts2rts_qp_counters_set_id[0x1];
1703 	u8         reserved_at_16a[0x2];
1704 	u8         vnic_env_int_rq_oob[0x1];
1705 	u8         sbcam_reg[0x1];
1706 	u8         reserved_at_16e[0x1];
1707 	u8         qcam_reg[0x1];
1708 	u8         gid_table_size[0x10];
1709 
1710 	u8         out_of_seq_cnt[0x1];
1711 	u8         vport_counters[0x1];
1712 	u8         retransmission_q_counters[0x1];
1713 	u8         debug[0x1];
1714 	u8         modify_rq_counter_set_id[0x1];
1715 	u8         rq_delay_drop[0x1];
1716 	u8         max_qp_cnt[0xa];
1717 	u8         pkey_table_size[0x10];
1718 
1719 	u8         vport_group_manager[0x1];
1720 	u8         vhca_group_manager[0x1];
1721 	u8         ib_virt[0x1];
1722 	u8         eth_virt[0x1];
1723 	u8         vnic_env_queue_counters[0x1];
1724 	u8         ets[0x1];
1725 	u8         nic_flow_table[0x1];
1726 	u8         eswitch_manager[0x1];
1727 	u8         device_memory[0x1];
1728 	u8         mcam_reg[0x1];
1729 	u8         pcam_reg[0x1];
1730 	u8         local_ca_ack_delay[0x5];
1731 	u8         port_module_event[0x1];
1732 	u8         enhanced_error_q_counters[0x1];
1733 	u8         ports_check[0x1];
1734 	u8         reserved_at_1b3[0x1];
1735 	u8         disable_link_up[0x1];
1736 	u8         beacon_led[0x1];
1737 	u8         port_type[0x2];
1738 	u8         num_ports[0x8];
1739 
1740 	u8         reserved_at_1c0[0x1];
1741 	u8         pps[0x1];
1742 	u8         pps_modify[0x1];
1743 	u8         log_max_msg[0x5];
1744 	u8         reserved_at_1c8[0x4];
1745 	u8         max_tc[0x4];
1746 	u8         temp_warn_event[0x1];
1747 	u8         dcbx[0x1];
1748 	u8         general_notification_event[0x1];
1749 	u8         reserved_at_1d3[0x2];
1750 	u8         fpga[0x1];
1751 	u8         rol_s[0x1];
1752 	u8         rol_g[0x1];
1753 	u8         reserved_at_1d8[0x1];
1754 	u8         wol_s[0x1];
1755 	u8         wol_g[0x1];
1756 	u8         wol_a[0x1];
1757 	u8         wol_b[0x1];
1758 	u8         wol_m[0x1];
1759 	u8         wol_u[0x1];
1760 	u8         wol_p[0x1];
1761 
1762 	u8         stat_rate_support[0x10];
1763 	u8         reserved_at_1f0[0x1];
1764 	u8         pci_sync_for_fw_update_event[0x1];
1765 	u8         reserved_at_1f2[0x6];
1766 	u8         init2_lag_tx_port_affinity[0x1];
1767 	u8         reserved_at_1fa[0x2];
1768 	u8         wqe_based_flow_table_update_cap[0x1];
1769 	u8         cqe_version[0x4];
1770 
1771 	u8         compact_address_vector[0x1];
1772 	u8         striding_rq[0x1];
1773 	u8         reserved_at_202[0x1];
1774 	u8         ipoib_enhanced_offloads[0x1];
1775 	u8         ipoib_basic_offloads[0x1];
1776 	u8         reserved_at_205[0x1];
1777 	u8         repeated_block_disabled[0x1];
1778 	u8         umr_modify_entity_size_disabled[0x1];
1779 	u8         umr_modify_atomic_disabled[0x1];
1780 	u8         umr_indirect_mkey_disabled[0x1];
1781 	u8         umr_fence[0x2];
1782 	u8         dc_req_scat_data_cqe[0x1];
1783 	u8         reserved_at_20d[0x2];
1784 	u8         drain_sigerr[0x1];
1785 	u8         cmdif_checksum[0x2];
1786 	u8         sigerr_cqe[0x1];
1787 	u8         reserved_at_213[0x1];
1788 	u8         wq_signature[0x1];
1789 	u8         sctr_data_cqe[0x1];
1790 	u8         reserved_at_216[0x1];
1791 	u8         sho[0x1];
1792 	u8         tph[0x1];
1793 	u8         rf[0x1];
1794 	u8         dct[0x1];
1795 	u8         qos[0x1];
1796 	u8         eth_net_offloads[0x1];
1797 	u8         roce[0x1];
1798 	u8         atomic[0x1];
1799 	u8         reserved_at_21f[0x1];
1800 
1801 	u8         cq_oi[0x1];
1802 	u8         cq_resize[0x1];
1803 	u8         cq_moderation[0x1];
1804 	u8         cq_period_mode_modify[0x1];
1805 	u8         reserved_at_224[0x2];
1806 	u8         cq_eq_remap[0x1];
1807 	u8         pg[0x1];
1808 	u8         block_lb_mc[0x1];
1809 	u8         reserved_at_229[0x1];
1810 	u8         scqe_break_moderation[0x1];
1811 	u8         cq_period_start_from_cqe[0x1];
1812 	u8         cd[0x1];
1813 	u8         reserved_at_22d[0x1];
1814 	u8         apm[0x1];
1815 	u8         vector_calc[0x1];
1816 	u8         umr_ptr_rlky[0x1];
1817 	u8	   imaicl[0x1];
1818 	u8	   qp_packet_based[0x1];
1819 	u8         reserved_at_233[0x3];
1820 	u8         qkv[0x1];
1821 	u8         pkv[0x1];
1822 	u8         set_deth_sqpn[0x1];
1823 	u8         reserved_at_239[0x3];
1824 	u8         xrc[0x1];
1825 	u8         ud[0x1];
1826 	u8         uc[0x1];
1827 	u8         rc[0x1];
1828 
1829 	u8         uar_4k[0x1];
1830 	u8         reserved_at_241[0x7];
1831 	u8         fl_rc_qp_when_roce_disabled[0x1];
1832 	u8         regexp_params[0x1];
1833 	u8         uar_sz[0x6];
1834 	u8         port_selection_cap[0x1];
1835 	u8         nic_cap_reg[0x1];
1836 	u8         umem_uid_0[0x1];
1837 	u8         reserved_at_253[0x5];
1838 	u8         log_pg_sz[0x8];
1839 
1840 	u8         bf[0x1];
1841 	u8         driver_version[0x1];
1842 	u8         pad_tx_eth_packet[0x1];
1843 	u8         reserved_at_263[0x3];
1844 	u8         mkey_by_name[0x1];
1845 	u8         reserved_at_267[0x4];
1846 
1847 	u8         log_bf_reg_size[0x5];
1848 
1849 	u8         reserved_at_270[0x3];
1850 	u8	   qp_error_syndrome[0x1];
1851 	u8	   reserved_at_274[0x2];
1852 	u8         lag_dct[0x2];
1853 	u8         lag_tx_port_affinity[0x1];
1854 	u8         lag_native_fdb_selection[0x1];
1855 	u8         reserved_at_27a[0x1];
1856 	u8         lag_master[0x1];
1857 	u8         num_lag_ports[0x4];
1858 
1859 	u8         reserved_at_280[0x10];
1860 	u8         max_wqe_sz_sq[0x10];
1861 
1862 	u8         reserved_at_2a0[0xb];
1863 	u8         shampo[0x1];
1864 	u8         reserved_at_2ac[0x4];
1865 	u8         max_wqe_sz_rq[0x10];
1866 
1867 	u8         max_flow_counter_31_16[0x10];
1868 	u8         max_wqe_sz_sq_dc[0x10];
1869 
1870 	u8         reserved_at_2e0[0x7];
1871 	u8         max_qp_mcg[0x19];
1872 
1873 	u8         reserved_at_300[0x10];
1874 	u8         flow_counter_bulk_alloc[0x8];
1875 	u8         log_max_mcg[0x8];
1876 
1877 	u8         reserved_at_320[0x3];
1878 	u8         log_max_transport_domain[0x5];
1879 	u8         reserved_at_328[0x2];
1880 	u8	   relaxed_ordering_read[0x1];
1881 	u8         log_max_pd[0x5];
1882 	u8         dp_ordering_ooo_all_ud[0x1];
1883 	u8         dp_ordering_ooo_all_uc[0x1];
1884 	u8         dp_ordering_ooo_all_xrc[0x1];
1885 	u8         dp_ordering_ooo_all_dc[0x1];
1886 	u8         dp_ordering_ooo_all_rc[0x1];
1887 	u8         pcie_reset_using_hotreset_method[0x1];
1888 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1889 	u8         vnic_env_cnt_steering_fail[0x1];
1890 	u8         vport_counter_local_loopback[0x1];
1891 	u8         q_counter_aggregation[0x1];
1892 	u8         q_counter_other_vport[0x1];
1893 	u8         log_max_xrcd[0x5];
1894 
1895 	u8         nic_receive_steering_discard[0x1];
1896 	u8         receive_discard_vport_down[0x1];
1897 	u8         transmit_discard_vport_down[0x1];
1898 	u8         eq_overrun_count[0x1];
1899 	u8         reserved_at_344[0x1];
1900 	u8         invalid_command_count[0x1];
1901 	u8         quota_exceeded_count[0x1];
1902 	u8         reserved_at_347[0x1];
1903 	u8         log_max_flow_counter_bulk[0x8];
1904 	u8         max_flow_counter_15_0[0x10];
1905 
1906 
1907 	u8         reserved_at_360[0x3];
1908 	u8         log_max_rq[0x5];
1909 	u8         reserved_at_368[0x3];
1910 	u8         log_max_sq[0x5];
1911 	u8         reserved_at_370[0x3];
1912 	u8         log_max_tir[0x5];
1913 	u8         reserved_at_378[0x3];
1914 	u8         log_max_tis[0x5];
1915 
1916 	u8         basic_cyclic_rcv_wqe[0x1];
1917 	u8         reserved_at_381[0x2];
1918 	u8         log_max_rmp[0x5];
1919 	u8         reserved_at_388[0x3];
1920 	u8         log_max_rqt[0x5];
1921 	u8         reserved_at_390[0x3];
1922 	u8         log_max_rqt_size[0x5];
1923 	u8         reserved_at_398[0x3];
1924 	u8         log_max_tis_per_sq[0x5];
1925 
1926 	u8         ext_stride_num_range[0x1];
1927 	u8         roce_rw_supported[0x1];
1928 	u8         log_max_current_uc_list_wr_supported[0x1];
1929 	u8         log_max_stride_sz_rq[0x5];
1930 	u8         reserved_at_3a8[0x3];
1931 	u8         log_min_stride_sz_rq[0x5];
1932 	u8         reserved_at_3b0[0x3];
1933 	u8         log_max_stride_sz_sq[0x5];
1934 	u8         reserved_at_3b8[0x3];
1935 	u8         log_min_stride_sz_sq[0x5];
1936 
1937 	u8         hairpin[0x1];
1938 	u8         reserved_at_3c1[0x2];
1939 	u8         log_max_hairpin_queues[0x5];
1940 	u8         reserved_at_3c8[0x3];
1941 	u8         log_max_hairpin_wq_data_sz[0x5];
1942 	u8         reserved_at_3d0[0x3];
1943 	u8         log_max_hairpin_num_packets[0x5];
1944 	u8         reserved_at_3d8[0x3];
1945 	u8         log_max_wq_sz[0x5];
1946 
1947 	u8         nic_vport_change_event[0x1];
1948 	u8         disable_local_lb_uc[0x1];
1949 	u8         disable_local_lb_mc[0x1];
1950 	u8         log_min_hairpin_wq_data_sz[0x5];
1951 	u8         reserved_at_3e8[0x1];
1952 	u8         silent_mode[0x1];
1953 	u8         vhca_state[0x1];
1954 	u8         log_max_vlan_list[0x5];
1955 	u8         reserved_at_3f0[0x3];
1956 	u8         log_max_current_mc_list[0x5];
1957 	u8         reserved_at_3f8[0x3];
1958 	u8         log_max_current_uc_list[0x5];
1959 
1960 	u8         general_obj_types[0x40];
1961 
1962 	u8         sq_ts_format[0x2];
1963 	u8         rq_ts_format[0x2];
1964 	u8         steering_format_version[0x4];
1965 	u8         create_qp_start_hint[0x18];
1966 
1967 	u8         reserved_at_460[0x1];
1968 	u8         ats[0x1];
1969 	u8         cross_vhca_rqt[0x1];
1970 	u8         log_max_uctx[0x5];
1971 	u8         reserved_at_468[0x1];
1972 	u8         crypto[0x1];
1973 	u8         ipsec_offload[0x1];
1974 	u8         log_max_umem[0x5];
1975 	u8         max_num_eqs[0x10];
1976 
1977 	u8         reserved_at_480[0x1];
1978 	u8         tls_tx[0x1];
1979 	u8         tls_rx[0x1];
1980 	u8         log_max_l2_table[0x5];
1981 	u8         reserved_at_488[0x8];
1982 	u8         log_uar_page_sz[0x10];
1983 
1984 	u8         reserved_at_4a0[0x20];
1985 	u8         device_frequency_mhz[0x20];
1986 	u8         device_frequency_khz[0x20];
1987 
1988 	u8         reserved_at_500[0x20];
1989 	u8	   num_of_uars_per_page[0x20];
1990 
1991 	u8         flex_parser_protocols[0x20];
1992 
1993 	u8         max_geneve_tlv_options[0x8];
1994 	u8         reserved_at_568[0x3];
1995 	u8         max_geneve_tlv_option_data_len[0x5];
1996 	u8         reserved_at_570[0x1];
1997 	u8         adv_rdma[0x1];
1998 	u8         reserved_at_572[0x7];
1999 	u8         adv_virtualization[0x1];
2000 	u8         reserved_at_57a[0x6];
2001 
2002 	u8	   reserved_at_580[0xb];
2003 	u8	   log_max_dci_stream_channels[0x5];
2004 	u8	   reserved_at_590[0x3];
2005 	u8	   log_max_dci_errored_streams[0x5];
2006 	u8	   reserved_at_598[0x8];
2007 
2008 	u8         reserved_at_5a0[0x10];
2009 	u8         enhanced_cqe_compression[0x1];
2010 	u8         reserved_at_5b1[0x1];
2011 	u8         crossing_vhca_mkey[0x1];
2012 	u8         log_max_dek[0x5];
2013 	u8         reserved_at_5b8[0x4];
2014 	u8         mini_cqe_resp_stride_index[0x1];
2015 	u8         cqe_128_always[0x1];
2016 	u8         cqe_compression_128[0x1];
2017 	u8         cqe_compression[0x1];
2018 
2019 	u8         cqe_compression_timeout[0x10];
2020 	u8         cqe_compression_max_num[0x10];
2021 
2022 	u8         reserved_at_5e0[0x8];
2023 	u8         flex_parser_id_gtpu_dw_0[0x4];
2024 	u8         reserved_at_5ec[0x4];
2025 	u8         tag_matching[0x1];
2026 	u8         rndv_offload_rc[0x1];
2027 	u8         rndv_offload_dc[0x1];
2028 	u8         log_tag_matching_list_sz[0x5];
2029 	u8         reserved_at_5f8[0x3];
2030 	u8         log_max_xrq[0x5];
2031 
2032 	u8	   affiliate_nic_vport_criteria[0x8];
2033 	u8	   native_port_num[0x8];
2034 	u8	   num_vhca_ports[0x8];
2035 	u8         flex_parser_id_gtpu_teid[0x4];
2036 	u8         reserved_at_61c[0x2];
2037 	u8	   sw_owner_id[0x1];
2038 	u8         reserved_at_61f[0x1];
2039 
2040 	u8         max_num_of_monitor_counters[0x10];
2041 	u8         num_ppcnt_monitor_counters[0x10];
2042 
2043 	u8         max_num_sf[0x10];
2044 	u8         num_q_monitor_counters[0x10];
2045 
2046 	u8         reserved_at_660[0x20];
2047 
2048 	u8         sf[0x1];
2049 	u8         sf_set_partition[0x1];
2050 	u8         reserved_at_682[0x1];
2051 	u8         log_max_sf[0x5];
2052 	u8         apu[0x1];
2053 	u8         reserved_at_689[0x4];
2054 	u8         migration[0x1];
2055 	u8         reserved_at_68e[0x2];
2056 	u8         log_min_sf_size[0x8];
2057 	u8         max_num_sf_partitions[0x8];
2058 
2059 	u8         uctx_cap[0x20];
2060 
2061 	u8         reserved_at_6c0[0x4];
2062 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2063 	u8         flex_parser_id_icmp_dw1[0x4];
2064 	u8         flex_parser_id_icmp_dw0[0x4];
2065 	u8         flex_parser_id_icmpv6_dw1[0x4];
2066 	u8         flex_parser_id_icmpv6_dw0[0x4];
2067 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2068 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2069 
2070 	u8         max_num_match_definer[0x10];
2071 	u8	   sf_base_id[0x10];
2072 
2073 	u8         flex_parser_id_gtpu_dw_2[0x4];
2074 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2075 	u8	   num_total_dynamic_vf_msix[0x18];
2076 	u8	   reserved_at_720[0x14];
2077 	u8	   dynamic_msix_table_size[0xc];
2078 	u8	   reserved_at_740[0xc];
2079 	u8	   min_dynamic_vf_msix_table_size[0x4];
2080 	u8	   reserved_at_750[0x2];
2081 	u8	   data_direct[0x1];
2082 	u8	   reserved_at_753[0x1];
2083 	u8	   max_dynamic_vf_msix_table_size[0xc];
2084 
2085 	u8         reserved_at_760[0x3];
2086 	u8         log_max_num_header_modify_argument[0x5];
2087 	u8         log_header_modify_argument_granularity_offset[0x4];
2088 	u8         log_header_modify_argument_granularity[0x4];
2089 	u8         reserved_at_770[0x3];
2090 	u8         log_header_modify_argument_max_alloc[0x5];
2091 	u8         reserved_at_778[0x8];
2092 
2093 	u8	   vhca_tunnel_commands[0x40];
2094 	u8         match_definer_format_supported[0x40];
2095 };
2096 
2097 enum {
2098 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2099 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2100 };
2101 
2102 enum {
2103 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2104 };
2105 
2106 struct mlx5_ifc_cmd_hca_cap_2_bits {
2107 	u8	   reserved_at_0[0x80];
2108 
2109 	u8         migratable[0x1];
2110 	u8         reserved_at_81[0x7];
2111 	u8         dp_ordering_force[0x1];
2112 	u8         reserved_at_89[0x9];
2113 	u8         query_vuid[0x1];
2114 	u8         reserved_at_93[0x5];
2115 	u8         umr_log_entity_size_5[0x1];
2116 	u8         reserved_at_99[0x7];
2117 
2118 	u8	   max_reformat_insert_size[0x8];
2119 	u8	   max_reformat_insert_offset[0x8];
2120 	u8	   max_reformat_remove_size[0x8];
2121 	u8	   max_reformat_remove_offset[0x8];
2122 
2123 	u8	   reserved_at_c0[0x8];
2124 	u8	   migration_multi_load[0x1];
2125 	u8	   migration_tracking_state[0x1];
2126 	u8	   multiplane_qp_ud[0x1];
2127 	u8	   reserved_at_cb[0x5];
2128 	u8	   migration_in_chunks[0x1];
2129 	u8	   reserved_at_d1[0x1];
2130 	u8	   sf_eq_usage[0x1];
2131 	u8	   reserved_at_d3[0x5];
2132 	u8	   multiplane[0x1];
2133 	u8	   reserved_at_d9[0x7];
2134 
2135 	u8	   cross_vhca_object_to_object_supported[0x20];
2136 
2137 	u8	   allowed_object_for_other_vhca_access[0x40];
2138 
2139 	u8	   reserved_at_140[0x60];
2140 
2141 	u8	   flow_table_type_2_type[0x8];
2142 	u8	   reserved_at_1a8[0x2];
2143 	u8         format_select_dw_8_6_ext[0x1];
2144 	u8	   log_min_mkey_entity_size[0x5];
2145 	u8	   reserved_at_1b0[0x10];
2146 
2147 	u8	   general_obj_types_127_64[0x40];
2148 	u8	   reserved_at_200[0x20];
2149 
2150 	u8	   reserved_at_220[0x1];
2151 	u8	   sw_vhca_id_valid[0x1];
2152 	u8	   sw_vhca_id[0xe];
2153 	u8	   reserved_at_230[0x10];
2154 
2155 	u8	   reserved_at_240[0xb];
2156 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2157 	u8	   reserved_at_250[0x10];
2158 
2159 	u8	   reserved_at_260[0x20];
2160 
2161 	u8	   format_select_dw_gtpu_dw_0[0x8];
2162 	u8	   format_select_dw_gtpu_dw_1[0x8];
2163 	u8	   format_select_dw_gtpu_dw_2[0x8];
2164 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2165 
2166 	u8	   generate_wqe_type[0x20];
2167 
2168 	u8	   reserved_at_2c0[0xc0];
2169 
2170 	u8	   reserved_at_380[0xb];
2171 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2172 	u8	   ec_vf_vport_base[0x10];
2173 
2174 	u8	   reserved_at_3a0[0xa];
2175 	u8	   max_mkey_log_entity_size_mtt[0x6];
2176 	u8	   max_rqt_vhca_id[0x10];
2177 
2178 	u8	   reserved_at_3c0[0x20];
2179 
2180 	u8	   reserved_at_3e0[0x10];
2181 	u8	   pcc_ifa2[0x1];
2182 	u8	   reserved_at_3f1[0xf];
2183 
2184 	u8	   reserved_at_400[0x1];
2185 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2186 	u8	   reserved_at_402[0xe];
2187 	u8	   return_reg_id[0x10];
2188 
2189 	u8	   reserved_at_420[0x1c];
2190 	u8	   flow_table_hash_type[0x4];
2191 
2192 	u8	   reserved_at_440[0x8];
2193 	u8	   max_num_eqs_24b[0x18];
2194 	u8	   reserved_at_460[0x3a0];
2195 };
2196 
2197 enum mlx5_ifc_flow_destination_type {
2198 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2199 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2200 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2201 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2202 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2203 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2204 };
2205 
2206 enum mlx5_flow_table_miss_action {
2207 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2208 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2209 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2210 };
2211 
2212 struct mlx5_ifc_dest_format_struct_bits {
2213 	u8         destination_type[0x8];
2214 	u8         destination_id[0x18];
2215 
2216 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2217 	u8         packet_reformat[0x1];
2218 	u8         reserved_at_22[0x6];
2219 	u8         destination_table_type[0x8];
2220 	u8         destination_eswitch_owner_vhca_id[0x10];
2221 };
2222 
2223 struct mlx5_ifc_flow_counter_list_bits {
2224 	u8         flow_counter_id[0x20];
2225 
2226 	u8         reserved_at_20[0x20];
2227 };
2228 
2229 struct mlx5_ifc_extended_dest_format_bits {
2230 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2231 
2232 	u8         packet_reformat_id[0x20];
2233 
2234 	u8         reserved_at_60[0x20];
2235 };
2236 
2237 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2238 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2239 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2240 };
2241 
2242 struct mlx5_ifc_fte_match_param_bits {
2243 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2244 
2245 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2246 
2247 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2248 
2249 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2250 
2251 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2252 
2253 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2254 
2255 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2256 
2257 	u8         reserved_at_e00[0x200];
2258 };
2259 
2260 enum {
2261 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2262 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2263 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2264 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2265 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2266 };
2267 
2268 struct mlx5_ifc_rx_hash_field_select_bits {
2269 	u8         l3_prot_type[0x1];
2270 	u8         l4_prot_type[0x1];
2271 	u8         selected_fields[0x1e];
2272 };
2273 
2274 enum {
2275 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2276 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2277 };
2278 
2279 enum {
2280 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2281 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2282 };
2283 
2284 struct mlx5_ifc_wq_bits {
2285 	u8         wq_type[0x4];
2286 	u8         wq_signature[0x1];
2287 	u8         end_padding_mode[0x2];
2288 	u8         cd_slave[0x1];
2289 	u8         reserved_at_8[0x18];
2290 
2291 	u8         hds_skip_first_sge[0x1];
2292 	u8         log2_hds_buf_size[0x3];
2293 	u8         reserved_at_24[0x7];
2294 	u8         page_offset[0x5];
2295 	u8         lwm[0x10];
2296 
2297 	u8         reserved_at_40[0x8];
2298 	u8         pd[0x18];
2299 
2300 	u8         reserved_at_60[0x8];
2301 	u8         uar_page[0x18];
2302 
2303 	u8         dbr_addr[0x40];
2304 
2305 	u8         hw_counter[0x20];
2306 
2307 	u8         sw_counter[0x20];
2308 
2309 	u8         reserved_at_100[0xc];
2310 	u8         log_wq_stride[0x4];
2311 	u8         reserved_at_110[0x3];
2312 	u8         log_wq_pg_sz[0x5];
2313 	u8         reserved_at_118[0x3];
2314 	u8         log_wq_sz[0x5];
2315 
2316 	u8         dbr_umem_valid[0x1];
2317 	u8         wq_umem_valid[0x1];
2318 	u8         reserved_at_122[0x1];
2319 	u8         log_hairpin_num_packets[0x5];
2320 	u8         reserved_at_128[0x3];
2321 	u8         log_hairpin_data_sz[0x5];
2322 
2323 	u8         reserved_at_130[0x4];
2324 	u8         log_wqe_num_of_strides[0x4];
2325 	u8         two_byte_shift_en[0x1];
2326 	u8         reserved_at_139[0x4];
2327 	u8         log_wqe_stride_size[0x3];
2328 
2329 	u8         dbr_umem_id[0x20];
2330 	u8         wq_umem_id[0x20];
2331 
2332 	u8         wq_umem_offset[0x40];
2333 
2334 	u8         headers_mkey[0x20];
2335 
2336 	u8         shampo_enable[0x1];
2337 	u8         reserved_at_1e1[0x1];
2338 	u8         shampo_mode[0x2];
2339 	u8         reserved_at_1e4[0x1];
2340 	u8         log_reservation_size[0x3];
2341 	u8         reserved_at_1e8[0x5];
2342 	u8         log_max_num_of_packets_per_reservation[0x3];
2343 	u8         reserved_at_1f0[0x6];
2344 	u8         log_headers_entry_size[0x2];
2345 	u8         reserved_at_1f8[0x4];
2346 	u8         log_headers_buffer_entry_num[0x4];
2347 
2348 	u8         reserved_at_200[0x400];
2349 
2350 	struct mlx5_ifc_cmd_pas_bits pas[];
2351 };
2352 
2353 struct mlx5_ifc_rq_num_bits {
2354 	u8         reserved_at_0[0x8];
2355 	u8         rq_num[0x18];
2356 };
2357 
2358 struct mlx5_ifc_rq_vhca_bits {
2359 	u8         reserved_at_0[0x8];
2360 	u8         rq_num[0x18];
2361 	u8         reserved_at_20[0x10];
2362 	u8         rq_vhca_id[0x10];
2363 };
2364 
2365 struct mlx5_ifc_mac_address_layout_bits {
2366 	u8         reserved_at_0[0x10];
2367 	u8         mac_addr_47_32[0x10];
2368 
2369 	u8         mac_addr_31_0[0x20];
2370 };
2371 
2372 struct mlx5_ifc_vlan_layout_bits {
2373 	u8         reserved_at_0[0x14];
2374 	u8         vlan[0x0c];
2375 
2376 	u8         reserved_at_20[0x20];
2377 };
2378 
2379 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2380 	u8         reserved_at_0[0xa0];
2381 
2382 	u8         min_time_between_cnps[0x20];
2383 
2384 	u8         reserved_at_c0[0x12];
2385 	u8         cnp_dscp[0x6];
2386 	u8         reserved_at_d8[0x4];
2387 	u8         cnp_prio_mode[0x1];
2388 	u8         cnp_802p_prio[0x3];
2389 
2390 	u8         reserved_at_e0[0x720];
2391 };
2392 
2393 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2394 	u8         reserved_at_0[0x60];
2395 
2396 	u8         reserved_at_60[0x4];
2397 	u8         clamp_tgt_rate[0x1];
2398 	u8         reserved_at_65[0x3];
2399 	u8         clamp_tgt_rate_after_time_inc[0x1];
2400 	u8         reserved_at_69[0x17];
2401 
2402 	u8         reserved_at_80[0x20];
2403 
2404 	u8         rpg_time_reset[0x20];
2405 
2406 	u8         rpg_byte_reset[0x20];
2407 
2408 	u8         rpg_threshold[0x20];
2409 
2410 	u8         rpg_max_rate[0x20];
2411 
2412 	u8         rpg_ai_rate[0x20];
2413 
2414 	u8         rpg_hai_rate[0x20];
2415 
2416 	u8         rpg_gd[0x20];
2417 
2418 	u8         rpg_min_dec_fac[0x20];
2419 
2420 	u8         rpg_min_rate[0x20];
2421 
2422 	u8         reserved_at_1c0[0xe0];
2423 
2424 	u8         rate_to_set_on_first_cnp[0x20];
2425 
2426 	u8         dce_tcp_g[0x20];
2427 
2428 	u8         dce_tcp_rtt[0x20];
2429 
2430 	u8         rate_reduce_monitor_period[0x20];
2431 
2432 	u8         reserved_at_320[0x20];
2433 
2434 	u8         initial_alpha_value[0x20];
2435 
2436 	u8         reserved_at_360[0x4a0];
2437 };
2438 
2439 struct mlx5_ifc_cong_control_r_roce_general_bits {
2440 	u8         reserved_at_0[0x80];
2441 
2442 	u8         reserved_at_80[0x10];
2443 	u8         rtt_resp_dscp_valid[0x1];
2444 	u8         reserved_at_91[0x9];
2445 	u8         rtt_resp_dscp[0x6];
2446 
2447 	u8         reserved_at_a0[0x760];
2448 };
2449 
2450 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2451 	u8         reserved_at_0[0x80];
2452 
2453 	u8         rppp_max_rps[0x20];
2454 
2455 	u8         rpg_time_reset[0x20];
2456 
2457 	u8         rpg_byte_reset[0x20];
2458 
2459 	u8         rpg_threshold[0x20];
2460 
2461 	u8         rpg_max_rate[0x20];
2462 
2463 	u8         rpg_ai_rate[0x20];
2464 
2465 	u8         rpg_hai_rate[0x20];
2466 
2467 	u8         rpg_gd[0x20];
2468 
2469 	u8         rpg_min_dec_fac[0x20];
2470 
2471 	u8         rpg_min_rate[0x20];
2472 
2473 	u8         reserved_at_1c0[0x640];
2474 };
2475 
2476 enum {
2477 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2478 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2479 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2480 };
2481 
2482 struct mlx5_ifc_resize_field_select_bits {
2483 	u8         resize_field_select[0x20];
2484 };
2485 
2486 struct mlx5_ifc_resource_dump_bits {
2487 	u8         more_dump[0x1];
2488 	u8         inline_dump[0x1];
2489 	u8         reserved_at_2[0xa];
2490 	u8         seq_num[0x4];
2491 	u8         segment_type[0x10];
2492 
2493 	u8         reserved_at_20[0x10];
2494 	u8         vhca_id[0x10];
2495 
2496 	u8         index1[0x20];
2497 
2498 	u8         index2[0x20];
2499 
2500 	u8         num_of_obj1[0x10];
2501 	u8         num_of_obj2[0x10];
2502 
2503 	u8         reserved_at_a0[0x20];
2504 
2505 	u8         device_opaque[0x40];
2506 
2507 	u8         mkey[0x20];
2508 
2509 	u8         size[0x20];
2510 
2511 	u8         address[0x40];
2512 
2513 	u8         inline_data[52][0x20];
2514 };
2515 
2516 struct mlx5_ifc_resource_dump_menu_record_bits {
2517 	u8         reserved_at_0[0x4];
2518 	u8         num_of_obj2_supports_active[0x1];
2519 	u8         num_of_obj2_supports_all[0x1];
2520 	u8         must_have_num_of_obj2[0x1];
2521 	u8         support_num_of_obj2[0x1];
2522 	u8         num_of_obj1_supports_active[0x1];
2523 	u8         num_of_obj1_supports_all[0x1];
2524 	u8         must_have_num_of_obj1[0x1];
2525 	u8         support_num_of_obj1[0x1];
2526 	u8         must_have_index2[0x1];
2527 	u8         support_index2[0x1];
2528 	u8         must_have_index1[0x1];
2529 	u8         support_index1[0x1];
2530 	u8         segment_type[0x10];
2531 
2532 	u8         segment_name[4][0x20];
2533 
2534 	u8         index1_name[4][0x20];
2535 
2536 	u8         index2_name[4][0x20];
2537 };
2538 
2539 struct mlx5_ifc_resource_dump_segment_header_bits {
2540 	u8         length_dw[0x10];
2541 	u8         segment_type[0x10];
2542 };
2543 
2544 struct mlx5_ifc_resource_dump_command_segment_bits {
2545 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2546 
2547 	u8         segment_called[0x10];
2548 	u8         vhca_id[0x10];
2549 
2550 	u8         index1[0x20];
2551 
2552 	u8         index2[0x20];
2553 
2554 	u8         num_of_obj1[0x10];
2555 	u8         num_of_obj2[0x10];
2556 };
2557 
2558 struct mlx5_ifc_resource_dump_error_segment_bits {
2559 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2560 
2561 	u8         reserved_at_20[0x10];
2562 	u8         syndrome_id[0x10];
2563 
2564 	u8         reserved_at_40[0x40];
2565 
2566 	u8         error[8][0x20];
2567 };
2568 
2569 struct mlx5_ifc_resource_dump_info_segment_bits {
2570 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2571 
2572 	u8         reserved_at_20[0x18];
2573 	u8         dump_version[0x8];
2574 
2575 	u8         hw_version[0x20];
2576 
2577 	u8         fw_version[0x20];
2578 };
2579 
2580 struct mlx5_ifc_resource_dump_menu_segment_bits {
2581 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2582 
2583 	u8         reserved_at_20[0x10];
2584 	u8         num_of_records[0x10];
2585 
2586 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2587 };
2588 
2589 struct mlx5_ifc_resource_dump_resource_segment_bits {
2590 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2591 
2592 	u8         reserved_at_20[0x20];
2593 
2594 	u8         index1[0x20];
2595 
2596 	u8         index2[0x20];
2597 
2598 	u8         payload[][0x20];
2599 };
2600 
2601 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2602 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2603 };
2604 
2605 struct mlx5_ifc_menu_resource_dump_response_bits {
2606 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2607 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2608 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2609 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2610 };
2611 
2612 enum {
2613 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2614 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2615 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2616 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2617 };
2618 
2619 struct mlx5_ifc_modify_field_select_bits {
2620 	u8         modify_field_select[0x20];
2621 };
2622 
2623 struct mlx5_ifc_field_select_r_roce_np_bits {
2624 	u8         field_select_r_roce_np[0x20];
2625 };
2626 
2627 struct mlx5_ifc_field_select_r_roce_rp_bits {
2628 	u8         field_select_r_roce_rp[0x20];
2629 };
2630 
2631 enum {
2632 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2633 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2634 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2635 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2636 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2637 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2638 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2639 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2640 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2641 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2642 };
2643 
2644 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2645 	u8         field_select_8021qaurp[0x20];
2646 };
2647 
2648 struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2649 	u8         total_successful_recovery_events[0x20];
2650 
2651 	u8         reserved_at_20[0x7a0];
2652 };
2653 
2654 struct mlx5_ifc_phys_layer_cntrs_bits {
2655 	u8         time_since_last_clear_high[0x20];
2656 
2657 	u8         time_since_last_clear_low[0x20];
2658 
2659 	u8         symbol_errors_high[0x20];
2660 
2661 	u8         symbol_errors_low[0x20];
2662 
2663 	u8         sync_headers_errors_high[0x20];
2664 
2665 	u8         sync_headers_errors_low[0x20];
2666 
2667 	u8         edpl_bip_errors_lane0_high[0x20];
2668 
2669 	u8         edpl_bip_errors_lane0_low[0x20];
2670 
2671 	u8         edpl_bip_errors_lane1_high[0x20];
2672 
2673 	u8         edpl_bip_errors_lane1_low[0x20];
2674 
2675 	u8         edpl_bip_errors_lane2_high[0x20];
2676 
2677 	u8         edpl_bip_errors_lane2_low[0x20];
2678 
2679 	u8         edpl_bip_errors_lane3_high[0x20];
2680 
2681 	u8         edpl_bip_errors_lane3_low[0x20];
2682 
2683 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2684 
2685 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2686 
2687 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2688 
2689 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2690 
2691 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2692 
2693 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2694 
2695 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2696 
2697 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2698 
2699 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2700 
2701 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2702 
2703 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2704 
2705 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2706 
2707 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2708 
2709 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2710 
2711 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2712 
2713 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2714 
2715 	u8         rs_fec_corrected_blocks_high[0x20];
2716 
2717 	u8         rs_fec_corrected_blocks_low[0x20];
2718 
2719 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2720 
2721 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2722 
2723 	u8         rs_fec_no_errors_blocks_high[0x20];
2724 
2725 	u8         rs_fec_no_errors_blocks_low[0x20];
2726 
2727 	u8         rs_fec_single_error_blocks_high[0x20];
2728 
2729 	u8         rs_fec_single_error_blocks_low[0x20];
2730 
2731 	u8         rs_fec_corrected_symbols_total_high[0x20];
2732 
2733 	u8         rs_fec_corrected_symbols_total_low[0x20];
2734 
2735 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2736 
2737 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2738 
2739 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2740 
2741 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2742 
2743 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2744 
2745 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2746 
2747 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2748 
2749 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2750 
2751 	u8         link_down_events[0x20];
2752 
2753 	u8         successful_recovery_events[0x20];
2754 
2755 	u8         reserved_at_640[0x180];
2756 };
2757 
2758 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2759 	u8         time_since_last_clear_high[0x20];
2760 
2761 	u8         time_since_last_clear_low[0x20];
2762 
2763 	u8         phy_received_bits_high[0x20];
2764 
2765 	u8         phy_received_bits_low[0x20];
2766 
2767 	u8         phy_symbol_errors_high[0x20];
2768 
2769 	u8         phy_symbol_errors_low[0x20];
2770 
2771 	u8         phy_corrected_bits_high[0x20];
2772 
2773 	u8         phy_corrected_bits_low[0x20];
2774 
2775 	u8         phy_corrected_bits_lane0_high[0x20];
2776 
2777 	u8         phy_corrected_bits_lane0_low[0x20];
2778 
2779 	u8         phy_corrected_bits_lane1_high[0x20];
2780 
2781 	u8         phy_corrected_bits_lane1_low[0x20];
2782 
2783 	u8         phy_corrected_bits_lane2_high[0x20];
2784 
2785 	u8         phy_corrected_bits_lane2_low[0x20];
2786 
2787 	u8         phy_corrected_bits_lane3_high[0x20];
2788 
2789 	u8         phy_corrected_bits_lane3_low[0x20];
2790 
2791 	u8         reserved_at_200[0x5c0];
2792 };
2793 
2794 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2795 	u8	   symbol_error_counter[0x10];
2796 
2797 	u8         link_error_recovery_counter[0x8];
2798 
2799 	u8         link_downed_counter[0x8];
2800 
2801 	u8         port_rcv_errors[0x10];
2802 
2803 	u8         port_rcv_remote_physical_errors[0x10];
2804 
2805 	u8         port_rcv_switch_relay_errors[0x10];
2806 
2807 	u8         port_xmit_discards[0x10];
2808 
2809 	u8         port_xmit_constraint_errors[0x8];
2810 
2811 	u8         port_rcv_constraint_errors[0x8];
2812 
2813 	u8         reserved_at_70[0x8];
2814 
2815 	u8         link_overrun_errors[0x8];
2816 
2817 	u8	   reserved_at_80[0x10];
2818 
2819 	u8         vl_15_dropped[0x10];
2820 
2821 	u8	   reserved_at_a0[0x80];
2822 
2823 	u8         port_xmit_wait[0x20];
2824 };
2825 
2826 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2827 	u8         reserved_at_0[0x300];
2828 
2829 	u8         port_xmit_data_high[0x20];
2830 
2831 	u8         port_xmit_data_low[0x20];
2832 
2833 	u8         port_rcv_data_high[0x20];
2834 
2835 	u8         port_rcv_data_low[0x20];
2836 
2837 	u8         port_xmit_pkts_high[0x20];
2838 
2839 	u8         port_xmit_pkts_low[0x20];
2840 
2841 	u8         port_rcv_pkts_high[0x20];
2842 
2843 	u8         port_rcv_pkts_low[0x20];
2844 
2845 	u8         reserved_at_400[0x80];
2846 
2847 	u8         port_unicast_xmit_pkts_high[0x20];
2848 
2849 	u8         port_unicast_xmit_pkts_low[0x20];
2850 
2851 	u8         port_multicast_xmit_pkts_high[0x20];
2852 
2853 	u8         port_multicast_xmit_pkts_low[0x20];
2854 
2855 	u8         port_unicast_rcv_pkts_high[0x20];
2856 
2857 	u8         port_unicast_rcv_pkts_low[0x20];
2858 
2859 	u8         port_multicast_rcv_pkts_high[0x20];
2860 
2861 	u8         port_multicast_rcv_pkts_low[0x20];
2862 
2863 	u8         reserved_at_580[0x240];
2864 };
2865 
2866 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2867 	u8         transmit_queue_high[0x20];
2868 
2869 	u8         transmit_queue_low[0x20];
2870 
2871 	u8         no_buffer_discard_uc_high[0x20];
2872 
2873 	u8         no_buffer_discard_uc_low[0x20];
2874 
2875 	u8         reserved_at_80[0x740];
2876 };
2877 
2878 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2879 	u8         wred_discard_high[0x20];
2880 
2881 	u8         wred_discard_low[0x20];
2882 
2883 	u8         ecn_marked_tc_high[0x20];
2884 
2885 	u8         ecn_marked_tc_low[0x20];
2886 
2887 	u8         reserved_at_80[0x740];
2888 };
2889 
2890 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2891 	u8         rx_octets_high[0x20];
2892 
2893 	u8         rx_octets_low[0x20];
2894 
2895 	u8         reserved_at_40[0xc0];
2896 
2897 	u8         rx_frames_high[0x20];
2898 
2899 	u8         rx_frames_low[0x20];
2900 
2901 	u8         tx_octets_high[0x20];
2902 
2903 	u8         tx_octets_low[0x20];
2904 
2905 	u8         reserved_at_180[0xc0];
2906 
2907 	u8         tx_frames_high[0x20];
2908 
2909 	u8         tx_frames_low[0x20];
2910 
2911 	u8         rx_pause_high[0x20];
2912 
2913 	u8         rx_pause_low[0x20];
2914 
2915 	u8         rx_pause_duration_high[0x20];
2916 
2917 	u8         rx_pause_duration_low[0x20];
2918 
2919 	u8         tx_pause_high[0x20];
2920 
2921 	u8         tx_pause_low[0x20];
2922 
2923 	u8         tx_pause_duration_high[0x20];
2924 
2925 	u8         tx_pause_duration_low[0x20];
2926 
2927 	u8         rx_pause_transition_high[0x20];
2928 
2929 	u8         rx_pause_transition_low[0x20];
2930 
2931 	u8         rx_discards_high[0x20];
2932 
2933 	u8         rx_discards_low[0x20];
2934 
2935 	u8         device_stall_minor_watermark_cnt_high[0x20];
2936 
2937 	u8         device_stall_minor_watermark_cnt_low[0x20];
2938 
2939 	u8         device_stall_critical_watermark_cnt_high[0x20];
2940 
2941 	u8         device_stall_critical_watermark_cnt_low[0x20];
2942 
2943 	u8         reserved_at_480[0x340];
2944 };
2945 
2946 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2947 	u8         port_transmit_wait_high[0x20];
2948 
2949 	u8         port_transmit_wait_low[0x20];
2950 
2951 	u8         reserved_at_40[0x100];
2952 
2953 	u8         rx_buffer_almost_full_high[0x20];
2954 
2955 	u8         rx_buffer_almost_full_low[0x20];
2956 
2957 	u8         rx_buffer_full_high[0x20];
2958 
2959 	u8         rx_buffer_full_low[0x20];
2960 
2961 	u8         rx_icrc_encapsulated_high[0x20];
2962 
2963 	u8         rx_icrc_encapsulated_low[0x20];
2964 
2965 	u8         reserved_at_200[0x5c0];
2966 };
2967 
2968 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2969 	u8         dot3stats_alignment_errors_high[0x20];
2970 
2971 	u8         dot3stats_alignment_errors_low[0x20];
2972 
2973 	u8         dot3stats_fcs_errors_high[0x20];
2974 
2975 	u8         dot3stats_fcs_errors_low[0x20];
2976 
2977 	u8         dot3stats_single_collision_frames_high[0x20];
2978 
2979 	u8         dot3stats_single_collision_frames_low[0x20];
2980 
2981 	u8         dot3stats_multiple_collision_frames_high[0x20];
2982 
2983 	u8         dot3stats_multiple_collision_frames_low[0x20];
2984 
2985 	u8         dot3stats_sqe_test_errors_high[0x20];
2986 
2987 	u8         dot3stats_sqe_test_errors_low[0x20];
2988 
2989 	u8         dot3stats_deferred_transmissions_high[0x20];
2990 
2991 	u8         dot3stats_deferred_transmissions_low[0x20];
2992 
2993 	u8         dot3stats_late_collisions_high[0x20];
2994 
2995 	u8         dot3stats_late_collisions_low[0x20];
2996 
2997 	u8         dot3stats_excessive_collisions_high[0x20];
2998 
2999 	u8         dot3stats_excessive_collisions_low[0x20];
3000 
3001 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
3002 
3003 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
3004 
3005 	u8         dot3stats_carrier_sense_errors_high[0x20];
3006 
3007 	u8         dot3stats_carrier_sense_errors_low[0x20];
3008 
3009 	u8         dot3stats_frame_too_longs_high[0x20];
3010 
3011 	u8         dot3stats_frame_too_longs_low[0x20];
3012 
3013 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3014 
3015 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3016 
3017 	u8         dot3stats_symbol_errors_high[0x20];
3018 
3019 	u8         dot3stats_symbol_errors_low[0x20];
3020 
3021 	u8         dot3control_in_unknown_opcodes_high[0x20];
3022 
3023 	u8         dot3control_in_unknown_opcodes_low[0x20];
3024 
3025 	u8         dot3in_pause_frames_high[0x20];
3026 
3027 	u8         dot3in_pause_frames_low[0x20];
3028 
3029 	u8         dot3out_pause_frames_high[0x20];
3030 
3031 	u8         dot3out_pause_frames_low[0x20];
3032 
3033 	u8         reserved_at_400[0x3c0];
3034 };
3035 
3036 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3037 	u8         ether_stats_drop_events_high[0x20];
3038 
3039 	u8         ether_stats_drop_events_low[0x20];
3040 
3041 	u8         ether_stats_octets_high[0x20];
3042 
3043 	u8         ether_stats_octets_low[0x20];
3044 
3045 	u8         ether_stats_pkts_high[0x20];
3046 
3047 	u8         ether_stats_pkts_low[0x20];
3048 
3049 	u8         ether_stats_broadcast_pkts_high[0x20];
3050 
3051 	u8         ether_stats_broadcast_pkts_low[0x20];
3052 
3053 	u8         ether_stats_multicast_pkts_high[0x20];
3054 
3055 	u8         ether_stats_multicast_pkts_low[0x20];
3056 
3057 	u8         ether_stats_crc_align_errors_high[0x20];
3058 
3059 	u8         ether_stats_crc_align_errors_low[0x20];
3060 
3061 	u8         ether_stats_undersize_pkts_high[0x20];
3062 
3063 	u8         ether_stats_undersize_pkts_low[0x20];
3064 
3065 	u8         ether_stats_oversize_pkts_high[0x20];
3066 
3067 	u8         ether_stats_oversize_pkts_low[0x20];
3068 
3069 	u8         ether_stats_fragments_high[0x20];
3070 
3071 	u8         ether_stats_fragments_low[0x20];
3072 
3073 	u8         ether_stats_jabbers_high[0x20];
3074 
3075 	u8         ether_stats_jabbers_low[0x20];
3076 
3077 	u8         ether_stats_collisions_high[0x20];
3078 
3079 	u8         ether_stats_collisions_low[0x20];
3080 
3081 	u8         ether_stats_pkts64octets_high[0x20];
3082 
3083 	u8         ether_stats_pkts64octets_low[0x20];
3084 
3085 	u8         ether_stats_pkts65to127octets_high[0x20];
3086 
3087 	u8         ether_stats_pkts65to127octets_low[0x20];
3088 
3089 	u8         ether_stats_pkts128to255octets_high[0x20];
3090 
3091 	u8         ether_stats_pkts128to255octets_low[0x20];
3092 
3093 	u8         ether_stats_pkts256to511octets_high[0x20];
3094 
3095 	u8         ether_stats_pkts256to511octets_low[0x20];
3096 
3097 	u8         ether_stats_pkts512to1023octets_high[0x20];
3098 
3099 	u8         ether_stats_pkts512to1023octets_low[0x20];
3100 
3101 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3102 
3103 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3104 
3105 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3106 
3107 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3108 
3109 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3110 
3111 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3112 
3113 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3114 
3115 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3116 
3117 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3118 
3119 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3120 
3121 	u8         reserved_at_540[0x280];
3122 };
3123 
3124 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3125 	u8         if_in_octets_high[0x20];
3126 
3127 	u8         if_in_octets_low[0x20];
3128 
3129 	u8         if_in_ucast_pkts_high[0x20];
3130 
3131 	u8         if_in_ucast_pkts_low[0x20];
3132 
3133 	u8         if_in_discards_high[0x20];
3134 
3135 	u8         if_in_discards_low[0x20];
3136 
3137 	u8         if_in_errors_high[0x20];
3138 
3139 	u8         if_in_errors_low[0x20];
3140 
3141 	u8         if_in_unknown_protos_high[0x20];
3142 
3143 	u8         if_in_unknown_protos_low[0x20];
3144 
3145 	u8         if_out_octets_high[0x20];
3146 
3147 	u8         if_out_octets_low[0x20];
3148 
3149 	u8         if_out_ucast_pkts_high[0x20];
3150 
3151 	u8         if_out_ucast_pkts_low[0x20];
3152 
3153 	u8         if_out_discards_high[0x20];
3154 
3155 	u8         if_out_discards_low[0x20];
3156 
3157 	u8         if_out_errors_high[0x20];
3158 
3159 	u8         if_out_errors_low[0x20];
3160 
3161 	u8         if_in_multicast_pkts_high[0x20];
3162 
3163 	u8         if_in_multicast_pkts_low[0x20];
3164 
3165 	u8         if_in_broadcast_pkts_high[0x20];
3166 
3167 	u8         if_in_broadcast_pkts_low[0x20];
3168 
3169 	u8         if_out_multicast_pkts_high[0x20];
3170 
3171 	u8         if_out_multicast_pkts_low[0x20];
3172 
3173 	u8         if_out_broadcast_pkts_high[0x20];
3174 
3175 	u8         if_out_broadcast_pkts_low[0x20];
3176 
3177 	u8         reserved_at_340[0x480];
3178 };
3179 
3180 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3181 	u8         a_frames_transmitted_ok_high[0x20];
3182 
3183 	u8         a_frames_transmitted_ok_low[0x20];
3184 
3185 	u8         a_frames_received_ok_high[0x20];
3186 
3187 	u8         a_frames_received_ok_low[0x20];
3188 
3189 	u8         a_frame_check_sequence_errors_high[0x20];
3190 
3191 	u8         a_frame_check_sequence_errors_low[0x20];
3192 
3193 	u8         a_alignment_errors_high[0x20];
3194 
3195 	u8         a_alignment_errors_low[0x20];
3196 
3197 	u8         a_octets_transmitted_ok_high[0x20];
3198 
3199 	u8         a_octets_transmitted_ok_low[0x20];
3200 
3201 	u8         a_octets_received_ok_high[0x20];
3202 
3203 	u8         a_octets_received_ok_low[0x20];
3204 
3205 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3206 
3207 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3208 
3209 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3210 
3211 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3212 
3213 	u8         a_multicast_frames_received_ok_high[0x20];
3214 
3215 	u8         a_multicast_frames_received_ok_low[0x20];
3216 
3217 	u8         a_broadcast_frames_received_ok_high[0x20];
3218 
3219 	u8         a_broadcast_frames_received_ok_low[0x20];
3220 
3221 	u8         a_in_range_length_errors_high[0x20];
3222 
3223 	u8         a_in_range_length_errors_low[0x20];
3224 
3225 	u8         a_out_of_range_length_field_high[0x20];
3226 
3227 	u8         a_out_of_range_length_field_low[0x20];
3228 
3229 	u8         a_frame_too_long_errors_high[0x20];
3230 
3231 	u8         a_frame_too_long_errors_low[0x20];
3232 
3233 	u8         a_symbol_error_during_carrier_high[0x20];
3234 
3235 	u8         a_symbol_error_during_carrier_low[0x20];
3236 
3237 	u8         a_mac_control_frames_transmitted_high[0x20];
3238 
3239 	u8         a_mac_control_frames_transmitted_low[0x20];
3240 
3241 	u8         a_mac_control_frames_received_high[0x20];
3242 
3243 	u8         a_mac_control_frames_received_low[0x20];
3244 
3245 	u8         a_unsupported_opcodes_received_high[0x20];
3246 
3247 	u8         a_unsupported_opcodes_received_low[0x20];
3248 
3249 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3250 
3251 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3252 
3253 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3254 
3255 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3256 
3257 	u8         reserved_at_4c0[0x300];
3258 };
3259 
3260 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3261 	u8         life_time_counter_high[0x20];
3262 
3263 	u8         life_time_counter_low[0x20];
3264 
3265 	u8         rx_errors[0x20];
3266 
3267 	u8         tx_errors[0x20];
3268 
3269 	u8         l0_to_recovery_eieos[0x20];
3270 
3271 	u8         l0_to_recovery_ts[0x20];
3272 
3273 	u8         l0_to_recovery_framing[0x20];
3274 
3275 	u8         l0_to_recovery_retrain[0x20];
3276 
3277 	u8         crc_error_dllp[0x20];
3278 
3279 	u8         crc_error_tlp[0x20];
3280 
3281 	u8         tx_overflow_buffer_pkt_high[0x20];
3282 
3283 	u8         tx_overflow_buffer_pkt_low[0x20];
3284 
3285 	u8         outbound_stalled_reads[0x20];
3286 
3287 	u8         outbound_stalled_writes[0x20];
3288 
3289 	u8         outbound_stalled_reads_events[0x20];
3290 
3291 	u8         outbound_stalled_writes_events[0x20];
3292 
3293 	u8         reserved_at_200[0x5c0];
3294 };
3295 
3296 struct mlx5_ifc_cmd_inter_comp_event_bits {
3297 	u8         command_completion_vector[0x20];
3298 
3299 	u8         reserved_at_20[0xc0];
3300 };
3301 
3302 struct mlx5_ifc_stall_vl_event_bits {
3303 	u8         reserved_at_0[0x18];
3304 	u8         port_num[0x1];
3305 	u8         reserved_at_19[0x3];
3306 	u8         vl[0x4];
3307 
3308 	u8         reserved_at_20[0xa0];
3309 };
3310 
3311 struct mlx5_ifc_db_bf_congestion_event_bits {
3312 	u8         event_subtype[0x8];
3313 	u8         reserved_at_8[0x8];
3314 	u8         congestion_level[0x8];
3315 	u8         reserved_at_18[0x8];
3316 
3317 	u8         reserved_at_20[0xa0];
3318 };
3319 
3320 struct mlx5_ifc_gpio_event_bits {
3321 	u8         reserved_at_0[0x60];
3322 
3323 	u8         gpio_event_hi[0x20];
3324 
3325 	u8         gpio_event_lo[0x20];
3326 
3327 	u8         reserved_at_a0[0x40];
3328 };
3329 
3330 struct mlx5_ifc_port_state_change_event_bits {
3331 	u8         reserved_at_0[0x40];
3332 
3333 	u8         port_num[0x4];
3334 	u8         reserved_at_44[0x1c];
3335 
3336 	u8         reserved_at_60[0x80];
3337 };
3338 
3339 struct mlx5_ifc_dropped_packet_logged_bits {
3340 	u8         reserved_at_0[0xe0];
3341 };
3342 
3343 struct mlx5_ifc_nic_cap_reg_bits {
3344 	u8	   reserved_at_0[0x1a];
3345 	u8	   vhca_icm_ctrl[0x1];
3346 	u8	   reserved_at_1b[0x5];
3347 
3348 	u8	   reserved_at_20[0x60];
3349 };
3350 
3351 struct mlx5_ifc_default_timeout_bits {
3352 	u8         to_multiplier[0x3];
3353 	u8         reserved_at_3[0x9];
3354 	u8         to_value[0x14];
3355 };
3356 
3357 struct mlx5_ifc_dtor_reg_bits {
3358 	u8         reserved_at_0[0x20];
3359 
3360 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3361 
3362 	u8         reserved_at_40[0x60];
3363 
3364 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3365 
3366 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3367 
3368 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3369 
3370 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3371 
3372 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3373 
3374 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3375 
3376 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3377 
3378 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3379 
3380 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3381 
3382 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3383 
3384 	u8         reserved_at_1c0[0x20];
3385 };
3386 
3387 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3388 	u8	   vhca_id_valid[0x1];
3389 	u8	   reserved_at_1[0xf];
3390 	u8	   vhca_id[0x10];
3391 
3392 	u8	   reserved_at_20[0xa0];
3393 
3394 	u8	   cur_alloc_icm[0x20];
3395 
3396 	u8	   reserved_at_e0[0x120];
3397 };
3398 
3399 enum {
3400 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3401 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3402 };
3403 
3404 struct mlx5_ifc_cq_error_bits {
3405 	u8         reserved_at_0[0x8];
3406 	u8         cqn[0x18];
3407 
3408 	u8         reserved_at_20[0x20];
3409 
3410 	u8         reserved_at_40[0x18];
3411 	u8         syndrome[0x8];
3412 
3413 	u8         reserved_at_60[0x80];
3414 };
3415 
3416 struct mlx5_ifc_rdma_page_fault_event_bits {
3417 	u8         bytes_committed[0x20];
3418 
3419 	u8         r_key[0x20];
3420 
3421 	u8         reserved_at_40[0x10];
3422 	u8         packet_len[0x10];
3423 
3424 	u8         rdma_op_len[0x20];
3425 
3426 	u8         rdma_va[0x40];
3427 
3428 	u8         reserved_at_c0[0x5];
3429 	u8         rdma[0x1];
3430 	u8         write[0x1];
3431 	u8         requestor[0x1];
3432 	u8         qp_number[0x18];
3433 };
3434 
3435 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3436 	u8         bytes_committed[0x20];
3437 
3438 	u8         reserved_at_20[0x10];
3439 	u8         wqe_index[0x10];
3440 
3441 	u8         reserved_at_40[0x10];
3442 	u8         len[0x10];
3443 
3444 	u8         reserved_at_60[0x60];
3445 
3446 	u8         reserved_at_c0[0x5];
3447 	u8         rdma[0x1];
3448 	u8         write_read[0x1];
3449 	u8         requestor[0x1];
3450 	u8         qpn[0x18];
3451 };
3452 
3453 struct mlx5_ifc_qp_events_bits {
3454 	u8         reserved_at_0[0xa0];
3455 
3456 	u8         type[0x8];
3457 	u8         reserved_at_a8[0x18];
3458 
3459 	u8         reserved_at_c0[0x8];
3460 	u8         qpn_rqn_sqn[0x18];
3461 };
3462 
3463 struct mlx5_ifc_dct_events_bits {
3464 	u8         reserved_at_0[0xc0];
3465 
3466 	u8         reserved_at_c0[0x8];
3467 	u8         dct_number[0x18];
3468 };
3469 
3470 struct mlx5_ifc_comp_event_bits {
3471 	u8         reserved_at_0[0xc0];
3472 
3473 	u8         reserved_at_c0[0x8];
3474 	u8         cq_number[0x18];
3475 };
3476 
3477 enum {
3478 	MLX5_QPC_STATE_RST        = 0x0,
3479 	MLX5_QPC_STATE_INIT       = 0x1,
3480 	MLX5_QPC_STATE_RTR        = 0x2,
3481 	MLX5_QPC_STATE_RTS        = 0x3,
3482 	MLX5_QPC_STATE_SQER       = 0x4,
3483 	MLX5_QPC_STATE_ERR        = 0x6,
3484 	MLX5_QPC_STATE_SQD        = 0x7,
3485 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3486 };
3487 
3488 enum {
3489 	MLX5_QPC_ST_RC            = 0x0,
3490 	MLX5_QPC_ST_UC            = 0x1,
3491 	MLX5_QPC_ST_UD            = 0x2,
3492 	MLX5_QPC_ST_XRC           = 0x3,
3493 	MLX5_QPC_ST_DCI           = 0x5,
3494 	MLX5_QPC_ST_QP0           = 0x7,
3495 	MLX5_QPC_ST_QP1           = 0x8,
3496 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3497 	MLX5_QPC_ST_REG_UMR       = 0xc,
3498 };
3499 
3500 enum {
3501 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3502 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3503 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3504 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3505 };
3506 
3507 enum {
3508 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3509 };
3510 
3511 enum {
3512 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3513 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3514 };
3515 
3516 enum {
3517 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3518 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3519 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3520 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3521 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3522 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3523 };
3524 
3525 enum {
3526 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3527 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3528 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3529 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3530 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3531 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3532 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3533 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3534 };
3535 
3536 enum {
3537 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3538 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3539 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3540 };
3541 
3542 enum {
3543 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3544 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3545 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3546 };
3547 
3548 enum {
3549 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3550 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3551 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3552 };
3553 
3554 struct mlx5_ifc_qpc_bits {
3555 	u8         state[0x4];
3556 	u8         lag_tx_port_affinity[0x4];
3557 	u8         st[0x8];
3558 	u8         reserved_at_10[0x2];
3559 	u8	   isolate_vl_tc[0x1];
3560 	u8         pm_state[0x2];
3561 	u8         reserved_at_15[0x1];
3562 	u8         req_e2e_credit_mode[0x2];
3563 	u8         offload_type[0x4];
3564 	u8         end_padding_mode[0x2];
3565 	u8         reserved_at_1e[0x2];
3566 
3567 	u8         wq_signature[0x1];
3568 	u8         block_lb_mc[0x1];
3569 	u8         atomic_like_write_en[0x1];
3570 	u8         latency_sensitive[0x1];
3571 	u8         reserved_at_24[0x1];
3572 	u8         drain_sigerr[0x1];
3573 	u8         reserved_at_26[0x1];
3574 	u8         dp_ordering_force[0x1];
3575 	u8         pd[0x18];
3576 
3577 	u8         mtu[0x3];
3578 	u8         log_msg_max[0x5];
3579 	u8         reserved_at_48[0x1];
3580 	u8         log_rq_size[0x4];
3581 	u8         log_rq_stride[0x3];
3582 	u8         no_sq[0x1];
3583 	u8         log_sq_size[0x4];
3584 	u8         reserved_at_55[0x1];
3585 	u8	   retry_mode[0x2];
3586 	u8	   ts_format[0x2];
3587 	u8         reserved_at_5a[0x1];
3588 	u8         rlky[0x1];
3589 	u8         ulp_stateless_offload_mode[0x4];
3590 
3591 	u8         counter_set_id[0x8];
3592 	u8         uar_page[0x18];
3593 
3594 	u8         reserved_at_80[0x8];
3595 	u8         user_index[0x18];
3596 
3597 	u8         reserved_at_a0[0x3];
3598 	u8         log_page_size[0x5];
3599 	u8         remote_qpn[0x18];
3600 
3601 	struct mlx5_ifc_ads_bits primary_address_path;
3602 
3603 	struct mlx5_ifc_ads_bits secondary_address_path;
3604 
3605 	u8         log_ack_req_freq[0x4];
3606 	u8         reserved_at_384[0x4];
3607 	u8         log_sra_max[0x3];
3608 	u8         reserved_at_38b[0x2];
3609 	u8         retry_count[0x3];
3610 	u8         rnr_retry[0x3];
3611 	u8         reserved_at_393[0x1];
3612 	u8         fre[0x1];
3613 	u8         cur_rnr_retry[0x3];
3614 	u8         cur_retry_count[0x3];
3615 	u8         reserved_at_39b[0x5];
3616 
3617 	u8         reserved_at_3a0[0x20];
3618 
3619 	u8         reserved_at_3c0[0x8];
3620 	u8         next_send_psn[0x18];
3621 
3622 	u8         reserved_at_3e0[0x3];
3623 	u8	   log_num_dci_stream_channels[0x5];
3624 	u8         cqn_snd[0x18];
3625 
3626 	u8         reserved_at_400[0x3];
3627 	u8	   log_num_dci_errored_streams[0x5];
3628 	u8         deth_sqpn[0x18];
3629 
3630 	u8         reserved_at_420[0x20];
3631 
3632 	u8         reserved_at_440[0x8];
3633 	u8         last_acked_psn[0x18];
3634 
3635 	u8         reserved_at_460[0x8];
3636 	u8         ssn[0x18];
3637 
3638 	u8         reserved_at_480[0x8];
3639 	u8         log_rra_max[0x3];
3640 	u8         reserved_at_48b[0x1];
3641 	u8         atomic_mode[0x4];
3642 	u8         rre[0x1];
3643 	u8         rwe[0x1];
3644 	u8         rae[0x1];
3645 	u8         reserved_at_493[0x1];
3646 	u8         page_offset[0x6];
3647 	u8         reserved_at_49a[0x2];
3648 	u8         dp_ordering_1[0x1];
3649 	u8         cd_slave_receive[0x1];
3650 	u8         cd_slave_send[0x1];
3651 	u8         cd_master[0x1];
3652 
3653 	u8         reserved_at_4a0[0x3];
3654 	u8         min_rnr_nak[0x5];
3655 	u8         next_rcv_psn[0x18];
3656 
3657 	u8         reserved_at_4c0[0x8];
3658 	u8         xrcd[0x18];
3659 
3660 	u8         reserved_at_4e0[0x8];
3661 	u8         cqn_rcv[0x18];
3662 
3663 	u8         dbr_addr[0x40];
3664 
3665 	u8         q_key[0x20];
3666 
3667 	u8         reserved_at_560[0x5];
3668 	u8         rq_type[0x3];
3669 	u8         srqn_rmpn_xrqn[0x18];
3670 
3671 	u8         reserved_at_580[0x8];
3672 	u8         rmsn[0x18];
3673 
3674 	u8         hw_sq_wqebb_counter[0x10];
3675 	u8         sw_sq_wqebb_counter[0x10];
3676 
3677 	u8         hw_rq_counter[0x20];
3678 
3679 	u8         sw_rq_counter[0x20];
3680 
3681 	u8         reserved_at_600[0x20];
3682 
3683 	u8         reserved_at_620[0xf];
3684 	u8         cgs[0x1];
3685 	u8         cs_req[0x8];
3686 	u8         cs_res[0x8];
3687 
3688 	u8         dc_access_key[0x40];
3689 
3690 	u8         reserved_at_680[0x3];
3691 	u8         dbr_umem_valid[0x1];
3692 
3693 	u8         reserved_at_684[0xbc];
3694 };
3695 
3696 struct mlx5_ifc_roce_addr_layout_bits {
3697 	u8         source_l3_address[16][0x8];
3698 
3699 	u8         reserved_at_80[0x3];
3700 	u8         vlan_valid[0x1];
3701 	u8         vlan_id[0xc];
3702 	u8         source_mac_47_32[0x10];
3703 
3704 	u8         source_mac_31_0[0x20];
3705 
3706 	u8         reserved_at_c0[0x14];
3707 	u8         roce_l3_type[0x4];
3708 	u8         roce_version[0x8];
3709 
3710 	u8         reserved_at_e0[0x20];
3711 };
3712 
3713 struct mlx5_ifc_crypto_cap_bits {
3714 	u8    reserved_at_0[0x3];
3715 	u8    synchronize_dek[0x1];
3716 	u8    int_kek_manual[0x1];
3717 	u8    int_kek_auto[0x1];
3718 	u8    reserved_at_6[0x1a];
3719 
3720 	u8    reserved_at_20[0x3];
3721 	u8    log_dek_max_alloc[0x5];
3722 	u8    reserved_at_28[0x3];
3723 	u8    log_max_num_deks[0x5];
3724 	u8    reserved_at_30[0x10];
3725 
3726 	u8    reserved_at_40[0x20];
3727 
3728 	u8    reserved_at_60[0x3];
3729 	u8    log_dek_granularity[0x5];
3730 	u8    reserved_at_68[0x3];
3731 	u8    log_max_num_int_kek[0x5];
3732 	u8    sw_wrapped_dek[0x10];
3733 
3734 	u8    reserved_at_80[0x780];
3735 };
3736 
3737 struct mlx5_ifc_shampo_cap_bits {
3738 	u8    reserved_at_0[0x3];
3739 	u8    shampo_log_max_reservation_size[0x5];
3740 	u8    reserved_at_8[0x3];
3741 	u8    shampo_log_min_reservation_size[0x5];
3742 	u8    shampo_min_mss_size[0x10];
3743 
3744 	u8    shampo_header_split[0x1];
3745 	u8    shampo_header_split_data_merge[0x1];
3746 	u8    reserved_at_22[0x1];
3747 	u8    shampo_log_max_headers_entry_size[0x5];
3748 	u8    reserved_at_28[0x18];
3749 
3750 	u8    reserved_at_40[0x7c0];
3751 };
3752 
3753 union mlx5_ifc_hca_cap_union_bits {
3754 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3755 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3756 	struct mlx5_ifc_odp_cap_bits odp_cap;
3757 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3758 	struct mlx5_ifc_roce_cap_bits roce_cap;
3759 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3760 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3761 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3762 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3763 	struct mlx5_ifc_esw_cap_bits esw_cap;
3764 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3765 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3766 	struct mlx5_ifc_qos_cap_bits qos_cap;
3767 	struct mlx5_ifc_debug_cap_bits debug_cap;
3768 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3769 	struct mlx5_ifc_tls_cap_bits tls_cap;
3770 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3771 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3772 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3773 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3774 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3775 	u8         reserved_at_0[0x8000];
3776 };
3777 
3778 enum {
3779 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3780 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3781 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3782 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3783 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3784 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3785 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3786 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3787 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3788 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3789 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3790 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3791 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3792 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3793 };
3794 
3795 enum {
3796 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3797 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3798 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3799 };
3800 
3801 enum {
3802 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3803 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3804 };
3805 
3806 struct mlx5_ifc_vlan_bits {
3807 	u8         ethtype[0x10];
3808 	u8         prio[0x3];
3809 	u8         cfi[0x1];
3810 	u8         vid[0xc];
3811 };
3812 
3813 enum {
3814 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3815 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3816 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3817 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3818 };
3819 
3820 enum {
3821 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3822 };
3823 
3824 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3825 	u8        return_reg_id[0x4];
3826 	u8        aso_type[0x4];
3827 	u8        reserved_at_8[0x14];
3828 	u8        action[0x1];
3829 	u8        init_color[0x2];
3830 	u8        meter_id[0x1];
3831 };
3832 
3833 union mlx5_ifc_exe_aso_ctrl {
3834 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3835 };
3836 
3837 struct mlx5_ifc_execute_aso_bits {
3838 	u8        valid[0x1];
3839 	u8        reserved_at_1[0x7];
3840 	u8        aso_object_id[0x18];
3841 
3842 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3843 };
3844 
3845 struct mlx5_ifc_flow_context_bits {
3846 	struct mlx5_ifc_vlan_bits push_vlan;
3847 
3848 	u8         group_id[0x20];
3849 
3850 	u8         reserved_at_40[0x8];
3851 	u8         flow_tag[0x18];
3852 
3853 	u8         reserved_at_60[0x10];
3854 	u8         action[0x10];
3855 
3856 	u8         extended_destination[0x1];
3857 	u8         uplink_hairpin_en[0x1];
3858 	u8         flow_source[0x2];
3859 	u8         encrypt_decrypt_type[0x4];
3860 	u8         destination_list_size[0x18];
3861 
3862 	u8         reserved_at_a0[0x8];
3863 	u8         flow_counter_list_size[0x18];
3864 
3865 	u8         packet_reformat_id[0x20];
3866 
3867 	u8         modify_header_id[0x20];
3868 
3869 	struct mlx5_ifc_vlan_bits push_vlan_2;
3870 
3871 	u8         encrypt_decrypt_obj_id[0x20];
3872 	u8         reserved_at_140[0xc0];
3873 
3874 	struct mlx5_ifc_fte_match_param_bits match_value;
3875 
3876 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3877 
3878 	u8         reserved_at_1300[0x500];
3879 
3880 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3881 };
3882 
3883 enum {
3884 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3885 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3886 };
3887 
3888 struct mlx5_ifc_xrc_srqc_bits {
3889 	u8         state[0x4];
3890 	u8         log_xrc_srq_size[0x4];
3891 	u8         reserved_at_8[0x18];
3892 
3893 	u8         wq_signature[0x1];
3894 	u8         cont_srq[0x1];
3895 	u8         reserved_at_22[0x1];
3896 	u8         rlky[0x1];
3897 	u8         basic_cyclic_rcv_wqe[0x1];
3898 	u8         log_rq_stride[0x3];
3899 	u8         xrcd[0x18];
3900 
3901 	u8         page_offset[0x6];
3902 	u8         reserved_at_46[0x1];
3903 	u8         dbr_umem_valid[0x1];
3904 	u8         cqn[0x18];
3905 
3906 	u8         reserved_at_60[0x20];
3907 
3908 	u8         user_index_equal_xrc_srqn[0x1];
3909 	u8         reserved_at_81[0x1];
3910 	u8         log_page_size[0x6];
3911 	u8         user_index[0x18];
3912 
3913 	u8         reserved_at_a0[0x20];
3914 
3915 	u8         reserved_at_c0[0x8];
3916 	u8         pd[0x18];
3917 
3918 	u8         lwm[0x10];
3919 	u8         wqe_cnt[0x10];
3920 
3921 	u8         reserved_at_100[0x40];
3922 
3923 	u8         db_record_addr_h[0x20];
3924 
3925 	u8         db_record_addr_l[0x1e];
3926 	u8         reserved_at_17e[0x2];
3927 
3928 	u8         reserved_at_180[0x80];
3929 };
3930 
3931 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3932 	u8         counter_error_queues[0x20];
3933 
3934 	u8         total_error_queues[0x20];
3935 
3936 	u8         send_queue_priority_update_flow[0x20];
3937 
3938 	u8         reserved_at_60[0x20];
3939 
3940 	u8         nic_receive_steering_discard[0x40];
3941 
3942 	u8         receive_discard_vport_down[0x40];
3943 
3944 	u8         transmit_discard_vport_down[0x40];
3945 
3946 	u8         async_eq_overrun[0x20];
3947 
3948 	u8         comp_eq_overrun[0x20];
3949 
3950 	u8         reserved_at_180[0x20];
3951 
3952 	u8         invalid_command[0x20];
3953 
3954 	u8         quota_exceeded_command[0x20];
3955 
3956 	u8         internal_rq_out_of_buffer[0x20];
3957 
3958 	u8         cq_overrun[0x20];
3959 
3960 	u8         eth_wqe_too_small[0x20];
3961 
3962 	u8         reserved_at_220[0xc0];
3963 
3964 	u8         generated_pkt_steering_fail[0x40];
3965 
3966 	u8         handled_pkt_steering_fail[0x40];
3967 
3968 	u8         reserved_at_360[0xc80];
3969 };
3970 
3971 struct mlx5_ifc_traffic_counter_bits {
3972 	u8         packets[0x40];
3973 
3974 	u8         octets[0x40];
3975 };
3976 
3977 struct mlx5_ifc_tisc_bits {
3978 	u8         strict_lag_tx_port_affinity[0x1];
3979 	u8         tls_en[0x1];
3980 	u8         reserved_at_2[0x2];
3981 	u8         lag_tx_port_affinity[0x04];
3982 
3983 	u8         reserved_at_8[0x4];
3984 	u8         prio[0x4];
3985 	u8         reserved_at_10[0x10];
3986 
3987 	u8         reserved_at_20[0x100];
3988 
3989 	u8         reserved_at_120[0x8];
3990 	u8         transport_domain[0x18];
3991 
3992 	u8         reserved_at_140[0x8];
3993 	u8         underlay_qpn[0x18];
3994 
3995 	u8         reserved_at_160[0x8];
3996 	u8         pd[0x18];
3997 
3998 	u8         reserved_at_180[0x380];
3999 };
4000 
4001 enum {
4002 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
4003 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
4004 };
4005 
4006 enum {
4007 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
4008 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
4009 };
4010 
4011 enum {
4012 	MLX5_RX_HASH_FN_NONE           = 0x0,
4013 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4014 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4015 };
4016 
4017 enum {
4018 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4019 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4020 };
4021 
4022 struct mlx5_ifc_tirc_bits {
4023 	u8         reserved_at_0[0x20];
4024 
4025 	u8         disp_type[0x4];
4026 	u8         tls_en[0x1];
4027 	u8         reserved_at_25[0x1b];
4028 
4029 	u8         reserved_at_40[0x40];
4030 
4031 	u8         reserved_at_80[0x4];
4032 	u8         lro_timeout_period_usecs[0x10];
4033 	u8         packet_merge_mask[0x4];
4034 	u8         lro_max_ip_payload_size[0x8];
4035 
4036 	u8         reserved_at_a0[0x40];
4037 
4038 	u8         reserved_at_e0[0x8];
4039 	u8         inline_rqn[0x18];
4040 
4041 	u8         rx_hash_symmetric[0x1];
4042 	u8         reserved_at_101[0x1];
4043 	u8         tunneled_offload_en[0x1];
4044 	u8         reserved_at_103[0x5];
4045 	u8         indirect_table[0x18];
4046 
4047 	u8         rx_hash_fn[0x4];
4048 	u8         reserved_at_124[0x2];
4049 	u8         self_lb_block[0x2];
4050 	u8         transport_domain[0x18];
4051 
4052 	u8         rx_hash_toeplitz_key[10][0x20];
4053 
4054 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4055 
4056 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4057 
4058 	u8         reserved_at_2c0[0x4c0];
4059 };
4060 
4061 enum {
4062 	MLX5_SRQC_STATE_GOOD   = 0x0,
4063 	MLX5_SRQC_STATE_ERROR  = 0x1,
4064 };
4065 
4066 struct mlx5_ifc_srqc_bits {
4067 	u8         state[0x4];
4068 	u8         log_srq_size[0x4];
4069 	u8         reserved_at_8[0x18];
4070 
4071 	u8         wq_signature[0x1];
4072 	u8         cont_srq[0x1];
4073 	u8         reserved_at_22[0x1];
4074 	u8         rlky[0x1];
4075 	u8         reserved_at_24[0x1];
4076 	u8         log_rq_stride[0x3];
4077 	u8         xrcd[0x18];
4078 
4079 	u8         page_offset[0x6];
4080 	u8         reserved_at_46[0x2];
4081 	u8         cqn[0x18];
4082 
4083 	u8         reserved_at_60[0x20];
4084 
4085 	u8         reserved_at_80[0x2];
4086 	u8         log_page_size[0x6];
4087 	u8         reserved_at_88[0x18];
4088 
4089 	u8         reserved_at_a0[0x20];
4090 
4091 	u8         reserved_at_c0[0x8];
4092 	u8         pd[0x18];
4093 
4094 	u8         lwm[0x10];
4095 	u8         wqe_cnt[0x10];
4096 
4097 	u8         reserved_at_100[0x40];
4098 
4099 	u8         dbr_addr[0x40];
4100 
4101 	u8         reserved_at_180[0x80];
4102 };
4103 
4104 enum {
4105 	MLX5_SQC_STATE_RST  = 0x0,
4106 	MLX5_SQC_STATE_RDY  = 0x1,
4107 	MLX5_SQC_STATE_ERR  = 0x3,
4108 };
4109 
4110 struct mlx5_ifc_sqc_bits {
4111 	u8         rlky[0x1];
4112 	u8         cd_master[0x1];
4113 	u8         fre[0x1];
4114 	u8         flush_in_error_en[0x1];
4115 	u8         allow_multi_pkt_send_wqe[0x1];
4116 	u8	   min_wqe_inline_mode[0x3];
4117 	u8         state[0x4];
4118 	u8         reg_umr[0x1];
4119 	u8         allow_swp[0x1];
4120 	u8         hairpin[0x1];
4121 	u8         non_wire[0x1];
4122 	u8         reserved_at_10[0xa];
4123 	u8	   ts_format[0x2];
4124 	u8	   reserved_at_1c[0x4];
4125 
4126 	u8         reserved_at_20[0x8];
4127 	u8         user_index[0x18];
4128 
4129 	u8         reserved_at_40[0x8];
4130 	u8         cqn[0x18];
4131 
4132 	u8         reserved_at_60[0x8];
4133 	u8         hairpin_peer_rq[0x18];
4134 
4135 	u8         reserved_at_80[0x10];
4136 	u8         hairpin_peer_vhca[0x10];
4137 
4138 	u8         reserved_at_a0[0x20];
4139 
4140 	u8         reserved_at_c0[0x8];
4141 	u8         ts_cqe_to_dest_cqn[0x18];
4142 
4143 	u8         reserved_at_e0[0x10];
4144 	u8         packet_pacing_rate_limit_index[0x10];
4145 	u8         tis_lst_sz[0x10];
4146 	u8         qos_queue_group_id[0x10];
4147 
4148 	u8         reserved_at_120[0x40];
4149 
4150 	u8         reserved_at_160[0x8];
4151 	u8         tis_num_0[0x18];
4152 
4153 	struct mlx5_ifc_wq_bits wq;
4154 };
4155 
4156 enum {
4157 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4158 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4159 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4160 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4161 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4162 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4163 };
4164 
4165 enum {
4166 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4167 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4168 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4169 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4170 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4171 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4172 };
4173 
4174 enum {
4175 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4176 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4177 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4178 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4179 };
4180 
4181 enum {
4182 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4183 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4184 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4185 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4186 };
4187 
4188 struct mlx5_ifc_tsar_element_bits {
4189 	u8         traffic_class[0x4];
4190 	u8         reserved_at_4[0x4];
4191 	u8         tsar_type[0x8];
4192 	u8         reserved_at_10[0x10];
4193 };
4194 
4195 struct mlx5_ifc_vport_element_bits {
4196 	u8         reserved_at_0[0x4];
4197 	u8         eswitch_owner_vhca_id_valid[0x1];
4198 	u8         eswitch_owner_vhca_id[0xb];
4199 	u8         vport_number[0x10];
4200 };
4201 
4202 struct mlx5_ifc_vport_tc_element_bits {
4203 	u8         traffic_class[0x4];
4204 	u8         eswitch_owner_vhca_id_valid[0x1];
4205 	u8         eswitch_owner_vhca_id[0xb];
4206 	u8         vport_number[0x10];
4207 };
4208 
4209 union mlx5_ifc_element_attributes_bits {
4210 	struct mlx5_ifc_tsar_element_bits tsar;
4211 	struct mlx5_ifc_vport_element_bits vport;
4212 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4213 	u8 reserved_at_0[0x20];
4214 };
4215 
4216 struct mlx5_ifc_scheduling_context_bits {
4217 	u8         element_type[0x8];
4218 	u8         reserved_at_8[0x18];
4219 
4220 	union mlx5_ifc_element_attributes_bits element_attributes;
4221 
4222 	u8         parent_element_id[0x20];
4223 
4224 	u8         reserved_at_60[0x40];
4225 
4226 	u8         bw_share[0x20];
4227 
4228 	u8         max_average_bw[0x20];
4229 
4230 	u8         max_bw_obj_id[0x20];
4231 
4232 	u8         reserved_at_100[0x100];
4233 };
4234 
4235 struct mlx5_ifc_rqtc_bits {
4236 	u8    reserved_at_0[0xa0];
4237 
4238 	u8    reserved_at_a0[0x5];
4239 	u8    list_q_type[0x3];
4240 	u8    reserved_at_a8[0x8];
4241 	u8    rqt_max_size[0x10];
4242 
4243 	u8    rq_vhca_id_format[0x1];
4244 	u8    reserved_at_c1[0xf];
4245 	u8    rqt_actual_size[0x10];
4246 
4247 	u8    reserved_at_e0[0x6a0];
4248 
4249 	union {
4250 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4251 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4252 	};
4253 };
4254 
4255 enum {
4256 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4257 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4258 };
4259 
4260 enum {
4261 	MLX5_RQC_STATE_RST  = 0x0,
4262 	MLX5_RQC_STATE_RDY  = 0x1,
4263 	MLX5_RQC_STATE_ERR  = 0x3,
4264 };
4265 
4266 enum {
4267 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4268 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4269 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4270 };
4271 
4272 enum {
4273 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4274 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4275 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4276 };
4277 
4278 struct mlx5_ifc_rqc_bits {
4279 	u8         rlky[0x1];
4280 	u8	   delay_drop_en[0x1];
4281 	u8         scatter_fcs[0x1];
4282 	u8         vsd[0x1];
4283 	u8         mem_rq_type[0x4];
4284 	u8         state[0x4];
4285 	u8         reserved_at_c[0x1];
4286 	u8         flush_in_error_en[0x1];
4287 	u8         hairpin[0x1];
4288 	u8         reserved_at_f[0xb];
4289 	u8	   ts_format[0x2];
4290 	u8	   reserved_at_1c[0x4];
4291 
4292 	u8         reserved_at_20[0x8];
4293 	u8         user_index[0x18];
4294 
4295 	u8         reserved_at_40[0x8];
4296 	u8         cqn[0x18];
4297 
4298 	u8         counter_set_id[0x8];
4299 	u8         reserved_at_68[0x18];
4300 
4301 	u8         reserved_at_80[0x8];
4302 	u8         rmpn[0x18];
4303 
4304 	u8         reserved_at_a0[0x8];
4305 	u8         hairpin_peer_sq[0x18];
4306 
4307 	u8         reserved_at_c0[0x10];
4308 	u8         hairpin_peer_vhca[0x10];
4309 
4310 	u8         reserved_at_e0[0x46];
4311 	u8         shampo_no_match_alignment_granularity[0x2];
4312 	u8         reserved_at_128[0x6];
4313 	u8         shampo_match_criteria_type[0x2];
4314 	u8         reservation_timeout[0x10];
4315 
4316 	u8         reserved_at_140[0x40];
4317 
4318 	struct mlx5_ifc_wq_bits wq;
4319 };
4320 
4321 enum {
4322 	MLX5_RMPC_STATE_RDY  = 0x1,
4323 	MLX5_RMPC_STATE_ERR  = 0x3,
4324 };
4325 
4326 struct mlx5_ifc_rmpc_bits {
4327 	u8         reserved_at_0[0x8];
4328 	u8         state[0x4];
4329 	u8         reserved_at_c[0x14];
4330 
4331 	u8         basic_cyclic_rcv_wqe[0x1];
4332 	u8         reserved_at_21[0x1f];
4333 
4334 	u8         reserved_at_40[0x140];
4335 
4336 	struct mlx5_ifc_wq_bits wq;
4337 };
4338 
4339 enum {
4340 	VHCA_ID_TYPE_HW = 0,
4341 	VHCA_ID_TYPE_SW = 1,
4342 };
4343 
4344 struct mlx5_ifc_nic_vport_context_bits {
4345 	u8         reserved_at_0[0x5];
4346 	u8         min_wqe_inline_mode[0x3];
4347 	u8         reserved_at_8[0x15];
4348 	u8         disable_mc_local_lb[0x1];
4349 	u8         disable_uc_local_lb[0x1];
4350 	u8         roce_en[0x1];
4351 
4352 	u8         arm_change_event[0x1];
4353 	u8         reserved_at_21[0x1a];
4354 	u8         event_on_mtu[0x1];
4355 	u8         event_on_promisc_change[0x1];
4356 	u8         event_on_vlan_change[0x1];
4357 	u8         event_on_mc_address_change[0x1];
4358 	u8         event_on_uc_address_change[0x1];
4359 
4360 	u8         vhca_id_type[0x1];
4361 	u8         reserved_at_41[0xb];
4362 	u8	   affiliation_criteria[0x4];
4363 	u8	   affiliated_vhca_id[0x10];
4364 
4365 	u8	   reserved_at_60[0xa0];
4366 
4367 	u8	   reserved_at_100[0x1];
4368 	u8         sd_group[0x3];
4369 	u8	   reserved_at_104[0x1c];
4370 
4371 	u8	   reserved_at_120[0x10];
4372 	u8         mtu[0x10];
4373 
4374 	u8         system_image_guid[0x40];
4375 	u8         port_guid[0x40];
4376 	u8         node_guid[0x40];
4377 
4378 	u8         reserved_at_200[0x140];
4379 	u8         qkey_violation_counter[0x10];
4380 	u8         reserved_at_350[0x430];
4381 
4382 	u8         promisc_uc[0x1];
4383 	u8         promisc_mc[0x1];
4384 	u8         promisc_all[0x1];
4385 	u8         reserved_at_783[0x2];
4386 	u8         allowed_list_type[0x3];
4387 	u8         reserved_at_788[0xc];
4388 	u8         allowed_list_size[0xc];
4389 
4390 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4391 
4392 	u8         reserved_at_7e0[0x20];
4393 
4394 	u8         current_uc_mac_address[][0x40];
4395 };
4396 
4397 enum {
4398 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4399 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4400 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4401 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4402 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4403 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4404 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4405 };
4406 
4407 struct mlx5_ifc_mkc_bits {
4408 	u8         reserved_at_0[0x1];
4409 	u8         free[0x1];
4410 	u8         reserved_at_2[0x1];
4411 	u8         access_mode_4_2[0x3];
4412 	u8         reserved_at_6[0x7];
4413 	u8         relaxed_ordering_write[0x1];
4414 	u8         reserved_at_e[0x1];
4415 	u8         small_fence_on_rdma_read_response[0x1];
4416 	u8         umr_en[0x1];
4417 	u8         a[0x1];
4418 	u8         rw[0x1];
4419 	u8         rr[0x1];
4420 	u8         lw[0x1];
4421 	u8         lr[0x1];
4422 	u8         access_mode_1_0[0x2];
4423 	u8         reserved_at_18[0x2];
4424 	u8         ma_translation_mode[0x2];
4425 	u8         reserved_at_1c[0x4];
4426 
4427 	u8         qpn[0x18];
4428 	u8         mkey_7_0[0x8];
4429 
4430 	u8         reserved_at_40[0x20];
4431 
4432 	u8         length64[0x1];
4433 	u8         bsf_en[0x1];
4434 	u8         sync_umr[0x1];
4435 	u8         reserved_at_63[0x2];
4436 	u8         expected_sigerr_count[0x1];
4437 	u8         reserved_at_66[0x1];
4438 	u8         en_rinval[0x1];
4439 	u8         pd[0x18];
4440 
4441 	u8         start_addr[0x40];
4442 
4443 	u8         len[0x40];
4444 
4445 	u8         bsf_octword_size[0x20];
4446 
4447 	u8         reserved_at_120[0x60];
4448 
4449 	u8         crossing_target_vhca_id[0x10];
4450 	u8         reserved_at_190[0x10];
4451 
4452 	u8         translations_octword_size[0x20];
4453 
4454 	u8         reserved_at_1c0[0x19];
4455 	u8         relaxed_ordering_read[0x1];
4456 	u8         log_page_size[0x6];
4457 
4458 	u8         reserved_at_1e0[0x20];
4459 };
4460 
4461 struct mlx5_ifc_pkey_bits {
4462 	u8         reserved_at_0[0x10];
4463 	u8         pkey[0x10];
4464 };
4465 
4466 struct mlx5_ifc_array128_auto_bits {
4467 	u8         array128_auto[16][0x8];
4468 };
4469 
4470 struct mlx5_ifc_hca_vport_context_bits {
4471 	u8         field_select[0x20];
4472 
4473 	u8         reserved_at_20[0xe0];
4474 
4475 	u8         sm_virt_aware[0x1];
4476 	u8         has_smi[0x1];
4477 	u8         has_raw[0x1];
4478 	u8         grh_required[0x1];
4479 	u8         reserved_at_104[0x4];
4480 	u8         num_port_plane[0x8];
4481 	u8         port_physical_state[0x4];
4482 	u8         vport_state_policy[0x4];
4483 	u8         port_state[0x4];
4484 	u8         vport_state[0x4];
4485 
4486 	u8         reserved_at_120[0x20];
4487 
4488 	u8         system_image_guid[0x40];
4489 
4490 	u8         port_guid[0x40];
4491 
4492 	u8         node_guid[0x40];
4493 
4494 	u8         cap_mask1[0x20];
4495 
4496 	u8         cap_mask1_field_select[0x20];
4497 
4498 	u8         cap_mask2[0x20];
4499 
4500 	u8         cap_mask2_field_select[0x20];
4501 
4502 	u8         reserved_at_280[0x80];
4503 
4504 	u8         lid[0x10];
4505 	u8         reserved_at_310[0x4];
4506 	u8         init_type_reply[0x4];
4507 	u8         lmc[0x3];
4508 	u8         subnet_timeout[0x5];
4509 
4510 	u8         sm_lid[0x10];
4511 	u8         sm_sl[0x4];
4512 	u8         reserved_at_334[0xc];
4513 
4514 	u8         qkey_violation_counter[0x10];
4515 	u8         pkey_violation_counter[0x10];
4516 
4517 	u8         reserved_at_360[0xca0];
4518 };
4519 
4520 struct mlx5_ifc_esw_vport_context_bits {
4521 	u8         fdb_to_vport_reg_c[0x1];
4522 	u8         reserved_at_1[0x2];
4523 	u8         vport_svlan_strip[0x1];
4524 	u8         vport_cvlan_strip[0x1];
4525 	u8         vport_svlan_insert[0x1];
4526 	u8         vport_cvlan_insert[0x2];
4527 	u8         fdb_to_vport_reg_c_id[0x8];
4528 	u8         reserved_at_10[0x10];
4529 
4530 	u8         reserved_at_20[0x20];
4531 
4532 	u8         svlan_cfi[0x1];
4533 	u8         svlan_pcp[0x3];
4534 	u8         svlan_id[0xc];
4535 	u8         cvlan_cfi[0x1];
4536 	u8         cvlan_pcp[0x3];
4537 	u8         cvlan_id[0xc];
4538 
4539 	u8         reserved_at_60[0x720];
4540 
4541 	u8         sw_steering_vport_icm_address_rx[0x40];
4542 
4543 	u8         sw_steering_vport_icm_address_tx[0x40];
4544 };
4545 
4546 enum {
4547 	MLX5_EQC_STATUS_OK                = 0x0,
4548 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4549 };
4550 
4551 enum {
4552 	MLX5_EQC_ST_ARMED  = 0x9,
4553 	MLX5_EQC_ST_FIRED  = 0xa,
4554 };
4555 
4556 struct mlx5_ifc_eqc_bits {
4557 	u8         status[0x4];
4558 	u8         reserved_at_4[0x9];
4559 	u8         ec[0x1];
4560 	u8         oi[0x1];
4561 	u8         reserved_at_f[0x5];
4562 	u8         st[0x4];
4563 	u8         reserved_at_18[0x8];
4564 
4565 	u8         reserved_at_20[0x20];
4566 
4567 	u8         reserved_at_40[0x14];
4568 	u8         page_offset[0x6];
4569 	u8         reserved_at_5a[0x6];
4570 
4571 	u8         reserved_at_60[0x3];
4572 	u8         log_eq_size[0x5];
4573 	u8         uar_page[0x18];
4574 
4575 	u8         reserved_at_80[0x20];
4576 
4577 	u8         reserved_at_a0[0x14];
4578 	u8         intr[0xc];
4579 
4580 	u8         reserved_at_c0[0x3];
4581 	u8         log_page_size[0x5];
4582 	u8         reserved_at_c8[0x18];
4583 
4584 	u8         reserved_at_e0[0x60];
4585 
4586 	u8         reserved_at_140[0x8];
4587 	u8         consumer_counter[0x18];
4588 
4589 	u8         reserved_at_160[0x8];
4590 	u8         producer_counter[0x18];
4591 
4592 	u8         reserved_at_180[0x80];
4593 };
4594 
4595 enum {
4596 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4597 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4598 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4599 };
4600 
4601 enum {
4602 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4603 	MLX5_DCTC_CS_RES_NA         = 0x1,
4604 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4605 };
4606 
4607 enum {
4608 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4609 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4610 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4611 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4612 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4613 };
4614 
4615 struct mlx5_ifc_dctc_bits {
4616 	u8         reserved_at_0[0x4];
4617 	u8         state[0x4];
4618 	u8         reserved_at_8[0x18];
4619 
4620 	u8         reserved_at_20[0x7];
4621 	u8         dp_ordering_force[0x1];
4622 	u8         user_index[0x18];
4623 
4624 	u8         reserved_at_40[0x8];
4625 	u8         cqn[0x18];
4626 
4627 	u8         counter_set_id[0x8];
4628 	u8         atomic_mode[0x4];
4629 	u8         rre[0x1];
4630 	u8         rwe[0x1];
4631 	u8         rae[0x1];
4632 	u8         atomic_like_write_en[0x1];
4633 	u8         latency_sensitive[0x1];
4634 	u8         rlky[0x1];
4635 	u8         free_ar[0x1];
4636 	u8         reserved_at_73[0x1];
4637 	u8         dp_ordering_1[0x1];
4638 	u8         reserved_at_75[0xb];
4639 
4640 	u8         reserved_at_80[0x8];
4641 	u8         cs_res[0x8];
4642 	u8         reserved_at_90[0x3];
4643 	u8         min_rnr_nak[0x5];
4644 	u8         reserved_at_98[0x8];
4645 
4646 	u8         reserved_at_a0[0x8];
4647 	u8         srqn_xrqn[0x18];
4648 
4649 	u8         reserved_at_c0[0x8];
4650 	u8         pd[0x18];
4651 
4652 	u8         tclass[0x8];
4653 	u8         reserved_at_e8[0x4];
4654 	u8         flow_label[0x14];
4655 
4656 	u8         dc_access_key[0x40];
4657 
4658 	u8         reserved_at_140[0x5];
4659 	u8         mtu[0x3];
4660 	u8         port[0x8];
4661 	u8         pkey_index[0x10];
4662 
4663 	u8         reserved_at_160[0x8];
4664 	u8         my_addr_index[0x8];
4665 	u8         reserved_at_170[0x8];
4666 	u8         hop_limit[0x8];
4667 
4668 	u8         dc_access_key_violation_count[0x20];
4669 
4670 	u8         reserved_at_1a0[0x14];
4671 	u8         dei_cfi[0x1];
4672 	u8         eth_prio[0x3];
4673 	u8         ecn[0x2];
4674 	u8         dscp[0x6];
4675 
4676 	u8         reserved_at_1c0[0x20];
4677 	u8         ece[0x20];
4678 };
4679 
4680 enum {
4681 	MLX5_CQC_STATUS_OK             = 0x0,
4682 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4683 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4684 };
4685 
4686 enum {
4687 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4688 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4689 };
4690 
4691 enum {
4692 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4693 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4694 	MLX5_CQC_ST_FIRED                                 = 0xa,
4695 };
4696 
4697 enum mlx5_cq_period_mode {
4698 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4699 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4700 	MLX5_CQ_PERIOD_NUM_MODES,
4701 };
4702 
4703 struct mlx5_ifc_cqc_bits {
4704 	u8         status[0x4];
4705 	u8         reserved_at_4[0x2];
4706 	u8         dbr_umem_valid[0x1];
4707 	u8         apu_cq[0x1];
4708 	u8         cqe_sz[0x3];
4709 	u8         cc[0x1];
4710 	u8         reserved_at_c[0x1];
4711 	u8         scqe_break_moderation_en[0x1];
4712 	u8         oi[0x1];
4713 	u8         cq_period_mode[0x2];
4714 	u8         cqe_comp_en[0x1];
4715 	u8         mini_cqe_res_format[0x2];
4716 	u8         st[0x4];
4717 	u8         reserved_at_18[0x6];
4718 	u8         cqe_compression_layout[0x2];
4719 
4720 	u8         reserved_at_20[0x20];
4721 
4722 	u8         reserved_at_40[0x14];
4723 	u8         page_offset[0x6];
4724 	u8         reserved_at_5a[0x6];
4725 
4726 	u8         reserved_at_60[0x3];
4727 	u8         log_cq_size[0x5];
4728 	u8         uar_page[0x18];
4729 
4730 	u8         reserved_at_80[0x4];
4731 	u8         cq_period[0xc];
4732 	u8         cq_max_count[0x10];
4733 
4734 	u8         c_eqn_or_apu_element[0x20];
4735 
4736 	u8         reserved_at_c0[0x3];
4737 	u8         log_page_size[0x5];
4738 	u8         reserved_at_c8[0x18];
4739 
4740 	u8         reserved_at_e0[0x20];
4741 
4742 	u8         reserved_at_100[0x8];
4743 	u8         last_notified_index[0x18];
4744 
4745 	u8         reserved_at_120[0x8];
4746 	u8         last_solicit_index[0x18];
4747 
4748 	u8         reserved_at_140[0x8];
4749 	u8         consumer_counter[0x18];
4750 
4751 	u8         reserved_at_160[0x8];
4752 	u8         producer_counter[0x18];
4753 
4754 	u8         reserved_at_180[0x40];
4755 
4756 	u8         dbr_addr[0x40];
4757 };
4758 
4759 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4760 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4761 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4762 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4763 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4764 	u8         reserved_at_0[0x800];
4765 };
4766 
4767 struct mlx5_ifc_query_adapter_param_block_bits {
4768 	u8         reserved_at_0[0xc0];
4769 
4770 	u8         reserved_at_c0[0x8];
4771 	u8         ieee_vendor_id[0x18];
4772 
4773 	u8         reserved_at_e0[0x10];
4774 	u8         vsd_vendor_id[0x10];
4775 
4776 	u8         vsd[208][0x8];
4777 
4778 	u8         vsd_contd_psid[16][0x8];
4779 };
4780 
4781 enum {
4782 	MLX5_XRQC_STATE_GOOD   = 0x0,
4783 	MLX5_XRQC_STATE_ERROR  = 0x1,
4784 };
4785 
4786 enum {
4787 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4788 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4789 };
4790 
4791 enum {
4792 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4793 };
4794 
4795 struct mlx5_ifc_tag_matching_topology_context_bits {
4796 	u8         log_matching_list_sz[0x4];
4797 	u8         reserved_at_4[0xc];
4798 	u8         append_next_index[0x10];
4799 
4800 	u8         sw_phase_cnt[0x10];
4801 	u8         hw_phase_cnt[0x10];
4802 
4803 	u8         reserved_at_40[0x40];
4804 };
4805 
4806 struct mlx5_ifc_xrqc_bits {
4807 	u8         state[0x4];
4808 	u8         rlkey[0x1];
4809 	u8         reserved_at_5[0xf];
4810 	u8         topology[0x4];
4811 	u8         reserved_at_18[0x4];
4812 	u8         offload[0x4];
4813 
4814 	u8         reserved_at_20[0x8];
4815 	u8         user_index[0x18];
4816 
4817 	u8         reserved_at_40[0x8];
4818 	u8         cqn[0x18];
4819 
4820 	u8         reserved_at_60[0xa0];
4821 
4822 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4823 
4824 	u8         reserved_at_180[0x280];
4825 
4826 	struct mlx5_ifc_wq_bits wq;
4827 };
4828 
4829 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4830 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4831 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4832 	u8         reserved_at_0[0x20];
4833 };
4834 
4835 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4836 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4837 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4838 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4839 	u8         reserved_at_0[0x20];
4840 };
4841 
4842 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4843 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4844 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4845 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4846 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4847 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4848 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4849 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4850 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4851 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4852 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4853 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4854 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4855 	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4856 	u8         reserved_at_0[0x7c0];
4857 };
4858 
4859 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4860 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4861 	u8         reserved_at_0[0x7c0];
4862 };
4863 
4864 union mlx5_ifc_event_auto_bits {
4865 	struct mlx5_ifc_comp_event_bits comp_event;
4866 	struct mlx5_ifc_dct_events_bits dct_events;
4867 	struct mlx5_ifc_qp_events_bits qp_events;
4868 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4869 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4870 	struct mlx5_ifc_cq_error_bits cq_error;
4871 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4872 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4873 	struct mlx5_ifc_gpio_event_bits gpio_event;
4874 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4875 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4876 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4877 	u8         reserved_at_0[0xe0];
4878 };
4879 
4880 struct mlx5_ifc_health_buffer_bits {
4881 	u8         reserved_at_0[0x100];
4882 
4883 	u8         assert_existptr[0x20];
4884 
4885 	u8         assert_callra[0x20];
4886 
4887 	u8         reserved_at_140[0x20];
4888 
4889 	u8         time[0x20];
4890 
4891 	u8         fw_version[0x20];
4892 
4893 	u8         hw_id[0x20];
4894 
4895 	u8         rfr[0x1];
4896 	u8         reserved_at_1c1[0x3];
4897 	u8         valid[0x1];
4898 	u8         severity[0x3];
4899 	u8         reserved_at_1c8[0x18];
4900 
4901 	u8         irisc_index[0x8];
4902 	u8         synd[0x8];
4903 	u8         ext_synd[0x10];
4904 };
4905 
4906 struct mlx5_ifc_register_loopback_control_bits {
4907 	u8         no_lb[0x1];
4908 	u8         reserved_at_1[0x7];
4909 	u8         port[0x8];
4910 	u8         reserved_at_10[0x10];
4911 
4912 	u8         reserved_at_20[0x60];
4913 };
4914 
4915 enum {
4916 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4917 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4918 };
4919 
4920 struct mlx5_ifc_teardown_hca_out_bits {
4921 	u8         status[0x8];
4922 	u8         reserved_at_8[0x18];
4923 
4924 	u8         syndrome[0x20];
4925 
4926 	u8         reserved_at_40[0x3f];
4927 
4928 	u8         state[0x1];
4929 };
4930 
4931 enum {
4932 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4933 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4934 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4935 };
4936 
4937 struct mlx5_ifc_teardown_hca_in_bits {
4938 	u8         opcode[0x10];
4939 	u8         reserved_at_10[0x10];
4940 
4941 	u8         reserved_at_20[0x10];
4942 	u8         op_mod[0x10];
4943 
4944 	u8         reserved_at_40[0x10];
4945 	u8         profile[0x10];
4946 
4947 	u8         reserved_at_60[0x20];
4948 };
4949 
4950 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4951 	u8         status[0x8];
4952 	u8         reserved_at_8[0x18];
4953 
4954 	u8         syndrome[0x20];
4955 
4956 	u8         reserved_at_40[0x40];
4957 };
4958 
4959 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4960 	u8         opcode[0x10];
4961 	u8         uid[0x10];
4962 
4963 	u8         reserved_at_20[0x10];
4964 	u8         op_mod[0x10];
4965 
4966 	u8         reserved_at_40[0x8];
4967 	u8         qpn[0x18];
4968 
4969 	u8         reserved_at_60[0x20];
4970 
4971 	u8         opt_param_mask[0x20];
4972 
4973 	u8         reserved_at_a0[0x20];
4974 
4975 	struct mlx5_ifc_qpc_bits qpc;
4976 
4977 	u8         reserved_at_800[0x80];
4978 };
4979 
4980 struct mlx5_ifc_sqd2rts_qp_out_bits {
4981 	u8         status[0x8];
4982 	u8         reserved_at_8[0x18];
4983 
4984 	u8         syndrome[0x20];
4985 
4986 	u8         reserved_at_40[0x40];
4987 };
4988 
4989 struct mlx5_ifc_sqd2rts_qp_in_bits {
4990 	u8         opcode[0x10];
4991 	u8         uid[0x10];
4992 
4993 	u8         reserved_at_20[0x10];
4994 	u8         op_mod[0x10];
4995 
4996 	u8         reserved_at_40[0x8];
4997 	u8         qpn[0x18];
4998 
4999 	u8         reserved_at_60[0x20];
5000 
5001 	u8         opt_param_mask[0x20];
5002 
5003 	u8         reserved_at_a0[0x20];
5004 
5005 	struct mlx5_ifc_qpc_bits qpc;
5006 
5007 	u8         reserved_at_800[0x80];
5008 };
5009 
5010 struct mlx5_ifc_set_roce_address_out_bits {
5011 	u8         status[0x8];
5012 	u8         reserved_at_8[0x18];
5013 
5014 	u8         syndrome[0x20];
5015 
5016 	u8         reserved_at_40[0x40];
5017 };
5018 
5019 struct mlx5_ifc_set_roce_address_in_bits {
5020 	u8         opcode[0x10];
5021 	u8         reserved_at_10[0x10];
5022 
5023 	u8         reserved_at_20[0x10];
5024 	u8         op_mod[0x10];
5025 
5026 	u8         roce_address_index[0x10];
5027 	u8         reserved_at_50[0xc];
5028 	u8	   vhca_port_num[0x4];
5029 
5030 	u8         reserved_at_60[0x20];
5031 
5032 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5033 };
5034 
5035 struct mlx5_ifc_set_mad_demux_out_bits {
5036 	u8         status[0x8];
5037 	u8         reserved_at_8[0x18];
5038 
5039 	u8         syndrome[0x20];
5040 
5041 	u8         reserved_at_40[0x40];
5042 };
5043 
5044 enum {
5045 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5046 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5047 };
5048 
5049 struct mlx5_ifc_set_mad_demux_in_bits {
5050 	u8         opcode[0x10];
5051 	u8         reserved_at_10[0x10];
5052 
5053 	u8         reserved_at_20[0x10];
5054 	u8         op_mod[0x10];
5055 
5056 	u8         reserved_at_40[0x20];
5057 
5058 	u8         reserved_at_60[0x6];
5059 	u8         demux_mode[0x2];
5060 	u8         reserved_at_68[0x18];
5061 };
5062 
5063 struct mlx5_ifc_set_l2_table_entry_out_bits {
5064 	u8         status[0x8];
5065 	u8         reserved_at_8[0x18];
5066 
5067 	u8         syndrome[0x20];
5068 
5069 	u8         reserved_at_40[0x40];
5070 };
5071 
5072 struct mlx5_ifc_set_l2_table_entry_in_bits {
5073 	u8         opcode[0x10];
5074 	u8         reserved_at_10[0x10];
5075 
5076 	u8         reserved_at_20[0x10];
5077 	u8         op_mod[0x10];
5078 
5079 	u8         reserved_at_40[0x60];
5080 
5081 	u8         reserved_at_a0[0x8];
5082 	u8         table_index[0x18];
5083 
5084 	u8         reserved_at_c0[0x20];
5085 
5086 	u8         reserved_at_e0[0x10];
5087 	u8         silent_mode_valid[0x1];
5088 	u8         silent_mode[0x1];
5089 	u8         reserved_at_f2[0x1];
5090 	u8         vlan_valid[0x1];
5091 	u8         vlan[0xc];
5092 
5093 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5094 
5095 	u8         reserved_at_140[0xc0];
5096 };
5097 
5098 struct mlx5_ifc_set_issi_out_bits {
5099 	u8         status[0x8];
5100 	u8         reserved_at_8[0x18];
5101 
5102 	u8         syndrome[0x20];
5103 
5104 	u8         reserved_at_40[0x40];
5105 };
5106 
5107 struct mlx5_ifc_set_issi_in_bits {
5108 	u8         opcode[0x10];
5109 	u8         reserved_at_10[0x10];
5110 
5111 	u8         reserved_at_20[0x10];
5112 	u8         op_mod[0x10];
5113 
5114 	u8         reserved_at_40[0x10];
5115 	u8         current_issi[0x10];
5116 
5117 	u8         reserved_at_60[0x20];
5118 };
5119 
5120 struct mlx5_ifc_set_hca_cap_out_bits {
5121 	u8         status[0x8];
5122 	u8         reserved_at_8[0x18];
5123 
5124 	u8         syndrome[0x20];
5125 
5126 	u8         reserved_at_40[0x40];
5127 };
5128 
5129 struct mlx5_ifc_set_hca_cap_in_bits {
5130 	u8         opcode[0x10];
5131 	u8         reserved_at_10[0x10];
5132 
5133 	u8         reserved_at_20[0x10];
5134 	u8         op_mod[0x10];
5135 
5136 	u8         other_function[0x1];
5137 	u8         ec_vf_function[0x1];
5138 	u8         reserved_at_42[0xe];
5139 	u8         function_id[0x10];
5140 
5141 	u8         reserved_at_60[0x20];
5142 
5143 	union mlx5_ifc_hca_cap_union_bits capability;
5144 };
5145 
5146 enum {
5147 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5148 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5149 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5150 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5151 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5152 };
5153 
5154 struct mlx5_ifc_set_fte_out_bits {
5155 	u8         status[0x8];
5156 	u8         reserved_at_8[0x18];
5157 
5158 	u8         syndrome[0x20];
5159 
5160 	u8         reserved_at_40[0x40];
5161 };
5162 
5163 struct mlx5_ifc_set_fte_in_bits {
5164 	u8         opcode[0x10];
5165 	u8         reserved_at_10[0x10];
5166 
5167 	u8         reserved_at_20[0x10];
5168 	u8         op_mod[0x10];
5169 
5170 	u8         other_vport[0x1];
5171 	u8         reserved_at_41[0xf];
5172 	u8         vport_number[0x10];
5173 
5174 	u8         reserved_at_60[0x20];
5175 
5176 	u8         table_type[0x8];
5177 	u8         reserved_at_88[0x18];
5178 
5179 	u8         reserved_at_a0[0x8];
5180 	u8         table_id[0x18];
5181 
5182 	u8         ignore_flow_level[0x1];
5183 	u8         reserved_at_c1[0x17];
5184 	u8         modify_enable_mask[0x8];
5185 
5186 	u8         reserved_at_e0[0x20];
5187 
5188 	u8         flow_index[0x20];
5189 
5190 	u8         reserved_at_120[0xe0];
5191 
5192 	struct mlx5_ifc_flow_context_bits flow_context;
5193 };
5194 
5195 struct mlx5_ifc_dest_format_bits {
5196 	u8         destination_type[0x8];
5197 	u8         destination_id[0x18];
5198 
5199 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5200 	u8         packet_reformat[0x1];
5201 	u8         reserved_at_22[0xe];
5202 	u8         destination_eswitch_owner_vhca_id[0x10];
5203 };
5204 
5205 struct mlx5_ifc_rts2rts_qp_out_bits {
5206 	u8         status[0x8];
5207 	u8         reserved_at_8[0x18];
5208 
5209 	u8         syndrome[0x20];
5210 
5211 	u8         reserved_at_40[0x20];
5212 	u8         ece[0x20];
5213 };
5214 
5215 struct mlx5_ifc_rts2rts_qp_in_bits {
5216 	u8         opcode[0x10];
5217 	u8         uid[0x10];
5218 
5219 	u8         reserved_at_20[0x10];
5220 	u8         op_mod[0x10];
5221 
5222 	u8         reserved_at_40[0x8];
5223 	u8         qpn[0x18];
5224 
5225 	u8         reserved_at_60[0x20];
5226 
5227 	u8         opt_param_mask[0x20];
5228 
5229 	u8         ece[0x20];
5230 
5231 	struct mlx5_ifc_qpc_bits qpc;
5232 
5233 	u8         reserved_at_800[0x80];
5234 };
5235 
5236 struct mlx5_ifc_rtr2rts_qp_out_bits {
5237 	u8         status[0x8];
5238 	u8         reserved_at_8[0x18];
5239 
5240 	u8         syndrome[0x20];
5241 
5242 	u8         reserved_at_40[0x20];
5243 	u8         ece[0x20];
5244 };
5245 
5246 struct mlx5_ifc_rtr2rts_qp_in_bits {
5247 	u8         opcode[0x10];
5248 	u8         uid[0x10];
5249 
5250 	u8         reserved_at_20[0x10];
5251 	u8         op_mod[0x10];
5252 
5253 	u8         reserved_at_40[0x8];
5254 	u8         qpn[0x18];
5255 
5256 	u8         reserved_at_60[0x20];
5257 
5258 	u8         opt_param_mask[0x20];
5259 
5260 	u8         ece[0x20];
5261 
5262 	struct mlx5_ifc_qpc_bits qpc;
5263 
5264 	u8         reserved_at_800[0x80];
5265 };
5266 
5267 struct mlx5_ifc_rst2init_qp_out_bits {
5268 	u8         status[0x8];
5269 	u8         reserved_at_8[0x18];
5270 
5271 	u8         syndrome[0x20];
5272 
5273 	u8         reserved_at_40[0x20];
5274 	u8         ece[0x20];
5275 };
5276 
5277 struct mlx5_ifc_rst2init_qp_in_bits {
5278 	u8         opcode[0x10];
5279 	u8         uid[0x10];
5280 
5281 	u8         reserved_at_20[0x10];
5282 	u8         op_mod[0x10];
5283 
5284 	u8         reserved_at_40[0x8];
5285 	u8         qpn[0x18];
5286 
5287 	u8         reserved_at_60[0x20];
5288 
5289 	u8         opt_param_mask[0x20];
5290 
5291 	u8         ece[0x20];
5292 
5293 	struct mlx5_ifc_qpc_bits qpc;
5294 
5295 	u8         reserved_at_800[0x80];
5296 };
5297 
5298 struct mlx5_ifc_query_xrq_out_bits {
5299 	u8         status[0x8];
5300 	u8         reserved_at_8[0x18];
5301 
5302 	u8         syndrome[0x20];
5303 
5304 	u8         reserved_at_40[0x40];
5305 
5306 	struct mlx5_ifc_xrqc_bits xrq_context;
5307 };
5308 
5309 struct mlx5_ifc_query_xrq_in_bits {
5310 	u8         opcode[0x10];
5311 	u8         reserved_at_10[0x10];
5312 
5313 	u8         reserved_at_20[0x10];
5314 	u8         op_mod[0x10];
5315 
5316 	u8         reserved_at_40[0x8];
5317 	u8         xrqn[0x18];
5318 
5319 	u8         reserved_at_60[0x20];
5320 };
5321 
5322 struct mlx5_ifc_query_xrc_srq_out_bits {
5323 	u8         status[0x8];
5324 	u8         reserved_at_8[0x18];
5325 
5326 	u8         syndrome[0x20];
5327 
5328 	u8         reserved_at_40[0x40];
5329 
5330 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5331 
5332 	u8         reserved_at_280[0x600];
5333 
5334 	u8         pas[][0x40];
5335 };
5336 
5337 struct mlx5_ifc_query_xrc_srq_in_bits {
5338 	u8         opcode[0x10];
5339 	u8         reserved_at_10[0x10];
5340 
5341 	u8         reserved_at_20[0x10];
5342 	u8         op_mod[0x10];
5343 
5344 	u8         reserved_at_40[0x8];
5345 	u8         xrc_srqn[0x18];
5346 
5347 	u8         reserved_at_60[0x20];
5348 };
5349 
5350 enum {
5351 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5352 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5353 };
5354 
5355 struct mlx5_ifc_query_vport_state_out_bits {
5356 	u8         status[0x8];
5357 	u8         reserved_at_8[0x18];
5358 
5359 	u8         syndrome[0x20];
5360 
5361 	u8         reserved_at_40[0x20];
5362 
5363 	u8         reserved_at_60[0x18];
5364 	u8         admin_state[0x4];
5365 	u8         state[0x4];
5366 };
5367 
5368 struct mlx5_ifc_array1024_auto_bits {
5369 	u8         array1024_auto[32][0x20];
5370 };
5371 
5372 struct mlx5_ifc_query_vuid_in_bits {
5373 	u8         opcode[0x10];
5374 	u8         uid[0x10];
5375 
5376 	u8         reserved_at_20[0x40];
5377 
5378 	u8         query_vfs_vuid[0x1];
5379 	u8         data_direct[0x1];
5380 	u8         reserved_at_62[0xe];
5381 	u8         vhca_id[0x10];
5382 };
5383 
5384 struct mlx5_ifc_query_vuid_out_bits {
5385 	u8        status[0x8];
5386 	u8        reserved_at_8[0x18];
5387 
5388 	u8        syndrome[0x20];
5389 
5390 	u8        reserved_at_40[0x1a0];
5391 
5392 	u8        reserved_at_1e0[0x10];
5393 	u8        num_of_entries[0x10];
5394 
5395 	struct mlx5_ifc_array1024_auto_bits vuid[];
5396 };
5397 
5398 enum {
5399 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5400 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5401 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5402 };
5403 
5404 struct mlx5_ifc_arm_monitor_counter_in_bits {
5405 	u8         opcode[0x10];
5406 	u8         uid[0x10];
5407 
5408 	u8         reserved_at_20[0x10];
5409 	u8         op_mod[0x10];
5410 
5411 	u8         reserved_at_40[0x20];
5412 
5413 	u8         reserved_at_60[0x20];
5414 };
5415 
5416 struct mlx5_ifc_arm_monitor_counter_out_bits {
5417 	u8         status[0x8];
5418 	u8         reserved_at_8[0x18];
5419 
5420 	u8         syndrome[0x20];
5421 
5422 	u8         reserved_at_40[0x40];
5423 };
5424 
5425 enum {
5426 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5427 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5428 };
5429 
5430 enum mlx5_monitor_counter_ppcnt {
5431 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5432 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5433 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5434 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5435 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5436 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5437 };
5438 
5439 enum {
5440 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5441 };
5442 
5443 struct mlx5_ifc_monitor_counter_output_bits {
5444 	u8         reserved_at_0[0x4];
5445 	u8         type[0x4];
5446 	u8         reserved_at_8[0x8];
5447 	u8         counter[0x10];
5448 
5449 	u8         counter_group_id[0x20];
5450 };
5451 
5452 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5453 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5454 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5455 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5456 
5457 struct mlx5_ifc_set_monitor_counter_in_bits {
5458 	u8         opcode[0x10];
5459 	u8         uid[0x10];
5460 
5461 	u8         reserved_at_20[0x10];
5462 	u8         op_mod[0x10];
5463 
5464 	u8         reserved_at_40[0x10];
5465 	u8         num_of_counters[0x10];
5466 
5467 	u8         reserved_at_60[0x20];
5468 
5469 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5470 };
5471 
5472 struct mlx5_ifc_set_monitor_counter_out_bits {
5473 	u8         status[0x8];
5474 	u8         reserved_at_8[0x18];
5475 
5476 	u8         syndrome[0x20];
5477 
5478 	u8         reserved_at_40[0x40];
5479 };
5480 
5481 struct mlx5_ifc_query_vport_state_in_bits {
5482 	u8         opcode[0x10];
5483 	u8         reserved_at_10[0x10];
5484 
5485 	u8         reserved_at_20[0x10];
5486 	u8         op_mod[0x10];
5487 
5488 	u8         other_vport[0x1];
5489 	u8         reserved_at_41[0xf];
5490 	u8         vport_number[0x10];
5491 
5492 	u8         reserved_at_60[0x20];
5493 };
5494 
5495 struct mlx5_ifc_query_vnic_env_out_bits {
5496 	u8         status[0x8];
5497 	u8         reserved_at_8[0x18];
5498 
5499 	u8         syndrome[0x20];
5500 
5501 	u8         reserved_at_40[0x40];
5502 
5503 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5504 };
5505 
5506 enum {
5507 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5508 };
5509 
5510 struct mlx5_ifc_query_vnic_env_in_bits {
5511 	u8         opcode[0x10];
5512 	u8         reserved_at_10[0x10];
5513 
5514 	u8         reserved_at_20[0x10];
5515 	u8         op_mod[0x10];
5516 
5517 	u8         other_vport[0x1];
5518 	u8         reserved_at_41[0xf];
5519 	u8         vport_number[0x10];
5520 
5521 	u8         reserved_at_60[0x20];
5522 };
5523 
5524 struct mlx5_ifc_query_vport_counter_out_bits {
5525 	u8         status[0x8];
5526 	u8         reserved_at_8[0x18];
5527 
5528 	u8         syndrome[0x20];
5529 
5530 	u8         reserved_at_40[0x40];
5531 
5532 	struct mlx5_ifc_traffic_counter_bits received_errors;
5533 
5534 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5535 
5536 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5537 
5538 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5539 
5540 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5541 
5542 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5543 
5544 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5545 
5546 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5547 
5548 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5549 
5550 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5551 
5552 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5553 
5554 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5555 
5556 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5557 
5558 	u8         reserved_at_700[0x980];
5559 };
5560 
5561 enum {
5562 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5563 };
5564 
5565 struct mlx5_ifc_query_vport_counter_in_bits {
5566 	u8         opcode[0x10];
5567 	u8         reserved_at_10[0x10];
5568 
5569 	u8         reserved_at_20[0x10];
5570 	u8         op_mod[0x10];
5571 
5572 	u8         other_vport[0x1];
5573 	u8         reserved_at_41[0xb];
5574 	u8	   port_num[0x4];
5575 	u8         vport_number[0x10];
5576 
5577 	u8         reserved_at_60[0x60];
5578 
5579 	u8         clear[0x1];
5580 	u8         reserved_at_c1[0x1f];
5581 
5582 	u8         reserved_at_e0[0x20];
5583 };
5584 
5585 struct mlx5_ifc_query_tis_out_bits {
5586 	u8         status[0x8];
5587 	u8         reserved_at_8[0x18];
5588 
5589 	u8         syndrome[0x20];
5590 
5591 	u8         reserved_at_40[0x40];
5592 
5593 	struct mlx5_ifc_tisc_bits tis_context;
5594 };
5595 
5596 struct mlx5_ifc_query_tis_in_bits {
5597 	u8         opcode[0x10];
5598 	u8         reserved_at_10[0x10];
5599 
5600 	u8         reserved_at_20[0x10];
5601 	u8         op_mod[0x10];
5602 
5603 	u8         reserved_at_40[0x8];
5604 	u8         tisn[0x18];
5605 
5606 	u8         reserved_at_60[0x20];
5607 };
5608 
5609 struct mlx5_ifc_query_tir_out_bits {
5610 	u8         status[0x8];
5611 	u8         reserved_at_8[0x18];
5612 
5613 	u8         syndrome[0x20];
5614 
5615 	u8         reserved_at_40[0xc0];
5616 
5617 	struct mlx5_ifc_tirc_bits tir_context;
5618 };
5619 
5620 struct mlx5_ifc_query_tir_in_bits {
5621 	u8         opcode[0x10];
5622 	u8         reserved_at_10[0x10];
5623 
5624 	u8         reserved_at_20[0x10];
5625 	u8         op_mod[0x10];
5626 
5627 	u8         reserved_at_40[0x8];
5628 	u8         tirn[0x18];
5629 
5630 	u8         reserved_at_60[0x20];
5631 };
5632 
5633 struct mlx5_ifc_query_srq_out_bits {
5634 	u8         status[0x8];
5635 	u8         reserved_at_8[0x18];
5636 
5637 	u8         syndrome[0x20];
5638 
5639 	u8         reserved_at_40[0x40];
5640 
5641 	struct mlx5_ifc_srqc_bits srq_context_entry;
5642 
5643 	u8         reserved_at_280[0x600];
5644 
5645 	u8         pas[][0x40];
5646 };
5647 
5648 struct mlx5_ifc_query_srq_in_bits {
5649 	u8         opcode[0x10];
5650 	u8         reserved_at_10[0x10];
5651 
5652 	u8         reserved_at_20[0x10];
5653 	u8         op_mod[0x10];
5654 
5655 	u8         reserved_at_40[0x8];
5656 	u8         srqn[0x18];
5657 
5658 	u8         reserved_at_60[0x20];
5659 };
5660 
5661 struct mlx5_ifc_query_sq_out_bits {
5662 	u8         status[0x8];
5663 	u8         reserved_at_8[0x18];
5664 
5665 	u8         syndrome[0x20];
5666 
5667 	u8         reserved_at_40[0xc0];
5668 
5669 	struct mlx5_ifc_sqc_bits sq_context;
5670 };
5671 
5672 struct mlx5_ifc_query_sq_in_bits {
5673 	u8         opcode[0x10];
5674 	u8         reserved_at_10[0x10];
5675 
5676 	u8         reserved_at_20[0x10];
5677 	u8         op_mod[0x10];
5678 
5679 	u8         reserved_at_40[0x8];
5680 	u8         sqn[0x18];
5681 
5682 	u8         reserved_at_60[0x20];
5683 };
5684 
5685 struct mlx5_ifc_query_special_contexts_out_bits {
5686 	u8         status[0x8];
5687 	u8         reserved_at_8[0x18];
5688 
5689 	u8         syndrome[0x20];
5690 
5691 	u8         dump_fill_mkey[0x20];
5692 
5693 	u8         resd_lkey[0x20];
5694 
5695 	u8         null_mkey[0x20];
5696 
5697 	u8	   terminate_scatter_list_mkey[0x20];
5698 
5699 	u8	   repeated_mkey[0x20];
5700 
5701 	u8         reserved_at_a0[0x20];
5702 };
5703 
5704 struct mlx5_ifc_query_special_contexts_in_bits {
5705 	u8         opcode[0x10];
5706 	u8         reserved_at_10[0x10];
5707 
5708 	u8         reserved_at_20[0x10];
5709 	u8         op_mod[0x10];
5710 
5711 	u8         reserved_at_40[0x40];
5712 };
5713 
5714 struct mlx5_ifc_query_scheduling_element_out_bits {
5715 	u8         opcode[0x10];
5716 	u8         reserved_at_10[0x10];
5717 
5718 	u8         reserved_at_20[0x10];
5719 	u8         op_mod[0x10];
5720 
5721 	u8         reserved_at_40[0xc0];
5722 
5723 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5724 
5725 	u8         reserved_at_300[0x100];
5726 };
5727 
5728 enum {
5729 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5730 	SCHEDULING_HIERARCHY_NIC = 0x3,
5731 };
5732 
5733 struct mlx5_ifc_query_scheduling_element_in_bits {
5734 	u8         opcode[0x10];
5735 	u8         reserved_at_10[0x10];
5736 
5737 	u8         reserved_at_20[0x10];
5738 	u8         op_mod[0x10];
5739 
5740 	u8         scheduling_hierarchy[0x8];
5741 	u8         reserved_at_48[0x18];
5742 
5743 	u8         scheduling_element_id[0x20];
5744 
5745 	u8         reserved_at_80[0x180];
5746 };
5747 
5748 struct mlx5_ifc_query_rqt_out_bits {
5749 	u8         status[0x8];
5750 	u8         reserved_at_8[0x18];
5751 
5752 	u8         syndrome[0x20];
5753 
5754 	u8         reserved_at_40[0xc0];
5755 
5756 	struct mlx5_ifc_rqtc_bits rqt_context;
5757 };
5758 
5759 struct mlx5_ifc_query_rqt_in_bits {
5760 	u8         opcode[0x10];
5761 	u8         reserved_at_10[0x10];
5762 
5763 	u8         reserved_at_20[0x10];
5764 	u8         op_mod[0x10];
5765 
5766 	u8         reserved_at_40[0x8];
5767 	u8         rqtn[0x18];
5768 
5769 	u8         reserved_at_60[0x20];
5770 };
5771 
5772 struct mlx5_ifc_query_rq_out_bits {
5773 	u8         status[0x8];
5774 	u8         reserved_at_8[0x18];
5775 
5776 	u8         syndrome[0x20];
5777 
5778 	u8         reserved_at_40[0xc0];
5779 
5780 	struct mlx5_ifc_rqc_bits rq_context;
5781 };
5782 
5783 struct mlx5_ifc_query_rq_in_bits {
5784 	u8         opcode[0x10];
5785 	u8         reserved_at_10[0x10];
5786 
5787 	u8         reserved_at_20[0x10];
5788 	u8         op_mod[0x10];
5789 
5790 	u8         reserved_at_40[0x8];
5791 	u8         rqn[0x18];
5792 
5793 	u8         reserved_at_60[0x20];
5794 };
5795 
5796 struct mlx5_ifc_query_roce_address_out_bits {
5797 	u8         status[0x8];
5798 	u8         reserved_at_8[0x18];
5799 
5800 	u8         syndrome[0x20];
5801 
5802 	u8         reserved_at_40[0x40];
5803 
5804 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5805 };
5806 
5807 struct mlx5_ifc_query_roce_address_in_bits {
5808 	u8         opcode[0x10];
5809 	u8         reserved_at_10[0x10];
5810 
5811 	u8         reserved_at_20[0x10];
5812 	u8         op_mod[0x10];
5813 
5814 	u8         roce_address_index[0x10];
5815 	u8         reserved_at_50[0xc];
5816 	u8	   vhca_port_num[0x4];
5817 
5818 	u8         reserved_at_60[0x20];
5819 };
5820 
5821 struct mlx5_ifc_query_rmp_out_bits {
5822 	u8         status[0x8];
5823 	u8         reserved_at_8[0x18];
5824 
5825 	u8         syndrome[0x20];
5826 
5827 	u8         reserved_at_40[0xc0];
5828 
5829 	struct mlx5_ifc_rmpc_bits rmp_context;
5830 };
5831 
5832 struct mlx5_ifc_query_rmp_in_bits {
5833 	u8         opcode[0x10];
5834 	u8         reserved_at_10[0x10];
5835 
5836 	u8         reserved_at_20[0x10];
5837 	u8         op_mod[0x10];
5838 
5839 	u8         reserved_at_40[0x8];
5840 	u8         rmpn[0x18];
5841 
5842 	u8         reserved_at_60[0x20];
5843 };
5844 
5845 struct mlx5_ifc_cqe_error_syndrome_bits {
5846 	u8         hw_error_syndrome[0x8];
5847 	u8         hw_syndrome_type[0x4];
5848 	u8         reserved_at_c[0x4];
5849 	u8         vendor_error_syndrome[0x8];
5850 	u8         syndrome[0x8];
5851 };
5852 
5853 struct mlx5_ifc_qp_context_extension_bits {
5854 	u8         reserved_at_0[0x60];
5855 
5856 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5857 
5858 	u8         reserved_at_80[0x580];
5859 };
5860 
5861 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5862 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5863 
5864 	u8         pas[0][0x40];
5865 };
5866 
5867 struct mlx5_ifc_qp_pas_list_in_bits {
5868 	struct mlx5_ifc_cmd_pas_bits pas[0];
5869 };
5870 
5871 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5872 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5873 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5874 };
5875 
5876 struct mlx5_ifc_query_qp_out_bits {
5877 	u8         status[0x8];
5878 	u8         reserved_at_8[0x18];
5879 
5880 	u8         syndrome[0x20];
5881 
5882 	u8         reserved_at_40[0x40];
5883 
5884 	u8         opt_param_mask[0x20];
5885 
5886 	u8         ece[0x20];
5887 
5888 	struct mlx5_ifc_qpc_bits qpc;
5889 
5890 	u8         reserved_at_800[0x80];
5891 
5892 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5893 };
5894 
5895 struct mlx5_ifc_query_qp_in_bits {
5896 	u8         opcode[0x10];
5897 	u8         reserved_at_10[0x10];
5898 
5899 	u8         reserved_at_20[0x10];
5900 	u8         op_mod[0x10];
5901 
5902 	u8         qpc_ext[0x1];
5903 	u8         reserved_at_41[0x7];
5904 	u8         qpn[0x18];
5905 
5906 	u8         reserved_at_60[0x20];
5907 };
5908 
5909 struct mlx5_ifc_query_q_counter_out_bits {
5910 	u8         status[0x8];
5911 	u8         reserved_at_8[0x18];
5912 
5913 	u8         syndrome[0x20];
5914 
5915 	u8         reserved_at_40[0x40];
5916 
5917 	u8         rx_write_requests[0x20];
5918 
5919 	u8         reserved_at_a0[0x20];
5920 
5921 	u8         rx_read_requests[0x20];
5922 
5923 	u8         reserved_at_e0[0x20];
5924 
5925 	u8         rx_atomic_requests[0x20];
5926 
5927 	u8         reserved_at_120[0x20];
5928 
5929 	u8         rx_dct_connect[0x20];
5930 
5931 	u8         reserved_at_160[0x20];
5932 
5933 	u8         out_of_buffer[0x20];
5934 
5935 	u8         reserved_at_1a0[0x20];
5936 
5937 	u8         out_of_sequence[0x20];
5938 
5939 	u8         reserved_at_1e0[0x20];
5940 
5941 	u8         duplicate_request[0x20];
5942 
5943 	u8         reserved_at_220[0x20];
5944 
5945 	u8         rnr_nak_retry_err[0x20];
5946 
5947 	u8         reserved_at_260[0x20];
5948 
5949 	u8         packet_seq_err[0x20];
5950 
5951 	u8         reserved_at_2a0[0x20];
5952 
5953 	u8         implied_nak_seq_err[0x20];
5954 
5955 	u8         reserved_at_2e0[0x20];
5956 
5957 	u8         local_ack_timeout_err[0x20];
5958 
5959 	u8         reserved_at_320[0x60];
5960 
5961 	u8         req_rnr_retries_exceeded[0x20];
5962 
5963 	u8         reserved_at_3a0[0x20];
5964 
5965 	u8         resp_local_length_error[0x20];
5966 
5967 	u8         req_local_length_error[0x20];
5968 
5969 	u8         resp_local_qp_error[0x20];
5970 
5971 	u8         local_operation_error[0x20];
5972 
5973 	u8         resp_local_protection[0x20];
5974 
5975 	u8         req_local_protection[0x20];
5976 
5977 	u8         resp_cqe_error[0x20];
5978 
5979 	u8         req_cqe_error[0x20];
5980 
5981 	u8         req_mw_binding[0x20];
5982 
5983 	u8         req_bad_response[0x20];
5984 
5985 	u8         req_remote_invalid_request[0x20];
5986 
5987 	u8         resp_remote_invalid_request[0x20];
5988 
5989 	u8         req_remote_access_errors[0x20];
5990 
5991 	u8	   resp_remote_access_errors[0x20];
5992 
5993 	u8         req_remote_operation_errors[0x20];
5994 
5995 	u8         req_transport_retries_exceeded[0x20];
5996 
5997 	u8         cq_overflow[0x20];
5998 
5999 	u8         resp_cqe_flush_error[0x20];
6000 
6001 	u8         req_cqe_flush_error[0x20];
6002 
6003 	u8         reserved_at_620[0x20];
6004 
6005 	u8         roce_adp_retrans[0x20];
6006 
6007 	u8         roce_adp_retrans_to[0x20];
6008 
6009 	u8         roce_slow_restart[0x20];
6010 
6011 	u8         roce_slow_restart_cnps[0x20];
6012 
6013 	u8         roce_slow_restart_trans[0x20];
6014 
6015 	u8         reserved_at_6e0[0x120];
6016 };
6017 
6018 struct mlx5_ifc_query_q_counter_in_bits {
6019 	u8         opcode[0x10];
6020 	u8         reserved_at_10[0x10];
6021 
6022 	u8         reserved_at_20[0x10];
6023 	u8         op_mod[0x10];
6024 
6025 	u8         other_vport[0x1];
6026 	u8         reserved_at_41[0xf];
6027 	u8         vport_number[0x10];
6028 
6029 	u8         reserved_at_60[0x60];
6030 
6031 	u8         clear[0x1];
6032 	u8         aggregate[0x1];
6033 	u8         reserved_at_c2[0x1e];
6034 
6035 	u8         reserved_at_e0[0x18];
6036 	u8         counter_set_id[0x8];
6037 };
6038 
6039 struct mlx5_ifc_query_pages_out_bits {
6040 	u8         status[0x8];
6041 	u8         reserved_at_8[0x18];
6042 
6043 	u8         syndrome[0x20];
6044 
6045 	u8         embedded_cpu_function[0x1];
6046 	u8         reserved_at_41[0xf];
6047 	u8         function_id[0x10];
6048 
6049 	u8         num_pages[0x20];
6050 };
6051 
6052 enum {
6053 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6054 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6055 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6056 };
6057 
6058 struct mlx5_ifc_query_pages_in_bits {
6059 	u8         opcode[0x10];
6060 	u8         reserved_at_10[0x10];
6061 
6062 	u8         reserved_at_20[0x10];
6063 	u8         op_mod[0x10];
6064 
6065 	u8         embedded_cpu_function[0x1];
6066 	u8         reserved_at_41[0xf];
6067 	u8         function_id[0x10];
6068 
6069 	u8         reserved_at_60[0x20];
6070 };
6071 
6072 struct mlx5_ifc_query_nic_vport_context_out_bits {
6073 	u8         status[0x8];
6074 	u8         reserved_at_8[0x18];
6075 
6076 	u8         syndrome[0x20];
6077 
6078 	u8         reserved_at_40[0x40];
6079 
6080 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6081 };
6082 
6083 struct mlx5_ifc_query_nic_vport_context_in_bits {
6084 	u8         opcode[0x10];
6085 	u8         reserved_at_10[0x10];
6086 
6087 	u8         reserved_at_20[0x10];
6088 	u8         op_mod[0x10];
6089 
6090 	u8         other_vport[0x1];
6091 	u8         reserved_at_41[0xf];
6092 	u8         vport_number[0x10];
6093 
6094 	u8         reserved_at_60[0x5];
6095 	u8         allowed_list_type[0x3];
6096 	u8         reserved_at_68[0x18];
6097 };
6098 
6099 struct mlx5_ifc_query_mkey_out_bits {
6100 	u8         status[0x8];
6101 	u8         reserved_at_8[0x18];
6102 
6103 	u8         syndrome[0x20];
6104 
6105 	u8         reserved_at_40[0x40];
6106 
6107 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6108 
6109 	u8         reserved_at_280[0x600];
6110 
6111 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6112 
6113 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6114 };
6115 
6116 struct mlx5_ifc_query_mkey_in_bits {
6117 	u8         opcode[0x10];
6118 	u8         reserved_at_10[0x10];
6119 
6120 	u8         reserved_at_20[0x10];
6121 	u8         op_mod[0x10];
6122 
6123 	u8         reserved_at_40[0x8];
6124 	u8         mkey_index[0x18];
6125 
6126 	u8         pg_access[0x1];
6127 	u8         reserved_at_61[0x1f];
6128 };
6129 
6130 struct mlx5_ifc_query_mad_demux_out_bits {
6131 	u8         status[0x8];
6132 	u8         reserved_at_8[0x18];
6133 
6134 	u8         syndrome[0x20];
6135 
6136 	u8         reserved_at_40[0x40];
6137 
6138 	u8         mad_dumux_parameters_block[0x20];
6139 };
6140 
6141 struct mlx5_ifc_query_mad_demux_in_bits {
6142 	u8         opcode[0x10];
6143 	u8         reserved_at_10[0x10];
6144 
6145 	u8         reserved_at_20[0x10];
6146 	u8         op_mod[0x10];
6147 
6148 	u8         reserved_at_40[0x40];
6149 };
6150 
6151 struct mlx5_ifc_query_l2_table_entry_out_bits {
6152 	u8         status[0x8];
6153 	u8         reserved_at_8[0x18];
6154 
6155 	u8         syndrome[0x20];
6156 
6157 	u8         reserved_at_40[0xa0];
6158 
6159 	u8         reserved_at_e0[0x13];
6160 	u8         vlan_valid[0x1];
6161 	u8         vlan[0xc];
6162 
6163 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6164 
6165 	u8         reserved_at_140[0xc0];
6166 };
6167 
6168 struct mlx5_ifc_query_l2_table_entry_in_bits {
6169 	u8         opcode[0x10];
6170 	u8         reserved_at_10[0x10];
6171 
6172 	u8         reserved_at_20[0x10];
6173 	u8         op_mod[0x10];
6174 
6175 	u8         reserved_at_40[0x60];
6176 
6177 	u8         reserved_at_a0[0x8];
6178 	u8         table_index[0x18];
6179 
6180 	u8         reserved_at_c0[0x140];
6181 };
6182 
6183 struct mlx5_ifc_query_issi_out_bits {
6184 	u8         status[0x8];
6185 	u8         reserved_at_8[0x18];
6186 
6187 	u8         syndrome[0x20];
6188 
6189 	u8         reserved_at_40[0x10];
6190 	u8         current_issi[0x10];
6191 
6192 	u8         reserved_at_60[0xa0];
6193 
6194 	u8         reserved_at_100[76][0x8];
6195 	u8         supported_issi_dw0[0x20];
6196 };
6197 
6198 struct mlx5_ifc_query_issi_in_bits {
6199 	u8         opcode[0x10];
6200 	u8         reserved_at_10[0x10];
6201 
6202 	u8         reserved_at_20[0x10];
6203 	u8         op_mod[0x10];
6204 
6205 	u8         reserved_at_40[0x40];
6206 };
6207 
6208 struct mlx5_ifc_set_driver_version_out_bits {
6209 	u8         status[0x8];
6210 	u8         reserved_0[0x18];
6211 
6212 	u8         syndrome[0x20];
6213 	u8         reserved_1[0x40];
6214 };
6215 
6216 struct mlx5_ifc_set_driver_version_in_bits {
6217 	u8         opcode[0x10];
6218 	u8         reserved_0[0x10];
6219 
6220 	u8         reserved_1[0x10];
6221 	u8         op_mod[0x10];
6222 
6223 	u8         reserved_2[0x40];
6224 	u8         driver_version[64][0x8];
6225 };
6226 
6227 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6228 	u8         status[0x8];
6229 	u8         reserved_at_8[0x18];
6230 
6231 	u8         syndrome[0x20];
6232 
6233 	u8         reserved_at_40[0x40];
6234 
6235 	struct mlx5_ifc_pkey_bits pkey[];
6236 };
6237 
6238 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6239 	u8         opcode[0x10];
6240 	u8         reserved_at_10[0x10];
6241 
6242 	u8         reserved_at_20[0x10];
6243 	u8         op_mod[0x10];
6244 
6245 	u8         other_vport[0x1];
6246 	u8         reserved_at_41[0xb];
6247 	u8         port_num[0x4];
6248 	u8         vport_number[0x10];
6249 
6250 	u8         reserved_at_60[0x10];
6251 	u8         pkey_index[0x10];
6252 };
6253 
6254 enum {
6255 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6256 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6257 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6258 };
6259 
6260 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6261 	u8         status[0x8];
6262 	u8         reserved_at_8[0x18];
6263 
6264 	u8         syndrome[0x20];
6265 
6266 	u8         reserved_at_40[0x20];
6267 
6268 	u8         gids_num[0x10];
6269 	u8         reserved_at_70[0x10];
6270 
6271 	struct mlx5_ifc_array128_auto_bits gid[];
6272 };
6273 
6274 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6275 	u8         opcode[0x10];
6276 	u8         reserved_at_10[0x10];
6277 
6278 	u8         reserved_at_20[0x10];
6279 	u8         op_mod[0x10];
6280 
6281 	u8         other_vport[0x1];
6282 	u8         reserved_at_41[0xb];
6283 	u8         port_num[0x4];
6284 	u8         vport_number[0x10];
6285 
6286 	u8         reserved_at_60[0x10];
6287 	u8         gid_index[0x10];
6288 };
6289 
6290 struct mlx5_ifc_query_hca_vport_context_out_bits {
6291 	u8         status[0x8];
6292 	u8         reserved_at_8[0x18];
6293 
6294 	u8         syndrome[0x20];
6295 
6296 	u8         reserved_at_40[0x40];
6297 
6298 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6299 };
6300 
6301 struct mlx5_ifc_query_hca_vport_context_in_bits {
6302 	u8         opcode[0x10];
6303 	u8         reserved_at_10[0x10];
6304 
6305 	u8         reserved_at_20[0x10];
6306 	u8         op_mod[0x10];
6307 
6308 	u8         other_vport[0x1];
6309 	u8         reserved_at_41[0xb];
6310 	u8         port_num[0x4];
6311 	u8         vport_number[0x10];
6312 
6313 	u8         reserved_at_60[0x20];
6314 };
6315 
6316 struct mlx5_ifc_query_hca_cap_out_bits {
6317 	u8         status[0x8];
6318 	u8         reserved_at_8[0x18];
6319 
6320 	u8         syndrome[0x20];
6321 
6322 	u8         reserved_at_40[0x40];
6323 
6324 	union mlx5_ifc_hca_cap_union_bits capability;
6325 };
6326 
6327 struct mlx5_ifc_query_hca_cap_in_bits {
6328 	u8         opcode[0x10];
6329 	u8         reserved_at_10[0x10];
6330 
6331 	u8         reserved_at_20[0x10];
6332 	u8         op_mod[0x10];
6333 
6334 	u8         other_function[0x1];
6335 	u8         ec_vf_function[0x1];
6336 	u8         reserved_at_42[0xe];
6337 	u8         function_id[0x10];
6338 
6339 	u8         reserved_at_60[0x20];
6340 };
6341 
6342 struct mlx5_ifc_other_hca_cap_bits {
6343 	u8         roce[0x1];
6344 	u8         reserved_at_1[0x27f];
6345 };
6346 
6347 struct mlx5_ifc_query_other_hca_cap_out_bits {
6348 	u8         status[0x8];
6349 	u8         reserved_at_8[0x18];
6350 
6351 	u8         syndrome[0x20];
6352 
6353 	u8         reserved_at_40[0x40];
6354 
6355 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6356 };
6357 
6358 struct mlx5_ifc_query_other_hca_cap_in_bits {
6359 	u8         opcode[0x10];
6360 	u8         reserved_at_10[0x10];
6361 
6362 	u8         reserved_at_20[0x10];
6363 	u8         op_mod[0x10];
6364 
6365 	u8         reserved_at_40[0x10];
6366 	u8         function_id[0x10];
6367 
6368 	u8         reserved_at_60[0x20];
6369 };
6370 
6371 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6372 	u8         status[0x8];
6373 	u8         reserved_at_8[0x18];
6374 
6375 	u8         syndrome[0x20];
6376 
6377 	u8         reserved_at_40[0x40];
6378 };
6379 
6380 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6381 	u8         opcode[0x10];
6382 	u8         reserved_at_10[0x10];
6383 
6384 	u8         reserved_at_20[0x10];
6385 	u8         op_mod[0x10];
6386 
6387 	u8         reserved_at_40[0x10];
6388 	u8         function_id[0x10];
6389 	u8         field_select[0x20];
6390 
6391 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6392 };
6393 
6394 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6395 	u8         sw_owner_icm_root_1[0x40];
6396 
6397 	u8         sw_owner_icm_root_0[0x40];
6398 };
6399 
6400 struct mlx5_ifc_rtc_params_bits {
6401 	u8         rtc_id_0[0x20];
6402 
6403 	u8         rtc_id_1[0x20];
6404 
6405 	u8         reserved_at_40[0x40];
6406 };
6407 
6408 struct mlx5_ifc_flow_table_context_bits {
6409 	u8         reformat_en[0x1];
6410 	u8         decap_en[0x1];
6411 	u8         sw_owner[0x1];
6412 	u8         termination_table[0x1];
6413 	u8         table_miss_action[0x4];
6414 	u8         level[0x8];
6415 	u8         rtc_valid[0x1];
6416 	u8         reserved_at_11[0x7];
6417 	u8         log_size[0x8];
6418 
6419 	u8         reserved_at_20[0x8];
6420 	u8         table_miss_id[0x18];
6421 
6422 	u8         reserved_at_40[0x8];
6423 	u8         lag_master_next_table_id[0x18];
6424 
6425 	u8         reserved_at_60[0x60];
6426 
6427 	union {
6428 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6429 		struct mlx5_ifc_rtc_params_bits hws;
6430 	};
6431 };
6432 
6433 struct mlx5_ifc_query_flow_table_out_bits {
6434 	u8         status[0x8];
6435 	u8         reserved_at_8[0x18];
6436 
6437 	u8         syndrome[0x20];
6438 
6439 	u8         reserved_at_40[0x80];
6440 
6441 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6442 };
6443 
6444 struct mlx5_ifc_query_flow_table_in_bits {
6445 	u8         opcode[0x10];
6446 	u8         reserved_at_10[0x10];
6447 
6448 	u8         reserved_at_20[0x10];
6449 	u8         op_mod[0x10];
6450 
6451 	u8         reserved_at_40[0x40];
6452 
6453 	u8         table_type[0x8];
6454 	u8         reserved_at_88[0x18];
6455 
6456 	u8         reserved_at_a0[0x8];
6457 	u8         table_id[0x18];
6458 
6459 	u8         reserved_at_c0[0x140];
6460 };
6461 
6462 struct mlx5_ifc_query_fte_out_bits {
6463 	u8         status[0x8];
6464 	u8         reserved_at_8[0x18];
6465 
6466 	u8         syndrome[0x20];
6467 
6468 	u8         reserved_at_40[0x1c0];
6469 
6470 	struct mlx5_ifc_flow_context_bits flow_context;
6471 };
6472 
6473 struct mlx5_ifc_query_fte_in_bits {
6474 	u8         opcode[0x10];
6475 	u8         reserved_at_10[0x10];
6476 
6477 	u8         reserved_at_20[0x10];
6478 	u8         op_mod[0x10];
6479 
6480 	u8         reserved_at_40[0x40];
6481 
6482 	u8         table_type[0x8];
6483 	u8         reserved_at_88[0x18];
6484 
6485 	u8         reserved_at_a0[0x8];
6486 	u8         table_id[0x18];
6487 
6488 	u8         reserved_at_c0[0x40];
6489 
6490 	u8         flow_index[0x20];
6491 
6492 	u8         reserved_at_120[0xe0];
6493 };
6494 
6495 struct mlx5_ifc_match_definer_format_0_bits {
6496 	u8         reserved_at_0[0x100];
6497 
6498 	u8         metadata_reg_c_0[0x20];
6499 
6500 	u8         metadata_reg_c_1[0x20];
6501 
6502 	u8         outer_dmac_47_16[0x20];
6503 
6504 	u8         outer_dmac_15_0[0x10];
6505 	u8         outer_ethertype[0x10];
6506 
6507 	u8         reserved_at_180[0x1];
6508 	u8         sx_sniffer[0x1];
6509 	u8         functional_lb[0x1];
6510 	u8         outer_ip_frag[0x1];
6511 	u8         outer_qp_type[0x2];
6512 	u8         outer_encap_type[0x2];
6513 	u8         port_number[0x2];
6514 	u8         outer_l3_type[0x2];
6515 	u8         outer_l4_type[0x2];
6516 	u8         outer_first_vlan_type[0x2];
6517 	u8         outer_first_vlan_prio[0x3];
6518 	u8         outer_first_vlan_cfi[0x1];
6519 	u8         outer_first_vlan_vid[0xc];
6520 
6521 	u8         outer_l4_type_ext[0x4];
6522 	u8         reserved_at_1a4[0x2];
6523 	u8         outer_ipsec_layer[0x2];
6524 	u8         outer_l2_type[0x2];
6525 	u8         force_lb[0x1];
6526 	u8         outer_l2_ok[0x1];
6527 	u8         outer_l3_ok[0x1];
6528 	u8         outer_l4_ok[0x1];
6529 	u8         outer_second_vlan_type[0x2];
6530 	u8         outer_second_vlan_prio[0x3];
6531 	u8         outer_second_vlan_cfi[0x1];
6532 	u8         outer_second_vlan_vid[0xc];
6533 
6534 	u8         outer_smac_47_16[0x20];
6535 
6536 	u8         outer_smac_15_0[0x10];
6537 	u8         inner_ipv4_checksum_ok[0x1];
6538 	u8         inner_l4_checksum_ok[0x1];
6539 	u8         outer_ipv4_checksum_ok[0x1];
6540 	u8         outer_l4_checksum_ok[0x1];
6541 	u8         inner_l3_ok[0x1];
6542 	u8         inner_l4_ok[0x1];
6543 	u8         outer_l3_ok_duplicate[0x1];
6544 	u8         outer_l4_ok_duplicate[0x1];
6545 	u8         outer_tcp_cwr[0x1];
6546 	u8         outer_tcp_ece[0x1];
6547 	u8         outer_tcp_urg[0x1];
6548 	u8         outer_tcp_ack[0x1];
6549 	u8         outer_tcp_psh[0x1];
6550 	u8         outer_tcp_rst[0x1];
6551 	u8         outer_tcp_syn[0x1];
6552 	u8         outer_tcp_fin[0x1];
6553 };
6554 
6555 struct mlx5_ifc_match_definer_format_22_bits {
6556 	u8         reserved_at_0[0x100];
6557 
6558 	u8         outer_ip_src_addr[0x20];
6559 
6560 	u8         outer_ip_dest_addr[0x20];
6561 
6562 	u8         outer_l4_sport[0x10];
6563 	u8         outer_l4_dport[0x10];
6564 
6565 	u8         reserved_at_160[0x1];
6566 	u8         sx_sniffer[0x1];
6567 	u8         functional_lb[0x1];
6568 	u8         outer_ip_frag[0x1];
6569 	u8         outer_qp_type[0x2];
6570 	u8         outer_encap_type[0x2];
6571 	u8         port_number[0x2];
6572 	u8         outer_l3_type[0x2];
6573 	u8         outer_l4_type[0x2];
6574 	u8         outer_first_vlan_type[0x2];
6575 	u8         outer_first_vlan_prio[0x3];
6576 	u8         outer_first_vlan_cfi[0x1];
6577 	u8         outer_first_vlan_vid[0xc];
6578 
6579 	u8         metadata_reg_c_0[0x20];
6580 
6581 	u8         outer_dmac_47_16[0x20];
6582 
6583 	u8         outer_smac_47_16[0x20];
6584 
6585 	u8         outer_smac_15_0[0x10];
6586 	u8         outer_dmac_15_0[0x10];
6587 };
6588 
6589 struct mlx5_ifc_match_definer_format_23_bits {
6590 	u8         reserved_at_0[0x100];
6591 
6592 	u8         inner_ip_src_addr[0x20];
6593 
6594 	u8         inner_ip_dest_addr[0x20];
6595 
6596 	u8         inner_l4_sport[0x10];
6597 	u8         inner_l4_dport[0x10];
6598 
6599 	u8         reserved_at_160[0x1];
6600 	u8         sx_sniffer[0x1];
6601 	u8         functional_lb[0x1];
6602 	u8         inner_ip_frag[0x1];
6603 	u8         inner_qp_type[0x2];
6604 	u8         inner_encap_type[0x2];
6605 	u8         port_number[0x2];
6606 	u8         inner_l3_type[0x2];
6607 	u8         inner_l4_type[0x2];
6608 	u8         inner_first_vlan_type[0x2];
6609 	u8         inner_first_vlan_prio[0x3];
6610 	u8         inner_first_vlan_cfi[0x1];
6611 	u8         inner_first_vlan_vid[0xc];
6612 
6613 	u8         tunnel_header_0[0x20];
6614 
6615 	u8         inner_dmac_47_16[0x20];
6616 
6617 	u8         inner_smac_47_16[0x20];
6618 
6619 	u8         inner_smac_15_0[0x10];
6620 	u8         inner_dmac_15_0[0x10];
6621 };
6622 
6623 struct mlx5_ifc_match_definer_format_29_bits {
6624 	u8         reserved_at_0[0xc0];
6625 
6626 	u8         outer_ip_dest_addr[0x80];
6627 
6628 	u8         outer_ip_src_addr[0x80];
6629 
6630 	u8         outer_l4_sport[0x10];
6631 	u8         outer_l4_dport[0x10];
6632 
6633 	u8         reserved_at_1e0[0x20];
6634 };
6635 
6636 struct mlx5_ifc_match_definer_format_30_bits {
6637 	u8         reserved_at_0[0xa0];
6638 
6639 	u8         outer_ip_dest_addr[0x80];
6640 
6641 	u8         outer_ip_src_addr[0x80];
6642 
6643 	u8         outer_dmac_47_16[0x20];
6644 
6645 	u8         outer_smac_47_16[0x20];
6646 
6647 	u8         outer_smac_15_0[0x10];
6648 	u8         outer_dmac_15_0[0x10];
6649 };
6650 
6651 struct mlx5_ifc_match_definer_format_31_bits {
6652 	u8         reserved_at_0[0xc0];
6653 
6654 	u8         inner_ip_dest_addr[0x80];
6655 
6656 	u8         inner_ip_src_addr[0x80];
6657 
6658 	u8         inner_l4_sport[0x10];
6659 	u8         inner_l4_dport[0x10];
6660 
6661 	u8         reserved_at_1e0[0x20];
6662 };
6663 
6664 struct mlx5_ifc_match_definer_format_32_bits {
6665 	u8         reserved_at_0[0xa0];
6666 
6667 	u8         inner_ip_dest_addr[0x80];
6668 
6669 	u8         inner_ip_src_addr[0x80];
6670 
6671 	u8         inner_dmac_47_16[0x20];
6672 
6673 	u8         inner_smac_47_16[0x20];
6674 
6675 	u8         inner_smac_15_0[0x10];
6676 	u8         inner_dmac_15_0[0x10];
6677 };
6678 
6679 enum {
6680 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6681 };
6682 
6683 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6684 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6685 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6686 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6687 
6688 struct mlx5_ifc_match_definer_match_mask_bits {
6689 	u8         reserved_at_1c0[5][0x20];
6690 	u8         match_dw_8[0x20];
6691 	u8         match_dw_7[0x20];
6692 	u8         match_dw_6[0x20];
6693 	u8         match_dw_5[0x20];
6694 	u8         match_dw_4[0x20];
6695 	u8         match_dw_3[0x20];
6696 	u8         match_dw_2[0x20];
6697 	u8         match_dw_1[0x20];
6698 	u8         match_dw_0[0x20];
6699 
6700 	u8         match_byte_7[0x8];
6701 	u8         match_byte_6[0x8];
6702 	u8         match_byte_5[0x8];
6703 	u8         match_byte_4[0x8];
6704 
6705 	u8         match_byte_3[0x8];
6706 	u8         match_byte_2[0x8];
6707 	u8         match_byte_1[0x8];
6708 	u8         match_byte_0[0x8];
6709 };
6710 
6711 struct mlx5_ifc_match_definer_bits {
6712 	u8         modify_field_select[0x40];
6713 
6714 	u8         reserved_at_40[0x40];
6715 
6716 	u8         reserved_at_80[0x10];
6717 	u8         format_id[0x10];
6718 
6719 	u8         reserved_at_a0[0x60];
6720 
6721 	u8         format_select_dw3[0x8];
6722 	u8         format_select_dw2[0x8];
6723 	u8         format_select_dw1[0x8];
6724 	u8         format_select_dw0[0x8];
6725 
6726 	u8         format_select_dw7[0x8];
6727 	u8         format_select_dw6[0x8];
6728 	u8         format_select_dw5[0x8];
6729 	u8         format_select_dw4[0x8];
6730 
6731 	u8         reserved_at_100[0x18];
6732 	u8         format_select_dw8[0x8];
6733 
6734 	u8         reserved_at_120[0x20];
6735 
6736 	u8         format_select_byte3[0x8];
6737 	u8         format_select_byte2[0x8];
6738 	u8         format_select_byte1[0x8];
6739 	u8         format_select_byte0[0x8];
6740 
6741 	u8         format_select_byte7[0x8];
6742 	u8         format_select_byte6[0x8];
6743 	u8         format_select_byte5[0x8];
6744 	u8         format_select_byte4[0x8];
6745 
6746 	u8         reserved_at_180[0x40];
6747 
6748 	union {
6749 		struct {
6750 			u8         match_mask[16][0x20];
6751 		};
6752 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6753 	};
6754 };
6755 
6756 struct mlx5_ifc_general_obj_create_param_bits {
6757 	u8         alias_object[0x1];
6758 	u8         reserved_at_1[0x2];
6759 	u8         log_obj_range[0x5];
6760 	u8         reserved_at_8[0x18];
6761 };
6762 
6763 struct mlx5_ifc_general_obj_query_param_bits {
6764 	u8         alias_object[0x1];
6765 	u8         obj_offset[0x1f];
6766 };
6767 
6768 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6769 	u8         opcode[0x10];
6770 	u8         uid[0x10];
6771 
6772 	u8         vhca_tunnel_id[0x10];
6773 	u8         obj_type[0x10];
6774 
6775 	u8         obj_id[0x20];
6776 
6777 	union {
6778 		struct mlx5_ifc_general_obj_create_param_bits create;
6779 		struct mlx5_ifc_general_obj_query_param_bits query;
6780 	} op_param;
6781 };
6782 
6783 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6784 	u8         status[0x8];
6785 	u8         reserved_at_8[0x18];
6786 
6787 	u8         syndrome[0x20];
6788 
6789 	u8         obj_id[0x20];
6790 
6791 	u8         reserved_at_60[0x20];
6792 };
6793 
6794 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6795 	u8 opcode[0x10];
6796 	u8 uid[0x10];
6797 	u8 reserved_at_20[0x10];
6798 	u8 op_mod[0x10];
6799 	u8 reserved_at_40[0x50];
6800 	u8 object_type_to_be_accessed[0x10];
6801 	u8 object_id_to_be_accessed[0x20];
6802 	u8 reserved_at_c0[0x40];
6803 	union {
6804 		u8 access_key_raw[0x100];
6805 		u8 access_key[8][0x20];
6806 	};
6807 };
6808 
6809 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6810 	u8 status[0x8];
6811 	u8 reserved_at_8[0x18];
6812 	u8 syndrome[0x20];
6813 	u8 reserved_at_40[0x40];
6814 };
6815 
6816 struct mlx5_ifc_modify_header_arg_bits {
6817 	u8         reserved_at_0[0x80];
6818 
6819 	u8         reserved_at_80[0x8];
6820 	u8         access_pd[0x18];
6821 };
6822 
6823 struct mlx5_ifc_create_modify_header_arg_in_bits {
6824 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6825 	struct mlx5_ifc_modify_header_arg_bits arg;
6826 };
6827 
6828 struct mlx5_ifc_create_match_definer_in_bits {
6829 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6830 
6831 	struct mlx5_ifc_match_definer_bits obj_context;
6832 };
6833 
6834 struct mlx5_ifc_create_match_definer_out_bits {
6835 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6836 };
6837 
6838 struct mlx5_ifc_alias_context_bits {
6839 	u8 vhca_id_to_be_accessed[0x10];
6840 	u8 reserved_at_10[0xd];
6841 	u8 status[0x3];
6842 	u8 object_id_to_be_accessed[0x20];
6843 	u8 reserved_at_40[0x40];
6844 	union {
6845 		u8 access_key_raw[0x100];
6846 		u8 access_key[8][0x20];
6847 	};
6848 	u8 metadata[0x80];
6849 };
6850 
6851 struct mlx5_ifc_create_alias_obj_in_bits {
6852 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6853 	struct mlx5_ifc_alias_context_bits alias_ctx;
6854 };
6855 
6856 enum {
6857 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6858 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6859 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6860 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6861 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6862 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6863 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6864 };
6865 
6866 struct mlx5_ifc_query_flow_group_out_bits {
6867 	u8         status[0x8];
6868 	u8         reserved_at_8[0x18];
6869 
6870 	u8         syndrome[0x20];
6871 
6872 	u8         reserved_at_40[0xa0];
6873 
6874 	u8         start_flow_index[0x20];
6875 
6876 	u8         reserved_at_100[0x20];
6877 
6878 	u8         end_flow_index[0x20];
6879 
6880 	u8         reserved_at_140[0xa0];
6881 
6882 	u8         reserved_at_1e0[0x18];
6883 	u8         match_criteria_enable[0x8];
6884 
6885 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6886 
6887 	u8         reserved_at_1200[0xe00];
6888 };
6889 
6890 struct mlx5_ifc_query_flow_group_in_bits {
6891 	u8         opcode[0x10];
6892 	u8         reserved_at_10[0x10];
6893 
6894 	u8         reserved_at_20[0x10];
6895 	u8         op_mod[0x10];
6896 
6897 	u8         reserved_at_40[0x40];
6898 
6899 	u8         table_type[0x8];
6900 	u8         reserved_at_88[0x18];
6901 
6902 	u8         reserved_at_a0[0x8];
6903 	u8         table_id[0x18];
6904 
6905 	u8         group_id[0x20];
6906 
6907 	u8         reserved_at_e0[0x120];
6908 };
6909 
6910 struct mlx5_ifc_query_flow_counter_out_bits {
6911 	u8         status[0x8];
6912 	u8         reserved_at_8[0x18];
6913 
6914 	u8         syndrome[0x20];
6915 
6916 	u8         reserved_at_40[0x40];
6917 
6918 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6919 };
6920 
6921 struct mlx5_ifc_query_flow_counter_in_bits {
6922 	u8         opcode[0x10];
6923 	u8         reserved_at_10[0x10];
6924 
6925 	u8         reserved_at_20[0x10];
6926 	u8         op_mod[0x10];
6927 
6928 	u8         reserved_at_40[0x80];
6929 
6930 	u8         clear[0x1];
6931 	u8         reserved_at_c1[0xf];
6932 	u8         num_of_counters[0x10];
6933 
6934 	u8         flow_counter_id[0x20];
6935 };
6936 
6937 struct mlx5_ifc_query_esw_vport_context_out_bits {
6938 	u8         status[0x8];
6939 	u8         reserved_at_8[0x18];
6940 
6941 	u8         syndrome[0x20];
6942 
6943 	u8         reserved_at_40[0x40];
6944 
6945 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6946 };
6947 
6948 struct mlx5_ifc_query_esw_vport_context_in_bits {
6949 	u8         opcode[0x10];
6950 	u8         reserved_at_10[0x10];
6951 
6952 	u8         reserved_at_20[0x10];
6953 	u8         op_mod[0x10];
6954 
6955 	u8         other_vport[0x1];
6956 	u8         reserved_at_41[0xf];
6957 	u8         vport_number[0x10];
6958 
6959 	u8         reserved_at_60[0x20];
6960 };
6961 
6962 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6963 	u8         status[0x8];
6964 	u8         reserved_at_8[0x18];
6965 
6966 	u8         syndrome[0x20];
6967 
6968 	u8         reserved_at_40[0x40];
6969 };
6970 
6971 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6972 	u8         reserved_at_0[0x1b];
6973 	u8         fdb_to_vport_reg_c_id[0x1];
6974 	u8         vport_cvlan_insert[0x1];
6975 	u8         vport_svlan_insert[0x1];
6976 	u8         vport_cvlan_strip[0x1];
6977 	u8         vport_svlan_strip[0x1];
6978 };
6979 
6980 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6981 	u8         opcode[0x10];
6982 	u8         reserved_at_10[0x10];
6983 
6984 	u8         reserved_at_20[0x10];
6985 	u8         op_mod[0x10];
6986 
6987 	u8         other_vport[0x1];
6988 	u8         reserved_at_41[0xf];
6989 	u8         vport_number[0x10];
6990 
6991 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6992 
6993 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6994 };
6995 
6996 struct mlx5_ifc_query_eq_out_bits {
6997 	u8         status[0x8];
6998 	u8         reserved_at_8[0x18];
6999 
7000 	u8         syndrome[0x20];
7001 
7002 	u8         reserved_at_40[0x40];
7003 
7004 	struct mlx5_ifc_eqc_bits eq_context_entry;
7005 
7006 	u8         reserved_at_280[0x40];
7007 
7008 	u8         event_bitmask[0x40];
7009 
7010 	u8         reserved_at_300[0x580];
7011 
7012 	u8         pas[][0x40];
7013 };
7014 
7015 struct mlx5_ifc_query_eq_in_bits {
7016 	u8         opcode[0x10];
7017 	u8         reserved_at_10[0x10];
7018 
7019 	u8         reserved_at_20[0x10];
7020 	u8         op_mod[0x10];
7021 
7022 	u8         reserved_at_40[0x18];
7023 	u8         eq_number[0x8];
7024 
7025 	u8         reserved_at_60[0x20];
7026 };
7027 
7028 struct mlx5_ifc_packet_reformat_context_in_bits {
7029 	u8         reformat_type[0x8];
7030 	u8         reserved_at_8[0x4];
7031 	u8         reformat_param_0[0x4];
7032 	u8         reserved_at_10[0x6];
7033 	u8         reformat_data_size[0xa];
7034 
7035 	u8         reformat_param_1[0x8];
7036 	u8         reserved_at_28[0x8];
7037 	u8         reformat_data[2][0x8];
7038 
7039 	u8         more_reformat_data[][0x8];
7040 };
7041 
7042 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7043 	u8         status[0x8];
7044 	u8         reserved_at_8[0x18];
7045 
7046 	u8         syndrome[0x20];
7047 
7048 	u8         reserved_at_40[0xa0];
7049 
7050 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7051 };
7052 
7053 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7054 	u8         opcode[0x10];
7055 	u8         reserved_at_10[0x10];
7056 
7057 	u8         reserved_at_20[0x10];
7058 	u8         op_mod[0x10];
7059 
7060 	u8         packet_reformat_id[0x20];
7061 
7062 	u8         reserved_at_60[0xa0];
7063 };
7064 
7065 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7066 	u8         status[0x8];
7067 	u8         reserved_at_8[0x18];
7068 
7069 	u8         syndrome[0x20];
7070 
7071 	u8         packet_reformat_id[0x20];
7072 
7073 	u8         reserved_at_60[0x20];
7074 };
7075 
7076 enum {
7077 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7078 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7079 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7080 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7081 };
7082 
7083 enum mlx5_reformat_ctx_type {
7084 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7085 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7086 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7087 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7088 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7089 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7090 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7091 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7092 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7093 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7094 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7095 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7096 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7097 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7098 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7099 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7100 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7101 };
7102 
7103 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7104 	u8         opcode[0x10];
7105 	u8         reserved_at_10[0x10];
7106 
7107 	u8         reserved_at_20[0x10];
7108 	u8         op_mod[0x10];
7109 
7110 	u8         reserved_at_40[0xa0];
7111 
7112 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7113 };
7114 
7115 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7116 	u8         status[0x8];
7117 	u8         reserved_at_8[0x18];
7118 
7119 	u8         syndrome[0x20];
7120 
7121 	u8         reserved_at_40[0x40];
7122 };
7123 
7124 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7125 	u8         opcode[0x10];
7126 	u8         reserved_at_10[0x10];
7127 
7128 	u8         reserved_20[0x10];
7129 	u8         op_mod[0x10];
7130 
7131 	u8         packet_reformat_id[0x20];
7132 
7133 	u8         reserved_60[0x20];
7134 };
7135 
7136 struct mlx5_ifc_set_action_in_bits {
7137 	u8         action_type[0x4];
7138 	u8         field[0xc];
7139 	u8         reserved_at_10[0x3];
7140 	u8         offset[0x5];
7141 	u8         reserved_at_18[0x3];
7142 	u8         length[0x5];
7143 
7144 	u8         data[0x20];
7145 };
7146 
7147 struct mlx5_ifc_add_action_in_bits {
7148 	u8         action_type[0x4];
7149 	u8         field[0xc];
7150 	u8         reserved_at_10[0x10];
7151 
7152 	u8         data[0x20];
7153 };
7154 
7155 struct mlx5_ifc_copy_action_in_bits {
7156 	u8         action_type[0x4];
7157 	u8         src_field[0xc];
7158 	u8         reserved_at_10[0x3];
7159 	u8         src_offset[0x5];
7160 	u8         reserved_at_18[0x3];
7161 	u8         length[0x5];
7162 
7163 	u8         reserved_at_20[0x4];
7164 	u8         dst_field[0xc];
7165 	u8         reserved_at_30[0x3];
7166 	u8         dst_offset[0x5];
7167 	u8         reserved_at_38[0x8];
7168 };
7169 
7170 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7171 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7172 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7173 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7174 	u8         reserved_at_0[0x40];
7175 };
7176 
7177 enum {
7178 	MLX5_ACTION_TYPE_SET   = 0x1,
7179 	MLX5_ACTION_TYPE_ADD   = 0x2,
7180 	MLX5_ACTION_TYPE_COPY  = 0x3,
7181 };
7182 
7183 enum {
7184 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7185 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7186 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7187 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7188 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7189 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7190 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7191 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7192 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7193 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7194 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7195 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7196 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7197 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7198 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7199 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7200 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7201 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7202 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7203 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7204 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7205 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7206 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7207 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7208 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7209 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7210 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7211 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7212 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7213 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7214 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7215 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7216 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7217 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7218 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7219 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7220 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7221 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7222 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7223 };
7224 
7225 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7226 	u8         status[0x8];
7227 	u8         reserved_at_8[0x18];
7228 
7229 	u8         syndrome[0x20];
7230 
7231 	u8         modify_header_id[0x20];
7232 
7233 	u8         reserved_at_60[0x20];
7234 };
7235 
7236 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7237 	u8         opcode[0x10];
7238 	u8         reserved_at_10[0x10];
7239 
7240 	u8         reserved_at_20[0x10];
7241 	u8         op_mod[0x10];
7242 
7243 	u8         reserved_at_40[0x20];
7244 
7245 	u8         table_type[0x8];
7246 	u8         reserved_at_68[0x10];
7247 	u8         num_of_actions[0x8];
7248 
7249 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7250 };
7251 
7252 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7253 	u8         status[0x8];
7254 	u8         reserved_at_8[0x18];
7255 
7256 	u8         syndrome[0x20];
7257 
7258 	u8         reserved_at_40[0x40];
7259 };
7260 
7261 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7262 	u8         opcode[0x10];
7263 	u8         reserved_at_10[0x10];
7264 
7265 	u8         reserved_at_20[0x10];
7266 	u8         op_mod[0x10];
7267 
7268 	u8         modify_header_id[0x20];
7269 
7270 	u8         reserved_at_60[0x20];
7271 };
7272 
7273 struct mlx5_ifc_query_modify_header_context_in_bits {
7274 	u8         opcode[0x10];
7275 	u8         uid[0x10];
7276 
7277 	u8         reserved_at_20[0x10];
7278 	u8         op_mod[0x10];
7279 
7280 	u8         modify_header_id[0x20];
7281 
7282 	u8         reserved_at_60[0xa0];
7283 };
7284 
7285 struct mlx5_ifc_query_dct_out_bits {
7286 	u8         status[0x8];
7287 	u8         reserved_at_8[0x18];
7288 
7289 	u8         syndrome[0x20];
7290 
7291 	u8         reserved_at_40[0x40];
7292 
7293 	struct mlx5_ifc_dctc_bits dct_context_entry;
7294 
7295 	u8         reserved_at_280[0x180];
7296 };
7297 
7298 struct mlx5_ifc_query_dct_in_bits {
7299 	u8         opcode[0x10];
7300 	u8         reserved_at_10[0x10];
7301 
7302 	u8         reserved_at_20[0x10];
7303 	u8         op_mod[0x10];
7304 
7305 	u8         reserved_at_40[0x8];
7306 	u8         dctn[0x18];
7307 
7308 	u8         reserved_at_60[0x20];
7309 };
7310 
7311 struct mlx5_ifc_query_cq_out_bits {
7312 	u8         status[0x8];
7313 	u8         reserved_at_8[0x18];
7314 
7315 	u8         syndrome[0x20];
7316 
7317 	u8         reserved_at_40[0x40];
7318 
7319 	struct mlx5_ifc_cqc_bits cq_context;
7320 
7321 	u8         reserved_at_280[0x600];
7322 
7323 	u8         pas[][0x40];
7324 };
7325 
7326 struct mlx5_ifc_query_cq_in_bits {
7327 	u8         opcode[0x10];
7328 	u8         reserved_at_10[0x10];
7329 
7330 	u8         reserved_at_20[0x10];
7331 	u8         op_mod[0x10];
7332 
7333 	u8         reserved_at_40[0x8];
7334 	u8         cqn[0x18];
7335 
7336 	u8         reserved_at_60[0x20];
7337 };
7338 
7339 struct mlx5_ifc_query_cong_status_out_bits {
7340 	u8         status[0x8];
7341 	u8         reserved_at_8[0x18];
7342 
7343 	u8         syndrome[0x20];
7344 
7345 	u8         reserved_at_40[0x20];
7346 
7347 	u8         enable[0x1];
7348 	u8         tag_enable[0x1];
7349 	u8         reserved_at_62[0x1e];
7350 };
7351 
7352 struct mlx5_ifc_query_cong_status_in_bits {
7353 	u8         opcode[0x10];
7354 	u8         reserved_at_10[0x10];
7355 
7356 	u8         reserved_at_20[0x10];
7357 	u8         op_mod[0x10];
7358 
7359 	u8         reserved_at_40[0x18];
7360 	u8         priority[0x4];
7361 	u8         cong_protocol[0x4];
7362 
7363 	u8         reserved_at_60[0x20];
7364 };
7365 
7366 struct mlx5_ifc_query_cong_statistics_out_bits {
7367 	u8         status[0x8];
7368 	u8         reserved_at_8[0x18];
7369 
7370 	u8         syndrome[0x20];
7371 
7372 	u8         reserved_at_40[0x40];
7373 
7374 	u8         rp_cur_flows[0x20];
7375 
7376 	u8         sum_flows[0x20];
7377 
7378 	u8         rp_cnp_ignored_high[0x20];
7379 
7380 	u8         rp_cnp_ignored_low[0x20];
7381 
7382 	u8         rp_cnp_handled_high[0x20];
7383 
7384 	u8         rp_cnp_handled_low[0x20];
7385 
7386 	u8         reserved_at_140[0x100];
7387 
7388 	u8         time_stamp_high[0x20];
7389 
7390 	u8         time_stamp_low[0x20];
7391 
7392 	u8         accumulators_period[0x20];
7393 
7394 	u8         np_ecn_marked_roce_packets_high[0x20];
7395 
7396 	u8         np_ecn_marked_roce_packets_low[0x20];
7397 
7398 	u8         np_cnp_sent_high[0x20];
7399 
7400 	u8         np_cnp_sent_low[0x20];
7401 
7402 	u8         reserved_at_320[0x560];
7403 };
7404 
7405 struct mlx5_ifc_query_cong_statistics_in_bits {
7406 	u8         opcode[0x10];
7407 	u8         reserved_at_10[0x10];
7408 
7409 	u8         reserved_at_20[0x10];
7410 	u8         op_mod[0x10];
7411 
7412 	u8         clear[0x1];
7413 	u8         reserved_at_41[0x1f];
7414 
7415 	u8         reserved_at_60[0x20];
7416 };
7417 
7418 struct mlx5_ifc_query_cong_params_out_bits {
7419 	u8         status[0x8];
7420 	u8         reserved_at_8[0x18];
7421 
7422 	u8         syndrome[0x20];
7423 
7424 	u8         reserved_at_40[0x40];
7425 
7426 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7427 };
7428 
7429 struct mlx5_ifc_query_cong_params_in_bits {
7430 	u8         opcode[0x10];
7431 	u8         reserved_at_10[0x10];
7432 
7433 	u8         reserved_at_20[0x10];
7434 	u8         op_mod[0x10];
7435 
7436 	u8         reserved_at_40[0x1c];
7437 	u8         cong_protocol[0x4];
7438 
7439 	u8         reserved_at_60[0x20];
7440 };
7441 
7442 struct mlx5_ifc_query_adapter_out_bits {
7443 	u8         status[0x8];
7444 	u8         reserved_at_8[0x18];
7445 
7446 	u8         syndrome[0x20];
7447 
7448 	u8         reserved_at_40[0x40];
7449 
7450 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7451 };
7452 
7453 struct mlx5_ifc_query_adapter_in_bits {
7454 	u8         opcode[0x10];
7455 	u8         reserved_at_10[0x10];
7456 
7457 	u8         reserved_at_20[0x10];
7458 	u8         op_mod[0x10];
7459 
7460 	u8         reserved_at_40[0x40];
7461 };
7462 
7463 struct mlx5_ifc_qp_2rst_out_bits {
7464 	u8         status[0x8];
7465 	u8         reserved_at_8[0x18];
7466 
7467 	u8         syndrome[0x20];
7468 
7469 	u8         reserved_at_40[0x40];
7470 };
7471 
7472 struct mlx5_ifc_qp_2rst_in_bits {
7473 	u8         opcode[0x10];
7474 	u8         uid[0x10];
7475 
7476 	u8         reserved_at_20[0x10];
7477 	u8         op_mod[0x10];
7478 
7479 	u8         reserved_at_40[0x8];
7480 	u8         qpn[0x18];
7481 
7482 	u8         reserved_at_60[0x20];
7483 };
7484 
7485 struct mlx5_ifc_qp_2err_out_bits {
7486 	u8         status[0x8];
7487 	u8         reserved_at_8[0x18];
7488 
7489 	u8         syndrome[0x20];
7490 
7491 	u8         reserved_at_40[0x40];
7492 };
7493 
7494 struct mlx5_ifc_qp_2err_in_bits {
7495 	u8         opcode[0x10];
7496 	u8         uid[0x10];
7497 
7498 	u8         reserved_at_20[0x10];
7499 	u8         op_mod[0x10];
7500 
7501 	u8         reserved_at_40[0x8];
7502 	u8         qpn[0x18];
7503 
7504 	u8         reserved_at_60[0x20];
7505 };
7506 
7507 struct mlx5_ifc_trans_page_fault_info_bits {
7508 	u8         error[0x1];
7509 	u8         reserved_at_1[0x4];
7510 	u8         page_fault_type[0x3];
7511 	u8         wq_number[0x18];
7512 
7513 	u8         reserved_at_20[0x8];
7514 	u8         fault_token[0x18];
7515 };
7516 
7517 struct mlx5_ifc_mem_page_fault_info_bits {
7518 	u8          error[0x1];
7519 	u8          reserved_at_1[0xf];
7520 	u8          fault_token_47_32[0x10];
7521 
7522 	u8          fault_token_31_0[0x20];
7523 };
7524 
7525 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7526 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7527 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7528 	u8          reserved_at_0[0x40];
7529 };
7530 
7531 struct mlx5_ifc_page_fault_resume_out_bits {
7532 	u8         status[0x8];
7533 	u8         reserved_at_8[0x18];
7534 
7535 	u8         syndrome[0x20];
7536 
7537 	u8         reserved_at_40[0x40];
7538 };
7539 
7540 struct mlx5_ifc_page_fault_resume_in_bits {
7541 	u8         opcode[0x10];
7542 	u8         reserved_at_10[0x10];
7543 
7544 	u8         reserved_at_20[0x10];
7545 	u8         op_mod[0x10];
7546 
7547 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7548 		page_fault_info;
7549 };
7550 
7551 struct mlx5_ifc_nop_out_bits {
7552 	u8         status[0x8];
7553 	u8         reserved_at_8[0x18];
7554 
7555 	u8         syndrome[0x20];
7556 
7557 	u8         reserved_at_40[0x40];
7558 };
7559 
7560 struct mlx5_ifc_nop_in_bits {
7561 	u8         opcode[0x10];
7562 	u8         reserved_at_10[0x10];
7563 
7564 	u8         reserved_at_20[0x10];
7565 	u8         op_mod[0x10];
7566 
7567 	u8         reserved_at_40[0x40];
7568 };
7569 
7570 struct mlx5_ifc_modify_vport_state_out_bits {
7571 	u8         status[0x8];
7572 	u8         reserved_at_8[0x18];
7573 
7574 	u8         syndrome[0x20];
7575 
7576 	u8         reserved_at_40[0x40];
7577 };
7578 
7579 struct mlx5_ifc_modify_vport_state_in_bits {
7580 	u8         opcode[0x10];
7581 	u8         reserved_at_10[0x10];
7582 
7583 	u8         reserved_at_20[0x10];
7584 	u8         op_mod[0x10];
7585 
7586 	u8         other_vport[0x1];
7587 	u8         reserved_at_41[0xf];
7588 	u8         vport_number[0x10];
7589 
7590 	u8         reserved_at_60[0x18];
7591 	u8         admin_state[0x4];
7592 	u8         reserved_at_7c[0x4];
7593 };
7594 
7595 struct mlx5_ifc_modify_tis_out_bits {
7596 	u8         status[0x8];
7597 	u8         reserved_at_8[0x18];
7598 
7599 	u8         syndrome[0x20];
7600 
7601 	u8         reserved_at_40[0x40];
7602 };
7603 
7604 struct mlx5_ifc_modify_tis_bitmask_bits {
7605 	u8         reserved_at_0[0x20];
7606 
7607 	u8         reserved_at_20[0x1d];
7608 	u8         lag_tx_port_affinity[0x1];
7609 	u8         strict_lag_tx_port_affinity[0x1];
7610 	u8         prio[0x1];
7611 };
7612 
7613 struct mlx5_ifc_modify_tis_in_bits {
7614 	u8         opcode[0x10];
7615 	u8         uid[0x10];
7616 
7617 	u8         reserved_at_20[0x10];
7618 	u8         op_mod[0x10];
7619 
7620 	u8         reserved_at_40[0x8];
7621 	u8         tisn[0x18];
7622 
7623 	u8         reserved_at_60[0x20];
7624 
7625 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7626 
7627 	u8         reserved_at_c0[0x40];
7628 
7629 	struct mlx5_ifc_tisc_bits ctx;
7630 };
7631 
7632 struct mlx5_ifc_modify_tir_bitmask_bits {
7633 	u8	   reserved_at_0[0x20];
7634 
7635 	u8         reserved_at_20[0x1b];
7636 	u8         self_lb_en[0x1];
7637 	u8         reserved_at_3c[0x1];
7638 	u8         hash[0x1];
7639 	u8         reserved_at_3e[0x1];
7640 	u8         packet_merge[0x1];
7641 };
7642 
7643 struct mlx5_ifc_modify_tir_out_bits {
7644 	u8         status[0x8];
7645 	u8         reserved_at_8[0x18];
7646 
7647 	u8         syndrome[0x20];
7648 
7649 	u8         reserved_at_40[0x40];
7650 };
7651 
7652 struct mlx5_ifc_modify_tir_in_bits {
7653 	u8         opcode[0x10];
7654 	u8         uid[0x10];
7655 
7656 	u8         reserved_at_20[0x10];
7657 	u8         op_mod[0x10];
7658 
7659 	u8         reserved_at_40[0x8];
7660 	u8         tirn[0x18];
7661 
7662 	u8         reserved_at_60[0x20];
7663 
7664 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7665 
7666 	u8         reserved_at_c0[0x40];
7667 
7668 	struct mlx5_ifc_tirc_bits ctx;
7669 };
7670 
7671 struct mlx5_ifc_modify_sq_out_bits {
7672 	u8         status[0x8];
7673 	u8         reserved_at_8[0x18];
7674 
7675 	u8         syndrome[0x20];
7676 
7677 	u8         reserved_at_40[0x40];
7678 };
7679 
7680 struct mlx5_ifc_modify_sq_in_bits {
7681 	u8         opcode[0x10];
7682 	u8         uid[0x10];
7683 
7684 	u8         reserved_at_20[0x10];
7685 	u8         op_mod[0x10];
7686 
7687 	u8         sq_state[0x4];
7688 	u8         reserved_at_44[0x4];
7689 	u8         sqn[0x18];
7690 
7691 	u8         reserved_at_60[0x20];
7692 
7693 	u8         modify_bitmask[0x40];
7694 
7695 	u8         reserved_at_c0[0x40];
7696 
7697 	struct mlx5_ifc_sqc_bits ctx;
7698 };
7699 
7700 struct mlx5_ifc_modify_scheduling_element_out_bits {
7701 	u8         status[0x8];
7702 	u8         reserved_at_8[0x18];
7703 
7704 	u8         syndrome[0x20];
7705 
7706 	u8         reserved_at_40[0x1c0];
7707 };
7708 
7709 enum {
7710 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7711 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7712 };
7713 
7714 struct mlx5_ifc_modify_scheduling_element_in_bits {
7715 	u8         opcode[0x10];
7716 	u8         reserved_at_10[0x10];
7717 
7718 	u8         reserved_at_20[0x10];
7719 	u8         op_mod[0x10];
7720 
7721 	u8         scheduling_hierarchy[0x8];
7722 	u8         reserved_at_48[0x18];
7723 
7724 	u8         scheduling_element_id[0x20];
7725 
7726 	u8         reserved_at_80[0x20];
7727 
7728 	u8         modify_bitmask[0x20];
7729 
7730 	u8         reserved_at_c0[0x40];
7731 
7732 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7733 
7734 	u8         reserved_at_300[0x100];
7735 };
7736 
7737 struct mlx5_ifc_modify_rqt_out_bits {
7738 	u8         status[0x8];
7739 	u8         reserved_at_8[0x18];
7740 
7741 	u8         syndrome[0x20];
7742 
7743 	u8         reserved_at_40[0x40];
7744 };
7745 
7746 struct mlx5_ifc_rqt_bitmask_bits {
7747 	u8	   reserved_at_0[0x20];
7748 
7749 	u8         reserved_at_20[0x1f];
7750 	u8         rqn_list[0x1];
7751 };
7752 
7753 struct mlx5_ifc_modify_rqt_in_bits {
7754 	u8         opcode[0x10];
7755 	u8         uid[0x10];
7756 
7757 	u8         reserved_at_20[0x10];
7758 	u8         op_mod[0x10];
7759 
7760 	u8         reserved_at_40[0x8];
7761 	u8         rqtn[0x18];
7762 
7763 	u8         reserved_at_60[0x20];
7764 
7765 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7766 
7767 	u8         reserved_at_c0[0x40];
7768 
7769 	struct mlx5_ifc_rqtc_bits ctx;
7770 };
7771 
7772 struct mlx5_ifc_modify_rq_out_bits {
7773 	u8         status[0x8];
7774 	u8         reserved_at_8[0x18];
7775 
7776 	u8         syndrome[0x20];
7777 
7778 	u8         reserved_at_40[0x40];
7779 };
7780 
7781 enum {
7782 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7783 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7784 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7785 };
7786 
7787 struct mlx5_ifc_modify_rq_in_bits {
7788 	u8         opcode[0x10];
7789 	u8         uid[0x10];
7790 
7791 	u8         reserved_at_20[0x10];
7792 	u8         op_mod[0x10];
7793 
7794 	u8         rq_state[0x4];
7795 	u8         reserved_at_44[0x4];
7796 	u8         rqn[0x18];
7797 
7798 	u8         reserved_at_60[0x20];
7799 
7800 	u8         modify_bitmask[0x40];
7801 
7802 	u8         reserved_at_c0[0x40];
7803 
7804 	struct mlx5_ifc_rqc_bits ctx;
7805 };
7806 
7807 struct mlx5_ifc_modify_rmp_out_bits {
7808 	u8         status[0x8];
7809 	u8         reserved_at_8[0x18];
7810 
7811 	u8         syndrome[0x20];
7812 
7813 	u8         reserved_at_40[0x40];
7814 };
7815 
7816 struct mlx5_ifc_rmp_bitmask_bits {
7817 	u8	   reserved_at_0[0x20];
7818 
7819 	u8         reserved_at_20[0x1f];
7820 	u8         lwm[0x1];
7821 };
7822 
7823 struct mlx5_ifc_modify_rmp_in_bits {
7824 	u8         opcode[0x10];
7825 	u8         uid[0x10];
7826 
7827 	u8         reserved_at_20[0x10];
7828 	u8         op_mod[0x10];
7829 
7830 	u8         rmp_state[0x4];
7831 	u8         reserved_at_44[0x4];
7832 	u8         rmpn[0x18];
7833 
7834 	u8         reserved_at_60[0x20];
7835 
7836 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7837 
7838 	u8         reserved_at_c0[0x40];
7839 
7840 	struct mlx5_ifc_rmpc_bits ctx;
7841 };
7842 
7843 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7844 	u8         status[0x8];
7845 	u8         reserved_at_8[0x18];
7846 
7847 	u8         syndrome[0x20];
7848 
7849 	u8         reserved_at_40[0x40];
7850 };
7851 
7852 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7853 	u8         reserved_at_0[0x12];
7854 	u8	   affiliation[0x1];
7855 	u8	   reserved_at_13[0x1];
7856 	u8         disable_uc_local_lb[0x1];
7857 	u8         disable_mc_local_lb[0x1];
7858 	u8         node_guid[0x1];
7859 	u8         port_guid[0x1];
7860 	u8         min_inline[0x1];
7861 	u8         mtu[0x1];
7862 	u8         change_event[0x1];
7863 	u8         promisc[0x1];
7864 	u8         permanent_address[0x1];
7865 	u8         addresses_list[0x1];
7866 	u8         roce_en[0x1];
7867 	u8         reserved_at_1f[0x1];
7868 };
7869 
7870 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7871 	u8         opcode[0x10];
7872 	u8         reserved_at_10[0x10];
7873 
7874 	u8         reserved_at_20[0x10];
7875 	u8         op_mod[0x10];
7876 
7877 	u8         other_vport[0x1];
7878 	u8         reserved_at_41[0xf];
7879 	u8         vport_number[0x10];
7880 
7881 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7882 
7883 	u8         reserved_at_80[0x780];
7884 
7885 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7886 };
7887 
7888 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7889 	u8         status[0x8];
7890 	u8         reserved_at_8[0x18];
7891 
7892 	u8         syndrome[0x20];
7893 
7894 	u8         reserved_at_40[0x40];
7895 };
7896 
7897 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7898 	u8         opcode[0x10];
7899 	u8         reserved_at_10[0x10];
7900 
7901 	u8         reserved_at_20[0x10];
7902 	u8         op_mod[0x10];
7903 
7904 	u8         other_vport[0x1];
7905 	u8         reserved_at_41[0xb];
7906 	u8         port_num[0x4];
7907 	u8         vport_number[0x10];
7908 
7909 	u8         reserved_at_60[0x20];
7910 
7911 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7912 };
7913 
7914 struct mlx5_ifc_modify_cq_out_bits {
7915 	u8         status[0x8];
7916 	u8         reserved_at_8[0x18];
7917 
7918 	u8         syndrome[0x20];
7919 
7920 	u8         reserved_at_40[0x40];
7921 };
7922 
7923 enum {
7924 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7925 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7926 };
7927 
7928 struct mlx5_ifc_modify_cq_in_bits {
7929 	u8         opcode[0x10];
7930 	u8         uid[0x10];
7931 
7932 	u8         reserved_at_20[0x10];
7933 	u8         op_mod[0x10];
7934 
7935 	u8         reserved_at_40[0x8];
7936 	u8         cqn[0x18];
7937 
7938 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7939 
7940 	struct mlx5_ifc_cqc_bits cq_context;
7941 
7942 	u8         reserved_at_280[0x60];
7943 
7944 	u8         cq_umem_valid[0x1];
7945 	u8         reserved_at_2e1[0x1f];
7946 
7947 	u8         reserved_at_300[0x580];
7948 
7949 	u8         pas[][0x40];
7950 };
7951 
7952 struct mlx5_ifc_modify_cong_status_out_bits {
7953 	u8         status[0x8];
7954 	u8         reserved_at_8[0x18];
7955 
7956 	u8         syndrome[0x20];
7957 
7958 	u8         reserved_at_40[0x40];
7959 };
7960 
7961 struct mlx5_ifc_modify_cong_status_in_bits {
7962 	u8         opcode[0x10];
7963 	u8         reserved_at_10[0x10];
7964 
7965 	u8         reserved_at_20[0x10];
7966 	u8         op_mod[0x10];
7967 
7968 	u8         reserved_at_40[0x18];
7969 	u8         priority[0x4];
7970 	u8         cong_protocol[0x4];
7971 
7972 	u8         enable[0x1];
7973 	u8         tag_enable[0x1];
7974 	u8         reserved_at_62[0x1e];
7975 };
7976 
7977 struct mlx5_ifc_modify_cong_params_out_bits {
7978 	u8         status[0x8];
7979 	u8         reserved_at_8[0x18];
7980 
7981 	u8         syndrome[0x20];
7982 
7983 	u8         reserved_at_40[0x40];
7984 };
7985 
7986 struct mlx5_ifc_modify_cong_params_in_bits {
7987 	u8         opcode[0x10];
7988 	u8         reserved_at_10[0x10];
7989 
7990 	u8         reserved_at_20[0x10];
7991 	u8         op_mod[0x10];
7992 
7993 	u8         reserved_at_40[0x1c];
7994 	u8         cong_protocol[0x4];
7995 
7996 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7997 
7998 	u8         reserved_at_80[0x80];
7999 
8000 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8001 };
8002 
8003 struct mlx5_ifc_manage_pages_out_bits {
8004 	u8         status[0x8];
8005 	u8         reserved_at_8[0x18];
8006 
8007 	u8         syndrome[0x20];
8008 
8009 	u8         output_num_entries[0x20];
8010 
8011 	u8         reserved_at_60[0x20];
8012 
8013 	u8         pas[][0x40];
8014 };
8015 
8016 enum {
8017 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8018 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8019 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8020 };
8021 
8022 struct mlx5_ifc_manage_pages_in_bits {
8023 	u8         opcode[0x10];
8024 	u8         reserved_at_10[0x10];
8025 
8026 	u8         reserved_at_20[0x10];
8027 	u8         op_mod[0x10];
8028 
8029 	u8         embedded_cpu_function[0x1];
8030 	u8         reserved_at_41[0xf];
8031 	u8         function_id[0x10];
8032 
8033 	u8         input_num_entries[0x20];
8034 
8035 	u8         pas[][0x40];
8036 };
8037 
8038 struct mlx5_ifc_mad_ifc_out_bits {
8039 	u8         status[0x8];
8040 	u8         reserved_at_8[0x18];
8041 
8042 	u8         syndrome[0x20];
8043 
8044 	u8         reserved_at_40[0x40];
8045 
8046 	u8         response_mad_packet[256][0x8];
8047 };
8048 
8049 struct mlx5_ifc_mad_ifc_in_bits {
8050 	u8         opcode[0x10];
8051 	u8         reserved_at_10[0x10];
8052 
8053 	u8         reserved_at_20[0x10];
8054 	u8         op_mod[0x10];
8055 
8056 	u8         remote_lid[0x10];
8057 	u8         plane_index[0x8];
8058 	u8         port[0x8];
8059 
8060 	u8         reserved_at_60[0x20];
8061 
8062 	u8         mad[256][0x8];
8063 };
8064 
8065 struct mlx5_ifc_init_hca_out_bits {
8066 	u8         status[0x8];
8067 	u8         reserved_at_8[0x18];
8068 
8069 	u8         syndrome[0x20];
8070 
8071 	u8         reserved_at_40[0x40];
8072 };
8073 
8074 struct mlx5_ifc_init_hca_in_bits {
8075 	u8         opcode[0x10];
8076 	u8         reserved_at_10[0x10];
8077 
8078 	u8         reserved_at_20[0x10];
8079 	u8         op_mod[0x10];
8080 
8081 	u8         reserved_at_40[0x20];
8082 
8083 	u8         reserved_at_60[0x2];
8084 	u8         sw_vhca_id[0xe];
8085 	u8         reserved_at_70[0x10];
8086 
8087 	u8	   sw_owner_id[4][0x20];
8088 };
8089 
8090 struct mlx5_ifc_init2rtr_qp_out_bits {
8091 	u8         status[0x8];
8092 	u8         reserved_at_8[0x18];
8093 
8094 	u8         syndrome[0x20];
8095 
8096 	u8         reserved_at_40[0x20];
8097 	u8         ece[0x20];
8098 };
8099 
8100 struct mlx5_ifc_init2rtr_qp_in_bits {
8101 	u8         opcode[0x10];
8102 	u8         uid[0x10];
8103 
8104 	u8         reserved_at_20[0x10];
8105 	u8         op_mod[0x10];
8106 
8107 	u8         reserved_at_40[0x8];
8108 	u8         qpn[0x18];
8109 
8110 	u8         reserved_at_60[0x20];
8111 
8112 	u8         opt_param_mask[0x20];
8113 
8114 	u8         ece[0x20];
8115 
8116 	struct mlx5_ifc_qpc_bits qpc;
8117 
8118 	u8         reserved_at_800[0x80];
8119 };
8120 
8121 struct mlx5_ifc_init2init_qp_out_bits {
8122 	u8         status[0x8];
8123 	u8         reserved_at_8[0x18];
8124 
8125 	u8         syndrome[0x20];
8126 
8127 	u8         reserved_at_40[0x20];
8128 	u8         ece[0x20];
8129 };
8130 
8131 struct mlx5_ifc_init2init_qp_in_bits {
8132 	u8         opcode[0x10];
8133 	u8         uid[0x10];
8134 
8135 	u8         reserved_at_20[0x10];
8136 	u8         op_mod[0x10];
8137 
8138 	u8         reserved_at_40[0x8];
8139 	u8         qpn[0x18];
8140 
8141 	u8         reserved_at_60[0x20];
8142 
8143 	u8         opt_param_mask[0x20];
8144 
8145 	u8         ece[0x20];
8146 
8147 	struct mlx5_ifc_qpc_bits qpc;
8148 
8149 	u8         reserved_at_800[0x80];
8150 };
8151 
8152 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8153 	u8         status[0x8];
8154 	u8         reserved_at_8[0x18];
8155 
8156 	u8         syndrome[0x20];
8157 
8158 	u8         reserved_at_40[0x40];
8159 
8160 	u8         packet_headers_log[128][0x8];
8161 
8162 	u8         packet_syndrome[64][0x8];
8163 };
8164 
8165 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8166 	u8         opcode[0x10];
8167 	u8         reserved_at_10[0x10];
8168 
8169 	u8         reserved_at_20[0x10];
8170 	u8         op_mod[0x10];
8171 
8172 	u8         reserved_at_40[0x40];
8173 };
8174 
8175 struct mlx5_ifc_gen_eqe_in_bits {
8176 	u8         opcode[0x10];
8177 	u8         reserved_at_10[0x10];
8178 
8179 	u8         reserved_at_20[0x10];
8180 	u8         op_mod[0x10];
8181 
8182 	u8         reserved_at_40[0x18];
8183 	u8         eq_number[0x8];
8184 
8185 	u8         reserved_at_60[0x20];
8186 
8187 	u8         eqe[64][0x8];
8188 };
8189 
8190 struct mlx5_ifc_gen_eq_out_bits {
8191 	u8         status[0x8];
8192 	u8         reserved_at_8[0x18];
8193 
8194 	u8         syndrome[0x20];
8195 
8196 	u8         reserved_at_40[0x40];
8197 };
8198 
8199 struct mlx5_ifc_enable_hca_out_bits {
8200 	u8         status[0x8];
8201 	u8         reserved_at_8[0x18];
8202 
8203 	u8         syndrome[0x20];
8204 
8205 	u8         reserved_at_40[0x20];
8206 };
8207 
8208 struct mlx5_ifc_enable_hca_in_bits {
8209 	u8         opcode[0x10];
8210 	u8         reserved_at_10[0x10];
8211 
8212 	u8         reserved_at_20[0x10];
8213 	u8         op_mod[0x10];
8214 
8215 	u8         embedded_cpu_function[0x1];
8216 	u8         reserved_at_41[0xf];
8217 	u8         function_id[0x10];
8218 
8219 	u8         reserved_at_60[0x20];
8220 };
8221 
8222 struct mlx5_ifc_drain_dct_out_bits {
8223 	u8         status[0x8];
8224 	u8         reserved_at_8[0x18];
8225 
8226 	u8         syndrome[0x20];
8227 
8228 	u8         reserved_at_40[0x40];
8229 };
8230 
8231 struct mlx5_ifc_drain_dct_in_bits {
8232 	u8         opcode[0x10];
8233 	u8         uid[0x10];
8234 
8235 	u8         reserved_at_20[0x10];
8236 	u8         op_mod[0x10];
8237 
8238 	u8         reserved_at_40[0x8];
8239 	u8         dctn[0x18];
8240 
8241 	u8         reserved_at_60[0x20];
8242 };
8243 
8244 struct mlx5_ifc_disable_hca_out_bits {
8245 	u8         status[0x8];
8246 	u8         reserved_at_8[0x18];
8247 
8248 	u8         syndrome[0x20];
8249 
8250 	u8         reserved_at_40[0x20];
8251 };
8252 
8253 struct mlx5_ifc_disable_hca_in_bits {
8254 	u8         opcode[0x10];
8255 	u8         reserved_at_10[0x10];
8256 
8257 	u8         reserved_at_20[0x10];
8258 	u8         op_mod[0x10];
8259 
8260 	u8         embedded_cpu_function[0x1];
8261 	u8         reserved_at_41[0xf];
8262 	u8         function_id[0x10];
8263 
8264 	u8         reserved_at_60[0x20];
8265 };
8266 
8267 struct mlx5_ifc_detach_from_mcg_out_bits {
8268 	u8         status[0x8];
8269 	u8         reserved_at_8[0x18];
8270 
8271 	u8         syndrome[0x20];
8272 
8273 	u8         reserved_at_40[0x40];
8274 };
8275 
8276 struct mlx5_ifc_detach_from_mcg_in_bits {
8277 	u8         opcode[0x10];
8278 	u8         uid[0x10];
8279 
8280 	u8         reserved_at_20[0x10];
8281 	u8         op_mod[0x10];
8282 
8283 	u8         reserved_at_40[0x8];
8284 	u8         qpn[0x18];
8285 
8286 	u8         reserved_at_60[0x20];
8287 
8288 	u8         multicast_gid[16][0x8];
8289 };
8290 
8291 struct mlx5_ifc_destroy_xrq_out_bits {
8292 	u8         status[0x8];
8293 	u8         reserved_at_8[0x18];
8294 
8295 	u8         syndrome[0x20];
8296 
8297 	u8         reserved_at_40[0x40];
8298 };
8299 
8300 struct mlx5_ifc_destroy_xrq_in_bits {
8301 	u8         opcode[0x10];
8302 	u8         uid[0x10];
8303 
8304 	u8         reserved_at_20[0x10];
8305 	u8         op_mod[0x10];
8306 
8307 	u8         reserved_at_40[0x8];
8308 	u8         xrqn[0x18];
8309 
8310 	u8         reserved_at_60[0x20];
8311 };
8312 
8313 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8314 	u8         status[0x8];
8315 	u8         reserved_at_8[0x18];
8316 
8317 	u8         syndrome[0x20];
8318 
8319 	u8         reserved_at_40[0x40];
8320 };
8321 
8322 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8323 	u8         opcode[0x10];
8324 	u8         uid[0x10];
8325 
8326 	u8         reserved_at_20[0x10];
8327 	u8         op_mod[0x10];
8328 
8329 	u8         reserved_at_40[0x8];
8330 	u8         xrc_srqn[0x18];
8331 
8332 	u8         reserved_at_60[0x20];
8333 };
8334 
8335 struct mlx5_ifc_destroy_tis_out_bits {
8336 	u8         status[0x8];
8337 	u8         reserved_at_8[0x18];
8338 
8339 	u8         syndrome[0x20];
8340 
8341 	u8         reserved_at_40[0x40];
8342 };
8343 
8344 struct mlx5_ifc_destroy_tis_in_bits {
8345 	u8         opcode[0x10];
8346 	u8         uid[0x10];
8347 
8348 	u8         reserved_at_20[0x10];
8349 	u8         op_mod[0x10];
8350 
8351 	u8         reserved_at_40[0x8];
8352 	u8         tisn[0x18];
8353 
8354 	u8         reserved_at_60[0x20];
8355 };
8356 
8357 struct mlx5_ifc_destroy_tir_out_bits {
8358 	u8         status[0x8];
8359 	u8         reserved_at_8[0x18];
8360 
8361 	u8         syndrome[0x20];
8362 
8363 	u8         reserved_at_40[0x40];
8364 };
8365 
8366 struct mlx5_ifc_destroy_tir_in_bits {
8367 	u8         opcode[0x10];
8368 	u8         uid[0x10];
8369 
8370 	u8         reserved_at_20[0x10];
8371 	u8         op_mod[0x10];
8372 
8373 	u8         reserved_at_40[0x8];
8374 	u8         tirn[0x18];
8375 
8376 	u8         reserved_at_60[0x20];
8377 };
8378 
8379 struct mlx5_ifc_destroy_srq_out_bits {
8380 	u8         status[0x8];
8381 	u8         reserved_at_8[0x18];
8382 
8383 	u8         syndrome[0x20];
8384 
8385 	u8         reserved_at_40[0x40];
8386 };
8387 
8388 struct mlx5_ifc_destroy_srq_in_bits {
8389 	u8         opcode[0x10];
8390 	u8         uid[0x10];
8391 
8392 	u8         reserved_at_20[0x10];
8393 	u8         op_mod[0x10];
8394 
8395 	u8         reserved_at_40[0x8];
8396 	u8         srqn[0x18];
8397 
8398 	u8         reserved_at_60[0x20];
8399 };
8400 
8401 struct mlx5_ifc_destroy_sq_out_bits {
8402 	u8         status[0x8];
8403 	u8         reserved_at_8[0x18];
8404 
8405 	u8         syndrome[0x20];
8406 
8407 	u8         reserved_at_40[0x40];
8408 };
8409 
8410 struct mlx5_ifc_destroy_sq_in_bits {
8411 	u8         opcode[0x10];
8412 	u8         uid[0x10];
8413 
8414 	u8         reserved_at_20[0x10];
8415 	u8         op_mod[0x10];
8416 
8417 	u8         reserved_at_40[0x8];
8418 	u8         sqn[0x18];
8419 
8420 	u8         reserved_at_60[0x20];
8421 };
8422 
8423 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8424 	u8         status[0x8];
8425 	u8         reserved_at_8[0x18];
8426 
8427 	u8         syndrome[0x20];
8428 
8429 	u8         reserved_at_40[0x1c0];
8430 };
8431 
8432 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8433 	u8         opcode[0x10];
8434 	u8         reserved_at_10[0x10];
8435 
8436 	u8         reserved_at_20[0x10];
8437 	u8         op_mod[0x10];
8438 
8439 	u8         scheduling_hierarchy[0x8];
8440 	u8         reserved_at_48[0x18];
8441 
8442 	u8         scheduling_element_id[0x20];
8443 
8444 	u8         reserved_at_80[0x180];
8445 };
8446 
8447 struct mlx5_ifc_destroy_rqt_out_bits {
8448 	u8         status[0x8];
8449 	u8         reserved_at_8[0x18];
8450 
8451 	u8         syndrome[0x20];
8452 
8453 	u8         reserved_at_40[0x40];
8454 };
8455 
8456 struct mlx5_ifc_destroy_rqt_in_bits {
8457 	u8         opcode[0x10];
8458 	u8         uid[0x10];
8459 
8460 	u8         reserved_at_20[0x10];
8461 	u8         op_mod[0x10];
8462 
8463 	u8         reserved_at_40[0x8];
8464 	u8         rqtn[0x18];
8465 
8466 	u8         reserved_at_60[0x20];
8467 };
8468 
8469 struct mlx5_ifc_destroy_rq_out_bits {
8470 	u8         status[0x8];
8471 	u8         reserved_at_8[0x18];
8472 
8473 	u8         syndrome[0x20];
8474 
8475 	u8         reserved_at_40[0x40];
8476 };
8477 
8478 struct mlx5_ifc_destroy_rq_in_bits {
8479 	u8         opcode[0x10];
8480 	u8         uid[0x10];
8481 
8482 	u8         reserved_at_20[0x10];
8483 	u8         op_mod[0x10];
8484 
8485 	u8         reserved_at_40[0x8];
8486 	u8         rqn[0x18];
8487 
8488 	u8         reserved_at_60[0x20];
8489 };
8490 
8491 struct mlx5_ifc_set_delay_drop_params_in_bits {
8492 	u8         opcode[0x10];
8493 	u8         reserved_at_10[0x10];
8494 
8495 	u8         reserved_at_20[0x10];
8496 	u8         op_mod[0x10];
8497 
8498 	u8         reserved_at_40[0x20];
8499 
8500 	u8         reserved_at_60[0x10];
8501 	u8         delay_drop_timeout[0x10];
8502 };
8503 
8504 struct mlx5_ifc_set_delay_drop_params_out_bits {
8505 	u8         status[0x8];
8506 	u8         reserved_at_8[0x18];
8507 
8508 	u8         syndrome[0x20];
8509 
8510 	u8         reserved_at_40[0x40];
8511 };
8512 
8513 struct mlx5_ifc_destroy_rmp_out_bits {
8514 	u8         status[0x8];
8515 	u8         reserved_at_8[0x18];
8516 
8517 	u8         syndrome[0x20];
8518 
8519 	u8         reserved_at_40[0x40];
8520 };
8521 
8522 struct mlx5_ifc_destroy_rmp_in_bits {
8523 	u8         opcode[0x10];
8524 	u8         uid[0x10];
8525 
8526 	u8         reserved_at_20[0x10];
8527 	u8         op_mod[0x10];
8528 
8529 	u8         reserved_at_40[0x8];
8530 	u8         rmpn[0x18];
8531 
8532 	u8         reserved_at_60[0x20];
8533 };
8534 
8535 struct mlx5_ifc_destroy_qp_out_bits {
8536 	u8         status[0x8];
8537 	u8         reserved_at_8[0x18];
8538 
8539 	u8         syndrome[0x20];
8540 
8541 	u8         reserved_at_40[0x40];
8542 };
8543 
8544 struct mlx5_ifc_destroy_qp_in_bits {
8545 	u8         opcode[0x10];
8546 	u8         uid[0x10];
8547 
8548 	u8         reserved_at_20[0x10];
8549 	u8         op_mod[0x10];
8550 
8551 	u8         reserved_at_40[0x8];
8552 	u8         qpn[0x18];
8553 
8554 	u8         reserved_at_60[0x20];
8555 };
8556 
8557 struct mlx5_ifc_destroy_psv_out_bits {
8558 	u8         status[0x8];
8559 	u8         reserved_at_8[0x18];
8560 
8561 	u8         syndrome[0x20];
8562 
8563 	u8         reserved_at_40[0x40];
8564 };
8565 
8566 struct mlx5_ifc_destroy_psv_in_bits {
8567 	u8         opcode[0x10];
8568 	u8         reserved_at_10[0x10];
8569 
8570 	u8         reserved_at_20[0x10];
8571 	u8         op_mod[0x10];
8572 
8573 	u8         reserved_at_40[0x8];
8574 	u8         psvn[0x18];
8575 
8576 	u8         reserved_at_60[0x20];
8577 };
8578 
8579 struct mlx5_ifc_destroy_mkey_out_bits {
8580 	u8         status[0x8];
8581 	u8         reserved_at_8[0x18];
8582 
8583 	u8         syndrome[0x20];
8584 
8585 	u8         reserved_at_40[0x40];
8586 };
8587 
8588 struct mlx5_ifc_destroy_mkey_in_bits {
8589 	u8         opcode[0x10];
8590 	u8         uid[0x10];
8591 
8592 	u8         reserved_at_20[0x10];
8593 	u8         op_mod[0x10];
8594 
8595 	u8         reserved_at_40[0x8];
8596 	u8         mkey_index[0x18];
8597 
8598 	u8         reserved_at_60[0x20];
8599 };
8600 
8601 struct mlx5_ifc_destroy_flow_table_out_bits {
8602 	u8         status[0x8];
8603 	u8         reserved_at_8[0x18];
8604 
8605 	u8         syndrome[0x20];
8606 
8607 	u8         reserved_at_40[0x40];
8608 };
8609 
8610 struct mlx5_ifc_destroy_flow_table_in_bits {
8611 	u8         opcode[0x10];
8612 	u8         reserved_at_10[0x10];
8613 
8614 	u8         reserved_at_20[0x10];
8615 	u8         op_mod[0x10];
8616 
8617 	u8         other_vport[0x1];
8618 	u8         reserved_at_41[0xf];
8619 	u8         vport_number[0x10];
8620 
8621 	u8         reserved_at_60[0x20];
8622 
8623 	u8         table_type[0x8];
8624 	u8         reserved_at_88[0x18];
8625 
8626 	u8         reserved_at_a0[0x8];
8627 	u8         table_id[0x18];
8628 
8629 	u8         reserved_at_c0[0x140];
8630 };
8631 
8632 struct mlx5_ifc_destroy_flow_group_out_bits {
8633 	u8         status[0x8];
8634 	u8         reserved_at_8[0x18];
8635 
8636 	u8         syndrome[0x20];
8637 
8638 	u8         reserved_at_40[0x40];
8639 };
8640 
8641 struct mlx5_ifc_destroy_flow_group_in_bits {
8642 	u8         opcode[0x10];
8643 	u8         reserved_at_10[0x10];
8644 
8645 	u8         reserved_at_20[0x10];
8646 	u8         op_mod[0x10];
8647 
8648 	u8         other_vport[0x1];
8649 	u8         reserved_at_41[0xf];
8650 	u8         vport_number[0x10];
8651 
8652 	u8         reserved_at_60[0x20];
8653 
8654 	u8         table_type[0x8];
8655 	u8         reserved_at_88[0x18];
8656 
8657 	u8         reserved_at_a0[0x8];
8658 	u8         table_id[0x18];
8659 
8660 	u8         group_id[0x20];
8661 
8662 	u8         reserved_at_e0[0x120];
8663 };
8664 
8665 struct mlx5_ifc_destroy_eq_out_bits {
8666 	u8         status[0x8];
8667 	u8         reserved_at_8[0x18];
8668 
8669 	u8         syndrome[0x20];
8670 
8671 	u8         reserved_at_40[0x40];
8672 };
8673 
8674 struct mlx5_ifc_destroy_eq_in_bits {
8675 	u8         opcode[0x10];
8676 	u8         reserved_at_10[0x10];
8677 
8678 	u8         reserved_at_20[0x10];
8679 	u8         op_mod[0x10];
8680 
8681 	u8         reserved_at_40[0x18];
8682 	u8         eq_number[0x8];
8683 
8684 	u8         reserved_at_60[0x20];
8685 };
8686 
8687 struct mlx5_ifc_destroy_dct_out_bits {
8688 	u8         status[0x8];
8689 	u8         reserved_at_8[0x18];
8690 
8691 	u8         syndrome[0x20];
8692 
8693 	u8         reserved_at_40[0x40];
8694 };
8695 
8696 struct mlx5_ifc_destroy_dct_in_bits {
8697 	u8         opcode[0x10];
8698 	u8         uid[0x10];
8699 
8700 	u8         reserved_at_20[0x10];
8701 	u8         op_mod[0x10];
8702 
8703 	u8         reserved_at_40[0x8];
8704 	u8         dctn[0x18];
8705 
8706 	u8         reserved_at_60[0x20];
8707 };
8708 
8709 struct mlx5_ifc_destroy_cq_out_bits {
8710 	u8         status[0x8];
8711 	u8         reserved_at_8[0x18];
8712 
8713 	u8         syndrome[0x20];
8714 
8715 	u8         reserved_at_40[0x40];
8716 };
8717 
8718 struct mlx5_ifc_destroy_cq_in_bits {
8719 	u8         opcode[0x10];
8720 	u8         uid[0x10];
8721 
8722 	u8         reserved_at_20[0x10];
8723 	u8         op_mod[0x10];
8724 
8725 	u8         reserved_at_40[0x8];
8726 	u8         cqn[0x18];
8727 
8728 	u8         reserved_at_60[0x20];
8729 };
8730 
8731 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8732 	u8         status[0x8];
8733 	u8         reserved_at_8[0x18];
8734 
8735 	u8         syndrome[0x20];
8736 
8737 	u8         reserved_at_40[0x40];
8738 };
8739 
8740 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8741 	u8         opcode[0x10];
8742 	u8         reserved_at_10[0x10];
8743 
8744 	u8         reserved_at_20[0x10];
8745 	u8         op_mod[0x10];
8746 
8747 	u8         reserved_at_40[0x20];
8748 
8749 	u8         reserved_at_60[0x10];
8750 	u8         vxlan_udp_port[0x10];
8751 };
8752 
8753 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8754 	u8         status[0x8];
8755 	u8         reserved_at_8[0x18];
8756 
8757 	u8         syndrome[0x20];
8758 
8759 	u8         reserved_at_40[0x40];
8760 };
8761 
8762 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8763 	u8         opcode[0x10];
8764 	u8         reserved_at_10[0x10];
8765 
8766 	u8         reserved_at_20[0x10];
8767 	u8         op_mod[0x10];
8768 
8769 	u8         reserved_at_40[0x60];
8770 
8771 	u8         reserved_at_a0[0x8];
8772 	u8         table_index[0x18];
8773 
8774 	u8         reserved_at_c0[0x140];
8775 };
8776 
8777 struct mlx5_ifc_delete_fte_out_bits {
8778 	u8         status[0x8];
8779 	u8         reserved_at_8[0x18];
8780 
8781 	u8         syndrome[0x20];
8782 
8783 	u8         reserved_at_40[0x40];
8784 };
8785 
8786 struct mlx5_ifc_delete_fte_in_bits {
8787 	u8         opcode[0x10];
8788 	u8         reserved_at_10[0x10];
8789 
8790 	u8         reserved_at_20[0x10];
8791 	u8         op_mod[0x10];
8792 
8793 	u8         other_vport[0x1];
8794 	u8         reserved_at_41[0xf];
8795 	u8         vport_number[0x10];
8796 
8797 	u8         reserved_at_60[0x20];
8798 
8799 	u8         table_type[0x8];
8800 	u8         reserved_at_88[0x18];
8801 
8802 	u8         reserved_at_a0[0x8];
8803 	u8         table_id[0x18];
8804 
8805 	u8         reserved_at_c0[0x40];
8806 
8807 	u8         flow_index[0x20];
8808 
8809 	u8         reserved_at_120[0xe0];
8810 };
8811 
8812 struct mlx5_ifc_dealloc_xrcd_out_bits {
8813 	u8         status[0x8];
8814 	u8         reserved_at_8[0x18];
8815 
8816 	u8         syndrome[0x20];
8817 
8818 	u8         reserved_at_40[0x40];
8819 };
8820 
8821 struct mlx5_ifc_dealloc_xrcd_in_bits {
8822 	u8         opcode[0x10];
8823 	u8         uid[0x10];
8824 
8825 	u8         reserved_at_20[0x10];
8826 	u8         op_mod[0x10];
8827 
8828 	u8         reserved_at_40[0x8];
8829 	u8         xrcd[0x18];
8830 
8831 	u8         reserved_at_60[0x20];
8832 };
8833 
8834 struct mlx5_ifc_dealloc_uar_out_bits {
8835 	u8         status[0x8];
8836 	u8         reserved_at_8[0x18];
8837 
8838 	u8         syndrome[0x20];
8839 
8840 	u8         reserved_at_40[0x40];
8841 };
8842 
8843 struct mlx5_ifc_dealloc_uar_in_bits {
8844 	u8         opcode[0x10];
8845 	u8         uid[0x10];
8846 
8847 	u8         reserved_at_20[0x10];
8848 	u8         op_mod[0x10];
8849 
8850 	u8         reserved_at_40[0x8];
8851 	u8         uar[0x18];
8852 
8853 	u8         reserved_at_60[0x20];
8854 };
8855 
8856 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8857 	u8         status[0x8];
8858 	u8         reserved_at_8[0x18];
8859 
8860 	u8         syndrome[0x20];
8861 
8862 	u8         reserved_at_40[0x40];
8863 };
8864 
8865 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8866 	u8         opcode[0x10];
8867 	u8         uid[0x10];
8868 
8869 	u8         reserved_at_20[0x10];
8870 	u8         op_mod[0x10];
8871 
8872 	u8         reserved_at_40[0x8];
8873 	u8         transport_domain[0x18];
8874 
8875 	u8         reserved_at_60[0x20];
8876 };
8877 
8878 struct mlx5_ifc_dealloc_q_counter_out_bits {
8879 	u8         status[0x8];
8880 	u8         reserved_at_8[0x18];
8881 
8882 	u8         syndrome[0x20];
8883 
8884 	u8         reserved_at_40[0x40];
8885 };
8886 
8887 struct mlx5_ifc_dealloc_q_counter_in_bits {
8888 	u8         opcode[0x10];
8889 	u8         reserved_at_10[0x10];
8890 
8891 	u8         reserved_at_20[0x10];
8892 	u8         op_mod[0x10];
8893 
8894 	u8         reserved_at_40[0x18];
8895 	u8         counter_set_id[0x8];
8896 
8897 	u8         reserved_at_60[0x20];
8898 };
8899 
8900 struct mlx5_ifc_dealloc_pd_out_bits {
8901 	u8         status[0x8];
8902 	u8         reserved_at_8[0x18];
8903 
8904 	u8         syndrome[0x20];
8905 
8906 	u8         reserved_at_40[0x40];
8907 };
8908 
8909 struct mlx5_ifc_dealloc_pd_in_bits {
8910 	u8         opcode[0x10];
8911 	u8         uid[0x10];
8912 
8913 	u8         reserved_at_20[0x10];
8914 	u8         op_mod[0x10];
8915 
8916 	u8         reserved_at_40[0x8];
8917 	u8         pd[0x18];
8918 
8919 	u8         reserved_at_60[0x20];
8920 };
8921 
8922 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8923 	u8         status[0x8];
8924 	u8         reserved_at_8[0x18];
8925 
8926 	u8         syndrome[0x20];
8927 
8928 	u8         reserved_at_40[0x40];
8929 };
8930 
8931 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8932 	u8         opcode[0x10];
8933 	u8         reserved_at_10[0x10];
8934 
8935 	u8         reserved_at_20[0x10];
8936 	u8         op_mod[0x10];
8937 
8938 	u8         flow_counter_id[0x20];
8939 
8940 	u8         reserved_at_60[0x20];
8941 };
8942 
8943 struct mlx5_ifc_create_xrq_out_bits {
8944 	u8         status[0x8];
8945 	u8         reserved_at_8[0x18];
8946 
8947 	u8         syndrome[0x20];
8948 
8949 	u8         reserved_at_40[0x8];
8950 	u8         xrqn[0x18];
8951 
8952 	u8         reserved_at_60[0x20];
8953 };
8954 
8955 struct mlx5_ifc_create_xrq_in_bits {
8956 	u8         opcode[0x10];
8957 	u8         uid[0x10];
8958 
8959 	u8         reserved_at_20[0x10];
8960 	u8         op_mod[0x10];
8961 
8962 	u8         reserved_at_40[0x40];
8963 
8964 	struct mlx5_ifc_xrqc_bits xrq_context;
8965 };
8966 
8967 struct mlx5_ifc_create_xrc_srq_out_bits {
8968 	u8         status[0x8];
8969 	u8         reserved_at_8[0x18];
8970 
8971 	u8         syndrome[0x20];
8972 
8973 	u8         reserved_at_40[0x8];
8974 	u8         xrc_srqn[0x18];
8975 
8976 	u8         reserved_at_60[0x20];
8977 };
8978 
8979 struct mlx5_ifc_create_xrc_srq_in_bits {
8980 	u8         opcode[0x10];
8981 	u8         uid[0x10];
8982 
8983 	u8         reserved_at_20[0x10];
8984 	u8         op_mod[0x10];
8985 
8986 	u8         reserved_at_40[0x40];
8987 
8988 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8989 
8990 	u8         reserved_at_280[0x60];
8991 
8992 	u8         xrc_srq_umem_valid[0x1];
8993 	u8         reserved_at_2e1[0x1f];
8994 
8995 	u8         reserved_at_300[0x580];
8996 
8997 	u8         pas[][0x40];
8998 };
8999 
9000 struct mlx5_ifc_create_tis_out_bits {
9001 	u8         status[0x8];
9002 	u8         reserved_at_8[0x18];
9003 
9004 	u8         syndrome[0x20];
9005 
9006 	u8         reserved_at_40[0x8];
9007 	u8         tisn[0x18];
9008 
9009 	u8         reserved_at_60[0x20];
9010 };
9011 
9012 struct mlx5_ifc_create_tis_in_bits {
9013 	u8         opcode[0x10];
9014 	u8         uid[0x10];
9015 
9016 	u8         reserved_at_20[0x10];
9017 	u8         op_mod[0x10];
9018 
9019 	u8         reserved_at_40[0xc0];
9020 
9021 	struct mlx5_ifc_tisc_bits ctx;
9022 };
9023 
9024 struct mlx5_ifc_create_tir_out_bits {
9025 	u8         status[0x8];
9026 	u8         icm_address_63_40[0x18];
9027 
9028 	u8         syndrome[0x20];
9029 
9030 	u8         icm_address_39_32[0x8];
9031 	u8         tirn[0x18];
9032 
9033 	u8         icm_address_31_0[0x20];
9034 };
9035 
9036 struct mlx5_ifc_create_tir_in_bits {
9037 	u8         opcode[0x10];
9038 	u8         uid[0x10];
9039 
9040 	u8         reserved_at_20[0x10];
9041 	u8         op_mod[0x10];
9042 
9043 	u8         reserved_at_40[0xc0];
9044 
9045 	struct mlx5_ifc_tirc_bits ctx;
9046 };
9047 
9048 struct mlx5_ifc_create_srq_out_bits {
9049 	u8         status[0x8];
9050 	u8         reserved_at_8[0x18];
9051 
9052 	u8         syndrome[0x20];
9053 
9054 	u8         reserved_at_40[0x8];
9055 	u8         srqn[0x18];
9056 
9057 	u8         reserved_at_60[0x20];
9058 };
9059 
9060 struct mlx5_ifc_create_srq_in_bits {
9061 	u8         opcode[0x10];
9062 	u8         uid[0x10];
9063 
9064 	u8         reserved_at_20[0x10];
9065 	u8         op_mod[0x10];
9066 
9067 	u8         reserved_at_40[0x40];
9068 
9069 	struct mlx5_ifc_srqc_bits srq_context_entry;
9070 
9071 	u8         reserved_at_280[0x600];
9072 
9073 	u8         pas[][0x40];
9074 };
9075 
9076 struct mlx5_ifc_create_sq_out_bits {
9077 	u8         status[0x8];
9078 	u8         reserved_at_8[0x18];
9079 
9080 	u8         syndrome[0x20];
9081 
9082 	u8         reserved_at_40[0x8];
9083 	u8         sqn[0x18];
9084 
9085 	u8         reserved_at_60[0x20];
9086 };
9087 
9088 struct mlx5_ifc_create_sq_in_bits {
9089 	u8         opcode[0x10];
9090 	u8         uid[0x10];
9091 
9092 	u8         reserved_at_20[0x10];
9093 	u8         op_mod[0x10];
9094 
9095 	u8         reserved_at_40[0xc0];
9096 
9097 	struct mlx5_ifc_sqc_bits ctx;
9098 };
9099 
9100 struct mlx5_ifc_create_scheduling_element_out_bits {
9101 	u8         status[0x8];
9102 	u8         reserved_at_8[0x18];
9103 
9104 	u8         syndrome[0x20];
9105 
9106 	u8         reserved_at_40[0x40];
9107 
9108 	u8         scheduling_element_id[0x20];
9109 
9110 	u8         reserved_at_a0[0x160];
9111 };
9112 
9113 struct mlx5_ifc_create_scheduling_element_in_bits {
9114 	u8         opcode[0x10];
9115 	u8         reserved_at_10[0x10];
9116 
9117 	u8         reserved_at_20[0x10];
9118 	u8         op_mod[0x10];
9119 
9120 	u8         scheduling_hierarchy[0x8];
9121 	u8         reserved_at_48[0x18];
9122 
9123 	u8         reserved_at_60[0xa0];
9124 
9125 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9126 
9127 	u8         reserved_at_300[0x100];
9128 };
9129 
9130 struct mlx5_ifc_create_rqt_out_bits {
9131 	u8         status[0x8];
9132 	u8         reserved_at_8[0x18];
9133 
9134 	u8         syndrome[0x20];
9135 
9136 	u8         reserved_at_40[0x8];
9137 	u8         rqtn[0x18];
9138 
9139 	u8         reserved_at_60[0x20];
9140 };
9141 
9142 struct mlx5_ifc_create_rqt_in_bits {
9143 	u8         opcode[0x10];
9144 	u8         uid[0x10];
9145 
9146 	u8         reserved_at_20[0x10];
9147 	u8         op_mod[0x10];
9148 
9149 	u8         reserved_at_40[0xc0];
9150 
9151 	struct mlx5_ifc_rqtc_bits rqt_context;
9152 };
9153 
9154 struct mlx5_ifc_create_rq_out_bits {
9155 	u8         status[0x8];
9156 	u8         reserved_at_8[0x18];
9157 
9158 	u8         syndrome[0x20];
9159 
9160 	u8         reserved_at_40[0x8];
9161 	u8         rqn[0x18];
9162 
9163 	u8         reserved_at_60[0x20];
9164 };
9165 
9166 struct mlx5_ifc_create_rq_in_bits {
9167 	u8         opcode[0x10];
9168 	u8         uid[0x10];
9169 
9170 	u8         reserved_at_20[0x10];
9171 	u8         op_mod[0x10];
9172 
9173 	u8         reserved_at_40[0xc0];
9174 
9175 	struct mlx5_ifc_rqc_bits ctx;
9176 };
9177 
9178 struct mlx5_ifc_create_rmp_out_bits {
9179 	u8         status[0x8];
9180 	u8         reserved_at_8[0x18];
9181 
9182 	u8         syndrome[0x20];
9183 
9184 	u8         reserved_at_40[0x8];
9185 	u8         rmpn[0x18];
9186 
9187 	u8         reserved_at_60[0x20];
9188 };
9189 
9190 struct mlx5_ifc_create_rmp_in_bits {
9191 	u8         opcode[0x10];
9192 	u8         uid[0x10];
9193 
9194 	u8         reserved_at_20[0x10];
9195 	u8         op_mod[0x10];
9196 
9197 	u8         reserved_at_40[0xc0];
9198 
9199 	struct mlx5_ifc_rmpc_bits ctx;
9200 };
9201 
9202 struct mlx5_ifc_create_qp_out_bits {
9203 	u8         status[0x8];
9204 	u8         reserved_at_8[0x18];
9205 
9206 	u8         syndrome[0x20];
9207 
9208 	u8         reserved_at_40[0x8];
9209 	u8         qpn[0x18];
9210 
9211 	u8         ece[0x20];
9212 };
9213 
9214 struct mlx5_ifc_create_qp_in_bits {
9215 	u8         opcode[0x10];
9216 	u8         uid[0x10];
9217 
9218 	u8         reserved_at_20[0x10];
9219 	u8         op_mod[0x10];
9220 
9221 	u8         qpc_ext[0x1];
9222 	u8         reserved_at_41[0x7];
9223 	u8         input_qpn[0x18];
9224 
9225 	u8         reserved_at_60[0x20];
9226 	u8         opt_param_mask[0x20];
9227 
9228 	u8         ece[0x20];
9229 
9230 	struct mlx5_ifc_qpc_bits qpc;
9231 
9232 	u8         wq_umem_offset[0x40];
9233 
9234 	u8         wq_umem_id[0x20];
9235 
9236 	u8         wq_umem_valid[0x1];
9237 	u8         reserved_at_861[0x1f];
9238 
9239 	u8         pas[][0x40];
9240 };
9241 
9242 struct mlx5_ifc_create_psv_out_bits {
9243 	u8         status[0x8];
9244 	u8         reserved_at_8[0x18];
9245 
9246 	u8         syndrome[0x20];
9247 
9248 	u8         reserved_at_40[0x40];
9249 
9250 	u8         reserved_at_80[0x8];
9251 	u8         psv0_index[0x18];
9252 
9253 	u8         reserved_at_a0[0x8];
9254 	u8         psv1_index[0x18];
9255 
9256 	u8         reserved_at_c0[0x8];
9257 	u8         psv2_index[0x18];
9258 
9259 	u8         reserved_at_e0[0x8];
9260 	u8         psv3_index[0x18];
9261 };
9262 
9263 struct mlx5_ifc_create_psv_in_bits {
9264 	u8         opcode[0x10];
9265 	u8         reserved_at_10[0x10];
9266 
9267 	u8         reserved_at_20[0x10];
9268 	u8         op_mod[0x10];
9269 
9270 	u8         num_psv[0x4];
9271 	u8         reserved_at_44[0x4];
9272 	u8         pd[0x18];
9273 
9274 	u8         reserved_at_60[0x20];
9275 };
9276 
9277 struct mlx5_ifc_create_mkey_out_bits {
9278 	u8         status[0x8];
9279 	u8         reserved_at_8[0x18];
9280 
9281 	u8         syndrome[0x20];
9282 
9283 	u8         reserved_at_40[0x8];
9284 	u8         mkey_index[0x18];
9285 
9286 	u8         reserved_at_60[0x20];
9287 };
9288 
9289 struct mlx5_ifc_create_mkey_in_bits {
9290 	u8         opcode[0x10];
9291 	u8         uid[0x10];
9292 
9293 	u8         reserved_at_20[0x10];
9294 	u8         op_mod[0x10];
9295 
9296 	u8         reserved_at_40[0x20];
9297 
9298 	u8         pg_access[0x1];
9299 	u8         mkey_umem_valid[0x1];
9300 	u8         data_direct[0x1];
9301 	u8         reserved_at_63[0x1d];
9302 
9303 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9304 
9305 	u8         reserved_at_280[0x80];
9306 
9307 	u8         translations_octword_actual_size[0x20];
9308 
9309 	u8         reserved_at_320[0x560];
9310 
9311 	u8         klm_pas_mtt[][0x20];
9312 };
9313 
9314 enum {
9315 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9316 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9317 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9318 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9319 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9320 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9321 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9322 };
9323 
9324 struct mlx5_ifc_create_flow_table_out_bits {
9325 	u8         status[0x8];
9326 	u8         icm_address_63_40[0x18];
9327 
9328 	u8         syndrome[0x20];
9329 
9330 	u8         icm_address_39_32[0x8];
9331 	u8         table_id[0x18];
9332 
9333 	u8         icm_address_31_0[0x20];
9334 };
9335 
9336 struct mlx5_ifc_create_flow_table_in_bits {
9337 	u8         opcode[0x10];
9338 	u8         uid[0x10];
9339 
9340 	u8         reserved_at_20[0x10];
9341 	u8         op_mod[0x10];
9342 
9343 	u8         other_vport[0x1];
9344 	u8         reserved_at_41[0xf];
9345 	u8         vport_number[0x10];
9346 
9347 	u8         reserved_at_60[0x20];
9348 
9349 	u8         table_type[0x8];
9350 	u8         reserved_at_88[0x18];
9351 
9352 	u8         reserved_at_a0[0x20];
9353 
9354 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9355 };
9356 
9357 struct mlx5_ifc_create_flow_group_out_bits {
9358 	u8         status[0x8];
9359 	u8         reserved_at_8[0x18];
9360 
9361 	u8         syndrome[0x20];
9362 
9363 	u8         reserved_at_40[0x8];
9364 	u8         group_id[0x18];
9365 
9366 	u8         reserved_at_60[0x20];
9367 };
9368 
9369 enum {
9370 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9371 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9372 };
9373 
9374 enum {
9375 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9376 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9377 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9378 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9379 };
9380 
9381 struct mlx5_ifc_create_flow_group_in_bits {
9382 	u8         opcode[0x10];
9383 	u8         reserved_at_10[0x10];
9384 
9385 	u8         reserved_at_20[0x10];
9386 	u8         op_mod[0x10];
9387 
9388 	u8         other_vport[0x1];
9389 	u8         reserved_at_41[0xf];
9390 	u8         vport_number[0x10];
9391 
9392 	u8         reserved_at_60[0x20];
9393 
9394 	u8         table_type[0x8];
9395 	u8         reserved_at_88[0x4];
9396 	u8         group_type[0x4];
9397 	u8         reserved_at_90[0x10];
9398 
9399 	u8         reserved_at_a0[0x8];
9400 	u8         table_id[0x18];
9401 
9402 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9403 
9404 	u8         reserved_at_c1[0x1f];
9405 
9406 	u8         start_flow_index[0x20];
9407 
9408 	u8         reserved_at_100[0x20];
9409 
9410 	u8         end_flow_index[0x20];
9411 
9412 	u8         reserved_at_140[0x10];
9413 	u8         match_definer_id[0x10];
9414 
9415 	u8         reserved_at_160[0x80];
9416 
9417 	u8         reserved_at_1e0[0x18];
9418 	u8         match_criteria_enable[0x8];
9419 
9420 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9421 
9422 	u8         reserved_at_1200[0xe00];
9423 };
9424 
9425 struct mlx5_ifc_create_eq_out_bits {
9426 	u8         status[0x8];
9427 	u8         reserved_at_8[0x18];
9428 
9429 	u8         syndrome[0x20];
9430 
9431 	u8         reserved_at_40[0x18];
9432 	u8         eq_number[0x8];
9433 
9434 	u8         reserved_at_60[0x20];
9435 };
9436 
9437 struct mlx5_ifc_create_eq_in_bits {
9438 	u8         opcode[0x10];
9439 	u8         uid[0x10];
9440 
9441 	u8         reserved_at_20[0x10];
9442 	u8         op_mod[0x10];
9443 
9444 	u8         reserved_at_40[0x40];
9445 
9446 	struct mlx5_ifc_eqc_bits eq_context_entry;
9447 
9448 	u8         reserved_at_280[0x40];
9449 
9450 	u8         event_bitmask[4][0x40];
9451 
9452 	u8         reserved_at_3c0[0x4c0];
9453 
9454 	u8         pas[][0x40];
9455 };
9456 
9457 struct mlx5_ifc_create_dct_out_bits {
9458 	u8         status[0x8];
9459 	u8         reserved_at_8[0x18];
9460 
9461 	u8         syndrome[0x20];
9462 
9463 	u8         reserved_at_40[0x8];
9464 	u8         dctn[0x18];
9465 
9466 	u8         ece[0x20];
9467 };
9468 
9469 struct mlx5_ifc_create_dct_in_bits {
9470 	u8         opcode[0x10];
9471 	u8         uid[0x10];
9472 
9473 	u8         reserved_at_20[0x10];
9474 	u8         op_mod[0x10];
9475 
9476 	u8         reserved_at_40[0x40];
9477 
9478 	struct mlx5_ifc_dctc_bits dct_context_entry;
9479 
9480 	u8         reserved_at_280[0x180];
9481 };
9482 
9483 struct mlx5_ifc_create_cq_out_bits {
9484 	u8         status[0x8];
9485 	u8         reserved_at_8[0x18];
9486 
9487 	u8         syndrome[0x20];
9488 
9489 	u8         reserved_at_40[0x8];
9490 	u8         cqn[0x18];
9491 
9492 	u8         reserved_at_60[0x20];
9493 };
9494 
9495 struct mlx5_ifc_create_cq_in_bits {
9496 	u8         opcode[0x10];
9497 	u8         uid[0x10];
9498 
9499 	u8         reserved_at_20[0x10];
9500 	u8         op_mod[0x10];
9501 
9502 	u8         reserved_at_40[0x40];
9503 
9504 	struct mlx5_ifc_cqc_bits cq_context;
9505 
9506 	u8         reserved_at_280[0x60];
9507 
9508 	u8         cq_umem_valid[0x1];
9509 	u8         reserved_at_2e1[0x59f];
9510 
9511 	u8         pas[][0x40];
9512 };
9513 
9514 struct mlx5_ifc_config_int_moderation_out_bits {
9515 	u8         status[0x8];
9516 	u8         reserved_at_8[0x18];
9517 
9518 	u8         syndrome[0x20];
9519 
9520 	u8         reserved_at_40[0x4];
9521 	u8         min_delay[0xc];
9522 	u8         int_vector[0x10];
9523 
9524 	u8         reserved_at_60[0x20];
9525 };
9526 
9527 enum {
9528 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9529 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9530 };
9531 
9532 struct mlx5_ifc_config_int_moderation_in_bits {
9533 	u8         opcode[0x10];
9534 	u8         reserved_at_10[0x10];
9535 
9536 	u8         reserved_at_20[0x10];
9537 	u8         op_mod[0x10];
9538 
9539 	u8         reserved_at_40[0x4];
9540 	u8         min_delay[0xc];
9541 	u8         int_vector[0x10];
9542 
9543 	u8         reserved_at_60[0x20];
9544 };
9545 
9546 struct mlx5_ifc_attach_to_mcg_out_bits {
9547 	u8         status[0x8];
9548 	u8         reserved_at_8[0x18];
9549 
9550 	u8         syndrome[0x20];
9551 
9552 	u8         reserved_at_40[0x40];
9553 };
9554 
9555 struct mlx5_ifc_attach_to_mcg_in_bits {
9556 	u8         opcode[0x10];
9557 	u8         uid[0x10];
9558 
9559 	u8         reserved_at_20[0x10];
9560 	u8         op_mod[0x10];
9561 
9562 	u8         reserved_at_40[0x8];
9563 	u8         qpn[0x18];
9564 
9565 	u8         reserved_at_60[0x20];
9566 
9567 	u8         multicast_gid[16][0x8];
9568 };
9569 
9570 struct mlx5_ifc_arm_xrq_out_bits {
9571 	u8         status[0x8];
9572 	u8         reserved_at_8[0x18];
9573 
9574 	u8         syndrome[0x20];
9575 
9576 	u8         reserved_at_40[0x40];
9577 };
9578 
9579 struct mlx5_ifc_arm_xrq_in_bits {
9580 	u8         opcode[0x10];
9581 	u8         reserved_at_10[0x10];
9582 
9583 	u8         reserved_at_20[0x10];
9584 	u8         op_mod[0x10];
9585 
9586 	u8         reserved_at_40[0x8];
9587 	u8         xrqn[0x18];
9588 
9589 	u8         reserved_at_60[0x10];
9590 	u8         lwm[0x10];
9591 };
9592 
9593 struct mlx5_ifc_arm_xrc_srq_out_bits {
9594 	u8         status[0x8];
9595 	u8         reserved_at_8[0x18];
9596 
9597 	u8         syndrome[0x20];
9598 
9599 	u8         reserved_at_40[0x40];
9600 };
9601 
9602 enum {
9603 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9604 };
9605 
9606 struct mlx5_ifc_arm_xrc_srq_in_bits {
9607 	u8         opcode[0x10];
9608 	u8         uid[0x10];
9609 
9610 	u8         reserved_at_20[0x10];
9611 	u8         op_mod[0x10];
9612 
9613 	u8         reserved_at_40[0x8];
9614 	u8         xrc_srqn[0x18];
9615 
9616 	u8         reserved_at_60[0x10];
9617 	u8         lwm[0x10];
9618 };
9619 
9620 struct mlx5_ifc_arm_rq_out_bits {
9621 	u8         status[0x8];
9622 	u8         reserved_at_8[0x18];
9623 
9624 	u8         syndrome[0x20];
9625 
9626 	u8         reserved_at_40[0x40];
9627 };
9628 
9629 enum {
9630 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9631 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9632 };
9633 
9634 struct mlx5_ifc_arm_rq_in_bits {
9635 	u8         opcode[0x10];
9636 	u8         uid[0x10];
9637 
9638 	u8         reserved_at_20[0x10];
9639 	u8         op_mod[0x10];
9640 
9641 	u8         reserved_at_40[0x8];
9642 	u8         srq_number[0x18];
9643 
9644 	u8         reserved_at_60[0x10];
9645 	u8         lwm[0x10];
9646 };
9647 
9648 struct mlx5_ifc_arm_dct_out_bits {
9649 	u8         status[0x8];
9650 	u8         reserved_at_8[0x18];
9651 
9652 	u8         syndrome[0x20];
9653 
9654 	u8         reserved_at_40[0x40];
9655 };
9656 
9657 struct mlx5_ifc_arm_dct_in_bits {
9658 	u8         opcode[0x10];
9659 	u8         reserved_at_10[0x10];
9660 
9661 	u8         reserved_at_20[0x10];
9662 	u8         op_mod[0x10];
9663 
9664 	u8         reserved_at_40[0x8];
9665 	u8         dct_number[0x18];
9666 
9667 	u8         reserved_at_60[0x20];
9668 };
9669 
9670 struct mlx5_ifc_alloc_xrcd_out_bits {
9671 	u8         status[0x8];
9672 	u8         reserved_at_8[0x18];
9673 
9674 	u8         syndrome[0x20];
9675 
9676 	u8         reserved_at_40[0x8];
9677 	u8         xrcd[0x18];
9678 
9679 	u8         reserved_at_60[0x20];
9680 };
9681 
9682 struct mlx5_ifc_alloc_xrcd_in_bits {
9683 	u8         opcode[0x10];
9684 	u8         uid[0x10];
9685 
9686 	u8         reserved_at_20[0x10];
9687 	u8         op_mod[0x10];
9688 
9689 	u8         reserved_at_40[0x40];
9690 };
9691 
9692 struct mlx5_ifc_alloc_uar_out_bits {
9693 	u8         status[0x8];
9694 	u8         reserved_at_8[0x18];
9695 
9696 	u8         syndrome[0x20];
9697 
9698 	u8         reserved_at_40[0x8];
9699 	u8         uar[0x18];
9700 
9701 	u8         reserved_at_60[0x20];
9702 };
9703 
9704 struct mlx5_ifc_alloc_uar_in_bits {
9705 	u8         opcode[0x10];
9706 	u8         uid[0x10];
9707 
9708 	u8         reserved_at_20[0x10];
9709 	u8         op_mod[0x10];
9710 
9711 	u8         reserved_at_40[0x40];
9712 };
9713 
9714 struct mlx5_ifc_alloc_transport_domain_out_bits {
9715 	u8         status[0x8];
9716 	u8         reserved_at_8[0x18];
9717 
9718 	u8         syndrome[0x20];
9719 
9720 	u8         reserved_at_40[0x8];
9721 	u8         transport_domain[0x18];
9722 
9723 	u8         reserved_at_60[0x20];
9724 };
9725 
9726 struct mlx5_ifc_alloc_transport_domain_in_bits {
9727 	u8         opcode[0x10];
9728 	u8         uid[0x10];
9729 
9730 	u8         reserved_at_20[0x10];
9731 	u8         op_mod[0x10];
9732 
9733 	u8         reserved_at_40[0x40];
9734 };
9735 
9736 struct mlx5_ifc_alloc_q_counter_out_bits {
9737 	u8         status[0x8];
9738 	u8         reserved_at_8[0x18];
9739 
9740 	u8         syndrome[0x20];
9741 
9742 	u8         reserved_at_40[0x18];
9743 	u8         counter_set_id[0x8];
9744 
9745 	u8         reserved_at_60[0x20];
9746 };
9747 
9748 struct mlx5_ifc_alloc_q_counter_in_bits {
9749 	u8         opcode[0x10];
9750 	u8         uid[0x10];
9751 
9752 	u8         reserved_at_20[0x10];
9753 	u8         op_mod[0x10];
9754 
9755 	u8         reserved_at_40[0x40];
9756 };
9757 
9758 struct mlx5_ifc_alloc_pd_out_bits {
9759 	u8         status[0x8];
9760 	u8         reserved_at_8[0x18];
9761 
9762 	u8         syndrome[0x20];
9763 
9764 	u8         reserved_at_40[0x8];
9765 	u8         pd[0x18];
9766 
9767 	u8         reserved_at_60[0x20];
9768 };
9769 
9770 struct mlx5_ifc_alloc_pd_in_bits {
9771 	u8         opcode[0x10];
9772 	u8         uid[0x10];
9773 
9774 	u8         reserved_at_20[0x10];
9775 	u8         op_mod[0x10];
9776 
9777 	u8         reserved_at_40[0x40];
9778 };
9779 
9780 struct mlx5_ifc_alloc_flow_counter_out_bits {
9781 	u8         status[0x8];
9782 	u8         reserved_at_8[0x18];
9783 
9784 	u8         syndrome[0x20];
9785 
9786 	u8         flow_counter_id[0x20];
9787 
9788 	u8         reserved_at_60[0x20];
9789 };
9790 
9791 struct mlx5_ifc_alloc_flow_counter_in_bits {
9792 	u8         opcode[0x10];
9793 	u8         reserved_at_10[0x10];
9794 
9795 	u8         reserved_at_20[0x10];
9796 	u8         op_mod[0x10];
9797 
9798 	u8         reserved_at_40[0x33];
9799 	u8         flow_counter_bulk_log_size[0x5];
9800 	u8         flow_counter_bulk[0x8];
9801 };
9802 
9803 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9804 	u8         status[0x8];
9805 	u8         reserved_at_8[0x18];
9806 
9807 	u8         syndrome[0x20];
9808 
9809 	u8         reserved_at_40[0x40];
9810 };
9811 
9812 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9813 	u8         opcode[0x10];
9814 	u8         reserved_at_10[0x10];
9815 
9816 	u8         reserved_at_20[0x10];
9817 	u8         op_mod[0x10];
9818 
9819 	u8         reserved_at_40[0x20];
9820 
9821 	u8         reserved_at_60[0x10];
9822 	u8         vxlan_udp_port[0x10];
9823 };
9824 
9825 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9826 	u8         status[0x8];
9827 	u8         reserved_at_8[0x18];
9828 
9829 	u8         syndrome[0x20];
9830 
9831 	u8         reserved_at_40[0x40];
9832 };
9833 
9834 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9835 	u8         rate_limit[0x20];
9836 
9837 	u8	   burst_upper_bound[0x20];
9838 
9839 	u8         reserved_at_40[0x10];
9840 	u8	   typical_packet_size[0x10];
9841 
9842 	u8         reserved_at_60[0x120];
9843 };
9844 
9845 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9846 	u8         opcode[0x10];
9847 	u8         uid[0x10];
9848 
9849 	u8         reserved_at_20[0x10];
9850 	u8         op_mod[0x10];
9851 
9852 	u8         reserved_at_40[0x10];
9853 	u8         rate_limit_index[0x10];
9854 
9855 	u8         reserved_at_60[0x20];
9856 
9857 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9858 };
9859 
9860 struct mlx5_ifc_access_register_out_bits {
9861 	u8         status[0x8];
9862 	u8         reserved_at_8[0x18];
9863 
9864 	u8         syndrome[0x20];
9865 
9866 	u8         reserved_at_40[0x40];
9867 
9868 	u8         register_data[][0x20];
9869 };
9870 
9871 enum {
9872 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9873 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9874 };
9875 
9876 struct mlx5_ifc_access_register_in_bits {
9877 	u8         opcode[0x10];
9878 	u8         reserved_at_10[0x10];
9879 
9880 	u8         reserved_at_20[0x10];
9881 	u8         op_mod[0x10];
9882 
9883 	u8         reserved_at_40[0x10];
9884 	u8         register_id[0x10];
9885 
9886 	u8         argument[0x20];
9887 
9888 	u8         register_data[][0x20];
9889 };
9890 
9891 struct mlx5_ifc_sltp_reg_bits {
9892 	u8         status[0x4];
9893 	u8         version[0x4];
9894 	u8         local_port[0x8];
9895 	u8         pnat[0x2];
9896 	u8         reserved_at_12[0x2];
9897 	u8         lane[0x4];
9898 	u8         reserved_at_18[0x8];
9899 
9900 	u8         reserved_at_20[0x20];
9901 
9902 	u8         reserved_at_40[0x7];
9903 	u8         polarity[0x1];
9904 	u8         ob_tap0[0x8];
9905 	u8         ob_tap1[0x8];
9906 	u8         ob_tap2[0x8];
9907 
9908 	u8         reserved_at_60[0xc];
9909 	u8         ob_preemp_mode[0x4];
9910 	u8         ob_reg[0x8];
9911 	u8         ob_bias[0x8];
9912 
9913 	u8         reserved_at_80[0x20];
9914 };
9915 
9916 struct mlx5_ifc_slrg_reg_bits {
9917 	u8         status[0x4];
9918 	u8         version[0x4];
9919 	u8         local_port[0x8];
9920 	u8         pnat[0x2];
9921 	u8         reserved_at_12[0x2];
9922 	u8         lane[0x4];
9923 	u8         reserved_at_18[0x8];
9924 
9925 	u8         time_to_link_up[0x10];
9926 	u8         reserved_at_30[0xc];
9927 	u8         grade_lane_speed[0x4];
9928 
9929 	u8         grade_version[0x8];
9930 	u8         grade[0x18];
9931 
9932 	u8         reserved_at_60[0x4];
9933 	u8         height_grade_type[0x4];
9934 	u8         height_grade[0x18];
9935 
9936 	u8         height_dz[0x10];
9937 	u8         height_dv[0x10];
9938 
9939 	u8         reserved_at_a0[0x10];
9940 	u8         height_sigma[0x10];
9941 
9942 	u8         reserved_at_c0[0x20];
9943 
9944 	u8         reserved_at_e0[0x4];
9945 	u8         phase_grade_type[0x4];
9946 	u8         phase_grade[0x18];
9947 
9948 	u8         reserved_at_100[0x8];
9949 	u8         phase_eo_pos[0x8];
9950 	u8         reserved_at_110[0x8];
9951 	u8         phase_eo_neg[0x8];
9952 
9953 	u8         ffe_set_tested[0x10];
9954 	u8         test_errors_per_lane[0x10];
9955 };
9956 
9957 struct mlx5_ifc_pvlc_reg_bits {
9958 	u8         reserved_at_0[0x8];
9959 	u8         local_port[0x8];
9960 	u8         reserved_at_10[0x10];
9961 
9962 	u8         reserved_at_20[0x1c];
9963 	u8         vl_hw_cap[0x4];
9964 
9965 	u8         reserved_at_40[0x1c];
9966 	u8         vl_admin[0x4];
9967 
9968 	u8         reserved_at_60[0x1c];
9969 	u8         vl_operational[0x4];
9970 };
9971 
9972 struct mlx5_ifc_pude_reg_bits {
9973 	u8         swid[0x8];
9974 	u8         local_port[0x8];
9975 	u8         reserved_at_10[0x4];
9976 	u8         admin_status[0x4];
9977 	u8         reserved_at_18[0x4];
9978 	u8         oper_status[0x4];
9979 
9980 	u8         reserved_at_20[0x60];
9981 };
9982 
9983 struct mlx5_ifc_ptys_reg_bits {
9984 	u8         reserved_at_0[0x1];
9985 	u8         an_disable_admin[0x1];
9986 	u8         an_disable_cap[0x1];
9987 	u8         reserved_at_3[0x5];
9988 	u8         local_port[0x8];
9989 	u8         reserved_at_10[0x8];
9990 	u8         plane_ind[0x4];
9991 	u8         reserved_at_1c[0x1];
9992 	u8         proto_mask[0x3];
9993 
9994 	u8         an_status[0x4];
9995 	u8         reserved_at_24[0xc];
9996 	u8         data_rate_oper[0x10];
9997 
9998 	u8         ext_eth_proto_capability[0x20];
9999 
10000 	u8         eth_proto_capability[0x20];
10001 
10002 	u8         ib_link_width_capability[0x10];
10003 	u8         ib_proto_capability[0x10];
10004 
10005 	u8         ext_eth_proto_admin[0x20];
10006 
10007 	u8         eth_proto_admin[0x20];
10008 
10009 	u8         ib_link_width_admin[0x10];
10010 	u8         ib_proto_admin[0x10];
10011 
10012 	u8         ext_eth_proto_oper[0x20];
10013 
10014 	u8         eth_proto_oper[0x20];
10015 
10016 	u8         ib_link_width_oper[0x10];
10017 	u8         ib_proto_oper[0x10];
10018 
10019 	u8         reserved_at_160[0x1c];
10020 	u8         connector_type[0x4];
10021 
10022 	u8         eth_proto_lp_advertise[0x20];
10023 
10024 	u8         reserved_at_1a0[0x60];
10025 };
10026 
10027 struct mlx5_ifc_mlcr_reg_bits {
10028 	u8         reserved_at_0[0x8];
10029 	u8         local_port[0x8];
10030 	u8         reserved_at_10[0x20];
10031 
10032 	u8         beacon_duration[0x10];
10033 	u8         reserved_at_40[0x10];
10034 
10035 	u8         beacon_remain[0x10];
10036 };
10037 
10038 struct mlx5_ifc_ptas_reg_bits {
10039 	u8         reserved_at_0[0x20];
10040 
10041 	u8         algorithm_options[0x10];
10042 	u8         reserved_at_30[0x4];
10043 	u8         repetitions_mode[0x4];
10044 	u8         num_of_repetitions[0x8];
10045 
10046 	u8         grade_version[0x8];
10047 	u8         height_grade_type[0x4];
10048 	u8         phase_grade_type[0x4];
10049 	u8         height_grade_weight[0x8];
10050 	u8         phase_grade_weight[0x8];
10051 
10052 	u8         gisim_measure_bits[0x10];
10053 	u8         adaptive_tap_measure_bits[0x10];
10054 
10055 	u8         ber_bath_high_error_threshold[0x10];
10056 	u8         ber_bath_mid_error_threshold[0x10];
10057 
10058 	u8         ber_bath_low_error_threshold[0x10];
10059 	u8         one_ratio_high_threshold[0x10];
10060 
10061 	u8         one_ratio_high_mid_threshold[0x10];
10062 	u8         one_ratio_low_mid_threshold[0x10];
10063 
10064 	u8         one_ratio_low_threshold[0x10];
10065 	u8         ndeo_error_threshold[0x10];
10066 
10067 	u8         mixer_offset_step_size[0x10];
10068 	u8         reserved_at_110[0x8];
10069 	u8         mix90_phase_for_voltage_bath[0x8];
10070 
10071 	u8         mixer_offset_start[0x10];
10072 	u8         mixer_offset_end[0x10];
10073 
10074 	u8         reserved_at_140[0x15];
10075 	u8         ber_test_time[0xb];
10076 };
10077 
10078 struct mlx5_ifc_pspa_reg_bits {
10079 	u8         swid[0x8];
10080 	u8         local_port[0x8];
10081 	u8         sub_port[0x8];
10082 	u8         reserved_at_18[0x8];
10083 
10084 	u8         reserved_at_20[0x20];
10085 };
10086 
10087 struct mlx5_ifc_pqdr_reg_bits {
10088 	u8         reserved_at_0[0x8];
10089 	u8         local_port[0x8];
10090 	u8         reserved_at_10[0x5];
10091 	u8         prio[0x3];
10092 	u8         reserved_at_18[0x6];
10093 	u8         mode[0x2];
10094 
10095 	u8         reserved_at_20[0x20];
10096 
10097 	u8         reserved_at_40[0x10];
10098 	u8         min_threshold[0x10];
10099 
10100 	u8         reserved_at_60[0x10];
10101 	u8         max_threshold[0x10];
10102 
10103 	u8         reserved_at_80[0x10];
10104 	u8         mark_probability_denominator[0x10];
10105 
10106 	u8         reserved_at_a0[0x60];
10107 };
10108 
10109 struct mlx5_ifc_ppsc_reg_bits {
10110 	u8         reserved_at_0[0x8];
10111 	u8         local_port[0x8];
10112 	u8         reserved_at_10[0x10];
10113 
10114 	u8         reserved_at_20[0x60];
10115 
10116 	u8         reserved_at_80[0x1c];
10117 	u8         wrps_admin[0x4];
10118 
10119 	u8         reserved_at_a0[0x1c];
10120 	u8         wrps_status[0x4];
10121 
10122 	u8         reserved_at_c0[0x8];
10123 	u8         up_threshold[0x8];
10124 	u8         reserved_at_d0[0x8];
10125 	u8         down_threshold[0x8];
10126 
10127 	u8         reserved_at_e0[0x20];
10128 
10129 	u8         reserved_at_100[0x1c];
10130 	u8         srps_admin[0x4];
10131 
10132 	u8         reserved_at_120[0x1c];
10133 	u8         srps_status[0x4];
10134 
10135 	u8         reserved_at_140[0x40];
10136 };
10137 
10138 struct mlx5_ifc_pplr_reg_bits {
10139 	u8         reserved_at_0[0x8];
10140 	u8         local_port[0x8];
10141 	u8         reserved_at_10[0x10];
10142 
10143 	u8         reserved_at_20[0x8];
10144 	u8         lb_cap[0x8];
10145 	u8         reserved_at_30[0x8];
10146 	u8         lb_en[0x8];
10147 };
10148 
10149 struct mlx5_ifc_pplm_reg_bits {
10150 	u8         reserved_at_0[0x8];
10151 	u8	   local_port[0x8];
10152 	u8	   reserved_at_10[0x10];
10153 
10154 	u8	   reserved_at_20[0x20];
10155 
10156 	u8	   port_profile_mode[0x8];
10157 	u8	   static_port_profile[0x8];
10158 	u8	   active_port_profile[0x8];
10159 	u8	   reserved_at_58[0x8];
10160 
10161 	u8	   retransmission_active[0x8];
10162 	u8	   fec_mode_active[0x18];
10163 
10164 	u8	   rs_fec_correction_bypass_cap[0x4];
10165 	u8	   reserved_at_84[0x8];
10166 	u8	   fec_override_cap_56g[0x4];
10167 	u8	   fec_override_cap_100g[0x4];
10168 	u8	   fec_override_cap_50g[0x4];
10169 	u8	   fec_override_cap_25g[0x4];
10170 	u8	   fec_override_cap_10g_40g[0x4];
10171 
10172 	u8	   rs_fec_correction_bypass_admin[0x4];
10173 	u8	   reserved_at_a4[0x8];
10174 	u8	   fec_override_admin_56g[0x4];
10175 	u8	   fec_override_admin_100g[0x4];
10176 	u8	   fec_override_admin_50g[0x4];
10177 	u8	   fec_override_admin_25g[0x4];
10178 	u8	   fec_override_admin_10g_40g[0x4];
10179 
10180 	u8         fec_override_cap_400g_8x[0x10];
10181 	u8         fec_override_cap_200g_4x[0x10];
10182 
10183 	u8         fec_override_cap_100g_2x[0x10];
10184 	u8         fec_override_cap_50g_1x[0x10];
10185 
10186 	u8         fec_override_admin_400g_8x[0x10];
10187 	u8         fec_override_admin_200g_4x[0x10];
10188 
10189 	u8         fec_override_admin_100g_2x[0x10];
10190 	u8         fec_override_admin_50g_1x[0x10];
10191 
10192 	u8         fec_override_cap_800g_8x[0x10];
10193 	u8         fec_override_cap_400g_4x[0x10];
10194 
10195 	u8         fec_override_cap_200g_2x[0x10];
10196 	u8         fec_override_cap_100g_1x[0x10];
10197 
10198 	u8         reserved_at_180[0xa0];
10199 
10200 	u8         fec_override_admin_800g_8x[0x10];
10201 	u8         fec_override_admin_400g_4x[0x10];
10202 
10203 	u8         fec_override_admin_200g_2x[0x10];
10204 	u8         fec_override_admin_100g_1x[0x10];
10205 
10206 	u8         reserved_at_260[0x60];
10207 
10208 	u8         fec_override_cap_1600g_8x[0x10];
10209 	u8         fec_override_cap_800g_4x[0x10];
10210 
10211 	u8         fec_override_cap_400g_2x[0x10];
10212 	u8         fec_override_cap_200g_1x[0x10];
10213 
10214 	u8         fec_override_admin_1600g_8x[0x10];
10215 	u8         fec_override_admin_800g_4x[0x10];
10216 
10217 	u8         fec_override_admin_400g_2x[0x10];
10218 	u8         fec_override_admin_200g_1x[0x10];
10219 
10220 	u8         reserved_at_340[0x80];
10221 };
10222 
10223 struct mlx5_ifc_ppcnt_reg_bits {
10224 	u8         swid[0x8];
10225 	u8         local_port[0x8];
10226 	u8         pnat[0x2];
10227 	u8         reserved_at_12[0x8];
10228 	u8         grp[0x6];
10229 
10230 	u8         clr[0x1];
10231 	u8         reserved_at_21[0x13];
10232 	u8         plane_ind[0x4];
10233 	u8         reserved_at_38[0x3];
10234 	u8         prio_tc[0x5];
10235 
10236 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10237 };
10238 
10239 struct mlx5_ifc_mpein_reg_bits {
10240 	u8         reserved_at_0[0x2];
10241 	u8         depth[0x6];
10242 	u8         pcie_index[0x8];
10243 	u8         node[0x8];
10244 	u8         reserved_at_18[0x8];
10245 
10246 	u8         capability_mask[0x20];
10247 
10248 	u8         reserved_at_40[0x8];
10249 	u8         link_width_enabled[0x8];
10250 	u8         link_speed_enabled[0x10];
10251 
10252 	u8         lane0_physical_position[0x8];
10253 	u8         link_width_active[0x8];
10254 	u8         link_speed_active[0x10];
10255 
10256 	u8         num_of_pfs[0x10];
10257 	u8         num_of_vfs[0x10];
10258 
10259 	u8         bdf0[0x10];
10260 	u8         reserved_at_b0[0x10];
10261 
10262 	u8         max_read_request_size[0x4];
10263 	u8         max_payload_size[0x4];
10264 	u8         reserved_at_c8[0x5];
10265 	u8         pwr_status[0x3];
10266 	u8         port_type[0x4];
10267 	u8         reserved_at_d4[0xb];
10268 	u8         lane_reversal[0x1];
10269 
10270 	u8         reserved_at_e0[0x14];
10271 	u8         pci_power[0xc];
10272 
10273 	u8         reserved_at_100[0x20];
10274 
10275 	u8         device_status[0x10];
10276 	u8         port_state[0x8];
10277 	u8         reserved_at_138[0x8];
10278 
10279 	u8         reserved_at_140[0x10];
10280 	u8         receiver_detect_result[0x10];
10281 
10282 	u8         reserved_at_160[0x20];
10283 };
10284 
10285 struct mlx5_ifc_mpcnt_reg_bits {
10286 	u8         reserved_at_0[0x8];
10287 	u8         pcie_index[0x8];
10288 	u8         reserved_at_10[0xa];
10289 	u8         grp[0x6];
10290 
10291 	u8         clr[0x1];
10292 	u8         reserved_at_21[0x1f];
10293 
10294 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10295 };
10296 
10297 struct mlx5_ifc_ppad_reg_bits {
10298 	u8         reserved_at_0[0x3];
10299 	u8         single_mac[0x1];
10300 	u8         reserved_at_4[0x4];
10301 	u8         local_port[0x8];
10302 	u8         mac_47_32[0x10];
10303 
10304 	u8         mac_31_0[0x20];
10305 
10306 	u8         reserved_at_40[0x40];
10307 };
10308 
10309 struct mlx5_ifc_pmtu_reg_bits {
10310 	u8         reserved_at_0[0x8];
10311 	u8         local_port[0x8];
10312 	u8         reserved_at_10[0x10];
10313 
10314 	u8         max_mtu[0x10];
10315 	u8         reserved_at_30[0x10];
10316 
10317 	u8         admin_mtu[0x10];
10318 	u8         reserved_at_50[0x10];
10319 
10320 	u8         oper_mtu[0x10];
10321 	u8         reserved_at_70[0x10];
10322 };
10323 
10324 struct mlx5_ifc_pmpr_reg_bits {
10325 	u8         reserved_at_0[0x8];
10326 	u8         module[0x8];
10327 	u8         reserved_at_10[0x10];
10328 
10329 	u8         reserved_at_20[0x18];
10330 	u8         attenuation_5g[0x8];
10331 
10332 	u8         reserved_at_40[0x18];
10333 	u8         attenuation_7g[0x8];
10334 
10335 	u8         reserved_at_60[0x18];
10336 	u8         attenuation_12g[0x8];
10337 };
10338 
10339 struct mlx5_ifc_pmpe_reg_bits {
10340 	u8         reserved_at_0[0x8];
10341 	u8         module[0x8];
10342 	u8         reserved_at_10[0xc];
10343 	u8         module_status[0x4];
10344 
10345 	u8         reserved_at_20[0x60];
10346 };
10347 
10348 struct mlx5_ifc_pmpc_reg_bits {
10349 	u8         module_state_updated[32][0x8];
10350 };
10351 
10352 struct mlx5_ifc_pmlpn_reg_bits {
10353 	u8         reserved_at_0[0x4];
10354 	u8         mlpn_status[0x4];
10355 	u8         local_port[0x8];
10356 	u8         reserved_at_10[0x10];
10357 
10358 	u8         e[0x1];
10359 	u8         reserved_at_21[0x1f];
10360 };
10361 
10362 struct mlx5_ifc_pmlp_reg_bits {
10363 	u8         rxtx[0x1];
10364 	u8         reserved_at_1[0x7];
10365 	u8         local_port[0x8];
10366 	u8         reserved_at_10[0x8];
10367 	u8         width[0x8];
10368 
10369 	u8         lane0_module_mapping[0x20];
10370 
10371 	u8         lane1_module_mapping[0x20];
10372 
10373 	u8         lane2_module_mapping[0x20];
10374 
10375 	u8         lane3_module_mapping[0x20];
10376 
10377 	u8         reserved_at_a0[0x160];
10378 };
10379 
10380 struct mlx5_ifc_pmaos_reg_bits {
10381 	u8         reserved_at_0[0x8];
10382 	u8         module[0x8];
10383 	u8         reserved_at_10[0x4];
10384 	u8         admin_status[0x4];
10385 	u8         reserved_at_18[0x4];
10386 	u8         oper_status[0x4];
10387 
10388 	u8         ase[0x1];
10389 	u8         ee[0x1];
10390 	u8         reserved_at_22[0x1c];
10391 	u8         e[0x2];
10392 
10393 	u8         reserved_at_40[0x40];
10394 };
10395 
10396 struct mlx5_ifc_plpc_reg_bits {
10397 	u8         reserved_at_0[0x4];
10398 	u8         profile_id[0xc];
10399 	u8         reserved_at_10[0x4];
10400 	u8         proto_mask[0x4];
10401 	u8         reserved_at_18[0x8];
10402 
10403 	u8         reserved_at_20[0x10];
10404 	u8         lane_speed[0x10];
10405 
10406 	u8         reserved_at_40[0x17];
10407 	u8         lpbf[0x1];
10408 	u8         fec_mode_policy[0x8];
10409 
10410 	u8         retransmission_capability[0x8];
10411 	u8         fec_mode_capability[0x18];
10412 
10413 	u8         retransmission_support_admin[0x8];
10414 	u8         fec_mode_support_admin[0x18];
10415 
10416 	u8         retransmission_request_admin[0x8];
10417 	u8         fec_mode_request_admin[0x18];
10418 
10419 	u8         reserved_at_c0[0x80];
10420 };
10421 
10422 struct mlx5_ifc_plib_reg_bits {
10423 	u8         reserved_at_0[0x8];
10424 	u8         local_port[0x8];
10425 	u8         reserved_at_10[0x8];
10426 	u8         ib_port[0x8];
10427 
10428 	u8         reserved_at_20[0x60];
10429 };
10430 
10431 struct mlx5_ifc_plbf_reg_bits {
10432 	u8         reserved_at_0[0x8];
10433 	u8         local_port[0x8];
10434 	u8         reserved_at_10[0xd];
10435 	u8         lbf_mode[0x3];
10436 
10437 	u8         reserved_at_20[0x20];
10438 };
10439 
10440 struct mlx5_ifc_pipg_reg_bits {
10441 	u8         reserved_at_0[0x8];
10442 	u8         local_port[0x8];
10443 	u8         reserved_at_10[0x10];
10444 
10445 	u8         dic[0x1];
10446 	u8         reserved_at_21[0x19];
10447 	u8         ipg[0x4];
10448 	u8         reserved_at_3e[0x2];
10449 };
10450 
10451 struct mlx5_ifc_pifr_reg_bits {
10452 	u8         reserved_at_0[0x8];
10453 	u8         local_port[0x8];
10454 	u8         reserved_at_10[0x10];
10455 
10456 	u8         reserved_at_20[0xe0];
10457 
10458 	u8         port_filter[8][0x20];
10459 
10460 	u8         port_filter_update_en[8][0x20];
10461 };
10462 
10463 struct mlx5_ifc_pfcc_reg_bits {
10464 	u8         reserved_at_0[0x8];
10465 	u8         local_port[0x8];
10466 	u8         reserved_at_10[0xb];
10467 	u8         ppan_mask_n[0x1];
10468 	u8         minor_stall_mask[0x1];
10469 	u8         critical_stall_mask[0x1];
10470 	u8         reserved_at_1e[0x2];
10471 
10472 	u8         ppan[0x4];
10473 	u8         reserved_at_24[0x4];
10474 	u8         prio_mask_tx[0x8];
10475 	u8         reserved_at_30[0x8];
10476 	u8         prio_mask_rx[0x8];
10477 
10478 	u8         pptx[0x1];
10479 	u8         aptx[0x1];
10480 	u8         pptx_mask_n[0x1];
10481 	u8         reserved_at_43[0x5];
10482 	u8         pfctx[0x8];
10483 	u8         reserved_at_50[0x10];
10484 
10485 	u8         pprx[0x1];
10486 	u8         aprx[0x1];
10487 	u8         pprx_mask_n[0x1];
10488 	u8         reserved_at_63[0x5];
10489 	u8         pfcrx[0x8];
10490 	u8         reserved_at_70[0x10];
10491 
10492 	u8         device_stall_minor_watermark[0x10];
10493 	u8         device_stall_critical_watermark[0x10];
10494 
10495 	u8         reserved_at_a0[0x60];
10496 };
10497 
10498 struct mlx5_ifc_pelc_reg_bits {
10499 	u8         op[0x4];
10500 	u8         reserved_at_4[0x4];
10501 	u8         local_port[0x8];
10502 	u8         reserved_at_10[0x10];
10503 
10504 	u8         op_admin[0x8];
10505 	u8         op_capability[0x8];
10506 	u8         op_request[0x8];
10507 	u8         op_active[0x8];
10508 
10509 	u8         admin[0x40];
10510 
10511 	u8         capability[0x40];
10512 
10513 	u8         request[0x40];
10514 
10515 	u8         active[0x40];
10516 
10517 	u8         reserved_at_140[0x80];
10518 };
10519 
10520 struct mlx5_ifc_peir_reg_bits {
10521 	u8         reserved_at_0[0x8];
10522 	u8         local_port[0x8];
10523 	u8         reserved_at_10[0x10];
10524 
10525 	u8         reserved_at_20[0xc];
10526 	u8         error_count[0x4];
10527 	u8         reserved_at_30[0x10];
10528 
10529 	u8         reserved_at_40[0xc];
10530 	u8         lane[0x4];
10531 	u8         reserved_at_50[0x8];
10532 	u8         error_type[0x8];
10533 };
10534 
10535 struct mlx5_ifc_mpegc_reg_bits {
10536 	u8         reserved_at_0[0x30];
10537 	u8         field_select[0x10];
10538 
10539 	u8         tx_overflow_sense[0x1];
10540 	u8         mark_cqe[0x1];
10541 	u8         mark_cnp[0x1];
10542 	u8         reserved_at_43[0x1b];
10543 	u8         tx_lossy_overflow_oper[0x2];
10544 
10545 	u8         reserved_at_60[0x100];
10546 };
10547 
10548 struct mlx5_ifc_mpir_reg_bits {
10549 	u8         sdm[0x1];
10550 	u8         reserved_at_1[0x1b];
10551 	u8         host_buses[0x4];
10552 
10553 	u8         reserved_at_20[0x20];
10554 
10555 	u8         local_port[0x8];
10556 	u8         reserved_at_28[0x18];
10557 
10558 	u8         reserved_at_60[0x20];
10559 };
10560 
10561 enum {
10562 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10563 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10564 };
10565 
10566 enum {
10567 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10568 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10569 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10570 };
10571 
10572 struct mlx5_ifc_mtutc_reg_bits {
10573 	u8         reserved_at_0[0x5];
10574 	u8         freq_adj_units[0x3];
10575 	u8         reserved_at_8[0x3];
10576 	u8         log_max_freq_adjustment[0x5];
10577 
10578 	u8         reserved_at_10[0xc];
10579 	u8         operation[0x4];
10580 
10581 	u8         freq_adjustment[0x20];
10582 
10583 	u8         reserved_at_40[0x40];
10584 
10585 	u8         utc_sec[0x20];
10586 
10587 	u8         reserved_at_a0[0x2];
10588 	u8         utc_nsec[0x1e];
10589 
10590 	u8         time_adjustment[0x20];
10591 };
10592 
10593 struct mlx5_ifc_pcam_enhanced_features_bits {
10594 	u8         reserved_at_0[0x10];
10595 	u8         ppcnt_recovery_counters[0x1];
10596 	u8         reserved_at_11[0xc];
10597 	u8         fec_200G_per_lane_in_pplm[0x1];
10598 	u8         reserved_at_1e[0x2a];
10599 	u8         fec_100G_per_lane_in_pplm[0x1];
10600 	u8         reserved_at_49[0x1f];
10601 	u8         fec_50G_per_lane_in_pplm[0x1];
10602 	u8         reserved_at_69[0x4];
10603 	u8         rx_icrc_encapsulated_counter[0x1];
10604 	u8	   reserved_at_6e[0x4];
10605 	u8         ptys_extended_ethernet[0x1];
10606 	u8	   reserved_at_73[0x3];
10607 	u8         pfcc_mask[0x1];
10608 	u8         reserved_at_77[0x3];
10609 	u8         per_lane_error_counters[0x1];
10610 	u8         rx_buffer_fullness_counters[0x1];
10611 	u8         ptys_connector_type[0x1];
10612 	u8         reserved_at_7d[0x1];
10613 	u8         ppcnt_discard_group[0x1];
10614 	u8         ppcnt_statistical_group[0x1];
10615 };
10616 
10617 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10618 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10619 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10620 
10621 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10622 	u8         pplm[0x1];
10623 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10624 
10625 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10626 	u8         pbmc[0x1];
10627 	u8         pptb[0x1];
10628 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10629 	u8         ppcnt[0x1];
10630 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10631 };
10632 
10633 struct mlx5_ifc_pcam_reg_bits {
10634 	u8         reserved_at_0[0x8];
10635 	u8         feature_group[0x8];
10636 	u8         reserved_at_10[0x8];
10637 	u8         access_reg_group[0x8];
10638 
10639 	u8         reserved_at_20[0x20];
10640 
10641 	union {
10642 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10643 		u8         reserved_at_0[0x80];
10644 	} port_access_reg_cap_mask;
10645 
10646 	u8         reserved_at_c0[0x80];
10647 
10648 	union {
10649 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10650 		u8         reserved_at_0[0x80];
10651 	} feature_cap_mask;
10652 
10653 	u8         reserved_at_1c0[0xc0];
10654 };
10655 
10656 struct mlx5_ifc_mcam_enhanced_features_bits {
10657 	u8         reserved_at_0[0x50];
10658 	u8         mtutc_freq_adj_units[0x1];
10659 	u8         mtutc_time_adjustment_extended_range[0x1];
10660 	u8         reserved_at_52[0xb];
10661 	u8         mcia_32dwords[0x1];
10662 	u8         out_pulse_duration_ns[0x1];
10663 	u8         npps_period[0x1];
10664 	u8         reserved_at_60[0xa];
10665 	u8         reset_state[0x1];
10666 	u8         ptpcyc2realtime_modify[0x1];
10667 	u8         reserved_at_6c[0x2];
10668 	u8         pci_status_and_power[0x1];
10669 	u8         reserved_at_6f[0x5];
10670 	u8         mark_tx_action_cnp[0x1];
10671 	u8         mark_tx_action_cqe[0x1];
10672 	u8         dynamic_tx_overflow[0x1];
10673 	u8         reserved_at_77[0x4];
10674 	u8         pcie_outbound_stalled[0x1];
10675 	u8         tx_overflow_buffer_pkt[0x1];
10676 	u8         mtpps_enh_out_per_adj[0x1];
10677 	u8         mtpps_fs[0x1];
10678 	u8         pcie_performance_group[0x1];
10679 };
10680 
10681 struct mlx5_ifc_mcam_access_reg_bits {
10682 	u8         reserved_at_0[0x1c];
10683 	u8         mcda[0x1];
10684 	u8         mcc[0x1];
10685 	u8         mcqi[0x1];
10686 	u8         mcqs[0x1];
10687 
10688 	u8         regs_95_to_90[0x6];
10689 	u8         mpir[0x1];
10690 	u8         regs_88_to_87[0x2];
10691 	u8         mpegc[0x1];
10692 	u8         mtutc[0x1];
10693 	u8         regs_84_to_68[0x11];
10694 	u8         tracer_registers[0x4];
10695 
10696 	u8         regs_63_to_46[0x12];
10697 	u8         mrtc[0x1];
10698 	u8         regs_44_to_41[0x4];
10699 	u8         mfrl[0x1];
10700 	u8         regs_39_to_32[0x8];
10701 
10702 	u8         regs_31_to_11[0x15];
10703 	u8         mtmp[0x1];
10704 	u8         regs_9_to_0[0xa];
10705 };
10706 
10707 struct mlx5_ifc_mcam_access_reg_bits1 {
10708 	u8         regs_127_to_96[0x20];
10709 
10710 	u8         regs_95_to_64[0x20];
10711 
10712 	u8         regs_63_to_32[0x20];
10713 
10714 	u8         regs_31_to_0[0x20];
10715 };
10716 
10717 struct mlx5_ifc_mcam_access_reg_bits2 {
10718 	u8         regs_127_to_99[0x1d];
10719 	u8         mirc[0x1];
10720 	u8         regs_97_to_96[0x2];
10721 
10722 	u8         regs_95_to_87[0x09];
10723 	u8         synce_registers[0x2];
10724 	u8         regs_84_to_64[0x15];
10725 
10726 	u8         regs_63_to_32[0x20];
10727 
10728 	u8         regs_31_to_0[0x20];
10729 };
10730 
10731 struct mlx5_ifc_mcam_access_reg_bits3 {
10732 	u8         regs_127_to_96[0x20];
10733 
10734 	u8         regs_95_to_64[0x20];
10735 
10736 	u8         regs_63_to_32[0x20];
10737 
10738 	u8         regs_31_to_3[0x1d];
10739 	u8         mrtcq[0x1];
10740 	u8         mtctr[0x1];
10741 	u8         mtptm[0x1];
10742 };
10743 
10744 struct mlx5_ifc_mcam_reg_bits {
10745 	u8         reserved_at_0[0x8];
10746 	u8         feature_group[0x8];
10747 	u8         reserved_at_10[0x8];
10748 	u8         access_reg_group[0x8];
10749 
10750 	u8         reserved_at_20[0x20];
10751 
10752 	union {
10753 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10754 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10755 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10756 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10757 		u8         reserved_at_0[0x80];
10758 	} mng_access_reg_cap_mask;
10759 
10760 	u8         reserved_at_c0[0x80];
10761 
10762 	union {
10763 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10764 		u8         reserved_at_0[0x80];
10765 	} mng_feature_cap_mask;
10766 
10767 	u8         reserved_at_1c0[0x80];
10768 };
10769 
10770 struct mlx5_ifc_qcam_access_reg_cap_mask {
10771 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10772 	u8         qpdpm[0x1];
10773 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10774 	u8         qdpm[0x1];
10775 	u8         qpts[0x1];
10776 	u8         qcap[0x1];
10777 	u8         qcam_access_reg_cap_mask_0[0x1];
10778 };
10779 
10780 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10781 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10782 	u8         qpts_trust_both[0x1];
10783 };
10784 
10785 struct mlx5_ifc_qcam_reg_bits {
10786 	u8         reserved_at_0[0x8];
10787 	u8         feature_group[0x8];
10788 	u8         reserved_at_10[0x8];
10789 	u8         access_reg_group[0x8];
10790 	u8         reserved_at_20[0x20];
10791 
10792 	union {
10793 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10794 		u8  reserved_at_0[0x80];
10795 	} qos_access_reg_cap_mask;
10796 
10797 	u8         reserved_at_c0[0x80];
10798 
10799 	union {
10800 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10801 		u8  reserved_at_0[0x80];
10802 	} qos_feature_cap_mask;
10803 
10804 	u8         reserved_at_1c0[0x80];
10805 };
10806 
10807 struct mlx5_ifc_core_dump_reg_bits {
10808 	u8         reserved_at_0[0x18];
10809 	u8         core_dump_type[0x8];
10810 
10811 	u8         reserved_at_20[0x30];
10812 	u8         vhca_id[0x10];
10813 
10814 	u8         reserved_at_60[0x8];
10815 	u8         qpn[0x18];
10816 	u8         reserved_at_80[0x180];
10817 };
10818 
10819 struct mlx5_ifc_pcap_reg_bits {
10820 	u8         reserved_at_0[0x8];
10821 	u8         local_port[0x8];
10822 	u8         reserved_at_10[0x10];
10823 
10824 	u8         port_capability_mask[4][0x20];
10825 };
10826 
10827 struct mlx5_ifc_paos_reg_bits {
10828 	u8         swid[0x8];
10829 	u8         local_port[0x8];
10830 	u8         reserved_at_10[0x4];
10831 	u8         admin_status[0x4];
10832 	u8         reserved_at_18[0x4];
10833 	u8         oper_status[0x4];
10834 
10835 	u8         ase[0x1];
10836 	u8         ee[0x1];
10837 	u8         reserved_at_22[0x1c];
10838 	u8         e[0x2];
10839 
10840 	u8         reserved_at_40[0x40];
10841 };
10842 
10843 struct mlx5_ifc_pamp_reg_bits {
10844 	u8         reserved_at_0[0x8];
10845 	u8         opamp_group[0x8];
10846 	u8         reserved_at_10[0xc];
10847 	u8         opamp_group_type[0x4];
10848 
10849 	u8         start_index[0x10];
10850 	u8         reserved_at_30[0x4];
10851 	u8         num_of_indices[0xc];
10852 
10853 	u8         index_data[18][0x10];
10854 };
10855 
10856 struct mlx5_ifc_pcmr_reg_bits {
10857 	u8         reserved_at_0[0x8];
10858 	u8         local_port[0x8];
10859 	u8         reserved_at_10[0x10];
10860 
10861 	u8         entropy_force_cap[0x1];
10862 	u8         entropy_calc_cap[0x1];
10863 	u8         entropy_gre_calc_cap[0x1];
10864 	u8         reserved_at_23[0xf];
10865 	u8         rx_ts_over_crc_cap[0x1];
10866 	u8         reserved_at_33[0xb];
10867 	u8         fcs_cap[0x1];
10868 	u8         reserved_at_3f[0x1];
10869 
10870 	u8         entropy_force[0x1];
10871 	u8         entropy_calc[0x1];
10872 	u8         entropy_gre_calc[0x1];
10873 	u8         reserved_at_43[0xf];
10874 	u8         rx_ts_over_crc[0x1];
10875 	u8         reserved_at_53[0xb];
10876 	u8         fcs_chk[0x1];
10877 	u8         reserved_at_5f[0x1];
10878 };
10879 
10880 struct mlx5_ifc_lane_2_module_mapping_bits {
10881 	u8         reserved_at_0[0x4];
10882 	u8         rx_lane[0x4];
10883 	u8         reserved_at_8[0x4];
10884 	u8         tx_lane[0x4];
10885 	u8         reserved_at_10[0x8];
10886 	u8         module[0x8];
10887 };
10888 
10889 struct mlx5_ifc_bufferx_reg_bits {
10890 	u8         reserved_at_0[0x6];
10891 	u8         lossy[0x1];
10892 	u8         epsb[0x1];
10893 	u8         reserved_at_8[0x8];
10894 	u8         size[0x10];
10895 
10896 	u8         xoff_threshold[0x10];
10897 	u8         xon_threshold[0x10];
10898 };
10899 
10900 struct mlx5_ifc_set_node_in_bits {
10901 	u8         node_description[64][0x8];
10902 };
10903 
10904 struct mlx5_ifc_register_power_settings_bits {
10905 	u8         reserved_at_0[0x18];
10906 	u8         power_settings_level[0x8];
10907 
10908 	u8         reserved_at_20[0x60];
10909 };
10910 
10911 struct mlx5_ifc_register_host_endianness_bits {
10912 	u8         he[0x1];
10913 	u8         reserved_at_1[0x1f];
10914 
10915 	u8         reserved_at_20[0x60];
10916 };
10917 
10918 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10919 	u8         reserved_at_0[0x20];
10920 
10921 	u8         mkey[0x20];
10922 
10923 	u8         addressh_63_32[0x20];
10924 
10925 	u8         addressl_31_0[0x20];
10926 };
10927 
10928 struct mlx5_ifc_ud_adrs_vector_bits {
10929 	u8         dc_key[0x40];
10930 
10931 	u8         ext[0x1];
10932 	u8         reserved_at_41[0x7];
10933 	u8         destination_qp_dct[0x18];
10934 
10935 	u8         static_rate[0x4];
10936 	u8         sl_eth_prio[0x4];
10937 	u8         fl[0x1];
10938 	u8         mlid[0x7];
10939 	u8         rlid_udp_sport[0x10];
10940 
10941 	u8         reserved_at_80[0x20];
10942 
10943 	u8         rmac_47_16[0x20];
10944 
10945 	u8         rmac_15_0[0x10];
10946 	u8         tclass[0x8];
10947 	u8         hop_limit[0x8];
10948 
10949 	u8         reserved_at_e0[0x1];
10950 	u8         grh[0x1];
10951 	u8         reserved_at_e2[0x2];
10952 	u8         src_addr_index[0x8];
10953 	u8         flow_label[0x14];
10954 
10955 	u8         rgid_rip[16][0x8];
10956 };
10957 
10958 struct mlx5_ifc_pages_req_event_bits {
10959 	u8         reserved_at_0[0x10];
10960 	u8         function_id[0x10];
10961 
10962 	u8         num_pages[0x20];
10963 
10964 	u8         reserved_at_40[0xa0];
10965 };
10966 
10967 struct mlx5_ifc_eqe_bits {
10968 	u8         reserved_at_0[0x8];
10969 	u8         event_type[0x8];
10970 	u8         reserved_at_10[0x8];
10971 	u8         event_sub_type[0x8];
10972 
10973 	u8         reserved_at_20[0xe0];
10974 
10975 	union mlx5_ifc_event_auto_bits event_data;
10976 
10977 	u8         reserved_at_1e0[0x10];
10978 	u8         signature[0x8];
10979 	u8         reserved_at_1f8[0x7];
10980 	u8         owner[0x1];
10981 };
10982 
10983 enum {
10984 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10985 };
10986 
10987 struct mlx5_ifc_cmd_queue_entry_bits {
10988 	u8         type[0x8];
10989 	u8         reserved_at_8[0x18];
10990 
10991 	u8         input_length[0x20];
10992 
10993 	u8         input_mailbox_pointer_63_32[0x20];
10994 
10995 	u8         input_mailbox_pointer_31_9[0x17];
10996 	u8         reserved_at_77[0x9];
10997 
10998 	u8         command_input_inline_data[16][0x8];
10999 
11000 	u8         command_output_inline_data[16][0x8];
11001 
11002 	u8         output_mailbox_pointer_63_32[0x20];
11003 
11004 	u8         output_mailbox_pointer_31_9[0x17];
11005 	u8         reserved_at_1b7[0x9];
11006 
11007 	u8         output_length[0x20];
11008 
11009 	u8         token[0x8];
11010 	u8         signature[0x8];
11011 	u8         reserved_at_1f0[0x8];
11012 	u8         status[0x7];
11013 	u8         ownership[0x1];
11014 };
11015 
11016 struct mlx5_ifc_cmd_out_bits {
11017 	u8         status[0x8];
11018 	u8         reserved_at_8[0x18];
11019 
11020 	u8         syndrome[0x20];
11021 
11022 	u8         command_output[0x20];
11023 };
11024 
11025 struct mlx5_ifc_cmd_in_bits {
11026 	u8         opcode[0x10];
11027 	u8         reserved_at_10[0x10];
11028 
11029 	u8         reserved_at_20[0x10];
11030 	u8         op_mod[0x10];
11031 
11032 	u8         command[][0x20];
11033 };
11034 
11035 struct mlx5_ifc_cmd_if_box_bits {
11036 	u8         mailbox_data[512][0x8];
11037 
11038 	u8         reserved_at_1000[0x180];
11039 
11040 	u8         next_pointer_63_32[0x20];
11041 
11042 	u8         next_pointer_31_10[0x16];
11043 	u8         reserved_at_11b6[0xa];
11044 
11045 	u8         block_number[0x20];
11046 
11047 	u8         reserved_at_11e0[0x8];
11048 	u8         token[0x8];
11049 	u8         ctrl_signature[0x8];
11050 	u8         signature[0x8];
11051 };
11052 
11053 struct mlx5_ifc_mtt_bits {
11054 	u8         ptag_63_32[0x20];
11055 
11056 	u8         ptag_31_8[0x18];
11057 	u8         reserved_at_38[0x6];
11058 	u8         wr_en[0x1];
11059 	u8         rd_en[0x1];
11060 };
11061 
11062 struct mlx5_ifc_query_wol_rol_out_bits {
11063 	u8         status[0x8];
11064 	u8         reserved_at_8[0x18];
11065 
11066 	u8         syndrome[0x20];
11067 
11068 	u8         reserved_at_40[0x10];
11069 	u8         rol_mode[0x8];
11070 	u8         wol_mode[0x8];
11071 
11072 	u8         reserved_at_60[0x20];
11073 };
11074 
11075 struct mlx5_ifc_query_wol_rol_in_bits {
11076 	u8         opcode[0x10];
11077 	u8         reserved_at_10[0x10];
11078 
11079 	u8         reserved_at_20[0x10];
11080 	u8         op_mod[0x10];
11081 
11082 	u8         reserved_at_40[0x40];
11083 };
11084 
11085 struct mlx5_ifc_set_wol_rol_out_bits {
11086 	u8         status[0x8];
11087 	u8         reserved_at_8[0x18];
11088 
11089 	u8         syndrome[0x20];
11090 
11091 	u8         reserved_at_40[0x40];
11092 };
11093 
11094 struct mlx5_ifc_set_wol_rol_in_bits {
11095 	u8         opcode[0x10];
11096 	u8         reserved_at_10[0x10];
11097 
11098 	u8         reserved_at_20[0x10];
11099 	u8         op_mod[0x10];
11100 
11101 	u8         rol_mode_valid[0x1];
11102 	u8         wol_mode_valid[0x1];
11103 	u8         reserved_at_42[0xe];
11104 	u8         rol_mode[0x8];
11105 	u8         wol_mode[0x8];
11106 
11107 	u8         reserved_at_60[0x20];
11108 };
11109 
11110 enum {
11111 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11112 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11113 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11114 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11115 };
11116 
11117 enum {
11118 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11119 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11120 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11121 };
11122 
11123 enum {
11124 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11125 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11126 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11127 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11128 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11129 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11130 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11131 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11132 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11133 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11134 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11135 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11136 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR           = 0x13,
11137 };
11138 
11139 struct mlx5_ifc_initial_seg_bits {
11140 	u8         fw_rev_minor[0x10];
11141 	u8         fw_rev_major[0x10];
11142 
11143 	u8         cmd_interface_rev[0x10];
11144 	u8         fw_rev_subminor[0x10];
11145 
11146 	u8         reserved_at_40[0x40];
11147 
11148 	u8         cmdq_phy_addr_63_32[0x20];
11149 
11150 	u8         cmdq_phy_addr_31_12[0x14];
11151 	u8         reserved_at_b4[0x2];
11152 	u8         nic_interface[0x2];
11153 	u8         log_cmdq_size[0x4];
11154 	u8         log_cmdq_stride[0x4];
11155 
11156 	u8         command_doorbell_vector[0x20];
11157 
11158 	u8         reserved_at_e0[0xf00];
11159 
11160 	u8         initializing[0x1];
11161 	u8         reserved_at_fe1[0x4];
11162 	u8         nic_interface_supported[0x3];
11163 	u8         embedded_cpu[0x1];
11164 	u8         reserved_at_fe9[0x17];
11165 
11166 	struct mlx5_ifc_health_buffer_bits health_buffer;
11167 
11168 	u8         no_dram_nic_offset[0x20];
11169 
11170 	u8         reserved_at_1220[0x6e40];
11171 
11172 	u8         reserved_at_8060[0x1f];
11173 	u8         clear_int[0x1];
11174 
11175 	u8         health_syndrome[0x8];
11176 	u8         health_counter[0x18];
11177 
11178 	u8         reserved_at_80a0[0x17fc0];
11179 };
11180 
11181 struct mlx5_ifc_mtpps_reg_bits {
11182 	u8         reserved_at_0[0xc];
11183 	u8         cap_number_of_pps_pins[0x4];
11184 	u8         reserved_at_10[0x4];
11185 	u8         cap_max_num_of_pps_in_pins[0x4];
11186 	u8         reserved_at_18[0x4];
11187 	u8         cap_max_num_of_pps_out_pins[0x4];
11188 
11189 	u8         reserved_at_20[0x13];
11190 	u8         cap_log_min_npps_period[0x5];
11191 	u8         reserved_at_38[0x3];
11192 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11193 
11194 	u8         reserved_at_40[0x4];
11195 	u8         cap_pin_3_mode[0x4];
11196 	u8         reserved_at_48[0x4];
11197 	u8         cap_pin_2_mode[0x4];
11198 	u8         reserved_at_50[0x4];
11199 	u8         cap_pin_1_mode[0x4];
11200 	u8         reserved_at_58[0x4];
11201 	u8         cap_pin_0_mode[0x4];
11202 
11203 	u8         reserved_at_60[0x4];
11204 	u8         cap_pin_7_mode[0x4];
11205 	u8         reserved_at_68[0x4];
11206 	u8         cap_pin_6_mode[0x4];
11207 	u8         reserved_at_70[0x4];
11208 	u8         cap_pin_5_mode[0x4];
11209 	u8         reserved_at_78[0x4];
11210 	u8         cap_pin_4_mode[0x4];
11211 
11212 	u8         field_select[0x20];
11213 	u8         reserved_at_a0[0x20];
11214 
11215 	u8         npps_period[0x40];
11216 
11217 	u8         enable[0x1];
11218 	u8         reserved_at_101[0xb];
11219 	u8         pattern[0x4];
11220 	u8         reserved_at_110[0x4];
11221 	u8         pin_mode[0x4];
11222 	u8         pin[0x8];
11223 
11224 	u8         reserved_at_120[0x2];
11225 	u8         out_pulse_duration_ns[0x1e];
11226 
11227 	u8         time_stamp[0x40];
11228 
11229 	u8         out_pulse_duration[0x10];
11230 	u8         out_periodic_adjustment[0x10];
11231 	u8         enhanced_out_periodic_adjustment[0x20];
11232 
11233 	u8         reserved_at_1c0[0x20];
11234 };
11235 
11236 struct mlx5_ifc_mtppse_reg_bits {
11237 	u8         reserved_at_0[0x18];
11238 	u8         pin[0x8];
11239 	u8         event_arm[0x1];
11240 	u8         reserved_at_21[0x1b];
11241 	u8         event_generation_mode[0x4];
11242 	u8         reserved_at_40[0x40];
11243 };
11244 
11245 struct mlx5_ifc_mcqs_reg_bits {
11246 	u8         last_index_flag[0x1];
11247 	u8         reserved_at_1[0x7];
11248 	u8         fw_device[0x8];
11249 	u8         component_index[0x10];
11250 
11251 	u8         reserved_at_20[0x10];
11252 	u8         identifier[0x10];
11253 
11254 	u8         reserved_at_40[0x17];
11255 	u8         component_status[0x5];
11256 	u8         component_update_state[0x4];
11257 
11258 	u8         last_update_state_changer_type[0x4];
11259 	u8         last_update_state_changer_host_id[0x4];
11260 	u8         reserved_at_68[0x18];
11261 };
11262 
11263 struct mlx5_ifc_mcqi_cap_bits {
11264 	u8         supported_info_bitmask[0x20];
11265 
11266 	u8         component_size[0x20];
11267 
11268 	u8         max_component_size[0x20];
11269 
11270 	u8         log_mcda_word_size[0x4];
11271 	u8         reserved_at_64[0xc];
11272 	u8         mcda_max_write_size[0x10];
11273 
11274 	u8         rd_en[0x1];
11275 	u8         reserved_at_81[0x1];
11276 	u8         match_chip_id[0x1];
11277 	u8         match_psid[0x1];
11278 	u8         check_user_timestamp[0x1];
11279 	u8         match_base_guid_mac[0x1];
11280 	u8         reserved_at_86[0x1a];
11281 };
11282 
11283 struct mlx5_ifc_mcqi_version_bits {
11284 	u8         reserved_at_0[0x2];
11285 	u8         build_time_valid[0x1];
11286 	u8         user_defined_time_valid[0x1];
11287 	u8         reserved_at_4[0x14];
11288 	u8         version_string_length[0x8];
11289 
11290 	u8         version[0x20];
11291 
11292 	u8         build_time[0x40];
11293 
11294 	u8         user_defined_time[0x40];
11295 
11296 	u8         build_tool_version[0x20];
11297 
11298 	u8         reserved_at_e0[0x20];
11299 
11300 	u8         version_string[92][0x8];
11301 };
11302 
11303 struct mlx5_ifc_mcqi_activation_method_bits {
11304 	u8         pending_server_ac_power_cycle[0x1];
11305 	u8         pending_server_dc_power_cycle[0x1];
11306 	u8         pending_server_reboot[0x1];
11307 	u8         pending_fw_reset[0x1];
11308 	u8         auto_activate[0x1];
11309 	u8         all_hosts_sync[0x1];
11310 	u8         device_hw_reset[0x1];
11311 	u8         reserved_at_7[0x19];
11312 };
11313 
11314 union mlx5_ifc_mcqi_reg_data_bits {
11315 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11316 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11317 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11318 };
11319 
11320 struct mlx5_ifc_mcqi_reg_bits {
11321 	u8         read_pending_component[0x1];
11322 	u8         reserved_at_1[0xf];
11323 	u8         component_index[0x10];
11324 
11325 	u8         reserved_at_20[0x20];
11326 
11327 	u8         reserved_at_40[0x1b];
11328 	u8         info_type[0x5];
11329 
11330 	u8         info_size[0x20];
11331 
11332 	u8         offset[0x20];
11333 
11334 	u8         reserved_at_a0[0x10];
11335 	u8         data_size[0x10];
11336 
11337 	union mlx5_ifc_mcqi_reg_data_bits data[];
11338 };
11339 
11340 struct mlx5_ifc_mcc_reg_bits {
11341 	u8         reserved_at_0[0x4];
11342 	u8         time_elapsed_since_last_cmd[0xc];
11343 	u8         reserved_at_10[0x8];
11344 	u8         instruction[0x8];
11345 
11346 	u8         reserved_at_20[0x10];
11347 	u8         component_index[0x10];
11348 
11349 	u8         reserved_at_40[0x8];
11350 	u8         update_handle[0x18];
11351 
11352 	u8         handle_owner_type[0x4];
11353 	u8         handle_owner_host_id[0x4];
11354 	u8         reserved_at_68[0x1];
11355 	u8         control_progress[0x7];
11356 	u8         error_code[0x8];
11357 	u8         reserved_at_78[0x4];
11358 	u8         control_state[0x4];
11359 
11360 	u8         component_size[0x20];
11361 
11362 	u8         reserved_at_a0[0x60];
11363 };
11364 
11365 struct mlx5_ifc_mcda_reg_bits {
11366 	u8         reserved_at_0[0x8];
11367 	u8         update_handle[0x18];
11368 
11369 	u8         offset[0x20];
11370 
11371 	u8         reserved_at_40[0x10];
11372 	u8         size[0x10];
11373 
11374 	u8         reserved_at_60[0x20];
11375 
11376 	u8         data[][0x20];
11377 };
11378 
11379 enum {
11380 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11381 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11382 };
11383 
11384 enum {
11385 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11386 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11387 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11388 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11389 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11390 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11391 };
11392 
11393 enum {
11394 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11395 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11396 };
11397 
11398 enum {
11399 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11400 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11401 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11402 };
11403 
11404 struct mlx5_ifc_mfrl_reg_bits {
11405 	u8         reserved_at_0[0x20];
11406 
11407 	u8         reserved_at_20[0x2];
11408 	u8         pci_sync_for_fw_update_start[0x1];
11409 	u8         pci_sync_for_fw_update_resp[0x2];
11410 	u8         rst_type_sel[0x3];
11411 	u8         pci_reset_req_method[0x3];
11412 	u8         reserved_at_2b[0x1];
11413 	u8         reset_state[0x4];
11414 	u8         reset_type[0x8];
11415 	u8         reset_level[0x8];
11416 };
11417 
11418 struct mlx5_ifc_mirc_reg_bits {
11419 	u8         reserved_at_0[0x18];
11420 	u8         status_code[0x8];
11421 
11422 	u8         reserved_at_20[0x20];
11423 };
11424 
11425 struct mlx5_ifc_pddr_monitor_opcode_bits {
11426 	u8         reserved_at_0[0x10];
11427 	u8         monitor_opcode[0x10];
11428 };
11429 
11430 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11431 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11432 	u8         reserved_at_0[0x20];
11433 };
11434 
11435 enum {
11436 	/* Monitor opcodes */
11437 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11438 };
11439 
11440 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11441 	u8         reserved_at_0[0x10];
11442 	u8         group_opcode[0x10];
11443 
11444 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11445 
11446 	u8         reserved_at_40[0x20];
11447 
11448 	u8         status_message[59][0x20];
11449 };
11450 
11451 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11452 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11453 	u8         reserved_at_0[0x7c0];
11454 };
11455 
11456 enum {
11457 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11458 };
11459 
11460 struct mlx5_ifc_pddr_reg_bits {
11461 	u8         reserved_at_0[0x8];
11462 	u8         local_port[0x8];
11463 	u8         pnat[0x2];
11464 	u8         reserved_at_12[0xe];
11465 
11466 	u8         reserved_at_20[0x18];
11467 	u8         page_select[0x8];
11468 
11469 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11470 };
11471 
11472 struct mlx5_ifc_mrtc_reg_bits {
11473 	u8         time_synced[0x1];
11474 	u8         reserved_at_1[0x1f];
11475 
11476 	u8         reserved_at_20[0x20];
11477 
11478 	u8         time_h[0x20];
11479 
11480 	u8         time_l[0x20];
11481 };
11482 
11483 struct mlx5_ifc_mtcap_reg_bits {
11484 	u8         reserved_at_0[0x19];
11485 	u8         sensor_count[0x7];
11486 
11487 	u8         reserved_at_20[0x20];
11488 
11489 	u8         sensor_map[0x40];
11490 };
11491 
11492 struct mlx5_ifc_mtmp_reg_bits {
11493 	u8         reserved_at_0[0x14];
11494 	u8         sensor_index[0xc];
11495 
11496 	u8         reserved_at_20[0x10];
11497 	u8         temperature[0x10];
11498 
11499 	u8         mte[0x1];
11500 	u8         mtr[0x1];
11501 	u8         reserved_at_42[0xe];
11502 	u8         max_temperature[0x10];
11503 
11504 	u8         tee[0x2];
11505 	u8         reserved_at_62[0xe];
11506 	u8         temp_threshold_hi[0x10];
11507 
11508 	u8         reserved_at_80[0x10];
11509 	u8         temp_threshold_lo[0x10];
11510 
11511 	u8         reserved_at_a0[0x20];
11512 
11513 	u8         sensor_name_hi[0x20];
11514 	u8         sensor_name_lo[0x20];
11515 };
11516 
11517 struct mlx5_ifc_mtptm_reg_bits {
11518 	u8         reserved_at_0[0x10];
11519 	u8         psta[0x1];
11520 	u8         reserved_at_11[0xf];
11521 
11522 	u8         reserved_at_20[0x60];
11523 };
11524 
11525 enum {
11526 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11527 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11528 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11529 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11530 };
11531 
11532 struct mlx5_ifc_mtctr_reg_bits {
11533 	u8         first_clock_timestamp_request[0x8];
11534 	u8         second_clock_timestamp_request[0x8];
11535 	u8         reserved_at_10[0x10];
11536 
11537 	u8         first_clock_valid[0x1];
11538 	u8         second_clock_valid[0x1];
11539 	u8         reserved_at_22[0x1e];
11540 
11541 	u8         first_clock_timestamp[0x40];
11542 	u8         second_clock_timestamp[0x40];
11543 };
11544 
11545 union mlx5_ifc_ports_control_registers_document_bits {
11546 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11547 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11548 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11549 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11550 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11551 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11552 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11553 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11554 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11555 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11556 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11557 	struct mlx5_ifc_paos_reg_bits paos_reg;
11558 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11559 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11560 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11561 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11562 	struct mlx5_ifc_peir_reg_bits peir_reg;
11563 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11564 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11565 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11566 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11567 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11568 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11569 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11570 	struct mlx5_ifc_plib_reg_bits plib_reg;
11571 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11572 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11573 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11574 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11575 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11576 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11577 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11578 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11579 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11580 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11581 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11582 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11583 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11584 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11585 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11586 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11587 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11588 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11589 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11590 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11591 	struct mlx5_ifc_pude_reg_bits pude_reg;
11592 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11593 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11594 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11595 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11596 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11597 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11598 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11599 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11600 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11601 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11602 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11603 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11604 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11605 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11606 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11607 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11608 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11609 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11610 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11611 	u8         reserved_at_0[0x60e0];
11612 };
11613 
11614 union mlx5_ifc_debug_enhancements_document_bits {
11615 	struct mlx5_ifc_health_buffer_bits health_buffer;
11616 	u8         reserved_at_0[0x200];
11617 };
11618 
11619 union mlx5_ifc_uplink_pci_interface_document_bits {
11620 	struct mlx5_ifc_initial_seg_bits initial_seg;
11621 	u8         reserved_at_0[0x20060];
11622 };
11623 
11624 struct mlx5_ifc_set_flow_table_root_out_bits {
11625 	u8         status[0x8];
11626 	u8         reserved_at_8[0x18];
11627 
11628 	u8         syndrome[0x20];
11629 
11630 	u8         reserved_at_40[0x40];
11631 };
11632 
11633 struct mlx5_ifc_set_flow_table_root_in_bits {
11634 	u8         opcode[0x10];
11635 	u8         reserved_at_10[0x10];
11636 
11637 	u8         reserved_at_20[0x10];
11638 	u8         op_mod[0x10];
11639 
11640 	u8         other_vport[0x1];
11641 	u8         reserved_at_41[0xf];
11642 	u8         vport_number[0x10];
11643 
11644 	u8         reserved_at_60[0x20];
11645 
11646 	u8         table_type[0x8];
11647 	u8         reserved_at_88[0x7];
11648 	u8         table_of_other_vport[0x1];
11649 	u8         table_vport_number[0x10];
11650 
11651 	u8         reserved_at_a0[0x8];
11652 	u8         table_id[0x18];
11653 
11654 	u8         reserved_at_c0[0x8];
11655 	u8         underlay_qpn[0x18];
11656 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11657 	u8         reserved_at_e1[0xf];
11658 	u8         table_eswitch_owner_vhca_id[0x10];
11659 	u8         reserved_at_100[0x100];
11660 };
11661 
11662 enum {
11663 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11664 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11665 };
11666 
11667 struct mlx5_ifc_modify_flow_table_out_bits {
11668 	u8         status[0x8];
11669 	u8         reserved_at_8[0x18];
11670 
11671 	u8         syndrome[0x20];
11672 
11673 	u8         reserved_at_40[0x40];
11674 };
11675 
11676 struct mlx5_ifc_modify_flow_table_in_bits {
11677 	u8         opcode[0x10];
11678 	u8         reserved_at_10[0x10];
11679 
11680 	u8         reserved_at_20[0x10];
11681 	u8         op_mod[0x10];
11682 
11683 	u8         other_vport[0x1];
11684 	u8         reserved_at_41[0xf];
11685 	u8         vport_number[0x10];
11686 
11687 	u8         reserved_at_60[0x10];
11688 	u8         modify_field_select[0x10];
11689 
11690 	u8         table_type[0x8];
11691 	u8         reserved_at_88[0x18];
11692 
11693 	u8         reserved_at_a0[0x8];
11694 	u8         table_id[0x18];
11695 
11696 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11697 };
11698 
11699 struct mlx5_ifc_ets_tcn_config_reg_bits {
11700 	u8         g[0x1];
11701 	u8         b[0x1];
11702 	u8         r[0x1];
11703 	u8         reserved_at_3[0x9];
11704 	u8         group[0x4];
11705 	u8         reserved_at_10[0x9];
11706 	u8         bw_allocation[0x7];
11707 
11708 	u8         reserved_at_20[0xc];
11709 	u8         max_bw_units[0x4];
11710 	u8         reserved_at_30[0x8];
11711 	u8         max_bw_value[0x8];
11712 };
11713 
11714 struct mlx5_ifc_ets_global_config_reg_bits {
11715 	u8         reserved_at_0[0x2];
11716 	u8         r[0x1];
11717 	u8         reserved_at_3[0x1d];
11718 
11719 	u8         reserved_at_20[0xc];
11720 	u8         max_bw_units[0x4];
11721 	u8         reserved_at_30[0x8];
11722 	u8         max_bw_value[0x8];
11723 };
11724 
11725 struct mlx5_ifc_qetc_reg_bits {
11726 	u8                                         reserved_at_0[0x8];
11727 	u8                                         port_number[0x8];
11728 	u8                                         reserved_at_10[0x30];
11729 
11730 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11731 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11732 };
11733 
11734 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11735 	u8         e[0x1];
11736 	u8         reserved_at_01[0x0b];
11737 	u8         prio[0x04];
11738 };
11739 
11740 struct mlx5_ifc_qpdpm_reg_bits {
11741 	u8                                     reserved_at_0[0x8];
11742 	u8                                     local_port[0x8];
11743 	u8                                     reserved_at_10[0x10];
11744 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11745 };
11746 
11747 struct mlx5_ifc_qpts_reg_bits {
11748 	u8         reserved_at_0[0x8];
11749 	u8         local_port[0x8];
11750 	u8         reserved_at_10[0x2d];
11751 	u8         trust_state[0x3];
11752 };
11753 
11754 struct mlx5_ifc_pptb_reg_bits {
11755 	u8         reserved_at_0[0x2];
11756 	u8         mm[0x2];
11757 	u8         reserved_at_4[0x4];
11758 	u8         local_port[0x8];
11759 	u8         reserved_at_10[0x6];
11760 	u8         cm[0x1];
11761 	u8         um[0x1];
11762 	u8         pm[0x8];
11763 
11764 	u8         prio_x_buff[0x20];
11765 
11766 	u8         pm_msb[0x8];
11767 	u8         reserved_at_48[0x10];
11768 	u8         ctrl_buff[0x4];
11769 	u8         untagged_buff[0x4];
11770 };
11771 
11772 struct mlx5_ifc_sbcam_reg_bits {
11773 	u8         reserved_at_0[0x8];
11774 	u8         feature_group[0x8];
11775 	u8         reserved_at_10[0x8];
11776 	u8         access_reg_group[0x8];
11777 
11778 	u8         reserved_at_20[0x20];
11779 
11780 	u8         sb_access_reg_cap_mask[4][0x20];
11781 
11782 	u8         reserved_at_c0[0x80];
11783 
11784 	u8         sb_feature_cap_mask[4][0x20];
11785 
11786 	u8         reserved_at_1c0[0x40];
11787 
11788 	u8         cap_total_buffer_size[0x20];
11789 
11790 	u8         cap_cell_size[0x10];
11791 	u8         cap_max_pg_buffers[0x8];
11792 	u8         cap_num_pool_supported[0x8];
11793 
11794 	u8         reserved_at_240[0x8];
11795 	u8         cap_sbsr_stat_size[0x8];
11796 	u8         cap_max_tclass_data[0x8];
11797 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11798 };
11799 
11800 struct mlx5_ifc_pbmc_reg_bits {
11801 	u8         reserved_at_0[0x8];
11802 	u8         local_port[0x8];
11803 	u8         reserved_at_10[0x10];
11804 
11805 	u8         xoff_timer_value[0x10];
11806 	u8         xoff_refresh[0x10];
11807 
11808 	u8         reserved_at_40[0x9];
11809 	u8         fullness_threshold[0x7];
11810 	u8         port_buffer_size[0x10];
11811 
11812 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11813 
11814 	u8         reserved_at_2e0[0x80];
11815 };
11816 
11817 struct mlx5_ifc_sbpr_reg_bits {
11818 	u8         desc[0x1];
11819 	u8         snap[0x1];
11820 	u8         reserved_at_2[0x4];
11821 	u8         dir[0x2];
11822 	u8         reserved_at_8[0x14];
11823 	u8         pool[0x4];
11824 
11825 	u8         infi_size[0x1];
11826 	u8         reserved_at_21[0x7];
11827 	u8         size[0x18];
11828 
11829 	u8         reserved_at_40[0x1c];
11830 	u8         mode[0x4];
11831 
11832 	u8         reserved_at_60[0x8];
11833 	u8         buff_occupancy[0x18];
11834 
11835 	u8         clr[0x1];
11836 	u8         reserved_at_81[0x7];
11837 	u8         max_buff_occupancy[0x18];
11838 
11839 	u8         reserved_at_a0[0x8];
11840 	u8         ext_buff_occupancy[0x18];
11841 };
11842 
11843 struct mlx5_ifc_sbcm_reg_bits {
11844 	u8         desc[0x1];
11845 	u8         snap[0x1];
11846 	u8         reserved_at_2[0x6];
11847 	u8         local_port[0x8];
11848 	u8         pnat[0x2];
11849 	u8         pg_buff[0x6];
11850 	u8         reserved_at_18[0x6];
11851 	u8         dir[0x2];
11852 
11853 	u8         reserved_at_20[0x1f];
11854 	u8         exc[0x1];
11855 
11856 	u8         reserved_at_40[0x40];
11857 
11858 	u8         reserved_at_80[0x8];
11859 	u8         buff_occupancy[0x18];
11860 
11861 	u8         clr[0x1];
11862 	u8         reserved_at_a1[0x7];
11863 	u8         max_buff_occupancy[0x18];
11864 
11865 	u8         reserved_at_c0[0x8];
11866 	u8         min_buff[0x18];
11867 
11868 	u8         infi_max[0x1];
11869 	u8         reserved_at_e1[0x7];
11870 	u8         max_buff[0x18];
11871 
11872 	u8         reserved_at_100[0x20];
11873 
11874 	u8         reserved_at_120[0x1c];
11875 	u8         pool[0x4];
11876 };
11877 
11878 struct mlx5_ifc_qtct_reg_bits {
11879 	u8         reserved_at_0[0x8];
11880 	u8         port_number[0x8];
11881 	u8         reserved_at_10[0xd];
11882 	u8         prio[0x3];
11883 
11884 	u8         reserved_at_20[0x1d];
11885 	u8         tclass[0x3];
11886 };
11887 
11888 struct mlx5_ifc_mcia_reg_bits {
11889 	u8         l[0x1];
11890 	u8         reserved_at_1[0x7];
11891 	u8         module[0x8];
11892 	u8         reserved_at_10[0x8];
11893 	u8         status[0x8];
11894 
11895 	u8         i2c_device_address[0x8];
11896 	u8         page_number[0x8];
11897 	u8         device_address[0x10];
11898 
11899 	u8         reserved_at_40[0x10];
11900 	u8         size[0x10];
11901 
11902 	u8         reserved_at_60[0x20];
11903 
11904 	u8         dword_0[0x20];
11905 	u8         dword_1[0x20];
11906 	u8         dword_2[0x20];
11907 	u8         dword_3[0x20];
11908 	u8         dword_4[0x20];
11909 	u8         dword_5[0x20];
11910 	u8         dword_6[0x20];
11911 	u8         dword_7[0x20];
11912 	u8         dword_8[0x20];
11913 	u8         dword_9[0x20];
11914 	u8         dword_10[0x20];
11915 	u8         dword_11[0x20];
11916 };
11917 
11918 struct mlx5_ifc_dcbx_param_bits {
11919 	u8         dcbx_cee_cap[0x1];
11920 	u8         dcbx_ieee_cap[0x1];
11921 	u8         dcbx_standby_cap[0x1];
11922 	u8         reserved_at_3[0x5];
11923 	u8         port_number[0x8];
11924 	u8         reserved_at_10[0xa];
11925 	u8         max_application_table_size[6];
11926 	u8         reserved_at_20[0x15];
11927 	u8         version_oper[0x3];
11928 	u8         reserved_at_38[5];
11929 	u8         version_admin[0x3];
11930 	u8         willing_admin[0x1];
11931 	u8         reserved_at_41[0x3];
11932 	u8         pfc_cap_oper[0x4];
11933 	u8         reserved_at_48[0x4];
11934 	u8         pfc_cap_admin[0x4];
11935 	u8         reserved_at_50[0x4];
11936 	u8         num_of_tc_oper[0x4];
11937 	u8         reserved_at_58[0x4];
11938 	u8         num_of_tc_admin[0x4];
11939 	u8         remote_willing[0x1];
11940 	u8         reserved_at_61[3];
11941 	u8         remote_pfc_cap[4];
11942 	u8         reserved_at_68[0x14];
11943 	u8         remote_num_of_tc[0x4];
11944 	u8         reserved_at_80[0x18];
11945 	u8         error[0x8];
11946 	u8         reserved_at_a0[0x160];
11947 };
11948 
11949 enum {
11950 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11951 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11952 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11953 };
11954 
11955 struct mlx5_ifc_lagc_bits {
11956 	u8         fdb_selection_mode[0x1];
11957 	u8         reserved_at_1[0x14];
11958 	u8         port_select_mode[0x3];
11959 	u8         reserved_at_18[0x5];
11960 	u8         lag_state[0x3];
11961 
11962 	u8         reserved_at_20[0xc];
11963 	u8         active_port[0x4];
11964 	u8         reserved_at_30[0x4];
11965 	u8         tx_remap_affinity_2[0x4];
11966 	u8         reserved_at_38[0x4];
11967 	u8         tx_remap_affinity_1[0x4];
11968 };
11969 
11970 struct mlx5_ifc_create_lag_out_bits {
11971 	u8         status[0x8];
11972 	u8         reserved_at_8[0x18];
11973 
11974 	u8         syndrome[0x20];
11975 
11976 	u8         reserved_at_40[0x40];
11977 };
11978 
11979 struct mlx5_ifc_create_lag_in_bits {
11980 	u8         opcode[0x10];
11981 	u8         reserved_at_10[0x10];
11982 
11983 	u8         reserved_at_20[0x10];
11984 	u8         op_mod[0x10];
11985 
11986 	struct mlx5_ifc_lagc_bits ctx;
11987 };
11988 
11989 struct mlx5_ifc_modify_lag_out_bits {
11990 	u8         status[0x8];
11991 	u8         reserved_at_8[0x18];
11992 
11993 	u8         syndrome[0x20];
11994 
11995 	u8         reserved_at_40[0x40];
11996 };
11997 
11998 struct mlx5_ifc_modify_lag_in_bits {
11999 	u8         opcode[0x10];
12000 	u8         reserved_at_10[0x10];
12001 
12002 	u8         reserved_at_20[0x10];
12003 	u8         op_mod[0x10];
12004 
12005 	u8         reserved_at_40[0x20];
12006 	u8         field_select[0x20];
12007 
12008 	struct mlx5_ifc_lagc_bits ctx;
12009 };
12010 
12011 struct mlx5_ifc_query_lag_out_bits {
12012 	u8         status[0x8];
12013 	u8         reserved_at_8[0x18];
12014 
12015 	u8         syndrome[0x20];
12016 
12017 	struct mlx5_ifc_lagc_bits ctx;
12018 };
12019 
12020 struct mlx5_ifc_query_lag_in_bits {
12021 	u8         opcode[0x10];
12022 	u8         reserved_at_10[0x10];
12023 
12024 	u8         reserved_at_20[0x10];
12025 	u8         op_mod[0x10];
12026 
12027 	u8         reserved_at_40[0x40];
12028 };
12029 
12030 struct mlx5_ifc_destroy_lag_out_bits {
12031 	u8         status[0x8];
12032 	u8         reserved_at_8[0x18];
12033 
12034 	u8         syndrome[0x20];
12035 
12036 	u8         reserved_at_40[0x40];
12037 };
12038 
12039 struct mlx5_ifc_destroy_lag_in_bits {
12040 	u8         opcode[0x10];
12041 	u8         reserved_at_10[0x10];
12042 
12043 	u8         reserved_at_20[0x10];
12044 	u8         op_mod[0x10];
12045 
12046 	u8         reserved_at_40[0x40];
12047 };
12048 
12049 struct mlx5_ifc_create_vport_lag_out_bits {
12050 	u8         status[0x8];
12051 	u8         reserved_at_8[0x18];
12052 
12053 	u8         syndrome[0x20];
12054 
12055 	u8         reserved_at_40[0x40];
12056 };
12057 
12058 struct mlx5_ifc_create_vport_lag_in_bits {
12059 	u8         opcode[0x10];
12060 	u8         reserved_at_10[0x10];
12061 
12062 	u8         reserved_at_20[0x10];
12063 	u8         op_mod[0x10];
12064 
12065 	u8         reserved_at_40[0x40];
12066 };
12067 
12068 struct mlx5_ifc_destroy_vport_lag_out_bits {
12069 	u8         status[0x8];
12070 	u8         reserved_at_8[0x18];
12071 
12072 	u8         syndrome[0x20];
12073 
12074 	u8         reserved_at_40[0x40];
12075 };
12076 
12077 struct mlx5_ifc_destroy_vport_lag_in_bits {
12078 	u8         opcode[0x10];
12079 	u8         reserved_at_10[0x10];
12080 
12081 	u8         reserved_at_20[0x10];
12082 	u8         op_mod[0x10];
12083 
12084 	u8         reserved_at_40[0x40];
12085 };
12086 
12087 enum {
12088 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12089 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12090 };
12091 
12092 struct mlx5_ifc_modify_memic_in_bits {
12093 	u8         opcode[0x10];
12094 	u8         uid[0x10];
12095 
12096 	u8         reserved_at_20[0x10];
12097 	u8         op_mod[0x10];
12098 
12099 	u8         reserved_at_40[0x20];
12100 
12101 	u8         reserved_at_60[0x18];
12102 	u8         memic_operation_type[0x8];
12103 
12104 	u8         memic_start_addr[0x40];
12105 
12106 	u8         reserved_at_c0[0x140];
12107 };
12108 
12109 struct mlx5_ifc_modify_memic_out_bits {
12110 	u8         status[0x8];
12111 	u8         reserved_at_8[0x18];
12112 
12113 	u8         syndrome[0x20];
12114 
12115 	u8         reserved_at_40[0x40];
12116 
12117 	u8         memic_operation_addr[0x40];
12118 
12119 	u8         reserved_at_c0[0x140];
12120 };
12121 
12122 struct mlx5_ifc_alloc_memic_in_bits {
12123 	u8         opcode[0x10];
12124 	u8         reserved_at_10[0x10];
12125 
12126 	u8         reserved_at_20[0x10];
12127 	u8         op_mod[0x10];
12128 
12129 	u8         reserved_at_30[0x20];
12130 
12131 	u8	   reserved_at_40[0x18];
12132 	u8	   log_memic_addr_alignment[0x8];
12133 
12134 	u8         range_start_addr[0x40];
12135 
12136 	u8         range_size[0x20];
12137 
12138 	u8         memic_size[0x20];
12139 };
12140 
12141 struct mlx5_ifc_alloc_memic_out_bits {
12142 	u8         status[0x8];
12143 	u8         reserved_at_8[0x18];
12144 
12145 	u8         syndrome[0x20];
12146 
12147 	u8         memic_start_addr[0x40];
12148 };
12149 
12150 struct mlx5_ifc_dealloc_memic_in_bits {
12151 	u8         opcode[0x10];
12152 	u8         reserved_at_10[0x10];
12153 
12154 	u8         reserved_at_20[0x10];
12155 	u8         op_mod[0x10];
12156 
12157 	u8         reserved_at_40[0x40];
12158 
12159 	u8         memic_start_addr[0x40];
12160 
12161 	u8         memic_size[0x20];
12162 
12163 	u8         reserved_at_e0[0x20];
12164 };
12165 
12166 struct mlx5_ifc_dealloc_memic_out_bits {
12167 	u8         status[0x8];
12168 	u8         reserved_at_8[0x18];
12169 
12170 	u8         syndrome[0x20];
12171 
12172 	u8         reserved_at_40[0x40];
12173 };
12174 
12175 struct mlx5_ifc_umem_bits {
12176 	u8         reserved_at_0[0x80];
12177 
12178 	u8         ats[0x1];
12179 	u8         reserved_at_81[0x1a];
12180 	u8         log_page_size[0x5];
12181 
12182 	u8         page_offset[0x20];
12183 
12184 	u8         num_of_mtt[0x40];
12185 
12186 	struct mlx5_ifc_mtt_bits  mtt[];
12187 };
12188 
12189 struct mlx5_ifc_uctx_bits {
12190 	u8         cap[0x20];
12191 
12192 	u8         reserved_at_20[0x160];
12193 };
12194 
12195 struct mlx5_ifc_sw_icm_bits {
12196 	u8         modify_field_select[0x40];
12197 
12198 	u8	   reserved_at_40[0x18];
12199 	u8         log_sw_icm_size[0x8];
12200 
12201 	u8         reserved_at_60[0x20];
12202 
12203 	u8         sw_icm_start_addr[0x40];
12204 
12205 	u8         reserved_at_c0[0x140];
12206 };
12207 
12208 struct mlx5_ifc_geneve_tlv_option_bits {
12209 	u8         modify_field_select[0x40];
12210 
12211 	u8         reserved_at_40[0x18];
12212 	u8         geneve_option_fte_index[0x8];
12213 
12214 	u8         option_class[0x10];
12215 	u8         option_type[0x8];
12216 	u8         reserved_at_78[0x3];
12217 	u8         option_data_length[0x5];
12218 
12219 	u8         reserved_at_80[0x180];
12220 };
12221 
12222 struct mlx5_ifc_create_umem_in_bits {
12223 	u8         opcode[0x10];
12224 	u8         uid[0x10];
12225 
12226 	u8         reserved_at_20[0x10];
12227 	u8         op_mod[0x10];
12228 
12229 	u8         reserved_at_40[0x40];
12230 
12231 	struct mlx5_ifc_umem_bits  umem;
12232 };
12233 
12234 struct mlx5_ifc_create_umem_out_bits {
12235 	u8         status[0x8];
12236 	u8         reserved_at_8[0x18];
12237 
12238 	u8         syndrome[0x20];
12239 
12240 	u8         reserved_at_40[0x8];
12241 	u8         umem_id[0x18];
12242 
12243 	u8         reserved_at_60[0x20];
12244 };
12245 
12246 struct mlx5_ifc_destroy_umem_in_bits {
12247 	u8        opcode[0x10];
12248 	u8        uid[0x10];
12249 
12250 	u8        reserved_at_20[0x10];
12251 	u8        op_mod[0x10];
12252 
12253 	u8        reserved_at_40[0x8];
12254 	u8        umem_id[0x18];
12255 
12256 	u8        reserved_at_60[0x20];
12257 };
12258 
12259 struct mlx5_ifc_destroy_umem_out_bits {
12260 	u8        status[0x8];
12261 	u8        reserved_at_8[0x18];
12262 
12263 	u8        syndrome[0x20];
12264 
12265 	u8        reserved_at_40[0x40];
12266 };
12267 
12268 struct mlx5_ifc_create_uctx_in_bits {
12269 	u8         opcode[0x10];
12270 	u8         reserved_at_10[0x10];
12271 
12272 	u8         reserved_at_20[0x10];
12273 	u8         op_mod[0x10];
12274 
12275 	u8         reserved_at_40[0x40];
12276 
12277 	struct mlx5_ifc_uctx_bits  uctx;
12278 };
12279 
12280 struct mlx5_ifc_create_uctx_out_bits {
12281 	u8         status[0x8];
12282 	u8         reserved_at_8[0x18];
12283 
12284 	u8         syndrome[0x20];
12285 
12286 	u8         reserved_at_40[0x10];
12287 	u8         uid[0x10];
12288 
12289 	u8         reserved_at_60[0x20];
12290 };
12291 
12292 struct mlx5_ifc_destroy_uctx_in_bits {
12293 	u8         opcode[0x10];
12294 	u8         reserved_at_10[0x10];
12295 
12296 	u8         reserved_at_20[0x10];
12297 	u8         op_mod[0x10];
12298 
12299 	u8         reserved_at_40[0x10];
12300 	u8         uid[0x10];
12301 
12302 	u8         reserved_at_60[0x20];
12303 };
12304 
12305 struct mlx5_ifc_destroy_uctx_out_bits {
12306 	u8         status[0x8];
12307 	u8         reserved_at_8[0x18];
12308 
12309 	u8         syndrome[0x20];
12310 
12311 	u8          reserved_at_40[0x40];
12312 };
12313 
12314 struct mlx5_ifc_create_sw_icm_in_bits {
12315 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12316 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12317 };
12318 
12319 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12320 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12321 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12322 };
12323 
12324 struct mlx5_ifc_mtrc_string_db_param_bits {
12325 	u8         string_db_base_address[0x20];
12326 
12327 	u8         reserved_at_20[0x8];
12328 	u8         string_db_size[0x18];
12329 };
12330 
12331 struct mlx5_ifc_mtrc_cap_bits {
12332 	u8         trace_owner[0x1];
12333 	u8         trace_to_memory[0x1];
12334 	u8         reserved_at_2[0x4];
12335 	u8         trc_ver[0x2];
12336 	u8         reserved_at_8[0x14];
12337 	u8         num_string_db[0x4];
12338 
12339 	u8         first_string_trace[0x8];
12340 	u8         num_string_trace[0x8];
12341 	u8         reserved_at_30[0x28];
12342 
12343 	u8         log_max_trace_buffer_size[0x8];
12344 
12345 	u8         reserved_at_60[0x20];
12346 
12347 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12348 
12349 	u8         reserved_at_280[0x180];
12350 };
12351 
12352 struct mlx5_ifc_mtrc_conf_bits {
12353 	u8         reserved_at_0[0x1c];
12354 	u8         trace_mode[0x4];
12355 	u8         reserved_at_20[0x18];
12356 	u8         log_trace_buffer_size[0x8];
12357 	u8         trace_mkey[0x20];
12358 	u8         reserved_at_60[0x3a0];
12359 };
12360 
12361 struct mlx5_ifc_mtrc_stdb_bits {
12362 	u8         string_db_index[0x4];
12363 	u8         reserved_at_4[0x4];
12364 	u8         read_size[0x18];
12365 	u8         start_offset[0x20];
12366 	u8         string_db_data[];
12367 };
12368 
12369 struct mlx5_ifc_mtrc_ctrl_bits {
12370 	u8         trace_status[0x2];
12371 	u8         reserved_at_2[0x2];
12372 	u8         arm_event[0x1];
12373 	u8         reserved_at_5[0xb];
12374 	u8         modify_field_select[0x10];
12375 	u8         reserved_at_20[0x2b];
12376 	u8         current_timestamp52_32[0x15];
12377 	u8         current_timestamp31_0[0x20];
12378 	u8         reserved_at_80[0x180];
12379 };
12380 
12381 struct mlx5_ifc_host_params_context_bits {
12382 	u8         host_number[0x8];
12383 	u8         reserved_at_8[0x7];
12384 	u8         host_pf_disabled[0x1];
12385 	u8         host_num_of_vfs[0x10];
12386 
12387 	u8         host_total_vfs[0x10];
12388 	u8         host_pci_bus[0x10];
12389 
12390 	u8         reserved_at_40[0x10];
12391 	u8         host_pci_device[0x10];
12392 
12393 	u8         reserved_at_60[0x10];
12394 	u8         host_pci_function[0x10];
12395 
12396 	u8         reserved_at_80[0x180];
12397 };
12398 
12399 struct mlx5_ifc_query_esw_functions_in_bits {
12400 	u8         opcode[0x10];
12401 	u8         reserved_at_10[0x10];
12402 
12403 	u8         reserved_at_20[0x10];
12404 	u8         op_mod[0x10];
12405 
12406 	u8         reserved_at_40[0x40];
12407 };
12408 
12409 struct mlx5_ifc_query_esw_functions_out_bits {
12410 	u8         status[0x8];
12411 	u8         reserved_at_8[0x18];
12412 
12413 	u8         syndrome[0x20];
12414 
12415 	u8         reserved_at_40[0x40];
12416 
12417 	struct mlx5_ifc_host_params_context_bits host_params_context;
12418 
12419 	u8         reserved_at_280[0x180];
12420 	u8         host_sf_enable[][0x40];
12421 };
12422 
12423 struct mlx5_ifc_sf_partition_bits {
12424 	u8         reserved_at_0[0x10];
12425 	u8         log_num_sf[0x8];
12426 	u8         log_sf_bar_size[0x8];
12427 };
12428 
12429 struct mlx5_ifc_query_sf_partitions_out_bits {
12430 	u8         status[0x8];
12431 	u8         reserved_at_8[0x18];
12432 
12433 	u8         syndrome[0x20];
12434 
12435 	u8         reserved_at_40[0x18];
12436 	u8         num_sf_partitions[0x8];
12437 
12438 	u8         reserved_at_60[0x20];
12439 
12440 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12441 };
12442 
12443 struct mlx5_ifc_query_sf_partitions_in_bits {
12444 	u8         opcode[0x10];
12445 	u8         reserved_at_10[0x10];
12446 
12447 	u8         reserved_at_20[0x10];
12448 	u8         op_mod[0x10];
12449 
12450 	u8         reserved_at_40[0x40];
12451 };
12452 
12453 struct mlx5_ifc_dealloc_sf_out_bits {
12454 	u8         status[0x8];
12455 	u8         reserved_at_8[0x18];
12456 
12457 	u8         syndrome[0x20];
12458 
12459 	u8         reserved_at_40[0x40];
12460 };
12461 
12462 struct mlx5_ifc_dealloc_sf_in_bits {
12463 	u8         opcode[0x10];
12464 	u8         reserved_at_10[0x10];
12465 
12466 	u8         reserved_at_20[0x10];
12467 	u8         op_mod[0x10];
12468 
12469 	u8         reserved_at_40[0x10];
12470 	u8         function_id[0x10];
12471 
12472 	u8         reserved_at_60[0x20];
12473 };
12474 
12475 struct mlx5_ifc_alloc_sf_out_bits {
12476 	u8         status[0x8];
12477 	u8         reserved_at_8[0x18];
12478 
12479 	u8         syndrome[0x20];
12480 
12481 	u8         reserved_at_40[0x40];
12482 };
12483 
12484 struct mlx5_ifc_alloc_sf_in_bits {
12485 	u8         opcode[0x10];
12486 	u8         reserved_at_10[0x10];
12487 
12488 	u8         reserved_at_20[0x10];
12489 	u8         op_mod[0x10];
12490 
12491 	u8         reserved_at_40[0x10];
12492 	u8         function_id[0x10];
12493 
12494 	u8         reserved_at_60[0x20];
12495 };
12496 
12497 struct mlx5_ifc_affiliated_event_header_bits {
12498 	u8         reserved_at_0[0x10];
12499 	u8         obj_type[0x10];
12500 
12501 	u8         obj_id[0x20];
12502 };
12503 
12504 enum {
12505 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12506 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12507 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12508 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12509 };
12510 
12511 enum {
12512 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = BIT_ULL(0x13),
12513 };
12514 
12515 enum {
12516 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12517 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12518 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12519 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12520 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12521 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12522 	MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12523 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12524 };
12525 
12526 enum {
12527 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12528 };
12529 
12530 enum {
12531 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12532 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12533 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12534 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12535 };
12536 
12537 enum {
12538 	MLX5_IPSEC_ASO_MODE              = 0x0,
12539 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12540 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12541 };
12542 
12543 enum {
12544 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12545 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12546 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12547 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12548 };
12549 
12550 struct mlx5_ifc_ipsec_aso_bits {
12551 	u8         valid[0x1];
12552 	u8         reserved_at_201[0x1];
12553 	u8         mode[0x2];
12554 	u8         window_sz[0x2];
12555 	u8         soft_lft_arm[0x1];
12556 	u8         hard_lft_arm[0x1];
12557 	u8         remove_flow_enable[0x1];
12558 	u8         esn_event_arm[0x1];
12559 	u8         reserved_at_20a[0x16];
12560 
12561 	u8         remove_flow_pkt_cnt[0x20];
12562 
12563 	u8         remove_flow_soft_lft[0x20];
12564 
12565 	u8         reserved_at_260[0x80];
12566 
12567 	u8         mode_parameter[0x20];
12568 
12569 	u8         replay_protection_window[0x100];
12570 };
12571 
12572 struct mlx5_ifc_ipsec_obj_bits {
12573 	u8         modify_field_select[0x40];
12574 	u8         full_offload[0x1];
12575 	u8         reserved_at_41[0x1];
12576 	u8         esn_en[0x1];
12577 	u8         esn_overlap[0x1];
12578 	u8         reserved_at_44[0x2];
12579 	u8         icv_length[0x2];
12580 	u8         reserved_at_48[0x4];
12581 	u8         aso_return_reg[0x4];
12582 	u8         reserved_at_50[0x10];
12583 
12584 	u8         esn_msb[0x20];
12585 
12586 	u8         reserved_at_80[0x8];
12587 	u8         dekn[0x18];
12588 
12589 	u8         salt[0x20];
12590 
12591 	u8         implicit_iv[0x40];
12592 
12593 	u8         reserved_at_100[0x8];
12594 	u8         ipsec_aso_access_pd[0x18];
12595 	u8         reserved_at_120[0xe0];
12596 
12597 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12598 };
12599 
12600 struct mlx5_ifc_create_ipsec_obj_in_bits {
12601 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12602 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12603 };
12604 
12605 enum {
12606 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12607 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12608 };
12609 
12610 struct mlx5_ifc_query_ipsec_obj_out_bits {
12611 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12612 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12613 };
12614 
12615 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12616 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12617 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12618 };
12619 
12620 enum {
12621 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12622 };
12623 
12624 enum {
12625 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12626 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12627 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12628 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12629 };
12630 
12631 #define MLX5_MACSEC_ASO_INC_SN  0x2
12632 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12633 
12634 struct mlx5_ifc_macsec_aso_bits {
12635 	u8    valid[0x1];
12636 	u8    reserved_at_1[0x1];
12637 	u8    mode[0x2];
12638 	u8    window_size[0x2];
12639 	u8    soft_lifetime_arm[0x1];
12640 	u8    hard_lifetime_arm[0x1];
12641 	u8    remove_flow_enable[0x1];
12642 	u8    epn_event_arm[0x1];
12643 	u8    reserved_at_a[0x16];
12644 
12645 	u8    remove_flow_packet_count[0x20];
12646 
12647 	u8    remove_flow_soft_lifetime[0x20];
12648 
12649 	u8    reserved_at_60[0x80];
12650 
12651 	u8    mode_parameter[0x20];
12652 
12653 	u8    replay_protection_window[8][0x20];
12654 };
12655 
12656 struct mlx5_ifc_macsec_offload_obj_bits {
12657 	u8    modify_field_select[0x40];
12658 
12659 	u8    confidentiality_en[0x1];
12660 	u8    reserved_at_41[0x1];
12661 	u8    epn_en[0x1];
12662 	u8    epn_overlap[0x1];
12663 	u8    reserved_at_44[0x2];
12664 	u8    confidentiality_offset[0x2];
12665 	u8    reserved_at_48[0x4];
12666 	u8    aso_return_reg[0x4];
12667 	u8    reserved_at_50[0x10];
12668 
12669 	u8    epn_msb[0x20];
12670 
12671 	u8    reserved_at_80[0x8];
12672 	u8    dekn[0x18];
12673 
12674 	u8    reserved_at_a0[0x20];
12675 
12676 	u8    sci[0x40];
12677 
12678 	u8    reserved_at_100[0x8];
12679 	u8    macsec_aso_access_pd[0x18];
12680 
12681 	u8    reserved_at_120[0x60];
12682 
12683 	u8    salt[3][0x20];
12684 
12685 	u8    reserved_at_1e0[0x20];
12686 
12687 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12688 };
12689 
12690 struct mlx5_ifc_create_macsec_obj_in_bits {
12691 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12692 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12693 };
12694 
12695 struct mlx5_ifc_modify_macsec_obj_in_bits {
12696 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12697 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12698 };
12699 
12700 enum {
12701 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12702 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12703 };
12704 
12705 struct mlx5_ifc_query_macsec_obj_out_bits {
12706 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12707 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12708 };
12709 
12710 struct mlx5_ifc_wrapped_dek_bits {
12711 	u8         gcm_iv[0x60];
12712 
12713 	u8         reserved_at_60[0x20];
12714 
12715 	u8         const0[0x1];
12716 	u8         key_size[0x1];
12717 	u8         reserved_at_82[0x2];
12718 	u8         key2_invalid[0x1];
12719 	u8         reserved_at_85[0x3];
12720 	u8         pd[0x18];
12721 
12722 	u8         key_purpose[0x5];
12723 	u8         reserved_at_a5[0x13];
12724 	u8         kek_id[0x8];
12725 
12726 	u8         reserved_at_c0[0x40];
12727 
12728 	u8         key1[0x8][0x20];
12729 
12730 	u8         key2[0x8][0x20];
12731 
12732 	u8         reserved_at_300[0x40];
12733 
12734 	u8         const1[0x1];
12735 	u8         reserved_at_341[0x1f];
12736 
12737 	u8         reserved_at_360[0x20];
12738 
12739 	u8         auth_tag[0x80];
12740 };
12741 
12742 struct mlx5_ifc_encryption_key_obj_bits {
12743 	u8         modify_field_select[0x40];
12744 
12745 	u8         state[0x8];
12746 	u8         sw_wrapped[0x1];
12747 	u8         reserved_at_49[0xb];
12748 	u8         key_size[0x4];
12749 	u8         reserved_at_58[0x4];
12750 	u8         key_purpose[0x4];
12751 
12752 	u8         reserved_at_60[0x8];
12753 	u8         pd[0x18];
12754 
12755 	u8         reserved_at_80[0x100];
12756 
12757 	u8         opaque[0x40];
12758 
12759 	u8         reserved_at_1c0[0x40];
12760 
12761 	u8         key[8][0x80];
12762 
12763 	u8         sw_wrapped_dek[8][0x80];
12764 
12765 	u8         reserved_at_a00[0x600];
12766 };
12767 
12768 struct mlx5_ifc_create_encryption_key_in_bits {
12769 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12770 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12771 };
12772 
12773 struct mlx5_ifc_modify_encryption_key_in_bits {
12774 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12775 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12776 };
12777 
12778 enum {
12779 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12780 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12781 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12782 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12783 };
12784 
12785 struct mlx5_ifc_flow_meter_parameters_bits {
12786 	u8         valid[0x1];
12787 	u8         bucket_overflow[0x1];
12788 	u8         start_color[0x2];
12789 	u8         both_buckets_on_green[0x1];
12790 	u8         reserved_at_5[0x1];
12791 	u8         meter_mode[0x2];
12792 	u8         reserved_at_8[0x18];
12793 
12794 	u8         reserved_at_20[0x20];
12795 
12796 	u8         reserved_at_40[0x3];
12797 	u8         cbs_exponent[0x5];
12798 	u8         cbs_mantissa[0x8];
12799 	u8         reserved_at_50[0x3];
12800 	u8         cir_exponent[0x5];
12801 	u8         cir_mantissa[0x8];
12802 
12803 	u8         reserved_at_60[0x20];
12804 
12805 	u8         reserved_at_80[0x3];
12806 	u8         ebs_exponent[0x5];
12807 	u8         ebs_mantissa[0x8];
12808 	u8         reserved_at_90[0x3];
12809 	u8         eir_exponent[0x5];
12810 	u8         eir_mantissa[0x8];
12811 
12812 	u8         reserved_at_a0[0x60];
12813 };
12814 
12815 struct mlx5_ifc_flow_meter_aso_obj_bits {
12816 	u8         modify_field_select[0x40];
12817 
12818 	u8         reserved_at_40[0x40];
12819 
12820 	u8         reserved_at_80[0x8];
12821 	u8         meter_aso_access_pd[0x18];
12822 
12823 	u8         reserved_at_a0[0x160];
12824 
12825 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12826 };
12827 
12828 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12829 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12830 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12831 };
12832 
12833 struct mlx5_ifc_int_kek_obj_bits {
12834 	u8         modify_field_select[0x40];
12835 
12836 	u8         state[0x8];
12837 	u8         auto_gen[0x1];
12838 	u8         reserved_at_49[0xb];
12839 	u8         key_size[0x4];
12840 	u8         reserved_at_58[0x8];
12841 
12842 	u8         reserved_at_60[0x8];
12843 	u8         pd[0x18];
12844 
12845 	u8         reserved_at_80[0x180];
12846 	u8         key[8][0x80];
12847 
12848 	u8         reserved_at_600[0x200];
12849 };
12850 
12851 struct mlx5_ifc_create_int_kek_obj_in_bits {
12852 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12853 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12854 };
12855 
12856 struct mlx5_ifc_create_int_kek_obj_out_bits {
12857 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12858 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12859 };
12860 
12861 struct mlx5_ifc_sampler_obj_bits {
12862 	u8         modify_field_select[0x40];
12863 
12864 	u8         table_type[0x8];
12865 	u8         level[0x8];
12866 	u8         reserved_at_50[0xf];
12867 	u8         ignore_flow_level[0x1];
12868 
12869 	u8         sample_ratio[0x20];
12870 
12871 	u8         reserved_at_80[0x8];
12872 	u8         sample_table_id[0x18];
12873 
12874 	u8         reserved_at_a0[0x8];
12875 	u8         default_table_id[0x18];
12876 
12877 	u8         sw_steering_icm_address_rx[0x40];
12878 	u8         sw_steering_icm_address_tx[0x40];
12879 
12880 	u8         reserved_at_140[0xa0];
12881 };
12882 
12883 struct mlx5_ifc_create_sampler_obj_in_bits {
12884 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12885 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12886 };
12887 
12888 struct mlx5_ifc_query_sampler_obj_out_bits {
12889 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12890 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12891 };
12892 
12893 enum {
12894 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12895 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12896 };
12897 
12898 enum {
12899 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12900 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12901 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12902 };
12903 
12904 struct mlx5_ifc_tls_static_params_bits {
12905 	u8         const_2[0x2];
12906 	u8         tls_version[0x4];
12907 	u8         const_1[0x2];
12908 	u8         reserved_at_8[0x14];
12909 	u8         encryption_standard[0x4];
12910 
12911 	u8         reserved_at_20[0x20];
12912 
12913 	u8         initial_record_number[0x40];
12914 
12915 	u8         resync_tcp_sn[0x20];
12916 
12917 	u8         gcm_iv[0x20];
12918 
12919 	u8         implicit_iv[0x40];
12920 
12921 	u8         reserved_at_100[0x8];
12922 	u8         dek_index[0x18];
12923 
12924 	u8         reserved_at_120[0xe0];
12925 };
12926 
12927 struct mlx5_ifc_tls_progress_params_bits {
12928 	u8         next_record_tcp_sn[0x20];
12929 
12930 	u8         hw_resync_tcp_sn[0x20];
12931 
12932 	u8         record_tracker_state[0x2];
12933 	u8         auth_state[0x2];
12934 	u8         reserved_at_44[0x4];
12935 	u8         hw_offset_record_number[0x18];
12936 };
12937 
12938 enum {
12939 	MLX5_MTT_PERM_READ	= 1 << 0,
12940 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12941 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12942 };
12943 
12944 enum {
12945 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12946 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12947 };
12948 
12949 struct mlx5_ifc_suspend_vhca_in_bits {
12950 	u8         opcode[0x10];
12951 	u8         uid[0x10];
12952 
12953 	u8         reserved_at_20[0x10];
12954 	u8         op_mod[0x10];
12955 
12956 	u8         reserved_at_40[0x10];
12957 	u8         vhca_id[0x10];
12958 
12959 	u8         reserved_at_60[0x20];
12960 };
12961 
12962 struct mlx5_ifc_suspend_vhca_out_bits {
12963 	u8         status[0x8];
12964 	u8         reserved_at_8[0x18];
12965 
12966 	u8         syndrome[0x20];
12967 
12968 	u8         reserved_at_40[0x40];
12969 };
12970 
12971 enum {
12972 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12973 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12974 };
12975 
12976 struct mlx5_ifc_resume_vhca_in_bits {
12977 	u8         opcode[0x10];
12978 	u8         uid[0x10];
12979 
12980 	u8         reserved_at_20[0x10];
12981 	u8         op_mod[0x10];
12982 
12983 	u8         reserved_at_40[0x10];
12984 	u8         vhca_id[0x10];
12985 
12986 	u8         reserved_at_60[0x20];
12987 };
12988 
12989 struct mlx5_ifc_resume_vhca_out_bits {
12990 	u8         status[0x8];
12991 	u8         reserved_at_8[0x18];
12992 
12993 	u8         syndrome[0x20];
12994 
12995 	u8         reserved_at_40[0x40];
12996 };
12997 
12998 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12999 	u8         opcode[0x10];
13000 	u8         uid[0x10];
13001 
13002 	u8         reserved_at_20[0x10];
13003 	u8         op_mod[0x10];
13004 
13005 	u8         incremental[0x1];
13006 	u8         chunk[0x1];
13007 	u8         reserved_at_42[0xe];
13008 	u8         vhca_id[0x10];
13009 
13010 	u8         reserved_at_60[0x20];
13011 };
13012 
13013 struct mlx5_ifc_query_vhca_migration_state_out_bits {
13014 	u8         status[0x8];
13015 	u8         reserved_at_8[0x18];
13016 
13017 	u8         syndrome[0x20];
13018 
13019 	u8         reserved_at_40[0x40];
13020 
13021 	u8         required_umem_size[0x20];
13022 
13023 	u8         reserved_at_a0[0x20];
13024 
13025 	u8         remaining_total_size[0x40];
13026 
13027 	u8         reserved_at_100[0x100];
13028 };
13029 
13030 struct mlx5_ifc_save_vhca_state_in_bits {
13031 	u8         opcode[0x10];
13032 	u8         uid[0x10];
13033 
13034 	u8         reserved_at_20[0x10];
13035 	u8         op_mod[0x10];
13036 
13037 	u8         incremental[0x1];
13038 	u8         set_track[0x1];
13039 	u8         reserved_at_42[0xe];
13040 	u8         vhca_id[0x10];
13041 
13042 	u8         reserved_at_60[0x20];
13043 
13044 	u8         va[0x40];
13045 
13046 	u8         mkey[0x20];
13047 
13048 	u8         size[0x20];
13049 };
13050 
13051 struct mlx5_ifc_save_vhca_state_out_bits {
13052 	u8         status[0x8];
13053 	u8         reserved_at_8[0x18];
13054 
13055 	u8         syndrome[0x20];
13056 
13057 	u8         actual_image_size[0x20];
13058 
13059 	u8         next_required_umem_size[0x20];
13060 };
13061 
13062 struct mlx5_ifc_load_vhca_state_in_bits {
13063 	u8         opcode[0x10];
13064 	u8         uid[0x10];
13065 
13066 	u8         reserved_at_20[0x10];
13067 	u8         op_mod[0x10];
13068 
13069 	u8         reserved_at_40[0x10];
13070 	u8         vhca_id[0x10];
13071 
13072 	u8         reserved_at_60[0x20];
13073 
13074 	u8         va[0x40];
13075 
13076 	u8         mkey[0x20];
13077 
13078 	u8         size[0x20];
13079 };
13080 
13081 struct mlx5_ifc_load_vhca_state_out_bits {
13082 	u8         status[0x8];
13083 	u8         reserved_at_8[0x18];
13084 
13085 	u8         syndrome[0x20];
13086 
13087 	u8         reserved_at_40[0x40];
13088 };
13089 
13090 struct mlx5_ifc_adv_rdma_cap_bits {
13091 	u8         rdma_transport_manager[0x1];
13092 	u8         rdma_transport_manager_other_eswitch[0x1];
13093 	u8         reserved_at_2[0x1e];
13094 
13095 	u8         rcx_type[0x8];
13096 	u8         reserved_at_28[0x2];
13097 	u8         ps_entry_log_max_value[0x6];
13098 	u8         reserved_at_30[0x6];
13099 	u8         qp_max_ps_num_entry[0xa];
13100 
13101 	u8         mp_max_num_queues[0x8];
13102 	u8         ps_user_context_max_log_size[0x8];
13103 	u8         message_based_qp_and_striding_wq[0x8];
13104 	u8         reserved_at_58[0x8];
13105 
13106 	u8         max_receive_send_message_size_stride[0x10];
13107 	u8         reserved_at_70[0x10];
13108 
13109 	u8         max_receive_send_message_size_byte[0x20];
13110 
13111 	u8         reserved_at_a0[0x160];
13112 
13113 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13114 
13115 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13116 
13117 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13118 
13119 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13120 
13121 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13122 
13123 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13124 
13125 	u8         reserved_at_800[0x3800];
13126 };
13127 
13128 struct mlx5_ifc_adv_virtualization_cap_bits {
13129 	u8         reserved_at_0[0x3];
13130 	u8         pg_track_log_max_num[0x5];
13131 	u8         pg_track_max_num_range[0x8];
13132 	u8         pg_track_log_min_addr_space[0x8];
13133 	u8         pg_track_log_max_addr_space[0x8];
13134 
13135 	u8         reserved_at_20[0x3];
13136 	u8         pg_track_log_min_msg_size[0x5];
13137 	u8         reserved_at_28[0x3];
13138 	u8         pg_track_log_max_msg_size[0x5];
13139 	u8         reserved_at_30[0x3];
13140 	u8         pg_track_log_min_page_size[0x5];
13141 	u8         reserved_at_38[0x3];
13142 	u8         pg_track_log_max_page_size[0x5];
13143 
13144 	u8         reserved_at_40[0x7c0];
13145 };
13146 
13147 struct mlx5_ifc_page_track_report_entry_bits {
13148 	u8         dirty_address_high[0x20];
13149 
13150 	u8         dirty_address_low[0x20];
13151 };
13152 
13153 enum {
13154 	MLX5_PAGE_TRACK_STATE_TRACKING,
13155 	MLX5_PAGE_TRACK_STATE_REPORTING,
13156 	MLX5_PAGE_TRACK_STATE_ERROR,
13157 };
13158 
13159 struct mlx5_ifc_page_track_range_bits {
13160 	u8         start_address[0x40];
13161 
13162 	u8         length[0x40];
13163 };
13164 
13165 struct mlx5_ifc_page_track_bits {
13166 	u8         modify_field_select[0x40];
13167 
13168 	u8         reserved_at_40[0x10];
13169 	u8         vhca_id[0x10];
13170 
13171 	u8         reserved_at_60[0x20];
13172 
13173 	u8         state[0x4];
13174 	u8         track_type[0x4];
13175 	u8         log_addr_space_size[0x8];
13176 	u8         reserved_at_90[0x3];
13177 	u8         log_page_size[0x5];
13178 	u8         reserved_at_98[0x3];
13179 	u8         log_msg_size[0x5];
13180 
13181 	u8         reserved_at_a0[0x8];
13182 	u8         reporting_qpn[0x18];
13183 
13184 	u8         reserved_at_c0[0x18];
13185 	u8         num_ranges[0x8];
13186 
13187 	u8         reserved_at_e0[0x20];
13188 
13189 	u8         range_start_address[0x40];
13190 
13191 	u8         length[0x40];
13192 
13193 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13194 };
13195 
13196 struct mlx5_ifc_create_page_track_obj_in_bits {
13197 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13198 	struct mlx5_ifc_page_track_bits obj_context;
13199 };
13200 
13201 struct mlx5_ifc_modify_page_track_obj_in_bits {
13202 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13203 	struct mlx5_ifc_page_track_bits obj_context;
13204 };
13205 
13206 struct mlx5_ifc_query_page_track_obj_out_bits {
13207 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13208 	struct mlx5_ifc_page_track_bits obj_context;
13209 };
13210 
13211 struct mlx5_ifc_msecq_reg_bits {
13212 	u8         reserved_at_0[0x20];
13213 
13214 	u8         reserved_at_20[0x12];
13215 	u8         network_option[0x2];
13216 	u8         local_ssm_code[0x4];
13217 	u8         local_enhanced_ssm_code[0x8];
13218 
13219 	u8         local_clock_identity[0x40];
13220 
13221 	u8         reserved_at_80[0x180];
13222 };
13223 
13224 enum {
13225 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13226 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13227 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13228 };
13229 
13230 enum mlx5_msees_admin_status {
13231 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13232 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13233 };
13234 
13235 enum mlx5_msees_oper_status {
13236 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13237 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13238 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13239 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13240 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13241 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13242 };
13243 
13244 enum mlx5_msees_failure_reason {
13245 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13246 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13247 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13248 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13249 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13250 };
13251 
13252 struct mlx5_ifc_msees_reg_bits {
13253 	u8         reserved_at_0[0x8];
13254 	u8         local_port[0x8];
13255 	u8         pnat[0x2];
13256 	u8         lp_msb[0x2];
13257 	u8         reserved_at_14[0xc];
13258 
13259 	u8         field_select[0x20];
13260 
13261 	u8         admin_status[0x4];
13262 	u8         oper_status[0x4];
13263 	u8         ho_acq[0x1];
13264 	u8         reserved_at_49[0xc];
13265 	u8         admin_freq_measure[0x1];
13266 	u8         oper_freq_measure[0x1];
13267 	u8         failure_reason[0x9];
13268 
13269 	u8         frequency_diff[0x20];
13270 
13271 	u8         reserved_at_80[0x180];
13272 };
13273 
13274 struct mlx5_ifc_mrtcq_reg_bits {
13275 	u8         reserved_at_0[0x40];
13276 
13277 	u8         rt_clock_identity[0x40];
13278 
13279 	u8         reserved_at_80[0x180];
13280 };
13281 
13282 #endif /* MLX5_IFC_H */
13283