1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63 #include "lib/sd.h"
64
65 extern const struct net_device_ops mlx5e_netdev_ops;
66 struct page_pool;
67
68 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
69 #define MLX5E_METADATA_ETHER_LEN 8
70
71 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
72
73 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
74 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
75
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8)
84 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
86 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
87 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
88 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
89 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
90
91 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
92 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
93 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
94 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
95 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
96 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
97
98 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
99 * These are theoretical maximums, which can be further restricted by
100 * capabilities. These values are used for static resource allocations and
101 * sanity checks.
102 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
103 * size actually used at runtime, but it's not a problem when calculating static
104 * array sizes.
105 */
106 #define MLX5_UMR_MAX_FLEX_SPACE \
107 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
108 MLX5_UMR_FLEX_ALIGNMENT))
109 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
110 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
111
112 #define MLX5E_MAX_RQ_NUM_MTTS \
113 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
114 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
115 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
116
117 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
118 #define MLX5E_LOG_MAX_RX_WQE_BULK \
119 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
120
121 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
122 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
123 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
124
125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
126 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
127 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
128
129 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
130
131 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
132 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024
133
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
142
143 #define MLX5E_MIN_NUM_CHANNELS 0x1
144 #define MLX5E_MAX_NUM_CHANNELS 256
145 #define MLX5E_TX_CQ_POLL_BUDGET 128
146 #define MLX5E_TX_XSK_POLL_BUDGET 64
147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
148
149 #define mlx5e_state_dereference(priv, p) \
150 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
151
152 enum mlx5e_devcom_events {
153 MPV_DEVCOM_MASTER_UP,
154 MPV_DEVCOM_MASTER_DOWN,
155 MPV_DEVCOM_IPSEC_MASTER_UP,
156 MPV_DEVCOM_IPSEC_MASTER_DOWN,
157 };
158
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)159 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
160 {
161 if (mlx5_lag_is_lacp_owner(mdev))
162 return 1;
163
164 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
165 }
166
mlx5_min_rx_wqes(int wq_type,u32 wq_size)167 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
168 {
169 switch (wq_type) {
170 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
171 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
172 wq_size / 2);
173 default:
174 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
175 wq_size / 2);
176 }
177 }
178
179 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)180 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
181 {
182 return is_kdump_kernel() ?
183 MLX5E_MIN_NUM_CHANNELS :
184 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,
185 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));
186 }
187
188 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
189 * bytes units. Driver hardens the limitation to 1KB (16
190 * WQEBBs), unless firmware capability is stricter.
191 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)192 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
193 {
194 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
195
196 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
197 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
198 }
199
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)200 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
201 {
202 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
203 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
204 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
205 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
206 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
207 * cache-aligned.
208 */
209 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
210
211 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
212 #if L1_CACHE_BYTES >= 128
213 wqebbs = ALIGN_DOWN(wqebbs, 2);
214 #endif
215 return wqebbs;
216 }
217
218 struct mlx5e_tx_wqe {
219 struct mlx5_wqe_ctrl_seg ctrl;
220 struct mlx5_wqe_eth_seg eth;
221 struct mlx5_wqe_data_seg data[];
222 };
223
224 struct mlx5e_rx_wqe_ll {
225 struct mlx5_wqe_srq_next_seg next;
226 struct mlx5_wqe_data_seg data[];
227 };
228
229 struct mlx5e_rx_wqe_cyc {
230 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
231 };
232
233 struct mlx5e_umr_wqe_hdr {
234 struct mlx5_wqe_ctrl_seg ctrl;
235 struct mlx5_wqe_umr_ctrl_seg uctrl;
236 struct mlx5_mkey_seg mkc;
237 };
238
239 struct mlx5e_umr_wqe {
240 struct mlx5e_umr_wqe_hdr hdr;
241 union {
242 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
243 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
244 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
245 };
246 };
247 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr),
248 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe");
249
250 enum mlx5e_priv_flag {
251 MLX5E_PFLAG_RX_CQE_BASED_MODER,
252 MLX5E_PFLAG_TX_CQE_BASED_MODER,
253 MLX5E_PFLAG_RX_CQE_COMPRESS,
254 MLX5E_PFLAG_RX_STRIDING_RQ,
255 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
256 MLX5E_PFLAG_XDP_TX_MPWQE,
257 MLX5E_PFLAG_SKB_TX_MPWQE,
258 MLX5E_PFLAG_TX_PORT_TS,
259 MLX5E_NUM_PFLAGS, /* Keep last */
260 };
261
262 #define MLX5E_SET_PFLAG(params, pflag, enable) \
263 do { \
264 if (enable) \
265 (params)->pflags |= BIT(pflag); \
266 else \
267 (params)->pflags &= ~(BIT(pflag)); \
268 } while (0)
269
270 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
271
272 enum packet_merge {
273 MLX5E_PACKET_MERGE_NONE,
274 MLX5E_PACKET_MERGE_LRO,
275 MLX5E_PACKET_MERGE_SHAMPO,
276 };
277
278 struct mlx5e_packet_merge_param {
279 enum packet_merge type;
280 u32 timeout;
281 struct {
282 u8 match_criteria_type;
283 u8 alignment_granularity;
284 } shampo;
285 };
286
287 struct mlx5e_params {
288 u8 log_sq_size;
289 u8 rq_wq_type;
290 u8 log_rq_mtu_frames;
291 u16 num_channels;
292 struct {
293 u16 mode;
294 u8 num_tc;
295 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
296 struct {
297 u64 max_rate[TC_MAX_QUEUE];
298 u32 hw_id[TC_MAX_QUEUE];
299 } channel;
300 } mqprio;
301 bool rx_cqe_compress_def;
302 struct dim_cq_moder rx_cq_moderation;
303 struct dim_cq_moder tx_cq_moderation;
304 struct mlx5e_packet_merge_param packet_merge;
305 u8 tx_min_inline_mode;
306 bool vlan_strip_disable;
307 bool scatter_fcs_en;
308 bool rx_dim_enabled;
309 bool tx_dim_enabled;
310 bool rx_moder_use_cqe_mode;
311 bool tx_moder_use_cqe_mode;
312 u32 pflags;
313 struct bpf_prog *xdp_prog;
314 struct mlx5e_xsk *xsk;
315 unsigned int sw_mtu;
316 int hard_mtu;
317 bool ptp_rx;
318 __be32 terminate_lkey_be;
319 };
320
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)321 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
322 {
323 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
324 params->mqprio.num_tc : 1;
325 }
326
327 /* Keep this enum consistent with the corresponding strings array
328 * declared in en/reporter_rx.c
329 */
330 enum {
331 MLX5E_RQ_STATE_ENABLED = 0,
332 MLX5E_RQ_STATE_RECOVERING,
333 MLX5E_RQ_STATE_DIM,
334 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
335 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
336 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
337 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
338 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
339 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
340 MLX5E_NUM_RQ_STATES, /* Must be kept last */
341 };
342
343 struct mlx5e_cq {
344 /* data path - accessed per cqe */
345 struct mlx5_cqwq wq;
346
347 /* data path - accessed per napi poll */
348 u16 event_ctr;
349 struct napi_struct *napi;
350 struct mlx5_core_cq mcq;
351 struct mlx5e_ch_stats *ch_stats;
352
353 /* control */
354 struct net_device *netdev;
355 struct mlx5_core_dev *mdev;
356 struct workqueue_struct *workqueue;
357 struct mlx5_wq_ctrl wq_ctrl;
358 } ____cacheline_aligned_in_smp;
359
360 struct mlx5e_cq_decomp {
361 /* cqe decompression */
362 struct mlx5_cqe64 title;
363 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
364 u8 mini_arr_idx;
365 u16 left;
366 u16 wqe_counter;
367 bool last_cqe_title;
368 } ____cacheline_aligned_in_smp;
369
370 enum mlx5e_dma_map_type {
371 MLX5E_DMA_MAP_SINGLE,
372 MLX5E_DMA_MAP_PAGE
373 };
374
375 struct mlx5e_sq_dma {
376 dma_addr_t addr;
377 u32 size;
378 enum mlx5e_dma_map_type type;
379 };
380
381 /* Keep this enum consistent with with the corresponding strings array
382 * declared in en/reporter_tx.c
383 */
384 enum {
385 MLX5E_SQ_STATE_ENABLED = 0,
386 MLX5E_SQ_STATE_MPWQE,
387 MLX5E_SQ_STATE_RECOVERING,
388 MLX5E_SQ_STATE_IPSEC,
389 MLX5E_SQ_STATE_DIM,
390 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
391 MLX5E_SQ_STATE_PENDING_XSK_TX,
392 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
393 MLX5E_NUM_SQ_STATES, /* Must be kept last */
394 };
395
396 struct mlx5e_tx_mpwqe {
397 /* Current MPWQE session */
398 struct mlx5e_tx_wqe *wqe;
399 u32 bytes_count;
400 u8 ds_count;
401 u8 ds_count_max;
402 u8 pkt_count;
403 u8 inline_on;
404 };
405
406 struct mlx5e_skb_fifo {
407 struct sk_buff **fifo;
408 u16 *pc;
409 u16 *cc;
410 u16 mask;
411 };
412
413 struct mlx5e_ptpsq;
414
415 struct mlx5e_txqsq {
416 /* data path */
417
418 /* dirtied @completion */
419 u16 cc;
420 u16 skb_fifo_cc;
421 u32 dma_fifo_cc;
422 struct dim *dim; /* Adaptive Moderation */
423
424 /* dirtied @xmit */
425 u16 pc ____cacheline_aligned_in_smp;
426 u16 skb_fifo_pc;
427 u32 dma_fifo_pc;
428 struct mlx5e_tx_mpwqe mpwqe;
429
430 struct mlx5e_cq cq;
431
432 /* read only */
433 struct mlx5_wq_cyc wq;
434 u32 dma_fifo_mask;
435 struct mlx5e_sq_stats *stats;
436 struct {
437 struct mlx5e_sq_dma *dma_fifo;
438 struct mlx5e_skb_fifo skb_fifo;
439 struct mlx5e_tx_wqe_info *wqe_info;
440 } db;
441 void __iomem *uar_map;
442 struct netdev_queue *txq;
443 u32 sqn;
444 u16 stop_room;
445 u8 max_sq_mpw_wqebbs;
446 u8 min_inline_mode;
447 struct device *pdev;
448 __be32 mkey_be;
449 unsigned long state;
450 unsigned int hw_mtu;
451 struct mlx5_clock *clock;
452 struct net_device *netdev;
453 struct mlx5_core_dev *mdev;
454 struct mlx5e_channel *channel;
455 struct mlx5e_priv *priv;
456
457 /* control path */
458 struct mlx5_wq_ctrl wq_ctrl;
459 int ch_ix;
460 int txq_ix;
461 u32 rate_limit;
462 struct work_struct recover_work;
463 struct mlx5e_ptpsq *ptpsq;
464 cqe_ts_to_ns ptp_cyc2time;
465 } ____cacheline_aligned_in_smp;
466
467 struct mlx5e_xdp_info_fifo {
468 union mlx5e_xdp_info *xi;
469 u32 *cc;
470 u32 *pc;
471 u32 mask;
472 };
473
474 struct mlx5e_xdpsq;
475 struct mlx5e_xmit_data;
476 struct xsk_tx_metadata;
477 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
478 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
479 struct mlx5e_xmit_data *,
480 int,
481 struct xsk_tx_metadata *);
482
483 struct mlx5e_xdpsq {
484 /* data path */
485
486 /* dirtied @completion */
487 u32 xdpi_fifo_cc;
488 u16 cc;
489
490 /* dirtied @xmit */
491 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
492 u16 pc;
493 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
494 struct mlx5e_tx_mpwqe mpwqe;
495
496 struct mlx5e_cq cq;
497
498 /* read only */
499 struct xsk_buff_pool *xsk_pool;
500 struct mlx5_wq_cyc wq;
501 struct mlx5e_xdpsq_stats *stats;
502 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
503 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
504 struct {
505 struct mlx5e_xdp_wqe_info *wqe_info;
506 struct mlx5e_xdp_info_fifo xdpi_fifo;
507 } db;
508 void __iomem *uar_map;
509 u32 sqn;
510 struct device *pdev;
511 __be32 mkey_be;
512 u16 stop_room;
513 u8 max_sq_mpw_wqebbs;
514 u8 min_inline_mode;
515 unsigned long state;
516 unsigned int hw_mtu;
517
518 /* control path */
519 struct mlx5_wq_ctrl wq_ctrl;
520 struct mlx5e_channel *channel;
521 } ____cacheline_aligned_in_smp;
522
523 struct mlx5e_ktls_resync_resp;
524
525 struct mlx5e_icosq {
526 /* data path */
527 u16 cc;
528 u16 pc;
529
530 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
531 struct mlx5e_cq cq;
532
533 /* write@xmit, read@completion */
534 struct {
535 struct mlx5e_icosq_wqe_info *wqe_info;
536 } db;
537
538 /* read only */
539 struct mlx5_wq_cyc wq;
540 void __iomem *uar_map;
541 u32 sqn;
542 u16 reserved_room;
543 unsigned long state;
544 struct mlx5e_ktls_resync_resp *ktls_resync;
545
546 /* control path */
547 struct mlx5_wq_ctrl wq_ctrl;
548 struct mlx5e_channel *channel;
549
550 struct work_struct recover_work;
551 } ____cacheline_aligned_in_smp;
552
553 struct mlx5e_frag_page {
554 struct page *page;
555 u16 frags;
556 };
557
558 enum mlx5e_wqe_frag_flag {
559 MLX5E_WQE_FRAG_LAST_IN_PAGE,
560 MLX5E_WQE_FRAG_SKIP_RELEASE,
561 };
562
563 struct mlx5e_wqe_frag_info {
564 union {
565 struct mlx5e_frag_page *frag_page;
566 struct xdp_buff **xskp;
567 };
568 u32 offset;
569 u8 flags;
570 };
571
572 union mlx5e_alloc_units {
573 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
574 DECLARE_FLEX_ARRAY(struct page *, pages);
575 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
576 };
577
578 struct mlx5e_mpw_info {
579 u16 consumed_strides;
580 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
581 struct mlx5e_frag_page linear_page;
582 union mlx5e_alloc_units alloc_units;
583 };
584
585 #define MLX5E_MAX_RX_FRAGS 4
586
587 struct mlx5e_rq;
588 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
589 typedef struct sk_buff *
590 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
591 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
592 u32 head_offset, u32 page_idx);
593 typedef struct sk_buff *
594 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
595 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
596 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
597 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
598 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
599
600 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
601 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
602
603 enum mlx5e_rq_flag {
604 MLX5E_RQ_FLAG_XDP_XMIT,
605 MLX5E_RQ_FLAG_XDP_REDIRECT,
606 };
607
608 struct mlx5e_rq_frag_info {
609 int frag_size;
610 int frag_stride;
611 };
612
613 struct mlx5e_rq_frags_info {
614 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
615 u8 num_frags;
616 u8 log_num_frags;
617 u16 wqe_bulk;
618 u16 refill_unit;
619 u8 wqe_index_mask;
620 };
621
622 struct mlx5e_dma_info {
623 dma_addr_t addr;
624 union {
625 struct mlx5e_frag_page *frag_page;
626 struct page *page;
627 };
628 };
629
630 struct mlx5e_shampo_hd {
631 u32 mkey;
632 struct mlx5e_frag_page *pages;
633 u32 hd_per_wq;
634 u16 hd_per_wqe;
635 u16 pages_per_wq;
636 unsigned long *bitmap;
637 u16 pi;
638 u16 ci;
639 __be32 key;
640 };
641
642 struct mlx5e_hw_gro_data {
643 struct sk_buff *skb;
644 struct flow_keys fk;
645 int second_ip_id;
646 };
647
648 enum mlx5e_mpwrq_umr_mode {
649 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
650 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
651 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
652 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
653 };
654
655 struct mlx5e_rq {
656 /* data path */
657 union {
658 struct {
659 struct mlx5_wq_cyc wq;
660 struct mlx5e_wqe_frag_info *frags;
661 union mlx5e_alloc_units *alloc_units;
662 struct mlx5e_rq_frags_info info;
663 mlx5e_fp_skb_from_cqe skb_from_cqe;
664 } wqe;
665 struct {
666 struct mlx5_wq_ll wq;
667 struct mlx5e_umr_wqe_hdr umr_wqe;
668 struct mlx5e_mpw_info *info;
669 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
670 __be32 umr_mkey_be;
671 u16 num_strides;
672 u16 actual_wq_head;
673 u8 log_stride_sz;
674 u8 umr_in_progress;
675 u8 umr_last_bulk;
676 u8 umr_completed;
677 u8 min_wqe_bulk;
678 u8 page_shift;
679 u8 pages_per_wqe;
680 u8 umr_wqebbs;
681 u8 mtts_per_wqe;
682 u8 umr_mode;
683 struct mlx5e_shampo_hd *shampo;
684 } mpwqe;
685 };
686 struct {
687 u16 headroom;
688 u32 frame0_sz;
689 u8 map_dir; /* dma map direction */
690 } buff;
691
692 struct device *pdev;
693 struct net_device *netdev;
694 struct mlx5e_rq_stats *stats;
695 struct mlx5e_cq cq;
696 struct mlx5e_cq_decomp cqd;
697 struct hwtstamp_config *tstamp;
698 struct mlx5_clock *clock;
699 struct mlx5e_icosq *icosq;
700 struct mlx5e_priv *priv;
701
702 struct mlx5e_hw_gro_data *hw_gro_data;
703
704 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
705 mlx5e_fp_post_rx_wqes post_wqes;
706 mlx5e_fp_dealloc_wqe dealloc_wqe;
707
708 unsigned long state;
709 int ix;
710 unsigned int hw_mtu;
711
712 struct dim *dim; /* Dynamic Interrupt Moderation */
713
714 /* XDP */
715 struct bpf_prog __rcu *xdp_prog;
716 struct mlx5e_xdpsq *xdpsq;
717 DECLARE_BITMAP(flags, 8);
718 struct page_pool *page_pool;
719
720 /* AF_XDP zero-copy */
721 struct xsk_buff_pool *xsk_pool;
722
723 struct work_struct recover_work;
724
725 /* control */
726 struct mlx5_wq_ctrl wq_ctrl;
727 __be32 mkey_be;
728 u8 wq_type;
729 u32 rqn;
730 struct mlx5_core_dev *mdev;
731 struct mlx5e_channel *channel;
732 struct mlx5e_dma_info wqe_overflow;
733
734 /* XDP read-mostly */
735 struct xdp_rxq_info xdp_rxq;
736 cqe_ts_to_ns ptp_cyc2time;
737 } ____cacheline_aligned_in_smp;
738
739 enum mlx5e_channel_state {
740 MLX5E_CHANNEL_STATE_XSK,
741 MLX5E_CHANNEL_NUM_STATES
742 };
743
744 struct mlx5e_channel {
745 /* data path */
746 struct mlx5e_rq rq;
747 struct mlx5e_xdpsq rq_xdpsq;
748 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC];
749 struct mlx5e_icosq icosq; /* internal control operations */
750 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
751 bool xdp;
752 struct napi_struct napi;
753 struct device *pdev;
754 struct net_device *netdev;
755 __be32 mkey_be;
756 u16 qos_sqs_size;
757 u8 num_tc;
758 u8 lag_port;
759
760 /* XDP_REDIRECT */
761 struct mlx5e_xdpsq *xdpsq;
762
763 /* AF_XDP zero-copy */
764 struct mlx5e_rq xskrq;
765 struct mlx5e_xdpsq xsksq;
766
767 /* Async ICOSQ */
768 struct mlx5e_icosq async_icosq;
769 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
770 spinlock_t async_icosq_lock;
771
772 /* data path - accessed per napi poll */
773 const struct cpumask *aff_mask;
774 struct mlx5e_ch_stats *stats;
775
776 /* control */
777 struct mlx5e_priv *priv;
778 struct mlx5_core_dev *mdev;
779 struct hwtstamp_config *tstamp;
780 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
781 int ix;
782 int vec_ix;
783 int sd_ix;
784 int cpu;
785 /* Sync between icosq recovery and XSK enable/disable. */
786 struct mutex icosq_recovery_lock;
787
788 /* coalescing configuration */
789 struct dim_cq_moder rx_cq_moder;
790 struct dim_cq_moder tx_cq_moder;
791 };
792
793 struct mlx5e_ptp;
794
795 struct mlx5e_channels {
796 struct mlx5e_channel **c;
797 struct mlx5e_ptp *ptp;
798 unsigned int num;
799 struct mlx5e_params params;
800 };
801
802 struct mlx5e_channel_stats {
803 struct mlx5e_ch_stats ch;
804 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
805 struct mlx5e_rq_stats rq;
806 struct mlx5e_rq_stats xskrq;
807 struct mlx5e_xdpsq_stats rq_xdpsq;
808 struct mlx5e_xdpsq_stats xdpsq;
809 struct mlx5e_xdpsq_stats xsksq;
810 } ____cacheline_aligned_in_smp;
811
812 struct mlx5e_ptp_stats {
813 struct mlx5e_ch_stats ch;
814 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
815 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];
816 struct mlx5e_rq_stats rq;
817 } ____cacheline_aligned_in_smp;
818
819 enum {
820 MLX5E_STATE_OPENED,
821 MLX5E_STATE_DESTROYING,
822 MLX5E_STATE_XDP_TX_ENABLED,
823 MLX5E_STATE_XDP_ACTIVE,
824 MLX5E_STATE_CHANNELS_ACTIVE,
825 };
826
827 struct mlx5e_modify_sq_param {
828 int curr_state;
829 int next_state;
830 int rl_update;
831 int rl_index;
832 bool qos_update;
833 u16 qos_queue_group_id;
834 };
835
836 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
837 struct mlx5e_hv_vhca_stats_agent {
838 struct mlx5_hv_vhca_agent *agent;
839 struct delayed_work work;
840 u16 delay;
841 void *buf;
842 };
843 #endif
844
845 struct mlx5e_xsk {
846 /* XSK buffer pools are stored separately from channels,
847 * because we don't want to lose them when channels are
848 * recreated. The kernel also stores buffer pool, but it doesn't
849 * distinguish between zero-copy and non-zero-copy UMEMs, so
850 * rely on our mechanism.
851 */
852 struct xsk_buff_pool **pools;
853 u16 refcnt;
854 bool ever_used;
855 };
856
857 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
858 * initialized, and used where we can't allocate them because that functions
859 * must not fail. Use with care and make sure the same variable is not used
860 * simultaneously by multiple users.
861 */
862 struct mlx5e_scratchpad {
863 cpumask_var_t cpumask;
864 };
865
866 struct mlx5e_trap;
867 struct mlx5e_htb;
868
869 struct mlx5e_priv {
870 /* priv data path fields - start */
871 struct mlx5e_selq selq;
872 struct mlx5e_txqsq **txq2sq;
873 struct mlx5e_sq_stats **txq2sq_stats;
874
875 #ifdef CONFIG_MLX5_CORE_EN_DCB
876 struct mlx5e_dcbx_dp dcbx_dp;
877 #endif
878 /* priv data path fields - end */
879
880 unsigned long state;
881 struct mutex state_lock; /* Protects Interface state */
882 struct mlx5e_rq drop_rq;
883
884 struct mlx5e_channels channels;
885 struct mlx5e_rx_res *rx_res;
886 u32 *tx_rates;
887
888 struct mlx5e_flow_steering *fs;
889
890 struct workqueue_struct *wq;
891 struct work_struct update_carrier_work;
892 struct work_struct set_rx_mode_work;
893 struct work_struct tx_timeout_work;
894 struct work_struct update_stats_work;
895 struct work_struct monitor_counters_work;
896 struct mlx5_nb monitor_counters_nb;
897
898 struct mlx5_core_dev *mdev;
899 struct net_device *netdev;
900 struct mlx5e_trap *en_trap;
901 struct mlx5e_stats stats;
902 struct mlx5e_channel_stats **channel_stats;
903 struct mlx5e_channel_stats trap_stats;
904 struct mlx5e_ptp_stats ptp_stats;
905 struct mlx5e_sq_stats **htb_qos_sq_stats;
906 u16 htb_max_qos_sqs;
907 u16 stats_nch;
908 u16 max_nch;
909 u8 max_opened_tc;
910 bool tx_ptp_opened;
911 bool rx_ptp_opened;
912 struct hwtstamp_config tstamp;
913 u16 q_counter[MLX5_SD_MAX_GROUP_SZ];
914 u16 drop_rq_q_counter;
915 struct notifier_block events_nb;
916 struct notifier_block blocking_events_nb;
917
918 struct udp_tunnel_nic_info nic_info;
919 #ifdef CONFIG_MLX5_CORE_EN_DCB
920 struct mlx5e_dcbx dcbx;
921 #endif
922
923 const struct mlx5e_profile *profile;
924 void *ppriv;
925 #ifdef CONFIG_MLX5_MACSEC
926 struct mlx5e_macsec *macsec;
927 #endif
928 #ifdef CONFIG_MLX5_EN_IPSEC
929 struct mlx5e_ipsec *ipsec;
930 #endif
931 #ifdef CONFIG_MLX5_EN_TLS
932 struct mlx5e_tls *tls;
933 #endif
934 struct devlink_health_reporter *tx_reporter;
935 struct devlink_health_reporter *rx_reporter;
936 struct mlx5e_xsk xsk;
937 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
938 struct mlx5e_hv_vhca_stats_agent stats_agent;
939 #endif
940 struct mlx5e_scratchpad scratchpad;
941 struct mlx5e_htb *htb;
942 struct mlx5e_mqprio_rl *mqprio_rl;
943 struct dentry *dfs_root;
944 struct mlx5_devcom_comp_dev *devcom;
945 };
946
947 struct mlx5e_dev {
948 struct mlx5e_priv *priv;
949 struct devlink_port dl_port;
950 };
951
952 struct mlx5e_rx_handlers {
953 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
954 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
955 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
956 };
957
958 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
959
960 enum mlx5e_profile_feature {
961 MLX5E_PROFILE_FEATURE_PTP_RX,
962 MLX5E_PROFILE_FEATURE_PTP_TX,
963 MLX5E_PROFILE_FEATURE_QOS_HTB,
964 MLX5E_PROFILE_FEATURE_FS_VLAN,
965 MLX5E_PROFILE_FEATURE_FS_TC,
966 };
967
968 struct mlx5e_profile {
969 int (*init)(struct mlx5_core_dev *mdev,
970 struct net_device *netdev);
971 void (*cleanup)(struct mlx5e_priv *priv);
972 int (*init_rx)(struct mlx5e_priv *priv);
973 void (*cleanup_rx)(struct mlx5e_priv *priv);
974 int (*init_tx)(struct mlx5e_priv *priv);
975 void (*cleanup_tx)(struct mlx5e_priv *priv);
976 void (*enable)(struct mlx5e_priv *priv);
977 void (*disable)(struct mlx5e_priv *priv);
978 int (*update_rx)(struct mlx5e_priv *priv);
979 void (*update_stats)(struct mlx5e_priv *priv);
980 void (*update_carrier)(struct mlx5e_priv *priv);
981 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
982 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,
983 u8 lag_port, u8 tc);
984 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
985 mlx5e_stats_grp_t *stats_grps;
986 const struct mlx5e_rx_handlers *rx_handlers;
987 int max_tc;
988 u32 features;
989 };
990
991 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
992 struct mlx5e_priv *priv,
993 const struct mlx5e_profile *profile,
994 u8 lag_port, u8 tc);
995
996 #define mlx5e_profile_feature_cap(profile, feature) \
997 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
998
999 void mlx5e_build_ptys2ethtool_map(void);
1000
1001 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1002 enum mlx5e_mpwrq_umr_mode umr_mode);
1003
1004 void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len);
1005 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq);
1006 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1007 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1008
1009 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1010 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1011 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1012 u64 *buf);
1013 void mlx5e_set_rx_mode_work(struct work_struct *work);
1014
1015 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1016 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1017 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1018
1019 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1020 u16 vid);
1021 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1022 u16 vid);
1023 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1024
1025 struct mlx5e_xsk_param;
1026
1027 struct mlx5e_rq_param;
1028 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1029 struct mlx5e_xsk_param *xsk, int node, u16 q_counter,
1030 struct mlx5e_rq *rq);
1031 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1032 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1033 void mlx5e_close_rq(struct mlx5e_rq *rq);
1034 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter);
1035 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1036
1037 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1038 bool dim_enabled);
1039 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1040 bool dim_enabled, bool keep_dim_state);
1041
1042 struct mlx5e_sq_param;
1043 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1044 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1045 struct mlx5e_xdpsq *sq, bool is_redirect);
1046 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1047
1048 struct mlx5e_create_cq_param {
1049 struct net_device *netdev;
1050 struct workqueue_struct *wq;
1051 struct napi_struct *napi;
1052 struct mlx5e_ch_stats *ch_stats;
1053 int node;
1054 int ix;
1055 };
1056
1057 struct mlx5e_cq_param;
1058 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
1059 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1060 struct mlx5e_cq *cq);
1061 void mlx5e_close_cq(struct mlx5e_cq *cq);
1062 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1063 u8 cq_period_mode);
1064 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1065 u16 cq_period, u16 cq_max_count, u8 cq_period_mode);
1066
1067 int mlx5e_open_locked(struct net_device *netdev);
1068 int mlx5e_close_locked(struct net_device *netdev);
1069
1070 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1071 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1072
1073 int mlx5e_open_channels(struct mlx5e_priv *priv,
1074 struct mlx5e_channels *chs);
1075 void mlx5e_close_channels(struct mlx5e_channels *chs);
1076
1077 /* Function pointer to be used to modify HW or kernel settings while
1078 * switching channels
1079 */
1080 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1081 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1082 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1083 { \
1084 return fn(priv); \
1085 }
1086 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1087 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1088 struct mlx5e_params *new_params,
1089 mlx5e_fp_preactivate preactivate,
1090 void *context, bool reset);
1091 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1092 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1093 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context);
1094 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1095 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1096 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1097
1098 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1099 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1100 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1101 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1102 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1103
1104 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1105 struct mlx5e_modify_sq_param *p);
1106 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1107 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1108 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1109 struct mlx5e_sq_stats *sq_stats);
1110 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1111 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1112 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1113 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1114 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1115 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1116 struct mlx5e_create_sq_param;
1117 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1118 struct mlx5e_sq_param *param,
1119 struct mlx5e_create_sq_param *csp,
1120 u16 qos_queue_group_id,
1121 u32 *sqn);
1122 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1123 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1124
1125 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1126 bool dim_enabled);
1127 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1128 bool dim_enabled, bool keep_dim_state);
1129
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1130 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1131 {
1132 return MLX5_CAP_ETH(mdev, swp) &&
1133 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1134 }
1135
1136 extern const struct ethtool_ops mlx5e_ethtool_ops;
1137
1138 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1139 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);
1140 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1141 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1142 bool enable_mc_lb);
1143 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1144
1145 /* common netdev helpers */
1146 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1147 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1148 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1149 struct mlx5e_rq *drop_rq);
1150 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1151
1152 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1153 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1154
1155 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1156 int mlx5e_close(struct net_device *netdev);
1157 int mlx5e_open(struct net_device *netdev);
1158
1159 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1160
1161 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1162 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1163 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1164 mlx5e_fp_preactivate preactivate);
1165 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1166
1167 /* ethtool helpers */
1168 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1169 struct ethtool_drvinfo *drvinfo);
1170 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1171 u32 stringset, u8 *data);
1172 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1173 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1174 struct ethtool_stats *stats, u64 *data);
1175 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1176 struct ethtool_ringparam *param,
1177 struct kernel_ethtool_ringparam *kernel_param);
1178 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1179 struct ethtool_ringparam *param,
1180 struct netlink_ext_ack *extack);
1181 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1182 struct ethtool_channels *ch);
1183 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1184 struct ethtool_channels *ch);
1185 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1186 struct ethtool_coalesce *coal,
1187 struct kernel_ethtool_coalesce *kernel_coal,
1188 struct netlink_ext_ack *extack);
1189 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1190 struct ethtool_coalesce *coal,
1191 struct kernel_ethtool_coalesce *kernel_coal,
1192 struct netlink_ext_ack *extack);
1193 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
1194 struct ethtool_coalesce *coal);
1195 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1196 struct ethtool_coalesce *coal);
1197 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1198 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1199 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1200 struct kernel_ethtool_ts_info *info);
1201 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1202 struct ethtool_flash *flash);
1203
1204 /* mlx5e generic netdev management API */
1205 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1206 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1207 {
1208 return !is_kdump_kernel() &&
1209 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1210 }
1211
1212 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1213 int mlx5e_priv_init(struct mlx5e_priv *priv,
1214 const struct mlx5e_profile *profile,
1215 struct net_device *netdev,
1216 struct mlx5_core_dev *mdev);
1217 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1218 struct net_device *
1219 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1220 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1221 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1222 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1223 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1224 const struct mlx5e_profile *new_profile, void *new_ppriv);
1225 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1226 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1227 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1228
1229 void mlx5e_set_xdp_feature(struct net_device *netdev);
1230 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1231 struct net_device *netdev,
1232 netdev_features_t features);
1233 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1234 #ifdef CONFIG_MLX5_ESWITCH
1235 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1236 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1237 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1238 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1239 #endif
1240 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1241 #endif /* __MLX5_EN_H__ */
1242