1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63 #include "lib/sd.h"
64
65 extern const struct net_device_ops mlx5e_netdev_ops;
66 struct page_pool;
67
68 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
69 #define MLX5E_METADATA_ETHER_LEN 8
70
71 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
72
73 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
74 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
75
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8)
84 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
86 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
87 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
88 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
89 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
90
91 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
92 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
93 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
94 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
95 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
96 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
97
98 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18
99
100 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
101 * These are theoretical maximums, which can be further restricted by
102 * capabilities. These values are used for static resource allocations and
103 * sanity checks.
104 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
105 * size actually used at runtime, but it's not a problem when calculating static
106 * array sizes.
107 */
108 #define MLX5_UMR_MAX_FLEX_SPACE \
109 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
110 MLX5_UMR_FLEX_ALIGNMENT))
111 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
112 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
113
114 #define MLX5E_MAX_RQ_NUM_MTTS \
115 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
116 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
117 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
118
119 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
120 #define MLX5E_LOG_MAX_RX_WQE_BULK \
121 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
122
123 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
124 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
125 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
126
127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
128 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
129 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
130
131 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
132
133 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
134 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024
135
136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
142 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
143 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
144
145 #define MLX5E_MIN_NUM_CHANNELS 0x1
146 #define MLX5E_MAX_NUM_CHANNELS 256
147 #define MLX5E_TX_CQ_POLL_BUDGET 128
148 #define MLX5E_TX_XSK_POLL_BUDGET 64
149 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
150
151 #define mlx5e_state_dereference(priv, p) \
152 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
153
154 enum mlx5e_devcom_events {
155 MPV_DEVCOM_MASTER_UP,
156 MPV_DEVCOM_MASTER_DOWN,
157 MPV_DEVCOM_IPSEC_MASTER_UP,
158 MPV_DEVCOM_IPSEC_MASTER_DOWN,
159 };
160
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)161 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
162 {
163 if (mlx5_lag_is_lacp_owner(mdev))
164 return 1;
165
166 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
167 }
168
mlx5_min_rx_wqes(int wq_type,u32 wq_size)169 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
170 {
171 switch (wq_type) {
172 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
173 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
174 wq_size / 2);
175 default:
176 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
177 wq_size / 2);
178 }
179 }
180
181 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)182 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
183 {
184 return is_kdump_kernel() ?
185 MLX5E_MIN_NUM_CHANNELS :
186 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,
187 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));
188 }
189
190 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
191 * bytes units. Driver hardens the limitation to 1KB (16
192 * WQEBBs), unless firmware capability is stricter.
193 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)194 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
195 {
196 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
197
198 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
199 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
200 }
201
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)202 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
203 {
204 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
205 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
206 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
207 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
208 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
209 * cache-aligned.
210 */
211 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
212
213 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
214 #if L1_CACHE_BYTES >= 128
215 wqebbs = ALIGN_DOWN(wqebbs, 2);
216 #endif
217 return wqebbs;
218 }
219
220 struct mlx5e_tx_wqe {
221 struct mlx5_wqe_ctrl_seg ctrl;
222 struct mlx5_wqe_eth_seg eth;
223 struct mlx5_wqe_data_seg data[];
224 };
225
226 struct mlx5e_rx_wqe_ll {
227 struct mlx5_wqe_srq_next_seg next;
228 struct mlx5_wqe_data_seg data[];
229 };
230
231 struct mlx5e_rx_wqe_cyc {
232 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
233 };
234
235 struct mlx5e_umr_wqe {
236 struct mlx5_wqe_ctrl_seg ctrl;
237 struct mlx5_wqe_umr_ctrl_seg uctrl;
238 struct mlx5_mkey_seg mkc;
239 union {
240 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
241 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
242 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
243 };
244 };
245
246 enum mlx5e_priv_flag {
247 MLX5E_PFLAG_RX_CQE_BASED_MODER,
248 MLX5E_PFLAG_TX_CQE_BASED_MODER,
249 MLX5E_PFLAG_RX_CQE_COMPRESS,
250 MLX5E_PFLAG_RX_STRIDING_RQ,
251 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
252 MLX5E_PFLAG_XDP_TX_MPWQE,
253 MLX5E_PFLAG_SKB_TX_MPWQE,
254 MLX5E_PFLAG_TX_PORT_TS,
255 MLX5E_NUM_PFLAGS, /* Keep last */
256 };
257
258 #define MLX5E_SET_PFLAG(params, pflag, enable) \
259 do { \
260 if (enable) \
261 (params)->pflags |= BIT(pflag); \
262 else \
263 (params)->pflags &= ~(BIT(pflag)); \
264 } while (0)
265
266 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
267
268 enum packet_merge {
269 MLX5E_PACKET_MERGE_NONE,
270 MLX5E_PACKET_MERGE_LRO,
271 MLX5E_PACKET_MERGE_SHAMPO,
272 };
273
274 struct mlx5e_packet_merge_param {
275 enum packet_merge type;
276 u32 timeout;
277 struct {
278 u8 match_criteria_type;
279 u8 alignment_granularity;
280 } shampo;
281 };
282
283 struct mlx5e_params {
284 u8 log_sq_size;
285 u8 rq_wq_type;
286 u8 log_rq_mtu_frames;
287 u16 num_channels;
288 struct {
289 u16 mode;
290 u8 num_tc;
291 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
292 struct {
293 u64 max_rate[TC_MAX_QUEUE];
294 u32 hw_id[TC_MAX_QUEUE];
295 } channel;
296 } mqprio;
297 bool rx_cqe_compress_def;
298 struct dim_cq_moder rx_cq_moderation;
299 struct dim_cq_moder tx_cq_moderation;
300 struct mlx5e_packet_merge_param packet_merge;
301 u8 tx_min_inline_mode;
302 bool vlan_strip_disable;
303 bool scatter_fcs_en;
304 bool rx_dim_enabled;
305 bool tx_dim_enabled;
306 bool rx_moder_use_cqe_mode;
307 bool tx_moder_use_cqe_mode;
308 u32 pflags;
309 struct bpf_prog *xdp_prog;
310 struct mlx5e_xsk *xsk;
311 unsigned int sw_mtu;
312 int hard_mtu;
313 bool ptp_rx;
314 __be32 terminate_lkey_be;
315 };
316
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)317 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
318 {
319 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
320 params->mqprio.num_tc : 1;
321 }
322
323 /* Keep this enum consistent with the corresponding strings array
324 * declared in en/reporter_rx.c
325 */
326 enum {
327 MLX5E_RQ_STATE_ENABLED = 0,
328 MLX5E_RQ_STATE_RECOVERING,
329 MLX5E_RQ_STATE_DIM,
330 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
331 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
332 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
333 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
334 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
335 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
336 MLX5E_NUM_RQ_STATES, /* Must be kept last */
337 };
338
339 struct mlx5e_cq {
340 /* data path - accessed per cqe */
341 struct mlx5_cqwq wq;
342
343 /* data path - accessed per napi poll */
344 u16 event_ctr;
345 struct napi_struct *napi;
346 struct mlx5_core_cq mcq;
347 struct mlx5e_ch_stats *ch_stats;
348
349 /* control */
350 struct net_device *netdev;
351 struct mlx5_core_dev *mdev;
352 struct workqueue_struct *workqueue;
353 struct mlx5_wq_ctrl wq_ctrl;
354 } ____cacheline_aligned_in_smp;
355
356 struct mlx5e_cq_decomp {
357 /* cqe decompression */
358 struct mlx5_cqe64 title;
359 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
360 u8 mini_arr_idx;
361 u16 left;
362 u16 wqe_counter;
363 bool last_cqe_title;
364 } ____cacheline_aligned_in_smp;
365
366 enum mlx5e_dma_map_type {
367 MLX5E_DMA_MAP_SINGLE,
368 MLX5E_DMA_MAP_PAGE
369 };
370
371 struct mlx5e_sq_dma {
372 dma_addr_t addr;
373 u32 size;
374 enum mlx5e_dma_map_type type;
375 };
376
377 /* Keep this enum consistent with with the corresponding strings array
378 * declared in en/reporter_tx.c
379 */
380 enum {
381 MLX5E_SQ_STATE_ENABLED = 0,
382 MLX5E_SQ_STATE_MPWQE,
383 MLX5E_SQ_STATE_RECOVERING,
384 MLX5E_SQ_STATE_IPSEC,
385 MLX5E_SQ_STATE_DIM,
386 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
387 MLX5E_SQ_STATE_PENDING_XSK_TX,
388 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
389 MLX5E_SQ_STATE_XDP_MULTIBUF,
390 MLX5E_NUM_SQ_STATES, /* Must be kept last */
391 };
392
393 struct mlx5e_tx_mpwqe {
394 /* Current MPWQE session */
395 struct mlx5e_tx_wqe *wqe;
396 u32 bytes_count;
397 u8 ds_count;
398 u8 pkt_count;
399 u8 inline_on;
400 };
401
402 struct mlx5e_skb_fifo {
403 struct sk_buff **fifo;
404 u16 *pc;
405 u16 *cc;
406 u16 mask;
407 };
408
409 struct mlx5e_ptpsq;
410
411 struct mlx5e_txqsq {
412 /* data path */
413
414 /* dirtied @completion */
415 u16 cc;
416 u16 skb_fifo_cc;
417 u32 dma_fifo_cc;
418 struct dim *dim; /* Adaptive Moderation */
419
420 /* dirtied @xmit */
421 u16 pc ____cacheline_aligned_in_smp;
422 u16 skb_fifo_pc;
423 u32 dma_fifo_pc;
424 struct mlx5e_tx_mpwqe mpwqe;
425
426 struct mlx5e_cq cq;
427
428 /* read only */
429 struct mlx5_wq_cyc wq;
430 u32 dma_fifo_mask;
431 struct mlx5e_sq_stats *stats;
432 struct {
433 struct mlx5e_sq_dma *dma_fifo;
434 struct mlx5e_skb_fifo skb_fifo;
435 struct mlx5e_tx_wqe_info *wqe_info;
436 } db;
437 void __iomem *uar_map;
438 struct netdev_queue *txq;
439 u32 sqn;
440 u16 stop_room;
441 u8 max_sq_mpw_wqebbs;
442 u8 min_inline_mode;
443 struct device *pdev;
444 __be32 mkey_be;
445 unsigned long state;
446 unsigned int hw_mtu;
447 struct mlx5_clock *clock;
448 struct net_device *netdev;
449 struct mlx5_core_dev *mdev;
450 struct mlx5e_channel *channel;
451 struct mlx5e_priv *priv;
452
453 /* control path */
454 struct mlx5_wq_ctrl wq_ctrl;
455 int ch_ix;
456 int txq_ix;
457 u32 rate_limit;
458 struct work_struct recover_work;
459 struct mlx5e_ptpsq *ptpsq;
460 cqe_ts_to_ns ptp_cyc2time;
461 } ____cacheline_aligned_in_smp;
462
463 struct mlx5e_xdp_info_fifo {
464 union mlx5e_xdp_info *xi;
465 u32 *cc;
466 u32 *pc;
467 u32 mask;
468 };
469
470 struct mlx5e_xdpsq;
471 struct mlx5e_xmit_data;
472 struct xsk_tx_metadata;
473 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
474 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
475 struct mlx5e_xmit_data *,
476 int,
477 struct xsk_tx_metadata *);
478
479 struct mlx5e_xdpsq {
480 /* data path */
481
482 /* dirtied @completion */
483 u32 xdpi_fifo_cc;
484 u16 cc;
485
486 /* dirtied @xmit */
487 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
488 u16 pc;
489 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
490 struct mlx5e_tx_mpwqe mpwqe;
491
492 struct mlx5e_cq cq;
493
494 /* read only */
495 struct xsk_buff_pool *xsk_pool;
496 struct mlx5_wq_cyc wq;
497 struct mlx5e_xdpsq_stats *stats;
498 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
499 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
500 struct {
501 struct mlx5e_xdp_wqe_info *wqe_info;
502 struct mlx5e_xdp_info_fifo xdpi_fifo;
503 } db;
504 void __iomem *uar_map;
505 u32 sqn;
506 struct device *pdev;
507 __be32 mkey_be;
508 u16 stop_room;
509 u8 max_sq_mpw_wqebbs;
510 u8 min_inline_mode;
511 unsigned long state;
512 unsigned int hw_mtu;
513
514 /* control path */
515 struct mlx5_wq_ctrl wq_ctrl;
516 struct mlx5e_channel *channel;
517 } ____cacheline_aligned_in_smp;
518
519 struct mlx5e_ktls_resync_resp;
520
521 struct mlx5e_icosq {
522 /* data path */
523 u16 cc;
524 u16 pc;
525
526 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
527 struct mlx5e_cq cq;
528
529 /* write@xmit, read@completion */
530 struct {
531 struct mlx5e_icosq_wqe_info *wqe_info;
532 } db;
533
534 /* read only */
535 struct mlx5_wq_cyc wq;
536 void __iomem *uar_map;
537 u32 sqn;
538 u16 reserved_room;
539 unsigned long state;
540 struct mlx5e_ktls_resync_resp *ktls_resync;
541
542 /* control path */
543 struct mlx5_wq_ctrl wq_ctrl;
544 struct mlx5e_channel *channel;
545
546 struct work_struct recover_work;
547 } ____cacheline_aligned_in_smp;
548
549 struct mlx5e_frag_page {
550 struct page *page;
551 u16 frags;
552 };
553
554 enum mlx5e_wqe_frag_flag {
555 MLX5E_WQE_FRAG_LAST_IN_PAGE,
556 MLX5E_WQE_FRAG_SKIP_RELEASE,
557 };
558
559 struct mlx5e_wqe_frag_info {
560 union {
561 struct mlx5e_frag_page *frag_page;
562 struct xdp_buff **xskp;
563 };
564 u32 offset;
565 u8 flags;
566 };
567
568 union mlx5e_alloc_units {
569 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
570 DECLARE_FLEX_ARRAY(struct page *, pages);
571 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
572 };
573
574 struct mlx5e_mpw_info {
575 u16 consumed_strides;
576 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
577 struct mlx5e_frag_page linear_page;
578 union mlx5e_alloc_units alloc_units;
579 };
580
581 #define MLX5E_MAX_RX_FRAGS 4
582
583 struct mlx5e_rq;
584 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
585 typedef struct sk_buff *
586 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
587 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
588 u32 head_offset, u32 page_idx);
589 typedef struct sk_buff *
590 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
591 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
592 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
593 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
594 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
595
596 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
597 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
598
599 enum mlx5e_rq_flag {
600 MLX5E_RQ_FLAG_XDP_XMIT,
601 MLX5E_RQ_FLAG_XDP_REDIRECT,
602 };
603
604 struct mlx5e_rq_frag_info {
605 int frag_size;
606 int frag_stride;
607 };
608
609 struct mlx5e_rq_frags_info {
610 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
611 u8 num_frags;
612 u8 log_num_frags;
613 u16 wqe_bulk;
614 u16 refill_unit;
615 u8 wqe_index_mask;
616 };
617
618 struct mlx5e_dma_info {
619 dma_addr_t addr;
620 union {
621 struct mlx5e_frag_page *frag_page;
622 struct page *page;
623 };
624 };
625
626 struct mlx5e_shampo_hd {
627 u32 mkey;
628 struct mlx5e_frag_page *pages;
629 u32 hd_per_wq;
630 u16 hd_per_wqe;
631 u16 pages_per_wq;
632 unsigned long *bitmap;
633 u16 pi;
634 u16 ci;
635 __be32 key;
636 };
637
638 struct mlx5e_hw_gro_data {
639 struct sk_buff *skb;
640 struct flow_keys fk;
641 int second_ip_id;
642 };
643
644 enum mlx5e_mpwrq_umr_mode {
645 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
646 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
647 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
648 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
649 };
650
651 struct mlx5e_rq {
652 /* data path */
653 union {
654 struct {
655 struct mlx5_wq_cyc wq;
656 struct mlx5e_wqe_frag_info *frags;
657 union mlx5e_alloc_units *alloc_units;
658 struct mlx5e_rq_frags_info info;
659 mlx5e_fp_skb_from_cqe skb_from_cqe;
660 } wqe;
661 struct {
662 struct mlx5_wq_ll wq;
663 struct mlx5e_umr_wqe umr_wqe;
664 struct mlx5e_mpw_info *info;
665 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
666 __be32 umr_mkey_be;
667 u16 num_strides;
668 u16 actual_wq_head;
669 u8 log_stride_sz;
670 u8 umr_in_progress;
671 u8 umr_last_bulk;
672 u8 umr_completed;
673 u8 min_wqe_bulk;
674 u8 page_shift;
675 u8 pages_per_wqe;
676 u8 umr_wqebbs;
677 u8 mtts_per_wqe;
678 u8 umr_mode;
679 struct mlx5e_shampo_hd *shampo;
680 } mpwqe;
681 };
682 struct {
683 u16 headroom;
684 u32 frame0_sz;
685 u8 map_dir; /* dma map direction */
686 } buff;
687
688 struct device *pdev;
689 struct net_device *netdev;
690 struct mlx5e_rq_stats *stats;
691 struct mlx5e_cq cq;
692 struct mlx5e_cq_decomp cqd;
693 struct hwtstamp_config *tstamp;
694 struct mlx5_clock *clock;
695 struct mlx5e_icosq *icosq;
696 struct mlx5e_priv *priv;
697
698 struct mlx5e_hw_gro_data *hw_gro_data;
699
700 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
701 mlx5e_fp_post_rx_wqes post_wqes;
702 mlx5e_fp_dealloc_wqe dealloc_wqe;
703
704 unsigned long state;
705 int ix;
706 unsigned int hw_mtu;
707
708 struct dim *dim; /* Dynamic Interrupt Moderation */
709
710 /* XDP */
711 struct bpf_prog __rcu *xdp_prog;
712 struct mlx5e_xdpsq *xdpsq;
713 DECLARE_BITMAP(flags, 8);
714 struct page_pool *page_pool;
715
716 /* AF_XDP zero-copy */
717 struct xsk_buff_pool *xsk_pool;
718
719 struct work_struct recover_work;
720
721 /* control */
722 struct mlx5_wq_ctrl wq_ctrl;
723 __be32 mkey_be;
724 u8 wq_type;
725 u32 rqn;
726 struct mlx5_core_dev *mdev;
727 struct mlx5e_channel *channel;
728 struct mlx5e_dma_info wqe_overflow;
729
730 /* XDP read-mostly */
731 struct xdp_rxq_info xdp_rxq;
732 cqe_ts_to_ns ptp_cyc2time;
733 } ____cacheline_aligned_in_smp;
734
735 enum mlx5e_channel_state {
736 MLX5E_CHANNEL_STATE_XSK,
737 MLX5E_CHANNEL_NUM_STATES
738 };
739
740 struct mlx5e_channel {
741 /* data path */
742 struct mlx5e_rq rq;
743 struct mlx5e_xdpsq rq_xdpsq;
744 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC];
745 struct mlx5e_icosq icosq; /* internal control operations */
746 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
747 bool xdp;
748 struct napi_struct napi;
749 struct device *pdev;
750 struct net_device *netdev;
751 __be32 mkey_be;
752 u16 qos_sqs_size;
753 u8 num_tc;
754 u8 lag_port;
755
756 /* XDP_REDIRECT */
757 struct mlx5e_xdpsq *xdpsq;
758
759 /* AF_XDP zero-copy */
760 struct mlx5e_rq xskrq;
761 struct mlx5e_xdpsq xsksq;
762
763 /* Async ICOSQ */
764 struct mlx5e_icosq async_icosq;
765 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
766 spinlock_t async_icosq_lock;
767
768 /* data path - accessed per napi poll */
769 const struct cpumask *aff_mask;
770 struct mlx5e_ch_stats *stats;
771
772 /* control */
773 struct mlx5e_priv *priv;
774 struct mlx5_core_dev *mdev;
775 struct hwtstamp_config *tstamp;
776 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
777 int ix;
778 int vec_ix;
779 int sd_ix;
780 int cpu;
781 /* Sync between icosq recovery and XSK enable/disable. */
782 struct mutex icosq_recovery_lock;
783
784 /* coalescing configuration */
785 struct dim_cq_moder rx_cq_moder;
786 struct dim_cq_moder tx_cq_moder;
787 };
788
789 struct mlx5e_ptp;
790
791 struct mlx5e_channels {
792 struct mlx5e_channel **c;
793 struct mlx5e_ptp *ptp;
794 unsigned int num;
795 struct mlx5e_params params;
796 };
797
798 struct mlx5e_channel_stats {
799 struct mlx5e_ch_stats ch;
800 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
801 struct mlx5e_rq_stats rq;
802 struct mlx5e_rq_stats xskrq;
803 struct mlx5e_xdpsq_stats rq_xdpsq;
804 struct mlx5e_xdpsq_stats xdpsq;
805 struct mlx5e_xdpsq_stats xsksq;
806 } ____cacheline_aligned_in_smp;
807
808 struct mlx5e_ptp_stats {
809 struct mlx5e_ch_stats ch;
810 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
811 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];
812 struct mlx5e_rq_stats rq;
813 } ____cacheline_aligned_in_smp;
814
815 enum {
816 MLX5E_STATE_OPENED,
817 MLX5E_STATE_DESTROYING,
818 MLX5E_STATE_XDP_TX_ENABLED,
819 MLX5E_STATE_XDP_ACTIVE,
820 MLX5E_STATE_CHANNELS_ACTIVE,
821 };
822
823 struct mlx5e_modify_sq_param {
824 int curr_state;
825 int next_state;
826 int rl_update;
827 int rl_index;
828 bool qos_update;
829 u16 qos_queue_group_id;
830 };
831
832 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
833 struct mlx5e_hv_vhca_stats_agent {
834 struct mlx5_hv_vhca_agent *agent;
835 struct delayed_work work;
836 u16 delay;
837 void *buf;
838 };
839 #endif
840
841 struct mlx5e_xsk {
842 /* XSK buffer pools are stored separately from channels,
843 * because we don't want to lose them when channels are
844 * recreated. The kernel also stores buffer pool, but it doesn't
845 * distinguish between zero-copy and non-zero-copy UMEMs, so
846 * rely on our mechanism.
847 */
848 struct xsk_buff_pool **pools;
849 u16 refcnt;
850 bool ever_used;
851 };
852
853 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
854 * initialized, and used where we can't allocate them because that functions
855 * must not fail. Use with care and make sure the same variable is not used
856 * simultaneously by multiple users.
857 */
858 struct mlx5e_scratchpad {
859 cpumask_var_t cpumask;
860 };
861
862 struct mlx5e_trap;
863 struct mlx5e_htb;
864
865 struct mlx5e_priv {
866 /* priv data path fields - start */
867 struct mlx5e_selq selq;
868 struct mlx5e_txqsq **txq2sq;
869 struct mlx5e_sq_stats **txq2sq_stats;
870
871 #ifdef CONFIG_MLX5_CORE_EN_DCB
872 struct mlx5e_dcbx_dp dcbx_dp;
873 #endif
874 /* priv data path fields - end */
875
876 unsigned long state;
877 struct mutex state_lock; /* Protects Interface state */
878 struct mlx5e_rq drop_rq;
879
880 struct mlx5e_channels channels;
881 struct mlx5e_rx_res *rx_res;
882 u32 *tx_rates;
883
884 struct mlx5e_flow_steering *fs;
885
886 struct workqueue_struct *wq;
887 struct work_struct update_carrier_work;
888 struct work_struct set_rx_mode_work;
889 struct work_struct tx_timeout_work;
890 struct work_struct update_stats_work;
891 struct work_struct monitor_counters_work;
892 struct mlx5_nb monitor_counters_nb;
893
894 struct mlx5_core_dev *mdev;
895 struct net_device *netdev;
896 struct mlx5e_trap *en_trap;
897 struct mlx5e_stats stats;
898 struct mlx5e_channel_stats **channel_stats;
899 struct mlx5e_channel_stats trap_stats;
900 struct mlx5e_ptp_stats ptp_stats;
901 struct mlx5e_sq_stats **htb_qos_sq_stats;
902 u16 htb_max_qos_sqs;
903 u16 stats_nch;
904 u16 max_nch;
905 u8 max_opened_tc;
906 bool tx_ptp_opened;
907 bool rx_ptp_opened;
908 struct hwtstamp_config tstamp;
909 u16 q_counter[MLX5_SD_MAX_GROUP_SZ];
910 u16 drop_rq_q_counter;
911 struct notifier_block events_nb;
912 struct notifier_block blocking_events_nb;
913
914 struct udp_tunnel_nic_info nic_info;
915 #ifdef CONFIG_MLX5_CORE_EN_DCB
916 struct mlx5e_dcbx dcbx;
917 #endif
918
919 const struct mlx5e_profile *profile;
920 void *ppriv;
921 #ifdef CONFIG_MLX5_MACSEC
922 struct mlx5e_macsec *macsec;
923 #endif
924 #ifdef CONFIG_MLX5_EN_IPSEC
925 struct mlx5e_ipsec *ipsec;
926 #endif
927 #ifdef CONFIG_MLX5_EN_TLS
928 struct mlx5e_tls *tls;
929 #endif
930 struct devlink_health_reporter *tx_reporter;
931 struct devlink_health_reporter *rx_reporter;
932 struct mlx5e_xsk xsk;
933 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
934 struct mlx5e_hv_vhca_stats_agent stats_agent;
935 #endif
936 struct mlx5e_scratchpad scratchpad;
937 struct mlx5e_htb *htb;
938 struct mlx5e_mqprio_rl *mqprio_rl;
939 struct dentry *dfs_root;
940 struct mlx5_devcom_comp_dev *devcom;
941 };
942
943 struct mlx5e_dev {
944 struct mlx5e_priv *priv;
945 struct devlink_port dl_port;
946 };
947
948 struct mlx5e_rx_handlers {
949 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
950 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
951 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
952 };
953
954 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
955
956 enum mlx5e_profile_feature {
957 MLX5E_PROFILE_FEATURE_PTP_RX,
958 MLX5E_PROFILE_FEATURE_PTP_TX,
959 MLX5E_PROFILE_FEATURE_QOS_HTB,
960 MLX5E_PROFILE_FEATURE_FS_VLAN,
961 MLX5E_PROFILE_FEATURE_FS_TC,
962 };
963
964 struct mlx5e_profile {
965 int (*init)(struct mlx5_core_dev *mdev,
966 struct net_device *netdev);
967 void (*cleanup)(struct mlx5e_priv *priv);
968 int (*init_rx)(struct mlx5e_priv *priv);
969 void (*cleanup_rx)(struct mlx5e_priv *priv);
970 int (*init_tx)(struct mlx5e_priv *priv);
971 void (*cleanup_tx)(struct mlx5e_priv *priv);
972 void (*enable)(struct mlx5e_priv *priv);
973 void (*disable)(struct mlx5e_priv *priv);
974 int (*update_rx)(struct mlx5e_priv *priv);
975 void (*update_stats)(struct mlx5e_priv *priv);
976 void (*update_carrier)(struct mlx5e_priv *priv);
977 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
978 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,
979 u8 lag_port, u8 tc);
980 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
981 mlx5e_stats_grp_t *stats_grps;
982 const struct mlx5e_rx_handlers *rx_handlers;
983 int max_tc;
984 u32 features;
985 };
986
987 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
988 struct mlx5e_priv *priv,
989 const struct mlx5e_profile *profile,
990 u8 lag_port, u8 tc);
991
992 #define mlx5e_profile_feature_cap(profile, feature) \
993 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
994
995 void mlx5e_build_ptys2ethtool_map(void);
996
997 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
998 enum mlx5e_mpwrq_umr_mode umr_mode);
999
1000 void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len);
1001 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq);
1002 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1003 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1004
1005 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1006 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1007 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1008 u64 *buf);
1009 void mlx5e_set_rx_mode_work(struct work_struct *work);
1010
1011 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1012 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1013 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1014
1015 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1016 u16 vid);
1017 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1018 u16 vid);
1019 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1020
1021 struct mlx5e_xsk_param;
1022
1023 struct mlx5e_rq_param;
1024 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1025 struct mlx5e_xsk_param *xsk, int node, u16 q_counter,
1026 struct mlx5e_rq *rq);
1027 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1028 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1029 void mlx5e_close_rq(struct mlx5e_rq *rq);
1030 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter);
1031 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1032
1033 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1034 bool dim_enabled);
1035 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1036 bool dim_enabled, bool keep_dim_state);
1037
1038 struct mlx5e_sq_param;
1039 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1040 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1041 struct mlx5e_xdpsq *sq, bool is_redirect);
1042 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1043
1044 struct mlx5e_create_cq_param {
1045 struct net_device *netdev;
1046 struct workqueue_struct *wq;
1047 struct napi_struct *napi;
1048 struct mlx5e_ch_stats *ch_stats;
1049 int node;
1050 int ix;
1051 };
1052
1053 struct mlx5e_cq_param;
1054 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
1055 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1056 struct mlx5e_cq *cq);
1057 void mlx5e_close_cq(struct mlx5e_cq *cq);
1058 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1059 u8 cq_period_mode);
1060 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1061 u16 cq_period, u16 cq_max_count, u8 cq_period_mode);
1062
1063 int mlx5e_open_locked(struct net_device *netdev);
1064 int mlx5e_close_locked(struct net_device *netdev);
1065
1066 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1067 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1068
1069 int mlx5e_open_channels(struct mlx5e_priv *priv,
1070 struct mlx5e_channels *chs);
1071 void mlx5e_close_channels(struct mlx5e_channels *chs);
1072
1073 /* Function pointer to be used to modify HW or kernel settings while
1074 * switching channels
1075 */
1076 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1077 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1078 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1079 { \
1080 return fn(priv); \
1081 }
1082 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1083 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1084 struct mlx5e_params *new_params,
1085 mlx5e_fp_preactivate preactivate,
1086 void *context, bool reset);
1087 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1088 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1089 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context);
1090 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1091 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1092 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1093
1094 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1095 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1096 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1097 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1098 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1099
1100 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1101 struct mlx5e_modify_sq_param *p);
1102 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1103 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1104 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1105 struct mlx5e_sq_stats *sq_stats);
1106 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1107 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1108 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1109 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1110 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1111 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1112 struct mlx5e_create_sq_param;
1113 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1114 struct mlx5e_sq_param *param,
1115 struct mlx5e_create_sq_param *csp,
1116 u16 qos_queue_group_id,
1117 u32 *sqn);
1118 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1119 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1120
1121 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1122 bool dim_enabled);
1123 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1124 bool dim_enabled, bool keep_dim_state);
1125
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1126 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1127 {
1128 return MLX5_CAP_ETH(mdev, swp) &&
1129 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1130 }
1131
1132 extern const struct ethtool_ops mlx5e_ethtool_ops;
1133
1134 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1135 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);
1136 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1137 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1138 bool enable_mc_lb);
1139 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1140
1141 /* common netdev helpers */
1142 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1143 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1144 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1145 struct mlx5e_rq *drop_rq);
1146 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1147
1148 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1149 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1150
1151 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1152 int mlx5e_close(struct net_device *netdev);
1153 int mlx5e_open(struct net_device *netdev);
1154
1155 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1156
1157 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1158 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1159 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1160 mlx5e_fp_preactivate preactivate);
1161 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1162
1163 /* ethtool helpers */
1164 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1165 struct ethtool_drvinfo *drvinfo);
1166 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1167 u32 stringset, u8 *data);
1168 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1169 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1170 struct ethtool_stats *stats, u64 *data);
1171 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1172 struct ethtool_ringparam *param,
1173 struct kernel_ethtool_ringparam *kernel_param);
1174 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1175 struct ethtool_ringparam *param,
1176 struct netlink_ext_ack *extack);
1177 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1178 struct ethtool_channels *ch);
1179 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1180 struct ethtool_channels *ch);
1181 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1182 struct ethtool_coalesce *coal,
1183 struct kernel_ethtool_coalesce *kernel_coal,
1184 struct netlink_ext_ack *extack);
1185 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1186 struct ethtool_coalesce *coal,
1187 struct kernel_ethtool_coalesce *kernel_coal,
1188 struct netlink_ext_ack *extack);
1189 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
1190 struct ethtool_coalesce *coal);
1191 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1192 struct ethtool_coalesce *coal);
1193 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1194 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1195 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1196 struct kernel_ethtool_ts_info *info);
1197 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1198 struct ethtool_flash *flash);
1199
1200 /* mlx5e generic netdev management API */
1201 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1202 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1203 {
1204 return !is_kdump_kernel() &&
1205 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1206 }
1207
1208 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1209 int mlx5e_priv_init(struct mlx5e_priv *priv,
1210 const struct mlx5e_profile *profile,
1211 struct net_device *netdev,
1212 struct mlx5_core_dev *mdev);
1213 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1214 struct net_device *
1215 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1216 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1217 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1218 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1219 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1220 const struct mlx5e_profile *new_profile, void *new_ppriv);
1221 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1222 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1223 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1224
1225 void mlx5e_set_xdp_feature(struct net_device *netdev);
1226 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1227 struct net_device *netdev,
1228 netdev_features_t features);
1229 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1230 #ifdef CONFIG_MLX5_ESWITCH
1231 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1232 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1233 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1234 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1235 #endif
1236 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1237 #endif /* __MLX5_EN_H__ */
1238