1 /* 2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_PORT_H__ 34 #define __MLX5_PORT_H__ 35 36 #include <linux/mlx5/driver.h> 37 38 enum mlx5_beacon_duration { 39 MLX5_BEACON_DURATION_OFF = 0x0, 40 MLX5_BEACON_DURATION_INF = 0xffff, 41 }; 42 43 enum mlx5_module_id { 44 MLX5_MODULE_ID_SFP = 0x3, 45 MLX5_MODULE_ID_QSFP = 0xC, 46 MLX5_MODULE_ID_QSFP_PLUS = 0xD, 47 MLX5_MODULE_ID_QSFP28 = 0x11, 48 MLX5_MODULE_ID_DSFP = 0x1B, 49 }; 50 51 enum mlx5_an_status { 52 MLX5_AN_UNAVAILABLE = 0, 53 MLX5_AN_COMPLETE = 1, 54 MLX5_AN_FAILED = 2, 55 MLX5_AN_LINK_UP = 3, 56 MLX5_AN_LINK_DOWN = 4, 57 }; 58 59 #define MLX5_I2C_ADDR_LOW 0x50 60 #define MLX5_I2C_ADDR_HIGH 0x51 61 #define MLX5_EEPROM_PAGE_LENGTH 256 62 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128 63 64 enum mlx5e_link_mode { 65 MLX5E_1000BASE_CX_SGMII = 0, 66 MLX5E_1000BASE_KX = 1, 67 MLX5E_10GBASE_CX4 = 2, 68 MLX5E_10GBASE_KX4 = 3, 69 MLX5E_10GBASE_KR = 4, 70 MLX5E_20GBASE_KR2 = 5, 71 MLX5E_40GBASE_CR4 = 6, 72 MLX5E_40GBASE_KR4 = 7, 73 MLX5E_56GBASE_R4 = 8, 74 MLX5E_10GBASE_CR = 12, 75 MLX5E_10GBASE_SR = 13, 76 MLX5E_10GBASE_ER = 14, 77 MLX5E_40GBASE_SR4 = 15, 78 MLX5E_40GBASE_LR4 = 16, 79 MLX5E_50GBASE_SR2 = 18, 80 MLX5E_100GBASE_CR4 = 20, 81 MLX5E_100GBASE_SR4 = 21, 82 MLX5E_100GBASE_KR4 = 22, 83 MLX5E_100GBASE_LR4 = 23, 84 MLX5E_100BASE_TX = 24, 85 MLX5E_1000BASE_T = 25, 86 MLX5E_10GBASE_T = 26, 87 MLX5E_25GBASE_CR = 27, 88 MLX5E_25GBASE_KR = 28, 89 MLX5E_25GBASE_SR = 29, 90 MLX5E_50GBASE_CR2 = 30, 91 MLX5E_50GBASE_KR2 = 31, 92 MLX5E_LINK_MODES_NUMBER, 93 }; 94 95 enum mlx5e_ext_link_mode { 96 MLX5E_SGMII_100M = 0, 97 MLX5E_1000BASE_X_SGMII = 1, 98 MLX5E_5GBASE_R = 3, 99 MLX5E_10GBASE_XFI_XAUI_1 = 4, 100 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, 101 MLX5E_25GAUI_1_25GBASE_CR_KR = 6, 102 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, 103 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, 104 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, 105 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, 106 MLX5E_100GAUI_1_100GBASE_CR_KR = 11, 107 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 108 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, 109 MLX5E_200GAUI_1_200GBASE_CR1_KR1 = 14, 110 MLX5E_400GAUI_8_400GBASE_CR8 = 15, 111 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, 112 MLX5E_400GAUI_2_400GBASE_CR2_KR2 = 17, 113 MLX5E_800GAUI_8_800GBASE_CR8_KR8 = 19, 114 MLX5E_800GAUI_4_800GBASE_CR4_KR4 = 20, 115 MLX5E_EXT_LINK_MODES_NUMBER, 116 }; 117 118 enum mlx5e_connector_type { 119 MLX5E_PORT_UNKNOWN = 0, 120 MLX5E_PORT_NONE = 1, 121 MLX5E_PORT_TP = 2, 122 MLX5E_PORT_AUI = 3, 123 MLX5E_PORT_BNC = 4, 124 MLX5E_PORT_MII = 5, 125 MLX5E_PORT_FIBRE = 6, 126 MLX5E_PORT_DA = 7, 127 MLX5E_PORT_OTHER = 8, 128 MLX5E_CONNECTOR_TYPE_NUMBER, 129 }; 130 131 enum mlx5_ptys_width { 132 MLX5_PTYS_WIDTH_1X = 1 << 0, 133 MLX5_PTYS_WIDTH_2X = 1 << 1, 134 MLX5_PTYS_WIDTH_4X = 1 << 2, 135 MLX5_PTYS_WIDTH_8X = 1 << 3, 136 MLX5_PTYS_WIDTH_12X = 1 << 4, 137 }; 138 139 #define MLX5E_PROT_MASK(link_mode) (1U << link_mode) 140 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ 141 (ext ? MLX5_GET(reg, out, ext_##field) : \ 142 MLX5_GET(reg, out, field)) 143 144 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 145 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 146 int ptys_size, int proto_mask, 147 u8 local_port, u8 plane_index); 148 149 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, 150 u16 *proto_oper, u8 local_port, u8 plane_index); 151 152 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port); 153 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, 154 u8 port); 155 156 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 157 u8 *vl_hw_cap, u8 local_port); 158 159 #endif /* __MLX5_PORT_H__ */ 160