1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This driver is tested for USB, SGMII, SATA and Display Port currently.
12 * PCIe should also work but that is experimental as of now.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/slab.h>
26
27 #include <dt-bindings/phy/phy.h>
28
29 /*
30 * Lane Registers
31 */
32
33 /* TX De-emphasis parameters */
34 #define L0_TX_ANA_TM_18 0x0048
35 #define L0_TX_ANA_TM_118 0x01d8
36 #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
37
38 /* DN Resistor calibration code parameters */
39 #define L0_TXPMA_ST_3 0x0b0c
40 #define L0_DN_CALIB_CODE 0x3f
41
42 /* PMA control parameters */
43 #define L0_TXPMD_TM_45 0x0cb4
44 #define L0_TXPMD_TM_48 0x0cc0
45 #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
46 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
47 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
48 #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
49 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
50 #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
51
52 /* PCS control parameters */
53 #define L0_TM_DIG_6 0x106c
54 #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
55 #define L0_TX_DIG_61 0x00f4
56 #define L0_TM_DISABLE_SCRAMBLE_ENCODER (BIT(3) | GENMASK(1, 0))
57
58 /* PLL Test Mode register parameters */
59 #define L0_TM_PLL_DIG_37 0x2094
60 #define L0_TM_COARSE_CODE_LIMIT 0x10
61
62 /* PLL SSC step size offsets */
63 #define L0_PLL_SS_STEPS_0_LSB 0x2368
64 #define L0_PLL_SS_STEPS_1_MSB 0x236c
65 #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
66 #define L0_PLL_SS_STEP_SIZE_1 0x2374
67 #define L0_PLL_SS_STEP_SIZE_2 0x2378
68 #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
69 #define L0_PLL_STATUS_READ_1 0x23e4
70
71 /* SSC step size parameters */
72 #define STEP_SIZE_0_MASK 0xff
73 #define STEP_SIZE_1_MASK 0xff
74 #define STEP_SIZE_2_MASK 0xff
75 #define STEP_SIZE_3_MASK 0x3
76 #define STEP_SIZE_SHIFT 8
77 #define FORCE_STEP_SIZE 0x10
78 #define FORCE_STEPS 0x20
79 #define STEPS_0_MASK 0xff
80 #define STEPS_1_MASK 0x07
81
82 /* Reference clock selection parameters */
83 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
84 #define L0_REF_CLK_LCL_SEL BIT(7)
85 #define L0_REF_CLK_SEL_MASK 0x9f
86
87 /* Calibration digital logic parameters */
88 #define L3_TM_CALIB_DIG19 0xec4c
89 #define L3_CALIB_DONE_STATUS 0xef14
90 #define L3_TM_CALIB_DIG18 0xec48
91 #define L3_TM_CALIB_DIG19_NSW 0x07
92 #define L3_TM_CALIB_DIG18_NSW 0xe0
93 #define L3_TM_OVERRIDE_NSW_CODE 0x20
94 #define L3_CALIB_DONE 0x02
95 #define L3_NSW_SHIFT 5
96 #define L3_NSW_PIPE_SHIFT 4
97 #define L3_NSW_CALIB_SHIFT 3
98
99 #define PHY_REG_OFFSET 0x4000
100
101 /*
102 * Global Registers
103 */
104
105 /* Refclk selection parameters */
106 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
107 #define PLL_FREQ_MASK 0x1f
108 #define PLL_STATUS_LOCKED 0x10
109
110 /* Inter Connect Matrix parameters */
111 #define ICM_CFG0 0x10010
112 #define ICM_CFG1 0x10014
113 #define ICM_CFG0_L0_MASK 0x07
114 #define ICM_CFG0_L1_MASK 0x70
115 #define ICM_CFG1_L2_MASK 0x07
116 #define ICM_CFG2_L3_MASK 0x70
117 #define ICM_CFG_SHIFT 4
118
119 /* Inter Connect Matrix allowed protocols */
120 #define ICM_PROTOCOL_PD 0x0
121 #define ICM_PROTOCOL_PCIE 0x1
122 #define ICM_PROTOCOL_SATA 0x2
123 #define ICM_PROTOCOL_USB 0x3
124 #define ICM_PROTOCOL_DP 0x4
125 #define ICM_PROTOCOL_SGMII 0x5
126
127 static const char *const xpsgtr_icm_str[] = {
128 [ICM_PROTOCOL_PD] = "none",
129 [ICM_PROTOCOL_PCIE] = "PCIe",
130 [ICM_PROTOCOL_SATA] = "SATA",
131 [ICM_PROTOCOL_USB] = "USB",
132 [ICM_PROTOCOL_DP] = "DisplayPort",
133 [ICM_PROTOCOL_SGMII] = "SGMII",
134 };
135
136 /* Test Mode common reset control parameters */
137 #define TM_CMN_RST 0x10018
138 #define TM_CMN_RST_EN 0x1
139 #define TM_CMN_RST_SET 0x2
140 #define TM_CMN_RST_MASK 0x3
141
142 /* Bus width parameters */
143 #define TX_PROT_BUS_WIDTH 0x10040
144 #define RX_PROT_BUS_WIDTH 0x10044
145 #define PROT_BUS_WIDTH_10 0x0
146 #define PROT_BUS_WIDTH_20 0x1
147 #define PROT_BUS_WIDTH_40 0x2
148 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
149 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
150
151 /* Number of GT lanes */
152 #define NUM_LANES 4
153
154 /* SIOU SATA control register */
155 #define SATA_CONTROL_OFFSET 0x0100
156
157 /* Total number of controllers */
158 #define CONTROLLERS_PER_LANE 5
159
160 /* Timeout values */
161 #define TIMEOUT_US 1000
162
163 /* Lane 0/1/2/3 offset */
164 #define DIG_8(n) ((0x4000 * (n)) + 0x1074)
165 #define ILL13(n) ((0x4000 * (n)) + 0x1994)
166 #define DIG_10(n) ((0x4000 * (n)) + 0x107c)
167 #define RST_DLY(n) ((0x4000 * (n)) + 0x19a4)
168 #define BYP_15(n) ((0x4000 * (n)) + 0x1038)
169 #define BYP_12(n) ((0x4000 * (n)) + 0x102c)
170 #define MISC3(n) ((0x4000 * (n)) + 0x19ac)
171 #define EQ11(n) ((0x4000 * (n)) + 0x1978)
172
173 static u32 save_reg_address[] = {
174 /* Lane 0/1/2/3 Register */
175 DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),
176 DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),
177 DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),
178 DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),
179 };
180
181 struct xpsgtr_dev;
182
183 /**
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * @refclk_rate: PLL reference clock frequency
186 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
188 * @step_size: step size of each step
189 */
190 struct xpsgtr_ssc {
191 u32 refclk_rate;
192 u8 pll_ref_clk;
193 u32 steps;
194 u32 step_size;
195 };
196
197 /**
198 * struct xpsgtr_phy - representation of a lane
199 * @phy: pointer to the kernel PHY device
200 * @instance: instance of the protocol type (such as the lane within a
201 * protocol, or the USB/Ethernet controller)
202 * @lane: lane number
203 * @protocol: protocol in which the lane operates
204 * @skip_phy_init: skip phy_init() if true
205 * @dev: pointer to the xpsgtr_dev instance
206 * @refclk: reference clock index
207 */
208 struct xpsgtr_phy {
209 struct phy *phy;
210 u8 instance;
211 u8 lane;
212 u8 protocol;
213 bool skip_phy_init;
214 struct xpsgtr_dev *dev;
215 unsigned int refclk;
216 };
217
218 /**
219 * struct xpsgtr_dev - representation of a ZynMP GT device
220 * @dev: pointer to device
221 * @serdes: serdes base address
222 * @siou: siou base address
223 * @gtr_mutex: mutex for locking
224 * @phys: PHY lanes
225 * @clk: reference clocks
226 * @tx_term_fix: fix for GT issue
227 * @saved_icm_cfg0: stored value of ICM CFG0 register
228 * @saved_icm_cfg1: stored value of ICM CFG1 register
229 * @saved_regs: registers to be saved/restored during suspend/resume
230 */
231 struct xpsgtr_dev {
232 struct device *dev;
233 void __iomem *serdes;
234 void __iomem *siou;
235 struct mutex gtr_mutex; /* mutex for locking */
236 struct xpsgtr_phy phys[NUM_LANES];
237 struct clk *clk[NUM_LANES];
238 bool tx_term_fix;
239 unsigned int saved_icm_cfg0;
240 unsigned int saved_icm_cfg1;
241 u32 *saved_regs;
242 };
243
244 /*
245 * Configuration Data
246 */
247
248 /* lookup table to hold all settings needed for a ref clock frequency */
249 static const struct xpsgtr_ssc ssc_lookup[] = {
250 { 19200000, 0x05, 608, 264020 },
251 { 20000000, 0x06, 634, 243454 },
252 { 24000000, 0x07, 760, 168973 },
253 { 26000000, 0x08, 824, 143860 },
254 { 27000000, 0x09, 856, 86551 },
255 { 38400000, 0x0a, 1218, 65896 },
256 { 40000000, 0x0b, 634, 243454 },
257 { 52000000, 0x0c, 824, 143860 },
258 { 100000000, 0x0d, 1058, 87533 },
259 { 108000000, 0x0e, 856, 86551 },
260 { 125000000, 0x0f, 992, 119497 },
261 { 135000000, 0x10, 1070, 55393 },
262 { 150000000, 0x11, 792, 187091 }
263 };
264
265 /*
266 * I/O Accessors
267 */
268
xpsgtr_read(struct xpsgtr_dev * gtr_dev,u32 reg)269 static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
270 {
271 return readl(gtr_dev->serdes + reg);
272 }
273
xpsgtr_write(struct xpsgtr_dev * gtr_dev,u32 reg,u32 value)274 static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
275 {
276 writel(value, gtr_dev->serdes + reg);
277 }
278
xpsgtr_clr_set(struct xpsgtr_dev * gtr_dev,u32 reg,u32 clr,u32 set)279 static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
280 u32 clr, u32 set)
281 {
282 u32 value = xpsgtr_read(gtr_dev, reg);
283
284 value &= ~clr;
285 value |= set;
286 xpsgtr_write(gtr_dev, reg, value);
287 }
288
xpsgtr_read_phy(struct xpsgtr_phy * gtr_phy,u32 reg)289 static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
290 {
291 void __iomem *addr = gtr_phy->dev->serdes
292 + gtr_phy->lane * PHY_REG_OFFSET + reg;
293
294 return readl(addr);
295 }
296
xpsgtr_write_phy(struct xpsgtr_phy * gtr_phy,u32 reg,u32 value)297 static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
298 u32 reg, u32 value)
299 {
300 void __iomem *addr = gtr_phy->dev->serdes
301 + gtr_phy->lane * PHY_REG_OFFSET + reg;
302
303 writel(value, addr);
304 }
305
xpsgtr_clr_set_phy(struct xpsgtr_phy * gtr_phy,u32 reg,u32 clr,u32 set)306 static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
307 u32 reg, u32 clr, u32 set)
308 {
309 void __iomem *addr = gtr_phy->dev->serdes
310 + gtr_phy->lane * PHY_REG_OFFSET + reg;
311
312 writel((readl(addr) & ~clr) | set, addr);
313 }
314
315 /**
316 * xpsgtr_save_lane_regs - Saves registers on suspend
317 * @gtr_dev: pointer to phy controller context structure
318 */
xpsgtr_save_lane_regs(struct xpsgtr_dev * gtr_dev)319 static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)
320 {
321 int i;
322
323 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
324 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,
325 save_reg_address[i]);
326 }
327
328 /**
329 * xpsgtr_restore_lane_regs - Restores registers on resume
330 * @gtr_dev: pointer to phy controller context structure
331 */
xpsgtr_restore_lane_regs(struct xpsgtr_dev * gtr_dev)332 static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)
333 {
334 int i;
335
336 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
337 xpsgtr_write(gtr_dev, save_reg_address[i],
338 gtr_dev->saved_regs[i]);
339 }
340
341 /*
342 * Hardware Configuration
343 */
344
345 /* Wait for the PLL to lock (with a timeout). */
xpsgtr_wait_pll_lock(struct phy * phy)346 static int xpsgtr_wait_pll_lock(struct phy *phy)
347 {
348 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
349 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
350 unsigned int timeout = TIMEOUT_US;
351 u8 protocol = gtr_phy->protocol;
352 int ret;
353
354 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
355
356 /*
357 * For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
358 * so we wait on the right PLL.
359 */
360 if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
361 gtr_phy->instance) {
362 int i;
363
364 for (i = 0; i < NUM_LANES; i++) {
365 gtr_phy = >r_dev->phys[i];
366
367 if (gtr_phy->protocol == protocol && !gtr_phy->instance)
368 goto got_phy;
369 }
370
371 return -EBUSY;
372 }
373
374 got_phy:
375 while (1) {
376 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
377
378 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
379 ret = 0;
380 break;
381 }
382
383 if (--timeout == 0) {
384 ret = -ETIMEDOUT;
385 break;
386 }
387
388 udelay(1);
389 }
390
391 if (ret == -ETIMEDOUT)
392 dev_err(gtr_dev->dev,
393 "lane %u (protocol %u, instance %u): PLL lock timeout\n",
394 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
395
396 return ret;
397 }
398
399 /* Get the spread spectrum (SSC) settings for the reference clock rate */
xpsgtr_find_sscs(struct xpsgtr_phy * gtr_phy)400 static const struct xpsgtr_ssc *xpsgtr_find_sscs(struct xpsgtr_phy *gtr_phy)
401 {
402 unsigned long rate;
403 struct clk *clk;
404 unsigned int i;
405
406 clk = gtr_phy->dev->clk[gtr_phy->refclk];
407 rate = clk_get_rate(clk);
408
409 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
410 /* Allow an error of 100 ppm */
411 unsigned long error = ssc_lookup[i].refclk_rate / 10000;
412
413 if (abs(rate - ssc_lookup[i].refclk_rate) < error)
414 return &ssc_lookup[i];
415 }
416
417 dev_err(gtr_phy->dev->dev, "Invalid rate %lu for reference clock %u\n",
418 rate, gtr_phy->refclk);
419
420 return NULL;
421 }
422
423 /* Configure PLL and spread-sprectrum clock. */
xpsgtr_configure_pll(struct xpsgtr_phy * gtr_phy)424 static int xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
425 {
426 const struct xpsgtr_ssc *ssc;
427 u32 step_size;
428
429 ssc = xpsgtr_find_sscs(gtr_phy);
430 if (!ssc)
431 return -EINVAL;
432
433 step_size = ssc->step_size;
434
435 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
436 PLL_FREQ_MASK, ssc->pll_ref_clk);
437
438 /* Enable lane clock sharing, if required */
439 if (gtr_phy->refclk == gtr_phy->lane)
440 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
441 L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL);
442 else
443 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
444 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
445
446 /* SSC step size [7:0] */
447 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
448 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
449
450 /* SSC step size [15:8] */
451 step_size >>= STEP_SIZE_SHIFT;
452 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
453 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
454
455 /* SSC step size [23:16] */
456 step_size >>= STEP_SIZE_SHIFT;
457 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
458 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
459
460 /* SSC steps [7:0] */
461 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
462 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
463
464 /* SSC steps [10:8] */
465 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
466 STEPS_1_MASK,
467 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
468
469 /* SSC step size [24:25] */
470 step_size >>= STEP_SIZE_SHIFT;
471 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
472 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
473 FORCE_STEP_SIZE | FORCE_STEPS);
474
475 return 0;
476 }
477
478 /* Configure the lane protocol. */
xpsgtr_lane_set_protocol(struct xpsgtr_phy * gtr_phy)479 static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
480 {
481 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
482 u8 protocol = gtr_phy->protocol;
483
484 switch (gtr_phy->lane) {
485 case 0:
486 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
487 break;
488 case 1:
489 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
490 protocol << ICM_CFG_SHIFT);
491 break;
492 case 2:
493 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
494 break;
495 case 3:
496 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
497 protocol << ICM_CFG_SHIFT);
498 break;
499 default:
500 /* We already checked 0 <= lane <= 3 */
501 break;
502 }
503 }
504
505 /**
506 * xpsgtr_bypass_scrambler_8b10b - Configure scrambler/encoder behavior
507 * @gtr_phy: pointer to lane context
508 * @bypass: true to enable scrambler/encoder bypass (SATA/SGMII),
509 * false to disable scrambler/encoder bypass (USB3)
510 *
511 * Uses RMW to preserve reserved and unrelated register fields.
512 */
xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy * gtr_phy,bool bypass)513 static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy,
514 bool bypass)
515 {
516 if (bypass) {
517 xpsgtr_clr_set_phy(gtr_phy, L0_TM_DIG_6,
518 L0_TM_DIS_DESCRAMBLE_DECODER,
519 L0_TM_DIS_DESCRAMBLE_DECODER);
520 xpsgtr_clr_set_phy(gtr_phy, L0_TX_DIG_61,
521 L0_TM_DISABLE_SCRAMBLE_ENCODER,
522 L0_TM_DISABLE_SCRAMBLE_ENCODER);
523 } else {
524 xpsgtr_clr_set_phy(gtr_phy, L0_TM_DIG_6,
525 L0_TM_DIS_DESCRAMBLE_DECODER, 0);
526 xpsgtr_clr_set_phy(gtr_phy, L0_TX_DIG_61,
527 L0_TM_DISABLE_SCRAMBLE_ENCODER, 0);
528 }
529 }
530
531 /* DP-specific initialization. */
xpsgtr_phy_init_dp(struct xpsgtr_phy * gtr_phy)532 static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
533 {
534 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
535 L0_TXPMD_TM_45_OVER_DP_MAIN |
536 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
537 L0_TXPMD_TM_45_OVER_DP_POST1 |
538 L0_TXPMD_TM_45_OVER_DP_POST2 |
539 L0_TXPMD_TM_45_ENABLE_DP_POST2);
540 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
541 L0_TX_ANA_TM_118_FORCE_17_0);
542 }
543
544 /* SATA-specific initialization. */
xpsgtr_phy_init_sata(struct xpsgtr_phy * gtr_phy)545 static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
546 {
547 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
548
549 xpsgtr_bypass_scrambler_8b10b(gtr_phy, true);
550
551 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
552 }
553
554 /* SGMII-specific initialization. */
xpsgtr_phy_init_sgmii(struct xpsgtr_phy * gtr_phy)555 static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
556 {
557 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
558 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
559 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
560
561 /* Set SGMII protocol TX and RX bus width to 10 bits. */
562 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
563 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
564
565 xpsgtr_bypass_scrambler_8b10b(gtr_phy, true);
566 }
567
568 /* Configure TX de-emphasis and margining for DP. */
xpsgtr_phy_configure_dp(struct xpsgtr_phy * gtr_phy,unsigned int pre,unsigned int voltage)569 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
570 unsigned int voltage)
571 {
572 static const u8 voltage_swing[4][4] = {
573 { 0x2a, 0x27, 0x24, 0x20 },
574 { 0x27, 0x23, 0x20, 0xff },
575 { 0x24, 0x20, 0xff, 0xff },
576 { 0xff, 0xff, 0xff, 0xff }
577 };
578 static const u8 pre_emphasis[4][4] = {
579 { 0x02, 0x02, 0x02, 0x02 },
580 { 0x01, 0x01, 0x01, 0xff },
581 { 0x00, 0x00, 0xff, 0xff },
582 { 0xff, 0xff, 0xff, 0xff }
583 };
584
585 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
586 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
587 }
588
589 /*
590 * PHY Operations
591 */
592
xpsgtr_phy_init_required(struct xpsgtr_phy * gtr_phy)593 static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
594 {
595 /*
596 * As USB may save the snapshot of the states during hibernation, doing
597 * phy_init() will put the USB controller into reset, resulting in the
598 * losing of the saved snapshot. So try to avoid phy_init() for USB
599 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
600 * shutdown during suspend or when gt lane is changed from current one)
601 */
602 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
603 return false;
604 else
605 return true;
606 }
607
608 /*
609 * There is a functional issue in the GT. The TX termination resistance can be
610 * out of spec due to a issue in the calibration logic. This is the workaround
611 * to fix it, required for XCZU9EG silicon.
612 */
xpsgtr_phy_tx_term_fix(struct xpsgtr_phy * gtr_phy)613 static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
614 {
615 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
616 u32 timeout = TIMEOUT_US;
617 u32 nsw;
618
619 /* Enabling Test Mode control for CMN Rest */
620 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
621
622 /* Set Test Mode reset */
623 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
624
625 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
626 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
627
628 /*
629 * As a part of work around sequence for PMOS calibration fix,
630 * we need to configure any lane ICM_CFG to valid protocol. This
631 * will deassert the CMN_Resetn signal.
632 */
633 xpsgtr_lane_set_protocol(gtr_phy);
634
635 /* Clear Test Mode reset */
636 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
637
638 dev_dbg(gtr_dev->dev, "calibrating...\n");
639
640 do {
641 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
642
643 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
644 break;
645
646 if (!--timeout) {
647 dev_err(gtr_dev->dev, "calibration time out\n");
648 return -ETIMEDOUT;
649 }
650
651 udelay(1);
652 } while (timeout > 0);
653
654 dev_dbg(gtr_dev->dev, "calibration done\n");
655
656 /* Reading NMOS Register Code */
657 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
658
659 /* Set Test Mode reset */
660 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
661
662 /* Writing NMOS register values back [5:3] */
663 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
664
665 /* Writing NMOS register value [2:0] */
666 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
667 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
668 (1 << L3_NSW_PIPE_SHIFT));
669
670 /* Clear Test Mode reset */
671 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
672
673 return 0;
674 }
675
xpsgtr_phy_init(struct phy * phy)676 static int xpsgtr_phy_init(struct phy *phy)
677 {
678 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
679 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
680 int ret;
681
682 mutex_lock(>r_dev->gtr_mutex);
683
684 /* Configure and enable the clock when peripheral phy_init call */
685 ret = clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]);
686 if (ret)
687 goto out;
688
689 /* Skip initialization if not required. */
690 if (!xpsgtr_phy_init_required(gtr_phy))
691 goto out;
692
693 if (gtr_dev->tx_term_fix) {
694 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
695 if (ret < 0)
696 goto out_disable_clk;
697
698 gtr_dev->tx_term_fix = false;
699 }
700
701 /* Enable coarse code saturation limiting logic. */
702 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
703
704 /*
705 * Configure the PLL, the lane protocol, and perform protocol-specific
706 * initialization.
707 */
708 ret = xpsgtr_configure_pll(gtr_phy);
709 if (ret)
710 goto out_disable_clk;
711
712 xpsgtr_lane_set_protocol(gtr_phy);
713
714 switch (gtr_phy->protocol) {
715 case ICM_PROTOCOL_DP:
716 xpsgtr_phy_init_dp(gtr_phy);
717 break;
718
719 case ICM_PROTOCOL_SATA:
720 xpsgtr_phy_init_sata(gtr_phy);
721 break;
722
723 case ICM_PROTOCOL_SGMII:
724 xpsgtr_phy_init_sgmii(gtr_phy);
725 break;
726
727 case ICM_PROTOCOL_USB:
728 xpsgtr_bypass_scrambler_8b10b(gtr_phy, false);
729 break;
730 }
731
732 goto out;
733
734 out_disable_clk:
735 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
736 out:
737 mutex_unlock(>r_dev->gtr_mutex);
738 return ret;
739 }
740
xpsgtr_phy_exit(struct phy * phy)741 static int xpsgtr_phy_exit(struct phy *phy)
742 {
743 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
744 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
745
746 gtr_phy->skip_phy_init = false;
747
748 /* Ensure that disable clock only, which configure for lane */
749 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
750
751 return 0;
752 }
753
xpsgtr_phy_power_on(struct phy * phy)754 static int xpsgtr_phy_power_on(struct phy *phy)
755 {
756 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
757 int ret = 0;
758
759 /* Skip initialization if not required. */
760 if (!xpsgtr_phy_init_required(gtr_phy))
761 return ret;
762 return xpsgtr_wait_pll_lock(phy);
763 }
764
xpsgtr_phy_configure(struct phy * phy,union phy_configure_opts * opts)765 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
766 {
767 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
768
769 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
770 return 0;
771
772 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
773
774 return 0;
775 }
776
777 static const struct phy_ops xpsgtr_phyops = {
778 .init = xpsgtr_phy_init,
779 .exit = xpsgtr_phy_exit,
780 .power_on = xpsgtr_phy_power_on,
781 .configure = xpsgtr_phy_configure,
782 .owner = THIS_MODULE,
783 };
784
785 /*
786 * OF Xlate Support
787 */
788
789 /* Set the lane protocol and instance based on the PHY type and instance number. */
xpsgtr_set_lane_type(struct xpsgtr_phy * gtr_phy,u8 phy_type,unsigned int phy_instance)790 static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
791 unsigned int phy_instance)
792 {
793 unsigned int num_phy_types;
794
795 switch (phy_type) {
796 case PHY_TYPE_SATA:
797 num_phy_types = 2;
798 gtr_phy->protocol = ICM_PROTOCOL_SATA;
799 break;
800 case PHY_TYPE_USB3:
801 num_phy_types = 2;
802 gtr_phy->protocol = ICM_PROTOCOL_USB;
803 break;
804 case PHY_TYPE_DP:
805 num_phy_types = 2;
806 gtr_phy->protocol = ICM_PROTOCOL_DP;
807 break;
808 case PHY_TYPE_PCIE:
809 num_phy_types = 4;
810 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
811 break;
812 case PHY_TYPE_SGMII:
813 num_phy_types = 4;
814 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
815 break;
816 default:
817 return -EINVAL;
818 }
819
820 if (phy_instance >= num_phy_types)
821 return -EINVAL;
822
823 gtr_phy->instance = phy_instance;
824 return 0;
825 }
826
827 /*
828 * Valid combinations of controllers and lanes (Interconnect Matrix). Each
829 * "instance" represents one controller for a lane. For PCIe and DP, the
830 * "instance" is the logical lane in the link. For SATA, USB, and SGMII,
831 * the instance is the index of the controller.
832 *
833 * This information is only used to validate the devicetree reference, and is
834 * not used when programming the hardware.
835 */
836 static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
837 /* PCIe, SATA, USB, DP, SGMII */
838 { 0, 0, 0, 1, 0 }, /* Lane 0 */
839 { 1, 1, 0, 0, 1 }, /* Lane 1 */
840 { 2, 0, 0, 1, 2 }, /* Lane 2 */
841 { 3, 1, 1, 0, 3 }, /* Lane 3 */
842 };
843
844 /* Translate OF phandle and args to PHY instance. */
xpsgtr_xlate(struct device * dev,const struct of_phandle_args * args)845 static struct phy *xpsgtr_xlate(struct device *dev,
846 const struct of_phandle_args *args)
847 {
848 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
849 struct xpsgtr_phy *gtr_phy;
850 unsigned int phy_instance;
851 unsigned int phy_lane;
852 unsigned int phy_type;
853 unsigned int refclk;
854 unsigned int i;
855 int ret;
856
857 if (args->args_count != 4) {
858 dev_err(dev, "Invalid number of cells in 'phy' property\n");
859 return ERR_PTR(-EINVAL);
860 }
861
862 /*
863 * Get the PHY parameters from the OF arguments and derive the lane
864 * type.
865 */
866 phy_lane = args->args[0];
867 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
868 dev_err(dev, "Invalid lane number %u\n", phy_lane);
869 return ERR_PTR(-ENODEV);
870 }
871
872 gtr_phy = >r_dev->phys[phy_lane];
873 phy_type = args->args[1];
874 phy_instance = args->args[2];
875
876 guard(mutex)(>r_phy->phy->mutex);
877 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
878 if (ret < 0) {
879 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
880 return ERR_PTR(ret);
881 }
882
883 refclk = args->args[3];
884 if (refclk >= ARRAY_SIZE(gtr_dev->clk)) {
885 dev_err(dev, "Invalid reference clock number %u\n", refclk);
886 return ERR_PTR(-EINVAL);
887 }
888
889 gtr_phy->refclk = refclk;
890
891 /*
892 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
893 * is allowed to operate on the lane.
894 */
895 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
896 if (icm_matrix[phy_lane][i] == gtr_phy->instance)
897 return gtr_phy->phy;
898 }
899
900 return ERR_PTR(-EINVAL);
901 }
902
903 /*
904 * DebugFS
905 */
906
xpsgtr_status_read(struct seq_file * seq,void * data)907 static int xpsgtr_status_read(struct seq_file *seq, void *data)
908 {
909 struct device *dev = seq->private;
910 struct xpsgtr_phy *gtr_phy = dev_get_drvdata(dev);
911 struct clk *clk;
912 u32 pll_status;
913
914 mutex_lock(>r_phy->phy->mutex);
915 pll_status = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
916 clk = gtr_phy->dev->clk[gtr_phy->refclk];
917
918 seq_printf(seq, "Lane: %u\n", gtr_phy->lane);
919 seq_printf(seq, "Protocol: %s\n",
920 xpsgtr_icm_str[gtr_phy->protocol]);
921 seq_printf(seq, "Instance: %u\n", gtr_phy->instance);
922 seq_printf(seq, "Reference clock: %u (%pC)\n", gtr_phy->refclk, clk);
923 seq_printf(seq, "Reference rate: %lu\n", clk_get_rate(clk));
924 seq_printf(seq, "PLL locked: %s\n",
925 pll_status & PLL_STATUS_LOCKED ? "yes" : "no");
926
927 mutex_unlock(>r_phy->phy->mutex);
928 return 0;
929 }
930
931 /*
932 * Power Management
933 */
934
xpsgtr_runtime_suspend(struct device * dev)935 static int xpsgtr_runtime_suspend(struct device *dev)
936 {
937 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
938
939 /* Save the snapshot ICM_CFG registers. */
940 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
941 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
942
943 xpsgtr_save_lane_regs(gtr_dev);
944
945 return 0;
946 }
947
xpsgtr_runtime_resume(struct device * dev)948 static int xpsgtr_runtime_resume(struct device *dev)
949 {
950 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
951 unsigned int icm_cfg0, icm_cfg1;
952 unsigned int i;
953 bool skip_phy_init;
954
955 xpsgtr_restore_lane_regs(gtr_dev);
956
957 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
958 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
959
960 /* Return if no GT lanes got configured before suspend. */
961 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
962 return 0;
963
964 /* Check if the ICM configurations changed after suspend. */
965 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
966 icm_cfg1 == gtr_dev->saved_icm_cfg1)
967 skip_phy_init = true;
968 else
969 skip_phy_init = false;
970
971 /* Update the skip_phy_init for all gtr_phy instances. */
972 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
973 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
974
975 return 0;
976 }
977
978 static DEFINE_RUNTIME_DEV_PM_OPS(xpsgtr_pm_ops, xpsgtr_runtime_suspend,
979 xpsgtr_runtime_resume, NULL);
980 /*
981 * Probe & Platform Driver
982 */
983
xpsgtr_get_ref_clocks(struct xpsgtr_dev * gtr_dev)984 static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
985 {
986 unsigned int refclk;
987
988 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->clk); ++refclk) {
989 struct clk *clk;
990 char name[8];
991
992 snprintf(name, sizeof(name), "ref%u", refclk);
993 clk = devm_clk_get_optional(gtr_dev->dev, name);
994 if (IS_ERR(clk)) {
995 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
996 "Failed to get ref clock %u\n",
997 refclk);
998 }
999
1000 if (!clk)
1001 continue;
1002
1003 gtr_dev->clk[refclk] = clk;
1004 }
1005
1006 return 0;
1007 }
1008
xpsgtr_probe(struct platform_device * pdev)1009 static int xpsgtr_probe(struct platform_device *pdev)
1010 {
1011 struct device_node *np = pdev->dev.of_node;
1012 struct xpsgtr_dev *gtr_dev;
1013 struct phy_provider *provider;
1014 unsigned int port;
1015 int ret;
1016
1017 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
1018 if (!gtr_dev)
1019 return -ENOMEM;
1020
1021 gtr_dev->dev = &pdev->dev;
1022 platform_set_drvdata(pdev, gtr_dev);
1023
1024 mutex_init(>r_dev->gtr_mutex);
1025
1026 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
1027 gtr_dev->tx_term_fix =
1028 of_property_read_bool(np, "xlnx,tx-termination-fix");
1029
1030 /* Acquire resources. */
1031 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
1032 if (IS_ERR(gtr_dev->serdes))
1033 return PTR_ERR(gtr_dev->serdes);
1034
1035 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
1036 if (IS_ERR(gtr_dev->siou))
1037 return PTR_ERR(gtr_dev->siou);
1038
1039 ret = xpsgtr_get_ref_clocks(gtr_dev);
1040 if (ret)
1041 return ret;
1042
1043 /* Create PHYs. */
1044 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
1045 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
1046 struct phy *phy;
1047
1048 gtr_phy->lane = port;
1049 gtr_phy->dev = gtr_dev;
1050
1051 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
1052 if (IS_ERR(phy)) {
1053 dev_err(&pdev->dev, "failed to create PHY\n");
1054 return PTR_ERR(phy);
1055 }
1056
1057 gtr_phy->phy = phy;
1058 phy_set_drvdata(phy, gtr_phy);
1059 debugfs_create_devm_seqfile(&phy->dev, "status", phy->debugfs,
1060 xpsgtr_status_read);
1061 }
1062
1063 /* Register the PHY provider. */
1064 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
1065 if (IS_ERR(provider)) {
1066 dev_err(&pdev->dev, "registering provider failed\n");
1067 return PTR_ERR(provider);
1068 }
1069
1070 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,
1071 sizeof(save_reg_address),
1072 GFP_KERNEL);
1073 if (!gtr_dev->saved_regs)
1074 return -ENOMEM;
1075
1076 pm_runtime_set_active(gtr_dev->dev);
1077 pm_runtime_enable(gtr_dev->dev);
1078
1079 ret = pm_runtime_resume_and_get(gtr_dev->dev);
1080 if (ret < 0) {
1081 pm_runtime_disable(gtr_dev->dev);
1082 return ret;
1083 }
1084
1085 return 0;
1086 }
1087
xpsgtr_remove(struct platform_device * pdev)1088 static void xpsgtr_remove(struct platform_device *pdev)
1089 {
1090 struct xpsgtr_dev *gtr_dev = platform_get_drvdata(pdev);
1091
1092 pm_runtime_disable(gtr_dev->dev);
1093 pm_runtime_put_noidle(gtr_dev->dev);
1094 pm_runtime_set_suspended(gtr_dev->dev);
1095 }
1096
1097 static const struct of_device_id xpsgtr_of_match[] = {
1098 { .compatible = "xlnx,zynqmp-psgtr", },
1099 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1100 {},
1101 };
1102 MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
1103
1104 static struct platform_driver xpsgtr_driver = {
1105 .probe = xpsgtr_probe,
1106 .remove = xpsgtr_remove,
1107 .driver = {
1108 .name = "xilinx-psgtr",
1109 .of_match_table = xpsgtr_of_match,
1110 .pm = pm_ptr(&xpsgtr_pm_ops),
1111 },
1112 };
1113
1114 module_platform_driver(xpsgtr_driver);
1115
1116 MODULE_AUTHOR("Xilinx Inc.");
1117 MODULE_LICENSE("GPL v2");
1118 MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");
1119