1 // SPDX-License-Identifier: GPL-2.0
2 /* NXP TJA1100 BroadRReach PHY driver
3 *
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */
6 #include <linux/delay.h>
7 #include <linux/ethtool.h>
8 #include <linux/ethtool_netlink.h>
9 #include <linux/kernel.h>
10 #include <linux/mdio.h>
11 #include <linux/mii.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy.h>
15 #include <linux/hwmon.h>
16 #include <linux/bitfield.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_irq.h>
19
20 #define PHY_ID_MASK 0xfffffff0
21 #define PHY_ID_TJA1100 0x0180dc40
22 #define PHY_ID_TJA1101 0x0180dd00
23 #define PHY_ID_TJA1102 0x0180dc80
24 #define PHY_ID_TJA1102S 0x0180dc90
25
26 #define MII_ECTRL 17
27 #define MII_ECTRL_LINK_CONTROL BIT(15)
28 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
29 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
30 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
31 #define MII_ECTRL_POWER_MODE_SLEEP (0xa << 11)
32 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
33 #define MII_ECTRL_CABLE_TEST BIT(5)
34 #define MII_ECTRL_CONFIG_EN BIT(2)
35 #define MII_ECTRL_WAKE_REQUEST BIT(0)
36
37 #define MII_CFG1 18
38 #define MII_CFG1_MASTER_SLAVE BIT(15)
39 #define MII_CFG1_AUTO_OP BIT(14)
40 #define MII_CFG1_INTERFACE_MODE_MASK GENMASK(9, 8)
41 #define MII_CFG1_MII_MODE (0x0 << 8)
42 #define MII_CFG1_RMII_MODE_REFCLK_IN BIT(8)
43 #define MII_CFG1_RMII_MODE_REFCLK_OUT BIT(9)
44 #define MII_CFG1_REVMII_MODE GENMASK(9, 8)
45 #define MII_CFG1_SLEEP_CONFIRM BIT(6)
46 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
47 #define MII_CFG1_LED_MODE_LINKUP 0
48 #define MII_CFG1_LED_ENABLE BIT(3)
49
50 #define MII_CFG2 19
51 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
52 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
53
54 #define MII_INTSRC 21
55 #define MII_INTSRC_LINK_FAIL BIT(10)
56 #define MII_INTSRC_LINK_UP BIT(9)
57 #define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
58 #define MII_INTSRC_UV_ERR BIT(3)
59 #define MII_INTSRC_TEMP_ERR BIT(1)
60
61 #define MII_INTEN 22
62 #define MII_INTEN_LINK_FAIL BIT(10)
63 #define MII_INTEN_LINK_UP BIT(9)
64 #define MII_INTEN_UV_ERR BIT(3)
65 #define MII_INTEN_TEMP_ERR BIT(1)
66
67 #define MII_COMMSTAT 23
68 #define MII_COMMSTAT_LINK_UP BIT(15)
69 #define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
70 #define MII_COMMSTAT_SQI_MAX 7
71
72 #define MII_GENSTAT 24
73 #define MII_GENSTAT_PLL_LOCKED BIT(14)
74
75 #define MII_EXTSTAT 25
76 #define MII_EXTSTAT_SHORT_DETECT BIT(8)
77 #define MII_EXTSTAT_OPEN_DETECT BIT(7)
78 #define MII_EXTSTAT_POLARITY_DETECT BIT(6)
79
80 #define MII_COMMCFG 27
81 #define MII_COMMCFG_AUTO_OP BIT(15)
82
83 #define MII_CFG3 28
84 #define MII_CFG3_PHY_EN BIT(0)
85
86 /* Configure REF_CLK as input in RMII mode */
87 #define TJA110X_RMII_MODE_REFCLK_IN BIT(0)
88
89 struct tja11xx_priv {
90 struct phy_device *phydev;
91 struct work_struct phy_register_work;
92 u32 flags;
93 };
94
95 struct tja11xx_phy_stats {
96 const char *string;
97 u8 reg;
98 u8 off;
99 u16 mask;
100 };
101
102 static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
103 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
104 { "phy_polarity_detect", 25, 6, BIT(6) },
105 { "phy_open_detect", 25, 7, BIT(7) },
106 { "phy_short_detect", 25, 8, BIT(8) },
107 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
108 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
109 };
110
tja11xx_check(struct phy_device * phydev,u8 reg,u16 mask,u16 set)111 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
112 {
113 int val;
114
115 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
116 150, 30000, false);
117 }
118
phy_modify_check(struct phy_device * phydev,u8 reg,u16 mask,u16 set)119 static int phy_modify_check(struct phy_device *phydev, u8 reg,
120 u16 mask, u16 set)
121 {
122 int ret;
123
124 ret = phy_modify(phydev, reg, mask, set);
125 if (ret)
126 return ret;
127
128 return tja11xx_check(phydev, reg, mask, set);
129 }
130
tja11xx_enable_reg_write(struct phy_device * phydev)131 static int tja11xx_enable_reg_write(struct phy_device *phydev)
132 {
133 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
134 }
135
tja11xx_enable_link_control(struct phy_device * phydev)136 static int tja11xx_enable_link_control(struct phy_device *phydev)
137 {
138 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
139 }
140
tja11xx_disable_link_control(struct phy_device * phydev)141 static int tja11xx_disable_link_control(struct phy_device *phydev)
142 {
143 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
144 }
145
tja11xx_wakeup(struct phy_device * phydev)146 static int tja11xx_wakeup(struct phy_device *phydev)
147 {
148 int ret;
149
150 ret = phy_read(phydev, MII_ECTRL);
151 if (ret < 0)
152 return ret;
153
154 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
155 case MII_ECTRL_POWER_MODE_NO_CHANGE:
156 break;
157 case MII_ECTRL_POWER_MODE_NORMAL:
158 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
159 if (ret)
160 return ret;
161
162 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
163 if (ret)
164 return ret;
165 break;
166 case MII_ECTRL_POWER_MODE_STANDBY:
167 ret = phy_modify_check(phydev, MII_ECTRL,
168 MII_ECTRL_POWER_MODE_MASK,
169 MII_ECTRL_POWER_MODE_STANDBY);
170 if (ret)
171 return ret;
172
173 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
174 MII_ECTRL_POWER_MODE_NORMAL);
175 if (ret)
176 return ret;
177
178 ret = phy_modify_check(phydev, MII_GENSTAT,
179 MII_GENSTAT_PLL_LOCKED,
180 MII_GENSTAT_PLL_LOCKED);
181 if (ret)
182 return ret;
183
184 return tja11xx_enable_link_control(phydev);
185 case MII_ECTRL_POWER_MODE_SLEEP:
186 switch (phydev->phy_id & PHY_ID_MASK) {
187 case PHY_ID_TJA1102S:
188 /* Enable PHY, maybe it is disabled due to pin strapping */
189 return phy_set_bits(phydev, MII_CFG3, MII_CFG3_PHY_EN);
190 default:
191 return 0;
192 }
193 default:
194 break;
195 }
196
197 return 0;
198 }
199
tja11xx_soft_reset(struct phy_device * phydev)200 static int tja11xx_soft_reset(struct phy_device *phydev)
201 {
202 int ret;
203
204 ret = tja11xx_enable_reg_write(phydev);
205 if (ret)
206 return ret;
207
208 return genphy_soft_reset(phydev);
209 }
210
tja11xx_config_aneg_cable_test(struct phy_device * phydev)211 static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
212 {
213 bool finished = false;
214 int ret;
215
216 if (phydev->link)
217 return 0;
218
219 if (!phydev->drv->cable_test_start ||
220 !phydev->drv->cable_test_get_status)
221 return 0;
222
223 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
224 if (ret)
225 return ret;
226
227 ret = phydev->drv->cable_test_start(phydev);
228 if (ret)
229 return ret;
230
231 /* According to the documentation this test takes 100 usec */
232 usleep_range(100, 200);
233
234 ret = phydev->drv->cable_test_get_status(phydev, &finished);
235 if (ret)
236 return ret;
237
238 if (finished)
239 ethnl_cable_test_finished(phydev);
240
241 return 0;
242 }
243
tja11xx_config_aneg(struct phy_device * phydev)244 static int tja11xx_config_aneg(struct phy_device *phydev)
245 {
246 int ret, changed = 0;
247 u16 ctl = 0;
248
249 switch (phydev->master_slave_set) {
250 case MASTER_SLAVE_CFG_MASTER_FORCE:
251 ctl |= MII_CFG1_MASTER_SLAVE;
252 break;
253 case MASTER_SLAVE_CFG_SLAVE_FORCE:
254 break;
255 case MASTER_SLAVE_CFG_UNKNOWN:
256 case MASTER_SLAVE_CFG_UNSUPPORTED:
257 goto do_test;
258 default:
259 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
260 return -ENOTSUPP;
261 }
262
263 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
264 if (changed < 0)
265 return changed;
266
267 do_test:
268 ret = tja11xx_config_aneg_cable_test(phydev);
269 if (ret)
270 return ret;
271
272 return __genphy_config_aneg(phydev, changed);
273 }
274
tja11xx_get_interface_mode(struct phy_device * phydev)275 static int tja11xx_get_interface_mode(struct phy_device *phydev)
276 {
277 struct tja11xx_priv *priv = phydev->priv;
278 int mii_mode;
279
280 switch (phydev->interface) {
281 case PHY_INTERFACE_MODE_MII:
282 mii_mode = MII_CFG1_MII_MODE;
283 break;
284 case PHY_INTERFACE_MODE_REVMII:
285 mii_mode = MII_CFG1_REVMII_MODE;
286 break;
287 case PHY_INTERFACE_MODE_RMII:
288 if (priv->flags & TJA110X_RMII_MODE_REFCLK_IN)
289 mii_mode = MII_CFG1_RMII_MODE_REFCLK_IN;
290 else
291 mii_mode = MII_CFG1_RMII_MODE_REFCLK_OUT;
292 break;
293 default:
294 return -EINVAL;
295 }
296
297 return mii_mode;
298 }
299
tja11xx_config_init(struct phy_device * phydev)300 static int tja11xx_config_init(struct phy_device *phydev)
301 {
302 u16 reg_mask, reg_val;
303 int ret;
304
305 ret = tja11xx_enable_reg_write(phydev);
306 if (ret)
307 return ret;
308
309 phydev->autoneg = AUTONEG_DISABLE;
310 phydev->speed = SPEED_100;
311 phydev->duplex = DUPLEX_FULL;
312
313 switch (phydev->phy_id & PHY_ID_MASK) {
314 case PHY_ID_TJA1100:
315 reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
316 MII_CFG1_LED_ENABLE;
317 reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
318 MII_CFG1_LED_ENABLE;
319
320 reg_mask |= MII_CFG1_INTERFACE_MODE_MASK;
321 ret = tja11xx_get_interface_mode(phydev);
322 if (ret < 0)
323 return ret;
324
325 reg_val |= (ret & 0xffff);
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
327 if (ret)
328 return ret;
329 break;
330 case PHY_ID_TJA1102S:
331 case PHY_ID_TJA1101:
332 reg_mask = MII_CFG1_INTERFACE_MODE_MASK;
333 ret = tja11xx_get_interface_mode(phydev);
334 if (ret < 0)
335 return ret;
336
337 reg_val = ret & 0xffff;
338 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
339 if (ret)
340 return ret;
341 fallthrough;
342 case PHY_ID_TJA1102:
343 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
344 if (ret)
345 return ret;
346 break;
347 default:
348 return -EINVAL;
349 }
350
351 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
352 if (ret)
353 return ret;
354
355 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
356 MII_CFG2_SLEEP_REQUEST_TO_16MS);
357 if (ret)
358 return ret;
359
360 ret = tja11xx_wakeup(phydev);
361 if (ret < 0)
362 return ret;
363
364 /* ACK interrupts by reading the status register */
365 ret = phy_read(phydev, MII_INTSRC);
366 if (ret < 0)
367 return ret;
368
369 return 0;
370 }
371
tja11xx_read_status(struct phy_device * phydev)372 static int tja11xx_read_status(struct phy_device *phydev)
373 {
374 int ret;
375
376 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
377 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
378
379 ret = genphy_update_link(phydev);
380 if (ret)
381 return ret;
382
383 ret = phy_read(phydev, MII_CFG1);
384 if (ret < 0)
385 return ret;
386
387 if (ret & MII_CFG1_MASTER_SLAVE)
388 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
389 else
390 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
391
392 if (phydev->link) {
393 ret = phy_read(phydev, MII_COMMSTAT);
394 if (ret < 0)
395 return ret;
396
397 if (!(ret & MII_COMMSTAT_LINK_UP))
398 phydev->link = 0;
399 }
400
401 return 0;
402 }
403
tja11xx_get_sqi(struct phy_device * phydev)404 static int tja11xx_get_sqi(struct phy_device *phydev)
405 {
406 int ret;
407
408 ret = phy_read(phydev, MII_COMMSTAT);
409 if (ret < 0)
410 return ret;
411
412 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
413 }
414
tja11xx_get_sqi_max(struct phy_device * phydev)415 static int tja11xx_get_sqi_max(struct phy_device *phydev)
416 {
417 return MII_COMMSTAT_SQI_MAX;
418 }
419
tja11xx_get_sset_count(struct phy_device * phydev)420 static int tja11xx_get_sset_count(struct phy_device *phydev)
421 {
422 return ARRAY_SIZE(tja11xx_hw_stats);
423 }
424
tja11xx_get_strings(struct phy_device * phydev,u8 * data)425 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
426 {
427 int i;
428
429 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++)
430 ethtool_puts(&data, tja11xx_hw_stats[i].string);
431 }
432
tja11xx_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)433 static void tja11xx_get_stats(struct phy_device *phydev,
434 struct ethtool_stats *stats, u64 *data)
435 {
436 int i, ret;
437
438 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
439 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
440 if (ret < 0)
441 data[i] = U64_MAX;
442 else {
443 data[i] = ret & tja11xx_hw_stats[i].mask;
444 data[i] >>= tja11xx_hw_stats[i].off;
445 }
446 }
447 }
448
tja11xx_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)449 static int tja11xx_hwmon_read(struct device *dev,
450 enum hwmon_sensor_types type,
451 u32 attr, int channel, long *value)
452 {
453 struct phy_device *phydev = dev_get_drvdata(dev);
454 int ret;
455
456 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
457 ret = phy_read(phydev, MII_INTSRC);
458 if (ret < 0)
459 return ret;
460
461 *value = !!(ret & MII_INTSRC_TEMP_ERR);
462 return 0;
463 }
464
465 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
466 ret = phy_read(phydev, MII_INTSRC);
467 if (ret < 0)
468 return ret;
469
470 *value = !!(ret & MII_INTSRC_UV_ERR);
471 return 0;
472 }
473
474 return -EOPNOTSUPP;
475 }
476
tja11xx_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)477 static umode_t tja11xx_hwmon_is_visible(const void *data,
478 enum hwmon_sensor_types type,
479 u32 attr, int channel)
480 {
481 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
482 return 0444;
483
484 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
485 return 0444;
486
487 return 0;
488 }
489
490 static const struct hwmon_channel_info * const tja11xx_hwmon_info[] = {
491 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
492 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
493 NULL
494 };
495
496 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
497 .is_visible = tja11xx_hwmon_is_visible,
498 .read = tja11xx_hwmon_read,
499 };
500
501 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
502 .ops = &tja11xx_hwmon_hwmon_ops,
503 .info = tja11xx_hwmon_info,
504 };
505
tja11xx_hwmon_register(struct phy_device * phydev,struct tja11xx_priv * priv)506 static int tja11xx_hwmon_register(struct phy_device *phydev,
507 struct tja11xx_priv *priv)
508 {
509 struct device *hdev, *dev = &phydev->mdio.dev;
510
511 hdev = devm_hwmon_device_register_with_info(dev, NULL, phydev,
512 &tja11xx_hwmon_chip_info,
513 NULL);
514 return PTR_ERR_OR_ZERO(hdev);
515 }
516
tja11xx_parse_dt(struct phy_device * phydev)517 static int tja11xx_parse_dt(struct phy_device *phydev)
518 {
519 struct device_node *node = phydev->mdio.dev.of_node;
520 struct tja11xx_priv *priv = phydev->priv;
521
522 if (!IS_ENABLED(CONFIG_OF_MDIO))
523 return 0;
524
525 if (of_property_read_bool(node, "nxp,rmii-refclk-in"))
526 priv->flags |= TJA110X_RMII_MODE_REFCLK_IN;
527
528 return 0;
529 }
530
tja11xx_probe(struct phy_device * phydev)531 static int tja11xx_probe(struct phy_device *phydev)
532 {
533 struct device *dev = &phydev->mdio.dev;
534 struct tja11xx_priv *priv;
535 int ret;
536
537 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
538 if (!priv)
539 return -ENOMEM;
540
541 priv->phydev = phydev;
542 phydev->priv = priv;
543
544 ret = tja11xx_parse_dt(phydev);
545 if (ret)
546 return ret;
547
548 return tja11xx_hwmon_register(phydev, priv);
549 }
550
tja1102_p1_register(struct work_struct * work)551 static void tja1102_p1_register(struct work_struct *work)
552 {
553 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
554 phy_register_work);
555 struct phy_device *phydev_phy0 = priv->phydev;
556 struct mii_bus *bus = phydev_phy0->mdio.bus;
557 struct device *dev = &phydev_phy0->mdio.dev;
558 struct device_node *np = dev->of_node;
559 struct device_node *child;
560 int ret;
561
562 for_each_available_child_of_node(np, child) {
563 struct phy_device *phy;
564 int addr;
565
566 addr = of_mdio_parse_addr(dev, child);
567 if (addr < 0) {
568 dev_err(dev, "Can't parse addr\n");
569 continue;
570 } else if (addr != phydev_phy0->mdio.addr + 1) {
571 /* Currently we care only about double PHY chip TJA1102.
572 * If some day NXP will decide to bring chips with more
573 * PHYs, this logic should be reworked.
574 */
575 dev_err(dev, "Unexpected address. Should be: %i\n",
576 phydev_phy0->mdio.addr + 1);
577 continue;
578 }
579
580 if (mdiobus_is_registered_device(bus, addr)) {
581 dev_err(dev, "device is already registered\n");
582 continue;
583 }
584
585 /* Real PHY ID of Port 1 is 0 */
586 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
587 if (IS_ERR(phy)) {
588 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
589 addr);
590 continue;
591 }
592
593 /* Overwrite parent device. phy_device_create() set parent to
594 * the mii_bus->dev, which is not correct in case.
595 */
596 phy->mdio.dev.parent = dev;
597
598 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
599 if (ret) {
600 /* All resources needed for Port 1 should be already
601 * available for Port 0. Both ports use the same
602 * interrupt line, so -EPROBE_DEFER would make no sense
603 * here.
604 */
605 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
606 ret);
607 phy_device_free(phy);
608 }
609 }
610 }
611
tja1102_p0_probe(struct phy_device * phydev)612 static int tja1102_p0_probe(struct phy_device *phydev)
613 {
614 struct device *dev = &phydev->mdio.dev;
615 struct tja11xx_priv *priv;
616 int ret;
617
618 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
619 if (!priv)
620 return -ENOMEM;
621
622 priv->phydev = phydev;
623 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
624
625 ret = tja11xx_hwmon_register(phydev, priv);
626 if (ret)
627 return ret;
628
629 schedule_work(&priv->phy_register_work);
630
631 return 0;
632 }
633
tja1102_match_phy_device(struct phy_device * phydev,bool port0)634 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
635 {
636 int ret;
637
638 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
639 return 0;
640
641 ret = phy_read(phydev, MII_PHYSID2);
642 if (ret < 0)
643 return ret;
644
645 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
646 * and undervoltage alarms.
647 */
648 if (port0)
649 return ret ? 1 : 0;
650
651 return !ret;
652 }
653
tja1102_p0_match_phy_device(struct phy_device * phydev)654 static int tja1102_p0_match_phy_device(struct phy_device *phydev)
655 {
656 return tja1102_match_phy_device(phydev, true);
657 }
658
tja1102_p1_match_phy_device(struct phy_device * phydev)659 static int tja1102_p1_match_phy_device(struct phy_device *phydev)
660 {
661 return tja1102_match_phy_device(phydev, false);
662 }
663
tja11xx_ack_interrupt(struct phy_device * phydev)664 static int tja11xx_ack_interrupt(struct phy_device *phydev)
665 {
666 int ret;
667
668 ret = phy_read(phydev, MII_INTSRC);
669
670 return (ret < 0) ? ret : 0;
671 }
672
tja11xx_config_intr(struct phy_device * phydev)673 static int tja11xx_config_intr(struct phy_device *phydev)
674 {
675 int value = 0;
676 int err;
677
678 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
679 err = tja11xx_ack_interrupt(phydev);
680 if (err)
681 return err;
682
683 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP |
684 MII_INTEN_UV_ERR | MII_INTEN_TEMP_ERR;
685 err = phy_write(phydev, MII_INTEN, value);
686 } else {
687 err = phy_write(phydev, MII_INTEN, value);
688 if (err)
689 return err;
690
691 err = tja11xx_ack_interrupt(phydev);
692 }
693
694 return err;
695 }
696
tja11xx_handle_interrupt(struct phy_device * phydev)697 static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
698 {
699 struct device *dev = &phydev->mdio.dev;
700 int irq_status;
701
702 irq_status = phy_read(phydev, MII_INTSRC);
703 if (irq_status < 0) {
704 phy_error(phydev);
705 return IRQ_NONE;
706 }
707
708 if (irq_status & MII_INTSRC_TEMP_ERR)
709 dev_warn(dev, "Overtemperature error detected (temp > 155C°).\n");
710 if (irq_status & MII_INTSRC_UV_ERR)
711 dev_warn(dev, "Undervoltage error detected.\n");
712
713 if (!(irq_status & MII_INTSRC_MASK))
714 return IRQ_NONE;
715
716 phy_trigger_machine(phydev);
717
718 return IRQ_HANDLED;
719 }
720
tja11xx_cable_test_start(struct phy_device * phydev)721 static int tja11xx_cable_test_start(struct phy_device *phydev)
722 {
723 int ret;
724
725 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
726 if (ret)
727 return ret;
728
729 ret = tja11xx_wakeup(phydev);
730 if (ret < 0)
731 return ret;
732
733 ret = tja11xx_disable_link_control(phydev);
734 if (ret < 0)
735 return ret;
736
737 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
738 }
739
740 /*
741 * | BI_DA+ | BI_DA- | Result
742 * | open | open | open
743 * | + short to - | - short to + | short
744 * | short to Vdd | open | open
745 * | open | shot to Vdd | open
746 * | short to Vdd | short to Vdd | short
747 * | shot to GND | open | open
748 * | open | shot to GND | open
749 * | short to GND | shot to GND | short
750 * | connected to active link partner (master) | shot and open
751 */
tja11xx_cable_test_report_trans(u32 result)752 static int tja11xx_cable_test_report_trans(u32 result)
753 {
754 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
755
756 if ((result & mask) == mask) {
757 /* connected to active link partner (master) */
758 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
759 } else if ((result & mask) == 0) {
760 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
761 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
762 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
763 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
764 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
765 } else {
766 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
767 }
768 }
769
tja11xx_cable_test_report(struct phy_device * phydev)770 static int tja11xx_cable_test_report(struct phy_device *phydev)
771 {
772 int ret;
773
774 ret = phy_read(phydev, MII_EXTSTAT);
775 if (ret < 0)
776 return ret;
777
778 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
779 tja11xx_cable_test_report_trans(ret));
780
781 return 0;
782 }
783
tja11xx_cable_test_get_status(struct phy_device * phydev,bool * finished)784 static int tja11xx_cable_test_get_status(struct phy_device *phydev,
785 bool *finished)
786 {
787 int ret;
788
789 *finished = false;
790
791 ret = phy_read(phydev, MII_ECTRL);
792 if (ret < 0)
793 return ret;
794
795 if (!(ret & MII_ECTRL_CABLE_TEST)) {
796 *finished = true;
797
798 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
799 if (ret)
800 return ret;
801
802 return tja11xx_cable_test_report(phydev);
803 }
804
805 return 0;
806 }
807
808 static struct phy_driver tja11xx_driver[] = {
809 {
810 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
811 .name = "NXP TJA1100",
812 .features = PHY_BASIC_T1_FEATURES,
813 .probe = tja11xx_probe,
814 .soft_reset = tja11xx_soft_reset,
815 .config_aneg = tja11xx_config_aneg,
816 .config_init = tja11xx_config_init,
817 .read_status = tja11xx_read_status,
818 .get_sqi = tja11xx_get_sqi,
819 .get_sqi_max = tja11xx_get_sqi_max,
820 .suspend = genphy_suspend,
821 .resume = genphy_resume,
822 .set_loopback = genphy_loopback,
823 /* Statistics */
824 .get_sset_count = tja11xx_get_sset_count,
825 .get_strings = tja11xx_get_strings,
826 .get_stats = tja11xx_get_stats,
827 }, {
828 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
829 .name = "NXP TJA1101",
830 .features = PHY_BASIC_T1_FEATURES,
831 .probe = tja11xx_probe,
832 .soft_reset = tja11xx_soft_reset,
833 .config_aneg = tja11xx_config_aneg,
834 .config_init = tja11xx_config_init,
835 .read_status = tja11xx_read_status,
836 .get_sqi = tja11xx_get_sqi,
837 .get_sqi_max = tja11xx_get_sqi_max,
838 .suspend = genphy_suspend,
839 .resume = genphy_resume,
840 .set_loopback = genphy_loopback,
841 /* Statistics */
842 .get_sset_count = tja11xx_get_sset_count,
843 .get_strings = tja11xx_get_strings,
844 .get_stats = tja11xx_get_stats,
845 }, {
846 .name = "NXP TJA1102 Port 0",
847 .features = PHY_BASIC_T1_FEATURES,
848 .flags = PHY_POLL_CABLE_TEST,
849 .probe = tja1102_p0_probe,
850 .soft_reset = tja11xx_soft_reset,
851 .config_aneg = tja11xx_config_aneg,
852 .config_init = tja11xx_config_init,
853 .read_status = tja11xx_read_status,
854 .get_sqi = tja11xx_get_sqi,
855 .get_sqi_max = tja11xx_get_sqi_max,
856 .match_phy_device = tja1102_p0_match_phy_device,
857 .suspend = genphy_suspend,
858 .resume = genphy_resume,
859 .set_loopback = genphy_loopback,
860 /* Statistics */
861 .get_sset_count = tja11xx_get_sset_count,
862 .get_strings = tja11xx_get_strings,
863 .get_stats = tja11xx_get_stats,
864 .config_intr = tja11xx_config_intr,
865 .handle_interrupt = tja11xx_handle_interrupt,
866 .cable_test_start = tja11xx_cable_test_start,
867 .cable_test_get_status = tja11xx_cable_test_get_status,
868 }, {
869 .name = "NXP TJA1102 Port 1",
870 .features = PHY_BASIC_T1_FEATURES,
871 .flags = PHY_POLL_CABLE_TEST,
872 /* currently no probe for Port 1 is need */
873 .soft_reset = tja11xx_soft_reset,
874 .config_aneg = tja11xx_config_aneg,
875 .config_init = tja11xx_config_init,
876 .read_status = tja11xx_read_status,
877 .get_sqi = tja11xx_get_sqi,
878 .get_sqi_max = tja11xx_get_sqi_max,
879 .match_phy_device = tja1102_p1_match_phy_device,
880 .suspend = genphy_suspend,
881 .resume = genphy_resume,
882 .set_loopback = genphy_loopback,
883 /* Statistics */
884 .get_sset_count = tja11xx_get_sset_count,
885 .get_strings = tja11xx_get_strings,
886 .get_stats = tja11xx_get_stats,
887 .config_intr = tja11xx_config_intr,
888 .handle_interrupt = tja11xx_handle_interrupt,
889 .cable_test_start = tja11xx_cable_test_start,
890 .cable_test_get_status = tja11xx_cable_test_get_status,
891 }, {
892 PHY_ID_MATCH_MODEL(PHY_ID_TJA1102S),
893 .name = "NXP TJA1102S",
894 .features = PHY_BASIC_T1_FEATURES,
895 .flags = PHY_POLL_CABLE_TEST,
896 .probe = tja11xx_probe,
897 .soft_reset = tja11xx_soft_reset,
898 .config_aneg = tja11xx_config_aneg,
899 .config_init = tja11xx_config_init,
900 .read_status = tja11xx_read_status,
901 .get_sqi = tja11xx_get_sqi,
902 .get_sqi_max = tja11xx_get_sqi_max,
903 .suspend = genphy_suspend,
904 .resume = genphy_resume,
905 .set_loopback = genphy_loopback,
906 /* Statistics */
907 .get_sset_count = tja11xx_get_sset_count,
908 .get_strings = tja11xx_get_strings,
909 .get_stats = tja11xx_get_stats,
910 .config_intr = tja11xx_config_intr,
911 .handle_interrupt = tja11xx_handle_interrupt,
912 .cable_test_start = tja11xx_cable_test_start,
913 .cable_test_get_status = tja11xx_cable_test_get_status,
914 }
915 };
916
917 module_phy_driver(tja11xx_driver);
918
919 static const struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
920 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
921 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
922 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
923 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102S) },
924 { }
925 };
926
927 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
928
929 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
930 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
931 MODULE_LICENSE("GPL");
932