1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CPUTYPE_H
6 #define __ASM_CPUTYPE_H
7
8 #define INVALID_HWID ULONG_MAX
9
10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14 #define MPIDR_LEVEL_BITS_SHIFT 3
15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18 #define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24 #define MIDR_REVISION_MASK 0xf
25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26 #define MIDR_PARTNUM_SHIFT 4
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28 #define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30 #define MIDR_ARCHITECTURE_SHIFT 16
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32 #define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34 #define MIDR_VARIANT_SHIFT 20
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36 #define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38 #define MIDR_IMPLEMENTOR_SHIFT 24
39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
40 #define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43 #define MIDR_CPU_MODEL(imp, partnum) \
44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48 #define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54 #define ARM_CPU_IMP_ARM 0x41
55 #define ARM_CPU_IMP_APM 0x50
56 #define ARM_CPU_IMP_CAVIUM 0x43
57 #define ARM_CPU_IMP_BRCM 0x42
58 #define ARM_CPU_IMP_QCOM 0x51
59 #define ARM_CPU_IMP_NVIDIA 0x4E
60 #define ARM_CPU_IMP_FUJITSU 0x46
61 #define ARM_CPU_IMP_HISI 0x48
62 #define ARM_CPU_IMP_APPLE 0x61
63 #define ARM_CPU_IMP_AMPERE 0xC0
64 #define ARM_CPU_IMP_MICROSOFT 0x6D
65
66 #define ARM_CPU_PART_AEM_V8 0xD0F
67 #define ARM_CPU_PART_FOUNDATION 0xD00
68 #define ARM_CPU_PART_CORTEX_A57 0xD07
69 #define ARM_CPU_PART_CORTEX_A72 0xD08
70 #define ARM_CPU_PART_CORTEX_A53 0xD03
71 #define ARM_CPU_PART_CORTEX_A73 0xD09
72 #define ARM_CPU_PART_CORTEX_A75 0xD0A
73 #define ARM_CPU_PART_CORTEX_A35 0xD04
74 #define ARM_CPU_PART_CORTEX_A55 0xD05
75 #define ARM_CPU_PART_CORTEX_A76 0xD0B
76 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
77 #define ARM_CPU_PART_CORTEX_A77 0xD0D
78 #define ARM_CPU_PART_CORTEX_A76AE 0xD0E
79 #define ARM_CPU_PART_NEOVERSE_V1 0xD40
80 #define ARM_CPU_PART_CORTEX_A78 0xD41
81 #define ARM_CPU_PART_CORTEX_A78AE 0xD42
82 #define ARM_CPU_PART_CORTEX_X1 0xD44
83 #define ARM_CPU_PART_CORTEX_A510 0xD46
84 #define ARM_CPU_PART_CORTEX_X1C 0xD4C
85 #define ARM_CPU_PART_CORTEX_A520 0xD80
86 #define ARM_CPU_PART_CORTEX_A710 0xD47
87 #define ARM_CPU_PART_CORTEX_A715 0xD4D
88 #define ARM_CPU_PART_CORTEX_X2 0xD48
89 #define ARM_CPU_PART_NEOVERSE_N2 0xD49
90 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
91 #define ARM_CPU_PART_CORTEX_X1C 0xD4C
92 #define ARM_CPU_PART_CORTEX_X3 0xD4E
93 #define ARM_CPU_PART_NEOVERSE_V2 0xD4F
94 #define ARM_CPU_PART_CORTEX_A720 0xD81
95 #define ARM_CPU_PART_CORTEX_X4 0xD82
96 #define ARM_CPU_PART_NEOVERSE_V3 0xD84
97 #define ARM_CPU_PART_CORTEX_X925 0xD85
98 #define ARM_CPU_PART_CORTEX_A725 0xD87
99 #define ARM_CPU_PART_CORTEX_A720AE 0xD89
100 #define ARM_CPU_PART_NEOVERSE_N3 0xD8E
101
102 #define APM_CPU_PART_XGENE 0x000
103 #define APM_CPU_VAR_POTENZA 0x00
104
105 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
106 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
107 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
108 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
109 /* OcteonTx2 series */
110 #define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
111 #define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
112 #define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
113 #define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
114 #define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
115 #define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
116
117 #define BRCM_CPU_PART_BRAHMA_B53 0x100
118 #define BRCM_CPU_PART_VULCAN 0x516
119
120 #define QCOM_CPU_PART_FALKOR_V1 0x800
121 #define QCOM_CPU_PART_FALKOR 0xC00
122 #define QCOM_CPU_PART_KRYO 0x200
123 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
124 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
125 #define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802
126 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
127 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
128 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
129 #define QCOM_CPU_PART_ORYON_X1 0x001
130
131 #define NVIDIA_CPU_PART_DENVER 0x003
132 #define NVIDIA_CPU_PART_CARMEL 0x004
133
134 #define FUJITSU_CPU_PART_A64FX 0x001
135
136 #define HISI_CPU_PART_TSV110 0xD01
137 #define HISI_CPU_PART_HIP09 0xD02
138 #define HISI_CPU_PART_HIP12 0xD06
139
140 #define APPLE_CPU_PART_M1_ICESTORM 0x022
141 #define APPLE_CPU_PART_M1_FIRESTORM 0x023
142 #define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
143 #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
144 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
145 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
146 #define APPLE_CPU_PART_M2_BLIZZARD 0x032
147 #define APPLE_CPU_PART_M2_AVALANCHE 0x033
148 #define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
149 #define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
150 #define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
151 #define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
152
153 #define AMPERE_CPU_PART_AMPERE1 0xAC3
154 #define AMPERE_CPU_PART_AMPERE1A 0xAC4
155
156 #define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
157
158 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
159 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
160 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
161 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
162 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
163 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
164 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
165 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
166 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
167 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
168 #define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76AE)
169 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
170 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
171 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
172 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
173 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
174 #define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
175 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
176 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
177 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
178 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
179 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
180 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
181 #define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
182 #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
183 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
184 #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
185 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
186 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
187 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
188 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
189 #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
190 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
191 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
192 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
193 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
194 #define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
195 #define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
196 #define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
197 #define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
198 #define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
199 #define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
200 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
201 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
202 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
203 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
204 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
205 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
206 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
207 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
208 #define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD)
209 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
210 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
211 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
212 #define MIDR_QCOM_ORYON_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_ORYON_X1)
213
214 /*
215 * NOTES:
216 * - Qualcomm Kryo 5XX Prime / Gold ID themselves as MIDR_CORTEX_A77
217 * - Qualcomm Kryo 5XX Silver IDs itself as MIDR_QCOM_KRYO_4XX_SILVER
218 * - Qualcomm Kryo 6XX Prime IDs itself as MIDR_CORTEX_X1
219 * - Qualcomm Kryo 6XX Gold IDs itself as ARM_CPU_PART_CORTEX_A78
220 * - Qualcomm Kryo 6XX Silver IDs itself as MIDR_CORTEX_A55
221 */
222
223 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
224 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
225 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
226 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
227 #define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
228 #define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)
229 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
230 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
231 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
232 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
233 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
234 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
235 #define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
236 #define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
237 #define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
238 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
239 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
240 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
241 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
242 #define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
243 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
244
245 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
246 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
247 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
248 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
249
250 #ifndef __ASSEMBLER__
251
252 #include <asm/sysreg.h>
253
254 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
255
256 /*
257 * Represent a range of MIDR values for a given CPU model and a
258 * range of variant/revision values.
259 *
260 * @model - CPU model as defined by MIDR_CPU_MODEL
261 * @rv_min - Minimum value for the revision/variant as defined by
262 * MIDR_CPU_VAR_REV
263 * @rv_max - Maximum value for the variant/revision for the range.
264 */
265 struct midr_range {
266 u32 model;
267 u32 rv_min;
268 u32 rv_max;
269 };
270
271 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
272 { \
273 .model = m, \
274 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
275 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
276 }
277
278 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
279 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
280 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
281
midr_is_cpu_model_range(u32 midr,u32 model,u32 rv_min,u32 rv_max)282 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
283 u32 rv_max)
284 {
285 u32 _model = midr & MIDR_CPU_MODEL_MASK;
286 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
287
288 return _model == model && rv >= rv_min && rv <= rv_max;
289 }
290
is_midr_in_range(u32 midr,struct midr_range const * range)291 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
292 {
293 return midr_is_cpu_model_range(midr, range->model,
294 range->rv_min, range->rv_max);
295 }
296
297 static inline bool
is_midr_in_range_list(u32 midr,struct midr_range const * ranges)298 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
299 {
300 while (ranges->model)
301 if (is_midr_in_range(midr, ranges++))
302 return true;
303 return false;
304 }
305
306 /*
307 * The CPU ID never changes at run time, so we might as well tell the
308 * compiler that it's constant. Use this function to read the CPU ID
309 * rather than directly reading processor_id or read_cpuid() directly.
310 */
read_cpuid_id(void)311 static inline u32 __attribute_const__ read_cpuid_id(void)
312 {
313 return read_cpuid(MIDR_EL1);
314 }
315
316 struct target_impl_cpu {
317 u64 midr;
318 u64 revidr;
319 u64 aidr;
320 };
321
322 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus);
323
read_cpuid_mpidr(void)324 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
325 {
326 return read_cpuid(MPIDR_EL1);
327 }
328
read_cpuid_implementor(void)329 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
330 {
331 return MIDR_IMPLEMENTOR(read_cpuid_id());
332 }
333
read_cpuid_part_number(void)334 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
335 {
336 return MIDR_PARTNUM(read_cpuid_id());
337 }
338
read_cpuid_cachetype(void)339 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
340 {
341 return read_cpuid(CTR_EL0);
342 }
343 #endif /* __ASSEMBLER__ */
344
345 #endif
346