1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
5 *
6 * Authors: Matthew Garrett
7 * Matt Turner
8 * Dave Airlie
9 */
10 #ifndef __MGAG200_DRV_H__
11 #define __MGAG200_DRV_H__
12
13 #include <video/vga.h>
14
15 #include <drm/drm_connector.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_encoder.h>
18 #include <drm/drm_gem.h>
19 #include <drm/drm_gem_shmem_helper.h>
20 #include <drm/drm_plane.h>
21
22 #include "mgag200_reg.h"
23
24 #define DRIVER_AUTHOR "Matthew Garrett"
25
26 #define DRIVER_NAME "mgag200"
27 #define DRIVER_DESC "MGA G200 SE"
28
29 #define DRIVER_MAJOR 1
30 #define DRIVER_MINOR 0
31 #define DRIVER_PATCHLEVEL 0
32
33 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
34 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
35 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
36 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
37
38 #define MGA_BIOS_OFFSET 0x7ffc
39
40 #define ATTR_INDEX 0x1fc0
41 #define ATTR_DATA 0x1fc1
42
43 #define WREG_MISC(v) \
44 WREG8(MGA_MISC_OUT, v)
45
46 #define RREG_MISC(v) \
47 ((v) = RREG8(MGA_MISC_IN))
48
49 #define WREG_MISC_MASKED(v, mask) \
50 do { \
51 u8 misc_; \
52 u8 mask_ = (mask); \
53 RREG_MISC(misc_); \
54 misc_ &= ~mask_; \
55 misc_ |= ((v) & mask_); \
56 WREG_MISC(misc_); \
57 } while (0)
58
59 #define WREG_ATTR(reg, v) \
60 do { \
61 RREG8(0x1fda); \
62 WREG8(ATTR_INDEX, reg); \
63 WREG8(ATTR_DATA, v); \
64 } while (0) \
65
66 #define RREG_SEQ(reg, v) \
67 do { \
68 WREG8(MGAREG_SEQ_INDEX, reg); \
69 v = RREG8(MGAREG_SEQ_DATA); \
70 } while (0) \
71
72 #define WREG_SEQ(reg, v) \
73 do { \
74 WREG8(MGAREG_SEQ_INDEX, reg); \
75 WREG8(MGAREG_SEQ_DATA, v); \
76 } while (0) \
77
78 #define RREG_CRT(reg, v) \
79 do { \
80 WREG8(MGAREG_CRTC_INDEX, reg); \
81 v = RREG8(MGAREG_CRTC_DATA); \
82 } while (0) \
83
84 #define WREG_CRT(reg, v) \
85 do { \
86 WREG8(MGAREG_CRTC_INDEX, reg); \
87 WREG8(MGAREG_CRTC_DATA, v); \
88 } while (0) \
89
90 #define RREG_ECRT(reg, v) \
91 do { \
92 WREG8(MGAREG_CRTCEXT_INDEX, reg); \
93 v = RREG8(MGAREG_CRTCEXT_DATA); \
94 } while (0) \
95
96 #define WREG_ECRT(reg, v) \
97 do { \
98 WREG8(MGAREG_CRTCEXT_INDEX, reg); \
99 WREG8(MGAREG_CRTCEXT_DATA, v); \
100 } while (0) \
101
102 #define GFX_INDEX 0x1fce
103 #define GFX_DATA 0x1fcf
104
105 #define WREG_GFX(reg, v) \
106 do { \
107 WREG8(GFX_INDEX, reg); \
108 WREG8(GFX_DATA, v); \
109 } while (0) \
110
111 #define DAC_INDEX 0x3c00
112 #define DAC_DATA 0x3c0a
113
114 #define WREG_DAC(reg, v) \
115 do { \
116 WREG8(DAC_INDEX, reg); \
117 WREG8(DAC_DATA, v); \
118 } while (0) \
119
120 #define MGA_MISC_OUT 0x1fc2
121 #define MGA_MISC_IN 0x1fcc
122
123 /*
124 * TODO: This is a pretty large set of default values for all kinds of
125 * settings. It should be split and set in the various DRM helpers,
126 * such as the CRTC reset or atomic_enable helpers. The PLL values
127 * probably belong to each model's PLL code.
128 */
129 #define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \
130 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \
131 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \
132 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \
133 /* 0x18: */ (xvrefctrl), \
134 /* 0x19: */ 0, \
135 /* 0x1a: */ (xpixclkctrl), \
136 /* 0x1b: */ 0xff, 0xbf, 0x20, \
137 /* 0x1e: */ (xmiscctrl), \
138 /* 0x1f: */ 0x20, \
139 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
140 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \
141 /* 0x2c: */ (xsyspllm), \
142 /* 0x2d: */ (xsysplln), \
143 /* 0x2e: */ (xsyspllp), \
144 /* 0x2f: */ 0x40, \
145 /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \
146 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \
147 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \
148 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \
149
150 #define MGAG200_LUT_SIZE 256
151
152 #define MGAG200_MAX_FB_HEIGHT 4096
153 #define MGAG200_MAX_FB_WIDTH 4096
154
155 struct mga_device;
156
157 /*
158 * Stores parameters for programming the PLLs
159 *
160 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz)
161 * Fo: output frequency
162 * Fvco = Fref * (N / M)
163 * Fo = Fvco / P
164 *
165 * S = [0..3]
166 */
167 struct mgag200_pll_values {
168 unsigned int m;
169 unsigned int n;
170 unsigned int p;
171 unsigned int s;
172 };
173
174 struct mgag200_crtc_state {
175 struct drm_crtc_state base;
176
177 /* Primary-plane format; required for modesetting and color mgmt. */
178 const struct drm_format_info *format;
179
180 struct mgag200_pll_values pixpllc;
181
182 bool set_vidrst;
183 };
184
to_mgag200_crtc_state(struct drm_crtc_state * base)185 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base)
186 {
187 return container_of(base, struct mgag200_crtc_state, base);
188 }
189
190 enum mga_type {
191 G200_PCI,
192 G200_AGP,
193 G200_SE_A,
194 G200_SE_B,
195 G200_WB,
196 G200_EV,
197 G200_EH,
198 G200_EH3,
199 G200_ER,
200 G200_EW3,
201 };
202
203 struct mgag200_device_info {
204 u16 max_hdisplay;
205 u16 max_vdisplay;
206
207 /*
208 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables
209 * the rsp test during mode validation.
210 */
211 unsigned long max_mem_bandwidth;
212
213 /* Synchronize scanout with BMC */
214 bool sync_bmc:1;
215
216 struct {
217 unsigned data_bit:3;
218 unsigned clock_bit:3;
219 } i2c;
220
221 /*
222 * HW does not handle 'startadd' register correctly. Always set
223 * it's value to 0.
224 */
225 bool bug_no_startadd:1;
226 };
227
228 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \
229 _sync_bmc, _i2c_data_bit, _i2c_clock_bit, \
230 _bug_no_startadd) \
231 { \
232 .max_hdisplay = (_max_hdisplay), \
233 .max_vdisplay = (_max_vdisplay), \
234 .max_mem_bandwidth = (_max_mem_bandwidth), \
235 .sync_bmc = (_sync_bmc), \
236 .i2c = { \
237 .data_bit = (_i2c_data_bit), \
238 .clock_bit = (_i2c_clock_bit), \
239 }, \
240 .bug_no_startadd = (_bug_no_startadd), \
241 }
242
243 struct mgag200_device_funcs {
244 /*
245 * Validate that the given state can be programmed into PIXPLLC. On
246 * success, the calculated parameters should be stored in the CRTC's
247 * state in struct @mgag200_crtc_state.pixpllc.
248 */
249 int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
250
251 /*
252 * Program PIXPLLC from the CRTC state. The parameters should have been
253 * stored in struct @mgag200_crtc_state.pixpllc by the corresponding
254 * implementation of @pixpllc_atomic_check.
255 */
256 void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
257 };
258
259 struct mga_device {
260 struct drm_device base;
261
262 const struct mgag200_device_info *info;
263 const struct mgag200_device_funcs *funcs;
264
265 struct resource *rmmio_res;
266 void __iomem *rmmio;
267 struct mutex rmmio_lock; /* Protects access to rmmio */
268
269 struct resource *vram_res;
270 void __iomem *vram;
271 resource_size_t vram_available;
272
273 struct drm_plane primary_plane;
274 struct drm_crtc crtc;
275 struct {
276 struct {
277 struct drm_encoder encoder;
278 struct drm_connector connector;
279 } vga;
280 } output;
281 };
282
to_mga_device(struct drm_device * dev)283 static inline struct mga_device *to_mga_device(struct drm_device *dev)
284 {
285 return container_of(dev, struct mga_device, base);
286 }
287
288 struct mgag200_g200_device {
289 struct mga_device base;
290
291 /* PLL constants */
292 long ref_clk;
293 long pclk_min;
294 long pclk_max;
295 };
296
to_mgag200_g200_device(struct drm_device * dev)297 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev)
298 {
299 return container_of(to_mga_device(dev), struct mgag200_g200_device, base);
300 }
301
302 struct mgag200_g200se_device {
303 struct mga_device base;
304
305 /* SE model number stored in reg 0x1e24 */
306 u32 unique_rev_id;
307 };
308
to_mgag200_g200se_device(struct drm_device * dev)309 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev)
310 {
311 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base);
312 }
313
314 /* mgag200_drv.c */
315 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2);
316 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size);
317 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev);
318 int mgag200_device_preinit(struct mga_device *mdev);
319 int mgag200_device_init(struct mga_device *mdev,
320 const struct mgag200_device_info *info,
321 const struct mgag200_device_funcs *funcs);
322
323 /* mgag200_<device type>.c */
324 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
325 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
326 enum mga_type type);
327 void mgag200_g200wb_init_registers(struct mga_device *mdev);
328 void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
329 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
330 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
331 void mgag200_g200eh_init_registers(struct mga_device *mdev);
332 void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
333 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev,
334 const struct drm_driver *drv);
335 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev,
336 const struct drm_driver *drv);
337 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev,
338 const struct drm_driver *drv);
339 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev,
340 const struct drm_driver *drv);
341
342 /*
343 * mgag200_mode.c
344 */
345
346 struct drm_crtc;
347 struct drm_crtc_state;
348 struct drm_display_mode;
349 struct drm_plane;
350 struct drm_atomic_state;
351 struct drm_scanout_buffer;
352
353 extern const uint32_t mgag200_primary_plane_formats[];
354 extern const size_t mgag200_primary_plane_formats_size;
355 extern const uint64_t mgag200_primary_plane_fmtmods[];
356
357 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane,
358 struct drm_atomic_state *new_state);
359 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
360 struct drm_atomic_state *old_state);
361 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane,
362 struct drm_atomic_state *state);
363 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
364 struct drm_atomic_state *old_state);
365 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane,
366 struct drm_scanout_buffer *sb);
367
368 #define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \
369 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \
370 .atomic_check = mgag200_primary_plane_helper_atomic_check, \
371 .atomic_update = mgag200_primary_plane_helper_atomic_update, \
372 .atomic_enable = mgag200_primary_plane_helper_atomic_enable, \
373 .atomic_disable = mgag200_primary_plane_helper_atomic_disable, \
374 .get_scanout_buffer = mgag200_primary_plane_helper_get_scanout_buffer
375
376 #define MGAG200_PRIMARY_PLANE_FUNCS \
377 .update_plane = drm_atomic_helper_update_plane, \
378 .disable_plane = drm_atomic_helper_disable_plane, \
379 .destroy = drm_plane_cleanup, \
380 DRM_GEM_SHADOW_PLANE_FUNCS
381
382 void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format);
383 void mgag200_crtc_set_gamma(struct mga_device *mdev,
384 const struct drm_format_info *format,
385 struct drm_color_lut *lut);
386
387 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
388 const struct drm_display_mode *mode);
389 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
390 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
391 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
392 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
393
394 #define MGAG200_CRTC_HELPER_FUNCS \
395 .mode_valid = mgag200_crtc_helper_mode_valid, \
396 .atomic_check = mgag200_crtc_helper_atomic_check, \
397 .atomic_flush = mgag200_crtc_helper_atomic_flush, \
398 .atomic_enable = mgag200_crtc_helper_atomic_enable, \
399 .atomic_disable = mgag200_crtc_helper_atomic_disable
400
401 void mgag200_crtc_reset(struct drm_crtc *crtc);
402 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc);
403 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state);
404
405 #define MGAG200_CRTC_FUNCS \
406 .reset = mgag200_crtc_reset, \
407 .destroy = drm_crtc_cleanup, \
408 .set_config = drm_atomic_helper_set_config, \
409 .page_flip = drm_atomic_helper_page_flip, \
410 .atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \
411 .atomic_destroy_state = mgag200_crtc_atomic_destroy_state
412
413 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode,
414 bool set_vidrst);
415 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format);
416 void mgag200_enable_display(struct mga_device *mdev);
417 void mgag200_init_registers(struct mga_device *mdev);
418 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available);
419
420 /* mgag200_vga_bmc.c */
421 int mgag200_vga_bmc_output_init(struct mga_device *mdev);
422
423 /* mgag200_vga.c */
424 int mgag200_vga_output_init(struct mga_device *mdev);
425
426 /* mgag200_bmc.c */
427 void mgag200_bmc_stop_scanout(struct mga_device *mdev);
428 void mgag200_bmc_start_scanout(struct mga_device *mdev);
429
430 #endif /* __MGAG200_DRV_H__ */
431