1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/nvmem-consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24
25 #define MESON_SAR_ADC_REG0 0x00
26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
46
47 #define MESON_SAR_ADC_CHAN_LIST 0x04
48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
50 (GENMASK(2, 0) << ((_chan) * 3))
51
52 #define MESON_SAR_ADC_AVG_CNTL 0x08
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
60 (GENMASK(1, 0) << ((_chan) * 2))
61
62 #define MESON_SAR_ADC_REG3 0x0c
63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
77
78 #define MESON_SAR_ADC_DELAY 0x10
79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
85
86 #define MESON_SAR_ADC_LAST_RD 0x14
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
89
90 #define MESON_SAR_ADC_FIFO_RD 0x18
91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
93
94 #define MESON_SAR_ADC_AUX_SW 0x1c
95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
96 (8 + (((_chan) - 2) * 3))
97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
104
105 #define MESON_SAR_ADC_CHAN_10_SW 0x20
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
122
123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
141
142 #define MESON_SAR_ADC_DELTA_10 0x28
143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
150
151 /*
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
155 */
156 #define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
158 #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6)
159 #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
160 #define MESON_SAR_ADC_REG11_EOC BIT(1)
161 #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
162
163 #define MESON_SAR_ADC_REG12 0x30
164 #define MESON_SAR_ADC_REG12_MPLL0_UNKNOWN BIT(0)
165 #define MESON_SAR_ADC_REG12_MPLL1_UNKNOWN BIT(1)
166 #define MESON_SAR_ADC_REG12_MPLL2_UNKNOWN BIT(2)
167
168 #define MESON_SAR_ADC_REG13 0x34
169 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
170
171 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
172 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
173 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
174 #define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL 7
175 #define MESON_SAR_ADC_TEMP_OFFSET 27
176
177 /* temperature sensor calibration information in eFuse */
178 #define MESON_SAR_ADC_EFUSE_BYTES 4
179 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
180 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
181
182 #define MESON_HHI_DPLL_TOP_0 0x318
183 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
184
185 /* for use with IIO_VAL_INT_PLUS_MICRO */
186 #define MILLION 1000000
187
188 #define MESON_SAR_ADC_CHAN(_chan) { \
189 .type = IIO_VOLTAGE, \
190 .indexed = 1, \
191 .channel = _chan, \
192 .address = _chan, \
193 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
194 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
195 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
196 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
197 BIT(IIO_CHAN_INFO_CALIBSCALE), \
198 .datasheet_name = "SAR_ADC_CH"#_chan, \
199 }
200
201 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
202 .type = IIO_TEMP, \
203 .channel = _chan, \
204 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
205 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
206 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
207 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
208 BIT(IIO_CHAN_INFO_SCALE), \
209 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
210 BIT(IIO_CHAN_INFO_CALIBSCALE), \
211 .datasheet_name = "TEMP_SENSOR", \
212 }
213
214 #define MESON_SAR_ADC_MUX(_chan, _sel) { \
215 .type = IIO_VOLTAGE, \
216 .channel = _chan, \
217 .indexed = 1, \
218 .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL, \
219 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
220 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
221 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
222 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
223 BIT(IIO_CHAN_INFO_CALIBSCALE), \
224 .datasheet_name = "SAR_ADC_MUX_"#_sel, \
225 }
226
227 enum meson_sar_adc_vref_sel {
228 VREF_CALIBATION_VOLTAGE = 0,
229 VREF_VDDA = 1,
230 };
231
232 enum meson_sar_adc_avg_mode {
233 NO_AVERAGING = 0x0,
234 MEAN_AVERAGING = 0x1,
235 MEDIAN_AVERAGING = 0x2,
236 };
237
238 enum meson_sar_adc_num_samples {
239 ONE_SAMPLE = 0x0,
240 TWO_SAMPLES = 0x1,
241 FOUR_SAMPLES = 0x2,
242 EIGHT_SAMPLES = 0x3,
243 };
244
245 enum meson_sar_adc_chan7_mux_sel {
246 CHAN7_MUX_VSS = 0x0,
247 CHAN7_MUX_VDD_DIV4 = 0x1,
248 CHAN7_MUX_VDD_DIV2 = 0x2,
249 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
250 CHAN7_MUX_VDD = 0x4,
251 CHAN7_MUX_CH7_INPUT = 0x7,
252 };
253
254 enum meson_sar_adc_channel_index {
255 NUM_CHAN_0,
256 NUM_CHAN_1,
257 NUM_CHAN_2,
258 NUM_CHAN_3,
259 NUM_CHAN_4,
260 NUM_CHAN_5,
261 NUM_CHAN_6,
262 NUM_CHAN_7,
263 NUM_CHAN_TEMP,
264 NUM_MUX_0_VSS,
265 NUM_MUX_1_VDD_DIV4,
266 NUM_MUX_2_VDD_DIV2,
267 NUM_MUX_3_VDD_MUL3_DIV4,
268 NUM_MUX_4_VDD,
269 };
270
271 static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = {
272 CHAN7_MUX_VSS,
273 CHAN7_MUX_VDD_DIV4,
274 CHAN7_MUX_VDD_DIV2,
275 CHAN7_MUX_VDD_MUL3_DIV4,
276 CHAN7_MUX_VDD,
277 };
278
279 static const char * const chan7_mux_names[] = {
280 [CHAN7_MUX_VSS] = "gnd",
281 [CHAN7_MUX_VDD_DIV4] = "0.25vdd",
282 [CHAN7_MUX_VDD_DIV2] = "0.5vdd",
283 [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd",
284 [CHAN7_MUX_VDD] = "vdd",
285 };
286
287 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
288 MESON_SAR_ADC_CHAN(NUM_CHAN_0),
289 MESON_SAR_ADC_CHAN(NUM_CHAN_1),
290 MESON_SAR_ADC_CHAN(NUM_CHAN_2),
291 MESON_SAR_ADC_CHAN(NUM_CHAN_3),
292 MESON_SAR_ADC_CHAN(NUM_CHAN_4),
293 MESON_SAR_ADC_CHAN(NUM_CHAN_5),
294 MESON_SAR_ADC_CHAN(NUM_CHAN_6),
295 MESON_SAR_ADC_CHAN(NUM_CHAN_7),
296 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
297 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
298 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
299 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
300 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
301 };
302
303 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
304 MESON_SAR_ADC_CHAN(NUM_CHAN_0),
305 MESON_SAR_ADC_CHAN(NUM_CHAN_1),
306 MESON_SAR_ADC_CHAN(NUM_CHAN_2),
307 MESON_SAR_ADC_CHAN(NUM_CHAN_3),
308 MESON_SAR_ADC_CHAN(NUM_CHAN_4),
309 MESON_SAR_ADC_CHAN(NUM_CHAN_5),
310 MESON_SAR_ADC_CHAN(NUM_CHAN_6),
311 MESON_SAR_ADC_CHAN(NUM_CHAN_7),
312 MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP),
313 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
314 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
315 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
316 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
317 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
318 };
319
320 struct meson_sar_adc_param {
321 bool has_bl30_integration;
322 unsigned long clock_rate;
323 unsigned int resolution;
324 const struct regmap_config *regmap_config;
325 u8 temperature_trimming_bits;
326 unsigned int temperature_multiplier;
327 unsigned int temperature_divider;
328 u8 disable_ring_counter;
329 bool has_vref_select;
330 u8 vref_select;
331 u8 cmv_select;
332 u8 adc_eoc;
333 enum meson_sar_adc_vref_sel vref_voltage;
334 bool enable_mpll_clock_workaround;
335 };
336
337 struct meson_sar_adc_data {
338 const struct meson_sar_adc_param *param;
339 const char *name;
340 };
341
342 struct meson_sar_adc_priv {
343 struct regmap *regmap;
344 struct regulator *vref;
345 const struct meson_sar_adc_param *param;
346 struct clk *clkin;
347 struct clk *core_clk;
348 struct clk *adc_sel_clk;
349 struct clk *adc_clk;
350 struct clk_gate clk_gate;
351 struct clk *adc_div_clk;
352 struct clk_divider clk_div;
353 struct completion done;
354 /* lock to protect against multiple access to the device */
355 struct mutex lock;
356 int calibbias;
357 int calibscale;
358 struct regmap *tsc_regmap;
359 bool temperature_sensor_calibrated;
360 u8 temperature_sensor_coefficient;
361 u16 temperature_sensor_adc_val;
362 enum meson_sar_adc_chan7_mux_sel chan7_mux_sel;
363 };
364
365 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
366 .reg_bits = 8,
367 .val_bits = 32,
368 .reg_stride = 4,
369 .max_register = MESON_SAR_ADC_REG13,
370 };
371
372 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
373 .reg_bits = 8,
374 .val_bits = 32,
375 .reg_stride = 4,
376 .max_register = MESON_SAR_ADC_DELTA_10,
377 };
378
379 static const struct iio_chan_spec *
find_channel_by_num(struct iio_dev * indio_dev,int num)380 find_channel_by_num(struct iio_dev *indio_dev, int num)
381 {
382 int i;
383
384 for (i = 0; i < indio_dev->num_channels; i++)
385 if (indio_dev->channels[i].channel == num)
386 return &indio_dev->channels[i];
387 return NULL;
388 }
389
meson_sar_adc_get_fifo_count(struct iio_dev * indio_dev)390 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
391 {
392 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
393 u32 regval;
394
395 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
396
397 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
398 }
399
meson_sar_adc_calib_val(struct iio_dev * indio_dev,int val)400 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
401 {
402 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
403 int tmp;
404
405 /* use val_calib = scale * val_raw + offset calibration function */
406 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
407
408 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
409 }
410
meson_sar_adc_wait_busy_clear(struct iio_dev * indio_dev)411 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
412 {
413 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
414 int val;
415
416 /*
417 * NOTE: we need a small delay before reading the status, otherwise
418 * the sample engine may not have started internally (which would
419 * seem to us that sampling is already finished).
420 */
421 udelay(1);
422 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
423 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
424 1, 10000);
425 }
426
meson_sar_adc_set_chan7_mux(struct iio_dev * indio_dev,enum meson_sar_adc_chan7_mux_sel sel)427 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
428 enum meson_sar_adc_chan7_mux_sel sel)
429 {
430 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
431 u32 regval;
432
433 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
434 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
435 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
436
437 usleep_range(10, 20);
438
439 priv->chan7_mux_sel = sel;
440 }
441
meson_sar_adc_read_raw_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)442 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
443 const struct iio_chan_spec *chan,
444 int *val)
445 {
446 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
447 struct device *dev = indio_dev->dev.parent;
448 int regval, fifo_chan, fifo_val, count;
449
450 if (!wait_for_completion_timeout(&priv->done,
451 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
452 return -ETIMEDOUT;
453
454 count = meson_sar_adc_get_fifo_count(indio_dev);
455 if (count != 1) {
456 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
457 return -EINVAL;
458 }
459
460 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
461 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
462 if (fifo_chan != chan->address) {
463 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
464 fifo_chan, chan->address);
465 return -EINVAL;
466 }
467
468 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
469 fifo_val &= GENMASK(priv->param->resolution - 1, 0);
470 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
471
472 return 0;
473 }
474
meson_sar_adc_set_averaging(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode mode,enum meson_sar_adc_num_samples samples)475 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
476 const struct iio_chan_spec *chan,
477 enum meson_sar_adc_avg_mode mode,
478 enum meson_sar_adc_num_samples samples)
479 {
480 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
481 int val, address = chan->address;
482
483 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
484 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
485 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
486 val);
487
488 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
489 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
490 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
491 }
492
meson_sar_adc_enable_channel(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)493 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
494 const struct iio_chan_spec *chan)
495 {
496 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
497 u32 regval;
498
499 /*
500 * the SAR ADC engine allows sampling multiple channels at the same
501 * time. to keep it simple we're only working with one *internal*
502 * channel, which starts counting at index 0 (which means: count = 1).
503 */
504 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
505 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
506 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
507
508 /* map channel index 0 to the channel which we want to read */
509 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
510 chan->address);
511 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
512 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
513
514 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
515 chan->address);
516 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
517 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
518 regval);
519
520 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
521 chan->address);
522 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
523 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
524 regval);
525
526 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
527 if (chan->type == IIO_TEMP)
528 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
529 else
530 regval = 0;
531
532 regmap_update_bits(priv->regmap,
533 MESON_SAR_ADC_DELTA_10,
534 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
535 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) {
536 enum meson_sar_adc_chan7_mux_sel sel;
537
538 if (chan->channel == NUM_CHAN_7)
539 sel = CHAN7_MUX_CH7_INPUT;
540 else
541 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS];
542 if (sel != priv->chan7_mux_sel)
543 meson_sar_adc_set_chan7_mux(indio_dev, sel);
544 }
545 }
546
meson_sar_adc_start_sample_engine(struct iio_dev * indio_dev)547 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
548 {
549 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
550
551 reinit_completion(&priv->done);
552
553 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
554 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
555
556 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
557 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
558
559 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
560 MESON_SAR_ADC_REG0_SAMPLING_START);
561 }
562
meson_sar_adc_stop_sample_engine(struct iio_dev * indio_dev)563 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
564 {
565 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
566
567 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
568 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
569
570 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
571 MESON_SAR_ADC_REG0_SAMPLING_STOP);
572
573 /* wait until all modules are stopped */
574 meson_sar_adc_wait_busy_clear(indio_dev);
575
576 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
577 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
578 }
579
meson_sar_adc_lock(struct iio_dev * indio_dev)580 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
581 {
582 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
583 int val, ret;
584
585 mutex_lock(&priv->lock);
586
587 if (priv->param->has_bl30_integration) {
588 /* prevent BL30 from using the SAR ADC while we are using it */
589 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY,
590 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
591
592 udelay(1);
593
594 /*
595 * wait until BL30 releases it's lock (so we can use the SAR
596 * ADC)
597 */
598 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
599 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
600 1, 10000);
601 if (ret) {
602 mutex_unlock(&priv->lock);
603 return ret;
604 }
605 }
606
607 return 0;
608 }
609
meson_sar_adc_unlock(struct iio_dev * indio_dev)610 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
611 {
612 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
613
614 if (priv->param->has_bl30_integration)
615 /* allow BL30 to use the SAR ADC again */
616 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY,
617 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
618
619 mutex_unlock(&priv->lock);
620 }
621
meson_sar_adc_clear_fifo(struct iio_dev * indio_dev)622 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
623 {
624 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
625 unsigned int count, tmp;
626
627 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
628 if (!meson_sar_adc_get_fifo_count(indio_dev))
629 break;
630
631 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
632 }
633 }
634
meson_sar_adc_get_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode avg_mode,enum meson_sar_adc_num_samples avg_samples,int * val)635 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
636 const struct iio_chan_spec *chan,
637 enum meson_sar_adc_avg_mode avg_mode,
638 enum meson_sar_adc_num_samples avg_samples,
639 int *val)
640 {
641 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
642 struct device *dev = indio_dev->dev.parent;
643 int ret;
644
645 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
646 return -ENOTSUPP;
647
648 ret = meson_sar_adc_lock(indio_dev);
649 if (ret)
650 return ret;
651
652 /* clear the FIFO to make sure we're not reading old values */
653 meson_sar_adc_clear_fifo(indio_dev);
654
655 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
656
657 meson_sar_adc_enable_channel(indio_dev, chan);
658
659 meson_sar_adc_start_sample_engine(indio_dev);
660 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
661 meson_sar_adc_stop_sample_engine(indio_dev);
662
663 meson_sar_adc_unlock(indio_dev);
664
665 if (ret) {
666 dev_warn(dev, "failed to read sample for channel %lu: %d\n",
667 chan->address, ret);
668 return ret;
669 }
670
671 return IIO_VAL_INT;
672 }
673
meson_sar_adc_iio_info_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)674 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
675 const struct iio_chan_spec *chan,
676 int *val, int *val2, long mask)
677 {
678 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
679 struct device *dev = indio_dev->dev.parent;
680 int ret;
681
682 switch (mask) {
683 case IIO_CHAN_INFO_RAW:
684 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
685 ONE_SAMPLE, val);
686
687 case IIO_CHAN_INFO_AVERAGE_RAW:
688 return meson_sar_adc_get_sample(indio_dev, chan,
689 MEAN_AVERAGING, EIGHT_SAMPLES,
690 val);
691
692 case IIO_CHAN_INFO_SCALE:
693 if (chan->type == IIO_VOLTAGE) {
694 ret = regulator_get_voltage(priv->vref);
695 if (ret < 0) {
696 dev_err(dev, "failed to get vref voltage: %d\n", ret);
697 return ret;
698 }
699
700 *val = ret / 1000;
701 *val2 = priv->param->resolution;
702 return IIO_VAL_FRACTIONAL_LOG2;
703 } else if (chan->type == IIO_TEMP) {
704 /* SoC specific multiplier and divider */
705 *val = priv->param->temperature_multiplier;
706 *val2 = priv->param->temperature_divider;
707
708 /* celsius to millicelsius */
709 *val *= 1000;
710
711 return IIO_VAL_FRACTIONAL;
712 } else {
713 return -EINVAL;
714 }
715
716 case IIO_CHAN_INFO_CALIBBIAS:
717 *val = priv->calibbias;
718 return IIO_VAL_INT;
719
720 case IIO_CHAN_INFO_CALIBSCALE:
721 *val = priv->calibscale / MILLION;
722 *val2 = priv->calibscale % MILLION;
723 return IIO_VAL_INT_PLUS_MICRO;
724
725 case IIO_CHAN_INFO_OFFSET:
726 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
727 priv->param->temperature_divider,
728 priv->param->temperature_multiplier);
729 *val -= priv->temperature_sensor_adc_val;
730 return IIO_VAL_INT;
731
732 default:
733 return -EINVAL;
734 }
735 }
736
meson_sar_adc_clk_init(struct iio_dev * indio_dev,void __iomem * base)737 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
738 void __iomem *base)
739 {
740 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
741 struct device *dev = indio_dev->dev.parent;
742 struct clk_init_data init;
743 const char *clk_parents[1];
744
745 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
746 if (!init.name)
747 return -ENOMEM;
748
749 init.flags = 0;
750 init.ops = &clk_divider_ops;
751 clk_parents[0] = __clk_get_name(priv->clkin);
752 init.parent_names = clk_parents;
753 init.num_parents = 1;
754
755 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
756 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
757 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
758 priv->clk_div.hw.init = &init;
759 priv->clk_div.flags = 0;
760
761 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
762 if (WARN_ON(IS_ERR(priv->adc_div_clk)))
763 return PTR_ERR(priv->adc_div_clk);
764
765 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
766 if (!init.name)
767 return -ENOMEM;
768
769 init.flags = CLK_SET_RATE_PARENT;
770 init.ops = &clk_gate_ops;
771 clk_parents[0] = __clk_get_name(priv->adc_div_clk);
772 init.parent_names = clk_parents;
773 init.num_parents = 1;
774
775 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
776 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
777 priv->clk_gate.hw.init = &init;
778
779 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
780 if (WARN_ON(IS_ERR(priv->adc_clk)))
781 return PTR_ERR(priv->adc_clk);
782
783 return 0;
784 }
785
meson_sar_adc_temp_sensor_init(struct iio_dev * indio_dev)786 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
787 {
788 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
789 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
790 struct device *dev = indio_dev->dev.parent;
791 struct nvmem_cell *temperature_calib;
792 size_t read_len;
793 int ret;
794
795 temperature_calib = nvmem_cell_get(dev, "temperature_calib");
796 if (IS_ERR(temperature_calib)) {
797 ret = PTR_ERR(temperature_calib);
798
799 /*
800 * leave the temperature sensor disabled if no calibration data
801 * was passed via nvmem-cells.
802 */
803 if (ret == -ENODEV)
804 return 0;
805
806 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
807 }
808
809 read_len = MESON_SAR_ADC_EFUSE_BYTES;
810 buf = nvmem_cell_read(temperature_calib, &read_len);
811 nvmem_cell_put(temperature_calib);
812 if (IS_ERR(buf))
813 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
814 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
815 kfree(buf);
816 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
817 }
818
819 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
820 if (IS_ERR(priv->tsc_regmap)) {
821 kfree(buf);
822 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
823 "failed to get amlogic,hhi-sysctrl regmap\n");
824 }
825
826 trimming_bits = priv->param->temperature_trimming_bits;
827 trimming_mask = BIT(trimming_bits) - 1;
828
829 priv->temperature_sensor_calibrated =
830 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
831 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
832
833 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
834 buf[3]);
835
836 priv->temperature_sensor_adc_val = buf[2];
837 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
838 priv->temperature_sensor_adc_val >>= trimming_bits;
839
840 kfree(buf);
841
842 return 0;
843 }
844
meson_sar_adc_init(struct iio_dev * indio_dev)845 static int meson_sar_adc_init(struct iio_dev *indio_dev)
846 {
847 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
848 struct device *dev = indio_dev->dev.parent;
849 int regval, i, ret;
850
851 /*
852 * make sure we start at CH7 input since the other muxes are only used
853 * for internal calibration.
854 */
855 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
856
857 if (priv->param->has_bl30_integration) {
858 /*
859 * leave sampling delay and the input clocks as configured by
860 * BL30 to make sure BL30 gets the values it expects when
861 * reading the temperature sensor.
862 */
863 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
864 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
865 return 0;
866 }
867
868 meson_sar_adc_stop_sample_engine(indio_dev);
869
870 /*
871 * disable this bit as seems to be only relevant for Meson6 (based
872 * on the vendor driver), which we don't support at the moment.
873 */
874 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
875 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
876
877 /* disable all channels by default */
878 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
879
880 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
881 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE);
882 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,
883 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
884
885 /* delay between two samples = (10+1) * 1uS */
886 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
887 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
888 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
889 10));
890 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
891 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
892 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
893 0));
894
895 /* delay between two samples = (10+1) * 1uS */
896 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
897 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
898 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
899 10));
900 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
901 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
902 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
903 1));
904
905 /*
906 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
907 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
908 */
909 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
910 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
911 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
912 regval);
913 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
914 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
915 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
916 regval);
917
918 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
919 MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
920
921 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
922 MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
923
924 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
925 MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
926
927 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
928 MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
929
930 /*
931 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
932 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
933 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
934 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
935 */
936 regval = 0;
937 for (i = 2; i <= 7; i++)
938 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
939 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
940 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
941 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
942
943 if (priv->temperature_sensor_calibrated) {
944 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
945 MESON_SAR_ADC_DELTA_10_TS_REVE1);
946 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
947 MESON_SAR_ADC_DELTA_10_TS_REVE0);
948
949 /*
950 * set bits [3:0] of the TSC (temperature sensor coefficient)
951 * to get the correct values when reading the temperature.
952 */
953 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
954 priv->temperature_sensor_coefficient);
955 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
956 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
957
958 if (priv->param->temperature_trimming_bits == 5) {
959 if (priv->temperature_sensor_coefficient & BIT(4))
960 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
961 else
962 regval = 0;
963
964 /*
965 * bit [4] (the 5th bit when starting to count at 1)
966 * of the TSC is located in the HHI register area.
967 */
968 regmap_update_bits(priv->tsc_regmap,
969 MESON_HHI_DPLL_TOP_0,
970 MESON_HHI_DPLL_TOP_0_TSC_BIT4,
971 regval);
972 }
973 } else {
974 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
975 MESON_SAR_ADC_DELTA_10_TS_REVE1);
976 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
977 MESON_SAR_ADC_DELTA_10_TS_REVE0);
978 }
979
980 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
981 priv->param->disable_ring_counter);
982 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
983 MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
984 regval);
985
986 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) {
987 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
988 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
989 MESON_SAR_ADC_REG11_EOC, regval);
990
991 if (priv->param->has_vref_select) {
992 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,
993 priv->param->vref_select);
994 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
995 MESON_SAR_ADC_REG11_VREF_SEL, regval);
996 }
997
998 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
999 priv->param->vref_voltage);
1000 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1001 MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
1002
1003 regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
1004 priv->param->cmv_select);
1005 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1006 MESON_SAR_ADC_REG11_CMV_SEL, regval);
1007
1008 if (priv->param->enable_mpll_clock_workaround) {
1009 dev_warn(dev,
1010 "Enabling unknown bits to make the MPLL clocks work. This may change so always update dtbs and kernel together\n");
1011 regmap_write(priv->regmap, MESON_SAR_ADC_REG12,
1012 MESON_SAR_ADC_REG12_MPLL0_UNKNOWN |
1013 MESON_SAR_ADC_REG12_MPLL1_UNKNOWN |
1014 MESON_SAR_ADC_REG12_MPLL2_UNKNOWN);
1015 }
1016 }
1017
1018 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
1019 if (ret)
1020 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
1021
1022 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
1023 if (ret)
1024 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
1025
1026 return 0;
1027 }
1028
meson_sar_adc_set_bandgap(struct iio_dev * indio_dev,bool on_off)1029 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
1030 {
1031 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1032
1033 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11)
1034 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1035 MESON_SAR_ADC_REG11_BANDGAP_EN,
1036 on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0);
1037 else
1038 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
1039 MESON_SAR_ADC_DELTA_10_TS_VBG_EN,
1040 on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0);
1041 }
1042
meson_sar_adc_hw_enable(struct iio_dev * indio_dev)1043 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
1044 {
1045 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1046 struct device *dev = indio_dev->dev.parent;
1047 int ret;
1048 u32 regval;
1049
1050 ret = meson_sar_adc_lock(indio_dev);
1051 if (ret) {
1052 dev_err(dev, "failed to lock adc\n");
1053 goto err_lock;
1054 }
1055
1056 ret = regulator_enable(priv->vref);
1057 if (ret < 0) {
1058 dev_err(dev, "failed to enable vref regulator\n");
1059 goto err_vref;
1060 }
1061
1062 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
1063 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
1064 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1065
1066 meson_sar_adc_set_bandgap(indio_dev, true);
1067
1068 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,
1069 MESON_SAR_ADC_REG3_ADC_EN);
1070
1071 udelay(5);
1072
1073 ret = clk_prepare_enable(priv->adc_clk);
1074 if (ret) {
1075 dev_err(dev, "failed to enable adc clk\n");
1076 goto err_adc_clk;
1077 }
1078
1079 meson_sar_adc_unlock(indio_dev);
1080
1081 return 0;
1082
1083 err_adc_clk:
1084 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
1085 MESON_SAR_ADC_REG3_ADC_EN);
1086 meson_sar_adc_set_bandgap(indio_dev, false);
1087 regulator_disable(priv->vref);
1088 err_vref:
1089 meson_sar_adc_unlock(indio_dev);
1090 err_lock:
1091 return ret;
1092 }
1093
meson_sar_adc_hw_disable(struct iio_dev * indio_dev)1094 static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
1095 {
1096 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1097 int ret;
1098
1099 /*
1100 * If taking the lock fails we have to assume that BL30 is broken. The
1101 * best we can do then is to release the resources anyhow.
1102 */
1103 ret = meson_sar_adc_lock(indio_dev);
1104 if (ret)
1105 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret));
1106
1107 clk_disable_unprepare(priv->adc_clk);
1108
1109 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
1110 MESON_SAR_ADC_REG3_ADC_EN);
1111
1112 meson_sar_adc_set_bandgap(indio_dev, false);
1113
1114 regulator_disable(priv->vref);
1115
1116 if (!ret)
1117 meson_sar_adc_unlock(indio_dev);
1118 }
1119
meson_sar_adc_irq(int irq,void * data)1120 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
1121 {
1122 struct iio_dev *indio_dev = data;
1123 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1124 unsigned int cnt, threshold;
1125 u32 regval;
1126
1127 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
1128 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
1129 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1130
1131 if (cnt < threshold)
1132 return IRQ_NONE;
1133
1134 complete(&priv->done);
1135
1136 return IRQ_HANDLED;
1137 }
1138
meson_sar_adc_calib(struct iio_dev * indio_dev)1139 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1140 {
1141 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1142 int ret, nominal0, nominal1, value0, value1;
1143
1144 /* use points 25% and 75% for calibration */
1145 nominal0 = (1 << priv->param->resolution) / 4;
1146 nominal1 = (1 << priv->param->resolution) * 3 / 4;
1147
1148 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1149 usleep_range(10, 20);
1150 ret = meson_sar_adc_get_sample(indio_dev,
1151 find_channel_by_num(indio_dev,
1152 NUM_MUX_1_VDD_DIV4),
1153 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1154 if (ret < 0)
1155 goto out;
1156
1157 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1158 usleep_range(10, 20);
1159 ret = meson_sar_adc_get_sample(indio_dev,
1160 find_channel_by_num(indio_dev,
1161 NUM_MUX_3_VDD_MUL3_DIV4),
1162 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1163 if (ret < 0)
1164 goto out;
1165
1166 if (value1 <= value0) {
1167 ret = -EINVAL;
1168 goto out;
1169 }
1170
1171 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1172 value1 - value0);
1173 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1174 MILLION);
1175 ret = 0;
1176 out:
1177 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1178
1179 return ret;
1180 }
1181
read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)1182 static int read_label(struct iio_dev *indio_dev,
1183 struct iio_chan_spec const *chan,
1184 char *label)
1185 {
1186 if (chan->type == IIO_TEMP)
1187 return sysfs_emit(label, "temp-sensor\n");
1188 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS)
1189 return sysfs_emit(label, "%s\n",
1190 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]);
1191 if (chan->type == IIO_VOLTAGE)
1192 return sysfs_emit(label, "channel-%d\n", chan->channel);
1193 return 0;
1194 }
1195
1196 static const struct iio_info meson_sar_adc_iio_info = {
1197 .read_raw = meson_sar_adc_iio_info_read_raw,
1198 .read_label = read_label,
1199 };
1200
1201 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1202 .has_bl30_integration = false,
1203 .clock_rate = 1150000,
1204 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1205 .resolution = 10,
1206 .temperature_trimming_bits = 4,
1207 .temperature_multiplier = 18 * 10000,
1208 .temperature_divider = 1024 * 10 * 85,
1209 };
1210
1211 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1212 .has_bl30_integration = false,
1213 .clock_rate = 1150000,
1214 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1215 .resolution = 10,
1216 .temperature_trimming_bits = 5,
1217 .temperature_multiplier = 10,
1218 .temperature_divider = 32,
1219 };
1220
1221 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1222 .has_bl30_integration = true,
1223 .clock_rate = 1200000,
1224 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1225 .resolution = 10,
1226 .vref_voltage = 1,
1227 .cmv_select = 1,
1228 };
1229
1230 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1231 .has_bl30_integration = true,
1232 .clock_rate = 1200000,
1233 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1234 .resolution = 12,
1235 .disable_ring_counter = 1,
1236 .vref_voltage = 1,
1237 .cmv_select = 1,
1238 };
1239
1240 static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = {
1241 .has_bl30_integration = true,
1242 .clock_rate = 1200000,
1243 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1244 .resolution = 12,
1245 .disable_ring_counter = 1,
1246 .vref_voltage = 1,
1247 .cmv_select = true,
1248 .enable_mpll_clock_workaround = true,
1249 };
1250
1251 static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
1252 .has_bl30_integration = true,
1253 .clock_rate = 1200000,
1254 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1255 .resolution = 12,
1256 .disable_ring_counter = 1,
1257 .vref_voltage = 1,
1258 .has_vref_select = true,
1259 .vref_select = VREF_VDDA,
1260 .cmv_select = 1,
1261 };
1262
1263 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
1264 .has_bl30_integration = false,
1265 .clock_rate = 1200000,
1266 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1267 .resolution = 12,
1268 .disable_ring_counter = 1,
1269 .adc_eoc = 1,
1270 .has_vref_select = true,
1271 .vref_select = VREF_VDDA,
1272 };
1273
1274 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1275 .param = &meson_sar_adc_meson8_param,
1276 .name = "meson-meson8-saradc",
1277 };
1278
1279 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1280 .param = &meson_sar_adc_meson8b_param,
1281 .name = "meson-meson8b-saradc",
1282 };
1283
1284 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1285 .param = &meson_sar_adc_meson8b_param,
1286 .name = "meson-meson8m2-saradc",
1287 };
1288
1289 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1290 .param = &meson_sar_adc_gxbb_param,
1291 .name = "meson-gxbb-saradc",
1292 };
1293
1294 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1295 .param = &meson_sar_adc_gxl_param,
1296 .name = "meson-gxl-saradc",
1297 };
1298
1299 static const struct meson_sar_adc_data meson_sar_adc_gxlx_data = {
1300 .param = &meson_sar_adc_gxlx_param,
1301 .name = "meson-gxlx-saradc",
1302 };
1303
1304 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1305 .param = &meson_sar_adc_gxl_param,
1306 .name = "meson-gxm-saradc",
1307 };
1308
1309 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1310 .param = &meson_sar_adc_axg_param,
1311 .name = "meson-axg-saradc",
1312 };
1313
1314 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1315 .param = &meson_sar_adc_g12a_param,
1316 .name = "meson-g12a-saradc",
1317 };
1318
1319 static const struct meson_sar_adc_data meson_sar_adc_s4_data = {
1320 .param = &meson_sar_adc_g12a_param,
1321 .name = "meson-s4-saradc",
1322 };
1323
1324 static const struct of_device_id meson_sar_adc_of_match[] = {
1325 {
1326 .compatible = "amlogic,meson8-saradc",
1327 .data = &meson_sar_adc_meson8_data,
1328 }, {
1329 .compatible = "amlogic,meson8b-saradc",
1330 .data = &meson_sar_adc_meson8b_data,
1331 }, {
1332 .compatible = "amlogic,meson8m2-saradc",
1333 .data = &meson_sar_adc_meson8m2_data,
1334 }, {
1335 .compatible = "amlogic,meson-gxbb-saradc",
1336 .data = &meson_sar_adc_gxbb_data,
1337 }, {
1338 .compatible = "amlogic,meson-gxl-saradc",
1339 .data = &meson_sar_adc_gxl_data,
1340 }, {
1341 .compatible = "amlogic,meson-gxlx-saradc",
1342 .data = &meson_sar_adc_gxlx_data,
1343 }, {
1344 .compatible = "amlogic,meson-gxm-saradc",
1345 .data = &meson_sar_adc_gxm_data,
1346 }, {
1347 .compatible = "amlogic,meson-axg-saradc",
1348 .data = &meson_sar_adc_axg_data,
1349 }, {
1350 .compatible = "amlogic,meson-g12a-saradc",
1351 .data = &meson_sar_adc_g12a_data,
1352 }, {
1353 .compatible = "amlogic,meson-s4-saradc",
1354 .data = &meson_sar_adc_s4_data,
1355 },
1356 { }
1357 };
1358 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1359
meson_sar_adc_probe(struct platform_device * pdev)1360 static int meson_sar_adc_probe(struct platform_device *pdev)
1361 {
1362 const struct meson_sar_adc_data *match_data;
1363 struct meson_sar_adc_priv *priv;
1364 struct device *dev = &pdev->dev;
1365 struct iio_dev *indio_dev;
1366 void __iomem *base;
1367 int irq, ret;
1368
1369 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1370 if (!indio_dev)
1371 return -ENOMEM;
1372
1373 priv = iio_priv(indio_dev);
1374 init_completion(&priv->done);
1375
1376 match_data = of_device_get_match_data(dev);
1377 if (!match_data)
1378 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
1379
1380 priv->param = match_data->param;
1381
1382 indio_dev->name = match_data->name;
1383 indio_dev->modes = INDIO_DIRECT_MODE;
1384 indio_dev->info = &meson_sar_adc_iio_info;
1385
1386 base = devm_platform_ioremap_resource(pdev, 0);
1387 if (IS_ERR(base))
1388 return PTR_ERR(base);
1389
1390 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
1391 if (IS_ERR(priv->regmap))
1392 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n");
1393
1394 irq = irq_of_parse_and_map(dev->of_node, 0);
1395 if (!irq)
1396 return dev_err_probe(dev, -EINVAL, "failed to get irq\n");
1397
1398 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
1399 if (ret)
1400 return dev_err_probe(dev, ret, "failed to request irq\n");
1401
1402 priv->clkin = devm_clk_get(dev, "clkin");
1403 if (IS_ERR(priv->clkin))
1404 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
1405
1406 priv->core_clk = devm_clk_get_enabled(dev, "core");
1407 if (IS_ERR(priv->core_clk))
1408 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
1409
1410 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
1411 if (IS_ERR(priv->adc_clk))
1412 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
1413
1414 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
1415 if (IS_ERR(priv->adc_sel_clk))
1416 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
1417
1418 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1419 if (!priv->adc_clk) {
1420 ret = meson_sar_adc_clk_init(indio_dev, base);
1421 if (ret)
1422 return dev_err_probe(dev, ret, "failed to init internal clk\n");
1423 }
1424
1425 priv->vref = devm_regulator_get(dev, "vref");
1426 if (IS_ERR(priv->vref))
1427 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
1428
1429 priv->calibscale = MILLION;
1430
1431 if (priv->param->temperature_trimming_bits) {
1432 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1433 if (ret)
1434 return ret;
1435 }
1436
1437 if (priv->temperature_sensor_calibrated) {
1438 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1439 indio_dev->num_channels =
1440 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1441 } else {
1442 indio_dev->channels = meson_sar_adc_iio_channels;
1443 indio_dev->num_channels =
1444 ARRAY_SIZE(meson_sar_adc_iio_channels);
1445 }
1446
1447 ret = meson_sar_adc_init(indio_dev);
1448 if (ret)
1449 goto err;
1450
1451 mutex_init(&priv->lock);
1452
1453 ret = meson_sar_adc_hw_enable(indio_dev);
1454 if (ret)
1455 goto err;
1456
1457 ret = meson_sar_adc_calib(indio_dev);
1458 if (ret)
1459 dev_warn(dev, "calibration failed\n");
1460
1461 platform_set_drvdata(pdev, indio_dev);
1462
1463 ret = iio_device_register(indio_dev);
1464 if (ret) {
1465 dev_err_probe(dev, ret, "failed to register iio device\n");
1466 goto err_hw;
1467 }
1468
1469 return 0;
1470
1471 err_hw:
1472 meson_sar_adc_hw_disable(indio_dev);
1473 err:
1474 return ret;
1475 }
1476
meson_sar_adc_remove(struct platform_device * pdev)1477 static void meson_sar_adc_remove(struct platform_device *pdev)
1478 {
1479 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1480
1481 iio_device_unregister(indio_dev);
1482
1483 meson_sar_adc_hw_disable(indio_dev);
1484 }
1485
meson_sar_adc_suspend(struct device * dev)1486 static int meson_sar_adc_suspend(struct device *dev)
1487 {
1488 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1489 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1490
1491 meson_sar_adc_hw_disable(indio_dev);
1492
1493 clk_disable_unprepare(priv->core_clk);
1494
1495 return 0;
1496 }
1497
meson_sar_adc_resume(struct device * dev)1498 static int meson_sar_adc_resume(struct device *dev)
1499 {
1500 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1501 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1502 int ret;
1503
1504 ret = clk_prepare_enable(priv->core_clk);
1505 if (ret) {
1506 dev_err(dev, "failed to enable core clk\n");
1507 return ret;
1508 }
1509
1510 return meson_sar_adc_hw_enable(indio_dev);
1511 }
1512
1513 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1514 meson_sar_adc_suspend, meson_sar_adc_resume);
1515
1516 static struct platform_driver meson_sar_adc_driver = {
1517 .probe = meson_sar_adc_probe,
1518 .remove = meson_sar_adc_remove,
1519 .driver = {
1520 .name = "meson-saradc",
1521 .of_match_table = meson_sar_adc_of_match,
1522 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
1523 },
1524 };
1525
1526 module_platform_driver(meson_sar_adc_driver);
1527
1528 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1529 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1530 MODULE_LICENSE("GPL v2");
1531