1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_REGS_H_ 7 #define _XE_GT_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 13 * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 15 */ 16 #define MEDIA_GT_GSI_OFFSET 0x380000 17 #define MEDIA_GT_GSI_LENGTH 0x40000 18 19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 21 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 22 #define MTL_CC_MASK REG_GENMASK(12, 9) 23 24 /* RPM unit config (Gen8+) */ 25 #define RPM_CONFIG0 XE_REG(0xd00) 26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 27 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 28 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 29 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 30 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 32 33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 36 37 #define GMD_ID XE_REG(0xd8c) 38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 40 #define GMD_ID_REVID REG_GENMASK(5, 0) 41 42 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 43 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 44 45 #define MCFG_MCR_SELECTOR XE_REG(0xfd0) 46 #define MTL_MCR_SELECTOR XE_REG(0xfd4) 47 #define SF_MCR_SELECTOR XE_REG(0xfd8) 48 #define MCR_SELECTOR XE_REG(0xfdc) 49 #define GAM_MCR_SELECTOR XE_REG(0xfe0) 50 #define MCR_MULTICAST REG_BIT(31) 51 #define MCR_SLICE_MASK REG_GENMASK(30, 27) 52 #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 53 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 54 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 55 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 56 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 57 58 #define PS_INVOCATION_COUNT XE_REG(0x2348) 59 60 #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 61 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 62 #define LE_SSE_MASK REG_GENMASK(18, 17) 63 #define LE_SSE(value) REG_FIELD_PREP(LE_SSE_MASK, value) 64 #define LE_COS_MASK REG_GENMASK(16, 15) 65 #define LE_SCF_MASK REG_BIT(14) 66 #define LE_SCF(value) REG_FIELD_PREP(LE_SCF_MASK, value) 67 #define LE_PFM_MASK REG_GENMASK(13, 11) 68 #define LE_PFM(value) REG_FIELD_PREP(LE_PFM_MASK, value) 69 #define LE_SCC_MASK REG_GENMASK(10, 8) 70 #define LE_SCC(value) REG_FIELD_PREP(LE_SCC_MASK, value) 71 #define LE_RSC_MASK REG_BIT(7) 72 #define LE_RSC(value) REG_FIELD_PREP(LE_RSC_MASK, value) 73 #define LE_AOM_MASK REG_BIT(6) 74 #define LE_AOM(value) REG_FIELD_PREP(LE_AOM_MASK, value) 75 #define LE_LRUM_MASK REG_GENMASK(5, 4) 76 #define LE_LRUM(value) REG_FIELD_PREP(LE_LRUM_MASK, value) 77 #define LE_TGT_CACHE_MASK REG_GENMASK(3, 2) 78 #define LE_TGT_CACHE(value) REG_FIELD_PREP(LE_TGT_CACHE_MASK, value) 79 #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) 80 #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) 81 82 #define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) 83 #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) 84 85 #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194) 86 #define CG_DIS_CNTLBUS REG_BIT(6) 87 88 #define CCS_AUX_INV XE_REG(0x4208) 89 90 #define VD0_AUX_INV XE_REG(0x4218) 91 #define VE0_AUX_INV XE_REG(0x4238) 92 93 #define VE1_AUX_INV XE_REG(0x42b8) 94 #define AUX_INV REG_BIT(0) 95 96 #define XE2_LMEM_CFG XE_REG(0x48b0) 97 98 #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4) 99 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 100 #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) 101 102 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 103 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 104 105 #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) 106 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 107 #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6) 108 109 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 110 #define TBIMR_FAST_CLIP REG_BIT(5) 111 112 #define FF_MODE XE_REG_MCR(0x6210) 113 #define DIS_TE_AUTOSTRIP REG_BIT(31) 114 #define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20) 115 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 116 #define DIS_MESH_AUTOSTRIP REG_BIT(15) 117 118 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 119 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 120 #define DIS_AUTOSTRIP REG_BIT(6) 121 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 122 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 123 124 #define FF_MODE2 XE_REG(0x6604) 125 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 126 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 127 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 128 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 129 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 130 131 #define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c) 132 133 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) 134 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 135 136 #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED) 137 #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14) 138 139 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 140 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 141 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 142 143 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 144 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 145 146 #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 147 #define FLSH_IGNORES_PSD REG_BIT(10) 148 #define FD_END_COLLECT REG_BIT(5) 149 150 #define SC_INSTDONE XE_REG(0x7100) 151 #define SC_INSTDONE_EXTRA XE_REG(0x7104) 152 #define SC_INSTDONE_EXTRA2 XE_REG(0x7108) 153 154 #define XEHPG_SC_INSTDONE XE_REG_MCR(0x7100) 155 #define XEHPG_SC_INSTDONE_EXTRA XE_REG_MCR(0x7104) 156 #define XEHPG_SC_INSTDONE_EXTRA2 XE_REG_MCR(0x7108) 157 158 #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 159 #define SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE REG_BIT(12) 160 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 161 162 #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 163 #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 164 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 165 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 166 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 167 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 168 169 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 170 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 171 172 #define XE2LPM_CCCHKNREG1 XE_REG(0x82a8) 173 174 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 175 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 176 177 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 178 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 179 180 #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 181 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 182 183 #define SQCNT1 XE_REG_MCR(0x8718) 184 #define XELPMP_SQCNT1 XE_REG(0x8718) 185 #define SQCNT1_PMON_ENABLE REG_BIT(30) 186 #define SQCNT1_OABPC REG_BIT(29) 187 #define ENFORCE_RAR REG_BIT(23) 188 189 #define XEHP_SQCM XE_REG_MCR(0x8724) 190 #define EN_32B_ACCESS REG_BIT(30) 191 192 #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 193 #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 194 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) 195 196 #define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) 197 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) 198 199 #define GSCPSMI_BASE XE_REG(0x880c) 200 201 #define CCCHKNREG1 XE_REG_MCR(0x8828) 202 #define L3CMPCTRL REG_BIT(23) 203 #define ENCOMPPERFFIX REG_BIT(18) 204 205 /* Fuse readout registers for GT */ 206 #define XEHP_FUSE4 XE_REG(0x9114) 207 #define CFEG_WMTP_DISABLE REG_BIT(20) 208 #define CCS_EN_MASK REG_GENMASK(19, 16) 209 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 210 211 #define MIRROR_FUSE3 XE_REG(0x9118) 212 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 213 #define L3BANK_PAIR_COUNT 4 214 #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4) 215 #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4) 216 #define L3BANK_MASK REG_GENMASK(3, 0) 217 #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0) 218 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 219 #define MAX_MSLICES 4 220 #define MEML3_EN_MASK REG_GENMASK(3, 0) 221 222 #define MIRROR_FUSE1 XE_REG(0x911c) 223 224 #define MIRROR_L3BANK_ENABLE XE_REG(0x9130) 225 #define XE3_L3BANK_ENABLE REG_GENMASK(31, 0) 226 227 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 228 #define XELP_EU_MASK REG_GENMASK(7, 0) 229 #define XELP_GT_SLICE_ENABLE XE_REG(0x9138) 230 #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 231 232 #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 233 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 234 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 235 236 #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 237 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 238 #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 239 #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 240 #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 241 242 #define GDRST XE_REG(0x941c) 243 #define GRDOM_GUC REG_BIT(3) 244 #define GRDOM_FULL REG_BIT(0) 245 246 #define MISCCPCTL XE_REG(0x9424) 247 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 248 249 #define UNSLCGCTL9430 XE_REG(0x9430) 250 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 251 252 #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 253 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 254 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 255 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 256 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 257 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 258 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 259 260 #define UNSLCGCTL9440 XE_REG(0x9440) 261 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 262 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 263 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 264 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 265 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 266 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 267 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 268 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 269 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 270 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 271 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 272 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 273 274 #define UNSLCGCTL9444 XE_REG(0x9444) 275 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 276 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 277 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 278 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 279 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 280 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 281 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 282 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 283 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 284 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 285 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 286 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 287 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 288 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 289 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 290 #define LTCDD_CLKGATE_DIS REG_BIT(10) 291 292 #define UNSLCGCTL9454 XE_REG(0x9454) 293 #define LSCFE_CLKGATE_DIS REG_BIT(4) 294 295 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 296 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 297 #define L3_CLKGATE_DIS REG_BIT(16) 298 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 299 #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 300 #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 301 #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 302 #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 303 304 #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 305 #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 306 307 #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 308 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 309 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 310 311 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 312 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 313 314 #define SSMCGCTL9530 XE_REG_MCR(0x9530) 315 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 316 317 #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 318 #define DFR_DISABLE REG_BIT(9) 319 320 #define RPNSWREQ XE_REG(0xa008) 321 #define REQ_RATIO_MASK REG_GENMASK(31, 23) 322 323 #define RP_CONTROL XE_REG(0xa024) 324 #define RPSWCTL_MASK REG_GENMASK(10, 9) 325 #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 326 #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 327 #define RC_CONTROL XE_REG(0xa090) 328 #define RC_CTL_HW_ENABLE REG_BIT(31) 329 #define RC_CTL_TO_MODE REG_BIT(28) 330 #define RC_CTL_RC6_ENABLE REG_BIT(18) 331 #define RC_STATE XE_REG(0xa094) 332 #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 333 #define MEDIA_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c4) 334 #define RENDER_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c8) 335 336 #define PMINTRMSK XE_REG(0xa168) 337 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 338 #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 339 340 #define FORCEWAKE_GT XE_REG(0xa188) 341 342 #define POWERGATE_ENABLE XE_REG(0xa210) 343 #define RENDER_POWERGATE_ENABLE REG_BIT(0) 344 #define MEDIA_POWERGATE_ENABLE REG_BIT(1) 345 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 346 #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 347 348 #define CTC_MODE XE_REG(0xa26c) 349 #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 350 #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0) 351 352 #define FORCEWAKE_RENDER XE_REG(0xa278) 353 354 #define POWERGATE_DOMAIN_STATUS XE_REG(0xa2a0) 355 #define MEDIA_SLICE3_AWAKE_STATUS REG_BIT(4) 356 #define MEDIA_SLICE2_AWAKE_STATUS REG_BIT(3) 357 #define MEDIA_SLICE1_AWAKE_STATUS REG_BIT(2) 358 #define RENDER_AWAKE_STATUS REG_BIT(1) 359 #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0) 360 361 #define MISC_STATUS_0 XE_REG(0xa500) 362 363 #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 364 #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 365 #define FORCEWAKE_GSC XE_REG(0xa618) 366 367 #define XELP_GARBCNTL XE_REG(0xb004) 368 #define XELP_BUS_HASH_CTL_BIT_EXC REG_BIT(7) 369 370 #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 371 #define XEHPC_OVRLSCCC REG_BIT(0) 372 373 #define LNCFCMOCS_REG_COUNT 32 374 #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 375 #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 376 #define L3_UPPER_LKUP_MASK REG_BIT(23) 377 #define L3_UPPER_GLBGO_MASK REG_BIT(22) 378 #define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20) 379 #define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17) 380 #define L3_UPPER_IDX_ESC_MASK REG_BIT(16) 381 #define L3_LKUP_MASK REG_BIT(7) 382 #define L3_LKUP(value) REG_FIELD_PREP(L3_LKUP_MASK, value) 383 #define L3_GLBGO_MASK REG_BIT(6) 384 #define L3_GLBGO(value) REG_FIELD_PREP(L3_GLBGO_MASK, value) 385 #define L3_CACHEABILITY_MASK REG_GENMASK(5, 4) 386 #define L3_CACHEABILITY(value) REG_FIELD_PREP(L3_CACHEABILITY_MASK, value) 387 #define L3_SCC_MASK REG_GENMASK(3, 1) 388 #define L3_SCC(value) REG_FIELD_PREP(L3_SCC_MASK, value) 389 #define L3_ESC_MASK REG_BIT(0) 390 #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value) 391 392 #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 393 #define XEHP_LNESPARE REG_BIT(19) 394 395 #define LSN_VC_REG2 XE_REG_MCR(0xb0c8) 396 #define LSN_LNI_WGT_MASK REG_GENMASK(31, 28) 397 #define LSN_LNI_WGT(value) REG_FIELD_PREP(LSN_LNI_WGT_MASK, value) 398 #define LSN_LNE_WGT_MASK REG_GENMASK(27, 24) 399 #define LSN_LNE_WGT(value) REG_FIELD_PREP(LSN_LNE_WGT_MASK, value) 400 #define LSN_DIM_X_WGT_MASK REG_GENMASK(23, 20) 401 #define LSN_DIM_X_WGT(value) REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value) 402 #define LSN_DIM_Y_WGT_MASK REG_GENMASK(19, 16) 403 #define LSN_DIM_Y_WGT(value) REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value) 404 #define LSN_DIM_Z_WGT_MASK REG_GENMASK(15, 12) 405 #define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value) 406 407 #define L3SQCREG2 XE_REG_MCR(0xb104) 408 #define COMPMEMRD256BOVRFETCHEN REG_BIT(20) 409 410 #define L3SQCREG3 XE_REG_MCR(0xb108) 411 #define COMPPWOVERFETCHEN REG_BIT(28) 412 413 #define SCRATCH3_LBCF XE_REG_MCR(0xb154) 414 #define RWFLUSHALLEN REG_BIT(17) 415 416 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 417 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 418 419 #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 420 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 421 422 #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 423 424 #define XE2_GLOBAL_INVAL XE_REG(0xb404) 425 426 #define XE2LPM_L3SQCREG2 XE_REG_MCR(0xb604) 427 428 #define XE2LPM_L3SQCREG3 XE_REG_MCR(0xb608) 429 430 #define XE2LPM_SCRATCH3_LBCF XE_REG_MCR(0xb654) 431 432 #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 433 434 #define XE2_TDF_CTRL XE_REG(0xb418) 435 #define TRANSIENT_FLUSH_REQUEST REG_BIT(0) 436 437 #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 438 #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 439 #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 440 #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 441 #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 442 #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 443 #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 444 #define FORCE_MISS_FTLB REG_BIT(3) 445 446 #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 447 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 448 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 449 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 450 451 #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 452 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 453 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 454 455 #define LMEM_CFG XE_REG(0xcf58) 456 #define LMEM_EN REG_BIT(31) 457 #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */ 458 459 #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 460 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 461 462 #define SAMPLER_INSTDONE XE_REG_MCR(0xe160) 463 #define ROW_INSTDONE XE_REG_MCR(0xe164) 464 465 #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 466 #define ENABLE_SMALLPL REG_BIT(15) 467 #define SMP_WAIT_FETCH_MERGING_COUNTER REG_GENMASK(11, 10) 468 #define SMP_FORCE_128B_OVERFETCH REG_FIELD_PREP(SMP_WAIT_FETCH_MERGING_COUNTER, 1) 469 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 470 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 471 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 472 473 #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 474 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 475 #define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6) 476 477 #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 478 #define DISABLE_ECC REG_BIT(5) 479 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 480 481 #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 482 #define DISABLE_GRF_CLEAR REG_BIT(13) 483 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 484 #define DISABLE_TDL_PUSH REG_BIT(9) 485 #define DIS_PICK_2ND_EU REG_BIT(7) 486 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 487 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 488 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 489 490 #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 491 #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) 492 #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 493 494 #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) 495 #define STK_ID_RESTRICT REG_BIT(12) 496 #define SLM_WMTP_RESTORE REG_BIT(11) 497 #define RES_CHK_SPR_DIS REG_BIT(6) 498 499 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 500 #define UGM_BACKUP_MODE REG_BIT(13) 501 #define MDQ_ARBITRATION_MODE REG_BIT(12) 502 #define STALL_DOP_GATING_DISABLE REG_BIT(5) 503 #define EARLY_EOT_DIS REG_BIT(1) 504 505 #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 506 #define DISABLE_READ_SUPPRESSION REG_BIT(15) 507 #define DISABLE_EARLY_READ REG_BIT(14) 508 #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 509 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 510 #define DISABLE_TDL_SVHS_GATING REG_BIT(1) 511 #define DISABLE_DOP_GATING REG_BIT(0) 512 513 #define RT_CTRL XE_REG_MCR(0xe530) 514 #define DIS_NULL_QUERY REG_BIT(10) 515 516 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) 517 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) 518 519 #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 520 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 521 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 522 523 #define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED) 524 #define QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE REG_BIT(12) 525 526 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 527 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 528 #define WR_REQ_CHAINING_DIS REG_BIT(26) 529 #define TGM_WRITE_EOM_FORCE REG_BIT(17) 530 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 531 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 532 533 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 534 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 535 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 536 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 537 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 538 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 539 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 540 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 541 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 542 543 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 544 #define COMP_CKN_IN REG_GENMASK(30, 29) 545 546 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 547 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 548 #define RCU_MODE_CCS_ENABLE REG_BIT(0) 549 550 /* 551 * Total of 4 cslices, where each cslice is in the form: 552 * [0-3] CCS ID 553 * [4-6] RSVD 554 * [7] Disabled 555 */ 556 #define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED) 557 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 558 #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 559 #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 560 #define CCS_MODE_CSLICE(cslice, ccs) \ 561 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 562 563 #define FORCEWAKE_ACK_GT XE_REG(0x130044) 564 565 /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */ 566 #define FORCEWAKE_KERNEL 0 567 #define FORCEWAKE_MT(bit) BIT(bit) 568 #define FORCEWAKE_MT_MASK(bit) BIT((bit) + 16) 569 570 #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 571 #define MTL_MEDIA_MC6 XE_REG(0x138048) 572 573 #define GT_CORE_STATUS XE_REG(0x138060) 574 #define RCN_MASK REG_GENMASK(2, 0) 575 #define GT_C0 0 576 #define GT_C6 3 577 578 #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 579 #define GT_GFX_RC6 XE_REG(0x138108) 580 581 #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 582 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 583 #define PROCHOT_MASK REG_BIT(0) 584 #define THERMAL_LIMIT_MASK REG_BIT(1) 585 #define RATL_MASK REG_BIT(5) 586 #define VR_THERMALERT_MASK REG_BIT(6) 587 #define VR_TDC_MASK REG_BIT(7) 588 #define POWER_LIMIT_4_MASK REG_BIT(8) 589 #define POWER_LIMIT_1_MASK REG_BIT(10) 590 #define POWER_LIMIT_2_MASK REG_BIT(11) 591 592 #define GT_PERF_STATUS XE_REG(0x1381b4) 593 #define VOLTAGE_MASK REG_GENMASK(10, 0) 594 595 #define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000) 596 597 #endif 598