1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _MACHINE_HYPERVISOR_H_ 31 #define _MACHINE_HYPERVISOR_H_ 32 33 /* 34 * These registers are only useful when in hypervisor context, 35 * e.g. specific to EL2, or controlling the hypervisor. 36 */ 37 38 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 39 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 40 /* Valid if HCR_EL2.E2H == 0 */ 41 #define CNTHCTL_EL1PCTEN (1 << 0) /* Allow physical counter access */ 42 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access */ 43 /* Valid if HCR_EL2.E2H == 1 */ 44 #define CNTHCTL_E2H_EL0PCTEN (1 << 0) /* Allow EL0 physical counter access */ 45 #define CNTHCTL_E2H_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 46 #define CNTHCTL_E2H_EL0VTEN (1 << 8) 47 #define CNTHCTL_E2H_EL0PTEN (1 << 9) 48 #define CNTHCTL_E2H_EL1PCTEN (1 << 10) /* Allow physical counter access */ 49 #define CNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer access */ 50 /* Unconditionally valid */ 51 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 52 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 53 54 /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */ 55 #define CNTPOFF_EL2_REG MRS_REG_ALT_NAME(CNTPOFF_EL2) 56 #define CNTPOFF_EL2_op0 3 57 #define CNTPOFF_EL2_op1 4 58 #define CNTPOFF_EL2_CRn 14 59 #define CNTPOFF_EL2_CRm 0 60 #define CNTPOFF_EL2_op2 6 61 62 /* CPTR_EL2 - Architecture feature trap register */ 63 /* Valid if HCR_EL2.E2H == 0 */ 64 #define CPTR_TRAP_ALL 0xc01037ff /* Enable all traps */ 65 #define CPTR_RES0 0x7fefc800 66 #define CPTR_RES1 0x000032ff 67 #define CPTR_TZ 0x00000100 68 #define CPTR_TFP 0x00000400 69 #define CPTR_TTA 0x00100000 70 /* Valid if HCR_EL2.E2H == 1 */ 71 #define CPTR_E2H_TRAP_ALL 0xd0000000 72 #define CPTR_E2H_ZPEN 0x00030000 73 #define CPTR_E2H_FPEN 0x00300000 74 #define CPTR_E2H_TTA 0x10000000 75 /* Unconditionally valid */ 76 #define CPTR_TCPAC 0x80000000 77 78 /* HCR_EL2 - Hypervisor Config Register */ 79 #define HCR_VM (UL(0x1) << 0) 80 #define HCR_SWIO (UL(0x1) << 1) 81 #define HCR_PTW (UL(0x1) << 2) 82 #define HCR_FMO (UL(0x1) << 3) 83 #define HCR_IMO (UL(0x1) << 4) 84 #define HCR_AMO (UL(0x1) << 5) 85 #define HCR_VF (UL(0x1) << 6) 86 #define HCR_VI (UL(0x1) << 7) 87 #define HCR_VSE (UL(0x1) << 8) 88 #define HCR_FB (UL(0x1) << 9) 89 #define HCR_BSU_MASK (UL(0x3) << 10) 90 #define HCR_BSU_IS (UL(0x1) << 10) 91 #define HCR_BSU_OS (UL(0x2) << 10) 92 #define HCR_BSU_FS (UL(0x3) << 10) 93 #define HCR_DC (UL(0x1) << 12) 94 #define HCR_TWI (UL(0x1) << 13) 95 #define HCR_TWE (UL(0x1) << 14) 96 #define HCR_TID0 (UL(0x1) << 15) 97 #define HCR_TID1 (UL(0x1) << 16) 98 #define HCR_TID2 (UL(0x1) << 17) 99 #define HCR_TID3 (UL(0x1) << 18) 100 #define HCR_TSC (UL(0x1) << 19) 101 #define HCR_TIDCP (UL(0x1) << 20) 102 #define HCR_TACR (UL(0x1) << 21) 103 #define HCR_TSW (UL(0x1) << 22) 104 #define HCR_TPCP (UL(0x1) << 23) 105 #define HCR_TPU (UL(0x1) << 24) 106 #define HCR_TTLB (UL(0x1) << 25) 107 #define HCR_TVM (UL(0x1) << 26) 108 #define HCR_TGE (UL(0x1) << 27) 109 #define HCR_TDZ (UL(0x1) << 28) 110 #define HCR_HCD (UL(0x1) << 29) 111 #define HCR_TRVM (UL(0x1) << 30) 112 #define HCR_RW (UL(0x1) << 31) 113 #define HCR_CD (UL(0x1) << 32) 114 #define HCR_ID (UL(0x1) << 33) 115 #define HCR_E2H (UL(0x1) << 34) 116 #define HCR_TLOR (UL(0x1) << 35) 117 #define HCR_TERR (UL(0x1) << 36) 118 #define HCR_TEA (UL(0x1) << 37) 119 #define HCR_MIOCNCE (UL(0x1) << 38) 120 /* Bit 39 is reserved */ 121 #define HCR_APK (UL(0x1) << 40) 122 #define HCR_API (UL(0x1) << 41) 123 #define HCR_NV (UL(0x1) << 42) 124 #define HCR_NV1 (UL(0x1) << 43) 125 #define HCR_AT (UL(0x1) << 44) 126 #define HCR_NV2 (UL(0x1) << 45) 127 #define HCR_FWB (UL(0x1) << 46) 128 #define HCR_FIEN (UL(0x1) << 47) 129 /* Bit 48 is reserved */ 130 #define HCR_TID4 (UL(0x1) << 49) 131 #define HCR_TICAB (UL(0x1) << 50) 132 #define HCR_AMVOFFEN (UL(0x1) << 51) 133 #define HCR_TOCU (UL(0x1) << 52) 134 #define HCR_EnSCXT (UL(0x1) << 53) 135 #define HCR_TTLBIS (UL(0x1) << 54) 136 #define HCR_TTLBOS (UL(0x1) << 55) 137 #define HCR_ATA (UL(0x1) << 56) 138 #define HCR_DCT (UL(0x1) << 57) 139 #define HCR_TID5 (UL(0x1) << 58) 140 #define HCR_TWEDEn (UL(0x1) << 59) 141 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 142 143 /* HCRX_EL2 - Extended Hypervisor Configuration Register */ 144 #define HCRX_EL2_REG MRS_REG_ALT_NAME(HCRX_EL2) 145 #define HCRX_EL2_op0 3 146 #define HCRX_EL2_op1 4 147 #define HCRX_EL2_CRn 1 148 #define HCRX_EL2_CRm 2 149 #define HCRX_EL2_op2 2 150 151 #define HCRX_EnAS0 (UL(0x1) << 0) 152 #define HCRX_EnALS (UL(0x1) << 1) 153 #define HCRX_EnASR (UL(0x1) << 2) 154 #define HCRX_FnXS (UL(0x1) << 3) 155 #define HCRX_FGTnXS (UL(0x1) << 4) 156 #define HCRX_SMPME (UL(0x1) << 5) 157 #define HCRX_TALLINT (UL(0x1) << 6) 158 #define HCRX_VINMI (UL(0x1) << 7) 159 #define HCRX_VFNMI (UL(0x1) << 8) 160 #define HCRX_CMOW (UL(0x1) << 9) 161 #define HCRX_MCE2 (UL(0x1) << 10) 162 #define HCRX_MSCEn (UL(0x1) << 11) 163 /* Bits 12 & 13 are reserved */ 164 #define HCRX_TCR2En (UL(0x1) << 14) 165 #define HCRX_SCTLR2En (UL(0x1) << 15) 166 #define HCRX_PTTWI (UL(0x1) << 16) 167 #define HCRX_D128En (UL(0x1) << 17) 168 #define HCRX_EnSNERR (UL(0x1) << 18) 169 #define HCRX_TMEA (UL(0x1) << 19) 170 #define HCRX_EnSDERR (UL(0x1) << 20) 171 #define HCRX_EnIDCP128 (UL(0x1) << 21) 172 #define HCRX_GCSEn (UL(0x1) << 22) 173 #define HCRX_EnFPM (UL(0x1) << 23) 174 #define HCRX_PACMEn (UL(0x1) << 24) 175 /* Bit 25 is reserved */ 176 #define HCRX_SRMASKEn (UL(0x1) << 26) 177 178 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 179 #define HPFAR_EL2_FIPA_SHIFT 4 180 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 181 #define HPFAR_EL2_FIPA_GET(x) \ 182 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) 183 /* HPFAR_EL2_FIPA holds the 4k page address */ 184 #define HPFAR_EL2_FIPA_ADDR(x) \ 185 (HPFAR_EL2_FIPA_GET(x) << 12) 186 /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ 187 #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) 188 189 /* ICC_SRE_EL2 */ 190 #define ICC_SRE_EL2_SRE (1UL << 0) 191 #define ICC_SRE_EL2_EN (1UL << 3) 192 193 /* SCTLR_EL2 - System Control Register */ 194 #define SCTLR_EL2_RES1 0x30c50830 195 #define SCTLR_EL2_M_SHIFT 0 196 #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) 197 #define SCTLR_EL2_A_SHIFT 1 198 #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) 199 #define SCTLR_EL2_C_SHIFT 2 200 #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) 201 #define SCTLR_EL2_SA_SHIFT 3 202 #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) 203 #define SCTLR_EL2_EOS_SHIFT 11 204 #define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT) 205 #define SCTLR_EL2_I_SHIFT 12 206 #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) 207 #define SCTLR_EL2_WXN_SHIFT 19 208 #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) 209 #define SCTLR_EL2_EIS_SHIFT 22 210 #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) 211 #define SCTLR_EL2_EE_SHIFT 25 212 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) 213 214 /* TCR_EL2 - Translation Control Register */ 215 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 216 #define TCR_EL2_T0SZ_SHIFT 0 217 #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) 218 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 219 /* Bits 7:6 are reserved */ 220 #define TCR_EL2_IRGN0_SHIFT 8 221 #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) 222 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) 223 #define TCR_EL2_ORGN0_SHIFT 10 224 #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) 225 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) 226 #define TCR_EL2_SH0_SHIFT 12 227 #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) 228 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) 229 #define TCR_EL2_TG0_SHIFT 14 230 #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) 231 #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) 232 #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) 233 #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) 234 #define TCR_EL2_PS_SHIFT 16 235 #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) 236 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) 237 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) 238 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) 239 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) 240 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) 241 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) 242 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) 243 #define TCR_EL2_HPD_SHIFT 24 244 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) 245 #define TCR_EL2_HWU59_SHIFT 25 246 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) 247 #define TCR_EL2_HWU60_SHIFT 26 248 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) 249 #define TCR_EL2_HWU61_SHIFT 27 250 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) 251 #define TCR_EL2_HWU62_SHIFT 28 252 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) 253 #define TCR_EL2_HWU \ 254 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) 255 256 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 257 #define VMPIDR_EL2_U 0x0000000040000000 258 #define VMPIDR_EL2_MT 0x0000000001000000 259 #define VMPIDR_EL2_RES1 0x0000000080000000 260 261 /* VTCR_EL2 - Virtualization Translation Control Register */ 262 #define VTCR_EL2_RES1 (0x1UL << 31) 263 #define VTCR_EL2_T0SZ_SHIFT 0 264 #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) 265 #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) 266 #define VTCR_EL2_SL0_SHIFT 6 267 #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) 268 #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) 269 #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) 270 #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) 271 #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) 272 #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) 273 #define VTCR_EL2_IRGN0_SHIFT 8 274 #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) 275 #define VTCR_EL2_ORGN0_SHIFT 10 276 #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) 277 #define VTCR_EL2_SH0_SHIFT 12 278 #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) 279 #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) 280 #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) 281 #define VTCR_EL2_TG0_SHIFT 14 282 #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) 283 #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) 284 #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) 285 #define VTCR_EL2_PS_SHIFT 16 286 #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) 287 #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) 288 #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) 289 #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) 290 #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) 291 #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) 292 #define VTCR_EL2_PS_52BIT (0x6UL << VTCR_EL2_PS_SHIFT) 293 #define VTCR_EL2_DS_SHIFT 32 294 #define VTCR_EL2_DS (0x1UL << VTCR_EL2_DS_SHIFT) 295 296 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 297 #define VTTBR_VMID_MASK 0xffff000000000000 298 #define VTTBR_VMID_SHIFT 48 299 /* Assumed to be 0 by locore.S */ 300 #define VTTBR_HOST 0x0000000000000000 301 302 /* MDCR_EL2 - Hyp Debug Control Register */ 303 #define MDCR_EL2_HPMN_MASK 0x1f 304 #define MDCR_EL2_HPMN_SHIFT 0 305 #define MDCR_EL2_TPMCR_SHIFT 5 306 #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) 307 #define MDCR_EL2_TPM_SHIFT 6 308 #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) 309 #define MDCR_EL2_HPME_SHIFT 7 310 #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) 311 #define MDCR_EL2_TDE_SHIFT 8 312 #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) 313 #define MDCR_EL2_TDA_SHIFT 9 314 #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) 315 #define MDCR_EL2_TDOSA_SHIFT 10 316 #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) 317 #define MDCR_EL2_TDRA_SHIFT 11 318 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) 319 #define MDCR_E2PB_SHIFT 12 320 #define MDCR_E2PB_MASK (0x3UL << MDCR_E2PB_SHIFT) 321 #define MDCR_TPMS_SHIFT 14 322 #define MDCR_TPMS (0x1UL << MDCR_TPMS_SHIFT) 323 #define MDCR_EnSPM_SHIFT 15 324 #define MDCR_EnSPM (0x1UL << MDCR_EnSPM_SHIFT) 325 #define MDCR_HPMD_SHIFT 17 326 #define MDCR_HPMD (0x1UL << MDCR_HPMD_SHIFT) 327 #define MDCR_TTRF_SHIFT 19 328 #define MDCR_TTRF (0x1UL << MDCR_TTRF_SHIFT) 329 #define MDCR_HCCD_SHIFT 23 330 #define MDCR_HCCD (0x1UL << MDCR_HCCD_SHIFT) 331 #define MDCR_E2TB_SHIFT 24 332 #define MDCR_E2TB_MASK (0x3UL << MDCR_E2TB_SHIFT) 333 #define MDCR_HLP_SHIFT 26 334 #define MDCR_HLP (0x1UL << MDCR_HLP_SHIFT) 335 #define MDCR_TDCC_SHIFT 27 336 #define MDCR_TDCC (0x1UL << MDCR_TDCC_SHIFT) 337 #define MDCR_MTPME_SHIFT 28 338 #define MDCR_MTPME (0x1UL << MDCR_MTPME_SHIFT) 339 #define MDCR_HPMFZO_SHIFT 29 340 #define MDCR_HPMFZO (0x1UL << MDCR_HPMFZO_SHIFT) 341 #define MDCR_PMSSE_SHIFT 30 342 #define MDCR_PMSSE_MASK (0x3UL << MDCR_PMSSE_SHIFT) 343 #define MDCR_HPMFZS_SHIFT 36 344 #define MDCR_HPMFZS (0x1UL << MDCR_HPMFZS_SHIFT) 345 #define MDCR_PMEE_SHIFT 40 346 #define MDCR_PMEE_MASK (0x3UL << MDCR_PMEE_SHIFT) 347 #define MDCR_EBWE_SHIFT 43 348 #define MDCR_EBWE (0x1UL << MDCR_EBWE_SHIFT) 349 350 #endif /* !_MACHINE_HYPERVISOR_H_ */ 351