1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 */
8
9 #include <linux/backlight.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14
15 #include <video/mipi_display.h>
16
17 #include <drm/drm_mipi_dsi.h>
18 #include <drm/drm_modes.h>
19 #include <drm/drm_panel.h>
20
21 #define OTM8009A_BACKLIGHT_DEFAULT 240
22 #define OTM8009A_BACKLIGHT_MAX 255
23
24 /* Manufacturer Command Set */
25 #define MCS_ADRSFT 0x0000 /* Address Shift Function */
26 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
27 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
28 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
29 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
30 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
31 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
32 #define MCS_NO_DOC1 0xC48A /* Command not documented */
33 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
34 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
35 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
36 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
37 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
38 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
39 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
40 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
41 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
42 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
43 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
44 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
45 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
46 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
47 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
48 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
49 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
50 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */
51 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
52 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
53 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
54 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */
55 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
56 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
57 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
58 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
59 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */
60 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
61 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
62
63 #define OTM8009A_HDISPLAY 480
64 #define OTM8009A_VDISPLAY 800
65
66 struct otm8009a {
67 struct device *dev;
68 struct drm_panel panel;
69 struct backlight_device *bl_dev;
70 struct gpio_desc *reset_gpio;
71 struct regulator *supply;
72 bool prepared;
73 };
74
75 static const struct drm_display_mode modes[] = {
76 { /* 50 Hz, preferred */
77 .clock = 29700,
78 .hdisplay = 480,
79 .hsync_start = 480 + 98,
80 .hsync_end = 480 + 98 + 32,
81 .htotal = 480 + 98 + 32 + 98,
82 .vdisplay = 800,
83 .vsync_start = 800 + 15,
84 .vsync_end = 800 + 15 + 10,
85 .vtotal = 800 + 15 + 10 + 14,
86 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
87 .width_mm = 52,
88 .height_mm = 86,
89 },
90 { /* 60 Hz */
91 .clock = 33000,
92 .hdisplay = 480,
93 .hsync_start = 480 + 70,
94 .hsync_end = 480 + 70 + 32,
95 .htotal = 480 + 70 + 32 + 72,
96 .vdisplay = 800,
97 .vsync_start = 800 + 15,
98 .vsync_end = 800 + 15 + 10,
99 .vtotal = 800 + 15 + 10 + 16,
100 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
101 .width_mm = 52,
102 .height_mm = 86,
103 },
104 };
105
panel_to_otm8009a(struct drm_panel * panel)106 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
107 {
108 return container_of(panel, struct otm8009a, panel);
109 }
110
111 #define dcs_write_cmd_at(ctx, cmd, seq...) \
112 ({ \
113 mipi_dsi_dcs_write_seq_multi(ctx, MCS_ADRSFT, (cmd) & 0xFF); \
114 mipi_dsi_dcs_write_seq_multi(ctx, (cmd) >> 8, seq); \
115 })
116
otm8009a_init_sequence(struct otm8009a * ctx)117 static int otm8009a_init_sequence(struct otm8009a *ctx)
118 {
119 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
120 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
121
122 /* Enter CMD2 */
123 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
124
125 /* Enter Orise Command2 */
126 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA2, 0x80, 0x09);
127
128 dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL, 0x30);
129 mipi_dsi_msleep(&dsi_ctx, 10);
130
131 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC1, 0x40);
132 mipi_dsi_msleep(&dsi_ctx, 10);
133
134 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL4 + 1, 0xA9);
135 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 1, 0x34);
136 dcs_write_cmd_at(&dsi_ctx, MCS_P_DRV_M, 0x50);
137 dcs_write_cmd_at(&dsi_ctx, MCS_VCOMDC, 0x4E);
138 dcs_write_cmd_at(&dsi_ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */
139 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 2, 0x01);
140 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 5, 0x34);
141 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 4, 0x33);
142 dcs_write_cmd_at(&dsi_ctx, MCS_GVDDSET, 0x79, 0x79);
143 dcs_write_cmd_at(&dsi_ctx, MCS_SD_CTRL + 1, 0x1B);
144 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 2, 0x83);
145 dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL + 1, 0x83);
146 dcs_write_cmd_at(&dsi_ctx, MCS_RGB_VID_SET, 0x0E);
147 dcs_write_cmd_at(&dsi_ctx, MCS_PANSET, 0x00, 0x01);
148
149 dcs_write_cmd_at(&dsi_ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
150 dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
151 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
152 dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
153 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
154 dcs_write_cmd_at(&dsi_ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
155 0x01, 0x02, 0x00, 0x00);
156
157 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC2, 0x00);
158
159 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
160 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
161 0, 0, 0, 0, 0);
162 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
163 0, 0, 0, 0, 0);
164 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
165 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
166 0, 0, 0, 0, 0);
167 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
168 4, 0, 0, 0, 0);
169 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
170 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
171 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
172
173 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
174 0x00, 0x00, 0x00, 0x00);
175 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
176 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
177 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
179 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
180 0x00, 0x00, 0x00, 0x00);
181 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
183 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
185
186 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 1, 0x66);
187
188 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC3, 0x06);
189
190 dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
191 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
192 0x01);
193 dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
194 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
195 0x01);
196
197 /* Exit CMD2 */
198 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
199
200 mipi_dsi_dcs_nop_multi(&dsi_ctx);
201
202 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
203 mipi_dsi_msleep(&dsi_ctx, 120);
204
205 /* Default portrait 480x800 rgb24 */
206 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
207
208 mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, OTM8009A_HDISPLAY - 1);
209
210 mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, OTM8009A_VDISPLAY - 1);
211
212 /* See otm8009a driver documentation for pixel format descriptions */
213 mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, MIPI_DCS_PIXEL_FMT_24BIT |
214 MIPI_DCS_PIXEL_FMT_24BIT << 4);
215
216 /* Disable CABC feature */
217 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
218
219 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
220
221 mipi_dsi_dcs_nop_multi(&dsi_ctx);
222
223 /* Send Command GRAM memory write (no parameters) */
224 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START);
225
226 /* Wait a short while to let the panel be ready before the 1st frame */
227 mipi_dsi_msleep(&dsi_ctx, 10);
228
229 return dsi_ctx.accum_err;
230 }
231
otm8009a_disable(struct drm_panel * panel)232 static int otm8009a_disable(struct drm_panel *panel)
233 {
234 struct otm8009a *ctx = panel_to_otm8009a(panel);
235 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
236 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
237
238 backlight_disable(ctx->bl_dev);
239
240 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
241 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
242 mipi_dsi_msleep(&dsi_ctx, 120);
243
244 return dsi_ctx.accum_err;
245 }
246
otm8009a_unprepare(struct drm_panel * panel)247 static int otm8009a_unprepare(struct drm_panel *panel)
248 {
249 struct otm8009a *ctx = panel_to_otm8009a(panel);
250
251 if (ctx->reset_gpio) {
252 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
253 msleep(20);
254 }
255
256 regulator_disable(ctx->supply);
257
258 ctx->prepared = false;
259
260 return 0;
261 }
262
otm8009a_prepare(struct drm_panel * panel)263 static int otm8009a_prepare(struct drm_panel *panel)
264 {
265 struct otm8009a *ctx = panel_to_otm8009a(panel);
266 int ret;
267
268 ret = regulator_enable(ctx->supply);
269 if (ret < 0) {
270 dev_err(panel->dev, "failed to enable supply: %d\n", ret);
271 return ret;
272 }
273
274 if (ctx->reset_gpio) {
275 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
276 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
277 msleep(20);
278 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
279 msleep(100);
280 }
281
282 ret = otm8009a_init_sequence(ctx);
283 if (ret)
284 return ret;
285
286 ctx->prepared = true;
287
288 return 0;
289 }
290
otm8009a_enable(struct drm_panel * panel)291 static int otm8009a_enable(struct drm_panel *panel)
292 {
293 struct otm8009a *ctx = panel_to_otm8009a(panel);
294
295 backlight_enable(ctx->bl_dev);
296
297 return 0;
298 }
299
otm8009a_get_modes(struct drm_panel * panel,struct drm_connector * connector)300 static int otm8009a_get_modes(struct drm_panel *panel,
301 struct drm_connector *connector)
302 {
303 struct drm_display_mode *mode;
304 unsigned int num_modes = ARRAY_SIZE(modes);
305 unsigned int i;
306
307 for (i = 0; i < num_modes; i++) {
308 mode = drm_mode_duplicate(connector->dev, &modes[i]);
309 if (!mode) {
310 dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
311 modes[i].hdisplay,
312 modes[i].vdisplay,
313 drm_mode_vrefresh(&modes[i]));
314 return -ENOMEM;
315 }
316
317 mode->type = DRM_MODE_TYPE_DRIVER;
318
319 /* Setting first mode as preferred */
320 if (!i)
321 mode->type |= DRM_MODE_TYPE_PREFERRED;
322
323 drm_mode_set_name(mode);
324 drm_mode_probed_add(connector, mode);
325 }
326
327 connector->display_info.width_mm = mode->width_mm;
328 connector->display_info.height_mm = mode->height_mm;
329
330 return num_modes;
331 }
332
333 static const struct drm_panel_funcs otm8009a_drm_funcs = {
334 .disable = otm8009a_disable,
335 .unprepare = otm8009a_unprepare,
336 .prepare = otm8009a_prepare,
337 .enable = otm8009a_enable,
338 .get_modes = otm8009a_get_modes,
339 };
340
341 /*
342 * DSI-BASED BACKLIGHT
343 */
344
otm8009a_backlight_update_status(struct backlight_device * bd)345 static int otm8009a_backlight_update_status(struct backlight_device *bd)
346 {
347 struct otm8009a *ctx = bl_get_data(bd);
348 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
349 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
350 u8 data[2];
351
352 if (!ctx->prepared) {
353 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n");
354 return -ENXIO;
355 }
356
357 if (bd->props.power <= BACKLIGHT_POWER_REDUCED) {
358 /* Power on the backlight with the requested brightness
359 * Note We can not use mipi_dsi_dcs_set_display_brightness()
360 * as otm8009a driver support only 8-bit brightness (1 param).
361 */
362 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
363 data[1] = bd->props.brightness;
364 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data));
365
366 /* set Brightness Control & Backlight on */
367 data[1] = 0x24;
368
369 } else {
370 /* Power off the backlight: set Brightness Control & Bl off */
371 data[1] = 0;
372 }
373
374 /* Update Brightness Control & Backlight */
375 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
376 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data));
377
378 return dsi_ctx.accum_err;
379 }
380
381 static const struct backlight_ops otm8009a_backlight_ops = {
382 .update_status = otm8009a_backlight_update_status,
383 };
384
otm8009a_probe(struct mipi_dsi_device * dsi)385 static int otm8009a_probe(struct mipi_dsi_device *dsi)
386 {
387 struct device *dev = &dsi->dev;
388 struct otm8009a *ctx;
389 int ret;
390
391 ctx = devm_drm_panel_alloc(dev, struct otm8009a, panel,
392 &otm8009a_drm_funcs,
393 DRM_MODE_CONNECTOR_DSI);
394 if (IS_ERR(ctx))
395 return PTR_ERR(ctx);
396
397 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
398 if (IS_ERR(ctx->reset_gpio)) {
399 dev_err(dev, "cannot get reset-gpio\n");
400 return PTR_ERR(ctx->reset_gpio);
401 }
402
403 ctx->supply = devm_regulator_get(dev, "power");
404 if (IS_ERR(ctx->supply)) {
405 ret = PTR_ERR(ctx->supply);
406 if (ret != -EPROBE_DEFER)
407 dev_err(dev, "failed to request regulator: %d\n", ret);
408 return ret;
409 }
410
411 mipi_dsi_set_drvdata(dsi, ctx);
412
413 ctx->dev = dev;
414
415 dsi->lanes = 2;
416 dsi->format = MIPI_DSI_FMT_RGB888;
417 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
418 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
419
420 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev),
421 dev, ctx,
422 &otm8009a_backlight_ops,
423 NULL);
424 if (IS_ERR(ctx->bl_dev)) {
425 ret = PTR_ERR(ctx->bl_dev);
426 dev_err(dev, "failed to register backlight: %d\n", ret);
427 return ret;
428 }
429
430 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;
431 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;
432 ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF;
433 ctx->bl_dev->props.type = BACKLIGHT_RAW;
434
435 drm_panel_add(&ctx->panel);
436
437 ret = mipi_dsi_attach(dsi);
438 if (ret < 0) {
439 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");
440 drm_panel_remove(&ctx->panel);
441 return ret;
442 }
443
444 return 0;
445 }
446
otm8009a_remove(struct mipi_dsi_device * dsi)447 static void otm8009a_remove(struct mipi_dsi_device *dsi)
448 {
449 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);
450
451 mipi_dsi_detach(dsi);
452 drm_panel_remove(&ctx->panel);
453 }
454
455 static const struct of_device_id orisetech_otm8009a_of_match[] = {
456 { .compatible = "orisetech,otm8009a" },
457 { }
458 };
459 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);
460
461 static struct mipi_dsi_driver orisetech_otm8009a_driver = {
462 .probe = otm8009a_probe,
463 .remove = otm8009a_remove,
464 .driver = {
465 .name = "panel-orisetech-otm8009a",
466 .of_match_table = orisetech_otm8009a_of_match,
467 },
468 };
469 module_mipi_dsi_driver(orisetech_otm8009a_driver);
470
471 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
472 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
473 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");
474 MODULE_LICENSE("GPL v2");
475