xref: /linux/drivers/rtc/rtc-ds1307.c (revision d2eedaa3909be9102d648a4a0a50ccf64f96c54f)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4  *
5  *  Copyright (C) 2005 James Chapman (ds1337 core)
6  *  Copyright (C) 2006 David Brownell
7  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9  */
10 
11 #include <linux/bcd.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/kstrtox.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/property.h>
18 #include <linux/rtc/ds1307.h>
19 #include <linux/rtc.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/hwmon.h>
23 #include <linux/hwmon-sysfs.h>
24 #include <linux/clk-provider.h>
25 #include <linux/regmap.h>
26 #include <linux/watchdog.h>
27 
28 /*
29  * We can't determine type by probing, but if we expect pre-Linux code
30  * to have set the chip up as a clock (turning on the oscillator and
31  * setting the date and time), Linux can ignore the non-clock features.
32  * That's a natural job for a factory or repair bench.
33  */
34 enum ds_type {
35 	unknown_ds_type, /* always first and 0 */
36 	ds_1307,
37 	ds_1308,
38 	ds_1337,
39 	ds_1338,
40 	ds_1339,
41 	ds_1340,
42 	ds_1341,
43 	ds_1388,
44 	ds_3231,
45 	m41t0,
46 	m41t00,
47 	m41t11,
48 	mcp794xx,
49 	rx_8025,
50 	rx_8130,
51 	last_ds_type /* always last */
52 	/* rs5c372 too?  different address... */
53 };
54 
55 /* RTC registers don't differ much, except for the century flag */
56 #define DS1307_REG_SECS		0x00	/* 00-59 */
57 #	define DS1307_BIT_CH		0x80
58 #	define DS1340_BIT_nEOSC		0x80
59 #	define MCP794XX_BIT_ST		0x80
60 #define DS1307_REG_MIN		0x01	/* 00-59 */
61 #	define M41T0_BIT_OF		0x80
62 #define DS1307_REG_HOUR		0x02	/* 00-23, or 1-12{am,pm} */
63 #	define DS1307_BIT_12HR		0x40	/* in REG_HOUR */
64 #	define DS1307_BIT_PM		0x20	/* in REG_HOUR */
65 #	define DS1340_BIT_CENTURY_EN	0x80	/* in REG_HOUR */
66 #	define DS1340_BIT_CENTURY	0x40	/* in REG_HOUR */
67 #define DS1307_REG_WDAY		0x03	/* 01-07 */
68 #	define MCP794XX_BIT_OSCRUN	BIT(5)
69 #	define MCP794XX_BIT_VBATEN	0x08
70 #define DS1307_REG_MDAY		0x04	/* 01-31 */
71 #define DS1307_REG_MONTH	0x05	/* 01-12 */
72 #	define DS1337_BIT_CENTURY	0x80	/* in REG_MONTH */
73 #define DS1307_REG_YEAR		0x06	/* 00-99 */
74 
75 /*
76  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
77  * start at 7, and they differ a LOT. Only control and status matter for
78  * basic RTC date and time functionality; be careful using them.
79  */
80 #define DS1307_REG_CONTROL	0x07		/* or ds1338 */
81 #	define DS1307_BIT_OUT		0x80
82 #	define DS1338_BIT_OSF		0x20
83 #	define DS1307_BIT_SQWE		0x10
84 #	define DS1307_BIT_RS1		0x02
85 #	define DS1307_BIT_RS0		0x01
86 #define DS1337_REG_CONTROL	0x0e
87 #	define DS1337_BIT_nEOSC		0x80
88 #	define DS1339_BIT_BBSQI		0x20
89 #	define DS3231_BIT_BBSQW		0x40 /* same as BBSQI */
90 #	define DS1337_BIT_RS2		0x10
91 #	define DS1337_BIT_RS1		0x08
92 #	define DS1337_BIT_INTCN		0x04
93 #	define DS1337_BIT_A2IE		0x02
94 #	define DS1337_BIT_A1IE		0x01
95 #define DS1340_REG_CONTROL	0x07
96 #	define DS1340_BIT_OUT		0x80
97 #	define DS1340_BIT_FT		0x40
98 #	define DS1340_BIT_CALIB_SIGN	0x20
99 #	define DS1340_M_CALIBRATION	0x1f
100 #define DS1340_REG_FLAG		0x09
101 #	define DS1340_BIT_OSF		0x80
102 #define DS1337_REG_STATUS	0x0f
103 #	define DS1337_BIT_OSF		0x80
104 #	define DS3231_BIT_EN32KHZ	0x08
105 #	define DS1337_BIT_A2I		0x02
106 #	define DS1337_BIT_A1I		0x01
107 #define DS1339_REG_ALARM1_SECS	0x07
108 
109 #define DS13XX_TRICKLE_CHARGER_MAGIC	0xa0
110 
111 #define RX8025_REG_CTRL1	0x0e
112 #	define RX8025_BIT_2412		0x20
113 #define RX8025_REG_CTRL2	0x0f
114 #	define RX8025_BIT_PON		0x10
115 #	define RX8025_BIT_VDET		0x40
116 #	define RX8025_BIT_XST		0x20
117 
118 #define RX8130_REG_ALARM_MIN		0x17
119 #define RX8130_REG_ALARM_HOUR		0x18
120 #define RX8130_REG_ALARM_WEEK_OR_DAY	0x19
121 #define RX8130_REG_EXTENSION		0x1c
122 #define RX8130_REG_EXTENSION_WADA	BIT(3)
123 #define RX8130_REG_FLAG			0x1d
124 #define RX8130_REG_FLAG_VLF		BIT(1)
125 #define RX8130_REG_FLAG_AF		BIT(3)
126 #define RX8130_REG_CONTROL0		0x1e
127 #define RX8130_REG_CONTROL0_AIE		BIT(3)
128 #define RX8130_REG_CONTROL1		0x1f
129 #define RX8130_REG_CONTROL1_INIEN	BIT(4)
130 #define RX8130_REG_CONTROL1_CHGEN	BIT(5)
131 
132 #define MCP794XX_REG_CONTROL		0x07
133 #	define MCP794XX_BIT_ALM0_EN	0x10
134 #	define MCP794XX_BIT_ALM1_EN	0x20
135 #define MCP794XX_REG_ALARM0_BASE	0x0a
136 #define MCP794XX_REG_ALARM0_CTRL	0x0d
137 #define MCP794XX_REG_ALARM1_BASE	0x11
138 #define MCP794XX_REG_ALARM1_CTRL	0x14
139 #	define MCP794XX_BIT_ALMX_IF	BIT(3)
140 #	define MCP794XX_BIT_ALMX_C0	BIT(4)
141 #	define MCP794XX_BIT_ALMX_C1	BIT(5)
142 #	define MCP794XX_BIT_ALMX_C2	BIT(6)
143 #	define MCP794XX_BIT_ALMX_POL	BIT(7)
144 #	define MCP794XX_MSK_ALMX_MATCH	(MCP794XX_BIT_ALMX_C0 | \
145 					 MCP794XX_BIT_ALMX_C1 | \
146 					 MCP794XX_BIT_ALMX_C2)
147 
148 #define M41TXX_REG_CONTROL	0x07
149 #	define M41TXX_BIT_OUT		BIT(7)
150 #	define M41TXX_BIT_FT		BIT(6)
151 #	define M41TXX_BIT_CALIB_SIGN	BIT(5)
152 #	define M41TXX_M_CALIBRATION	GENMASK(4, 0)
153 
154 #define DS1388_REG_WDOG_HUN_SECS	0x08
155 #define DS1388_REG_WDOG_SECS		0x09
156 #define DS1388_REG_FLAG			0x0b
157 #	define DS1388_BIT_WF		BIT(6)
158 #	define DS1388_BIT_OSF		BIT(7)
159 #define DS1388_REG_CONTROL		0x0c
160 #	define DS1388_BIT_RST		BIT(0)
161 #	define DS1388_BIT_WDE		BIT(1)
162 #	define DS1388_BIT_nEOSC		BIT(7)
163 
164 /* negative offset step is -2.034ppm */
165 #define M41TXX_NEG_OFFSET_STEP_PPB	2034
166 /* positive offset step is +4.068ppm */
167 #define M41TXX_POS_OFFSET_STEP_PPB	4068
168 /* Min and max values supported with 'offset' interface by M41TXX */
169 #define M41TXX_MIN_OFFSET	((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
170 #define M41TXX_MAX_OFFSET	((31) * M41TXX_POS_OFFSET_STEP_PPB)
171 
172 struct ds1307 {
173 	enum ds_type		type;
174 	struct device		*dev;
175 	struct regmap		*regmap;
176 	const char		*name;
177 	struct rtc_device	*rtc;
178 #ifdef CONFIG_COMMON_CLK
179 	struct clk_hw		clks[2];
180 #endif
181 };
182 
183 struct chip_desc {
184 	unsigned		alarm:1;
185 	u16			nvram_offset;
186 	u16			nvram_size;
187 	u8			offset; /* register's offset */
188 	u8			century_reg;
189 	u8			century_enable_bit;
190 	u8			century_bit;
191 	u8			bbsqi_bit;
192 	irq_handler_t		irq_handler;
193 	const struct rtc_class_ops *rtc_ops;
194 	u16			trickle_charger_reg;
195 	u8			(*do_trickle_setup)(struct ds1307 *, u32,
196 						    bool);
197 	/* Does the RTC require trickle-resistor-ohms to select the value of
198 	 * the resistor between Vcc and Vbackup?
199 	 */
200 	bool			requires_trickle_resistor;
201 	/* Some RTC's batteries and supercaps were charged by default, others
202 	 * allow charging but were not configured previously to do so.
203 	 * Remember this behavior to stay backwards compatible.
204 	 */
205 	bool			charge_default;
206 };
207 
208 static const struct chip_desc chips[last_ds_type];
209 
ds1307_get_time(struct device * dev,struct rtc_time * t)210 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
211 {
212 	struct ds1307	*ds1307 = dev_get_drvdata(dev);
213 	int		tmp, ret;
214 	const struct chip_desc *chip = &chips[ds1307->type];
215 	u8 regs[7];
216 
217 	if (ds1307->type == rx_8130) {
218 		unsigned int regflag;
219 		ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
220 		if (ret) {
221 			dev_err(dev, "%s error %d\n", "read", ret);
222 			return ret;
223 		}
224 
225 		if (regflag & RX8130_REG_FLAG_VLF) {
226 			dev_warn_once(dev, "oscillator failed, set time!\n");
227 			return -EINVAL;
228 		}
229 	}
230 
231 	/* read the RTC date and time registers all at once */
232 	ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
233 			       sizeof(regs));
234 	if (ret) {
235 		dev_err(dev, "%s error %d\n", "read", ret);
236 		return ret;
237 	}
238 
239 	dev_dbg(dev, "%s: %7ph\n", "read", regs);
240 
241 	/* if oscillator fail bit is set, no data can be trusted */
242 	if (ds1307->type == m41t0 &&
243 	    regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
244 		dev_warn_once(dev, "oscillator failed, set time!\n");
245 		return -EINVAL;
246 	} else if (ds1307->type == mcp794xx &&
247 	    !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) {
248 		dev_warn_once(dev, "oscillator failed, set time!\n");
249 		return -EINVAL;
250 	}
251 
252 	tmp = regs[DS1307_REG_SECS];
253 	switch (ds1307->type) {
254 	case ds_1307:
255 	case m41t0:
256 	case m41t00:
257 	case m41t11:
258 		if (tmp & DS1307_BIT_CH)
259 			return -EINVAL;
260 		break;
261 	case ds_1308:
262 	case ds_1338:
263 		if (tmp & DS1307_BIT_CH)
264 			return -EINVAL;
265 
266 		ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
267 		if (ret)
268 			return ret;
269 		if (tmp & DS1338_BIT_OSF)
270 			return -EINVAL;
271 		break;
272 	case ds_1340:
273 		if (tmp & DS1340_BIT_nEOSC)
274 			return -EINVAL;
275 
276 		ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
277 		if (ret)
278 			return ret;
279 		if (tmp & DS1340_BIT_OSF)
280 			return -EINVAL;
281 		break;
282 	case ds_1341:
283 		ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &tmp);
284 		if (ret)
285 			return ret;
286 		if (tmp & DS1337_BIT_OSF)
287 			return -EINVAL;
288 		break;
289 	case ds_1388:
290 		ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
291 		if (ret)
292 			return ret;
293 		if (tmp & DS1388_BIT_OSF)
294 			return -EINVAL;
295 		break;
296 	case mcp794xx:
297 		if (!(tmp & MCP794XX_BIT_ST))
298 			return -EINVAL;
299 
300 		break;
301 	default:
302 		break;
303 	}
304 
305 	t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
306 	t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
307 	tmp = regs[DS1307_REG_HOUR] & 0x3f;
308 	t->tm_hour = bcd2bin(tmp);
309 	/* rx8130 is bit position, not BCD */
310 	if (ds1307->type == rx_8130)
311 		t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
312 	else
313 		t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
314 	t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
315 	tmp = regs[DS1307_REG_MONTH] & 0x1f;
316 	t->tm_mon = bcd2bin(tmp) - 1;
317 	t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
318 
319 	if (regs[chip->century_reg] & chip->century_bit &&
320 	    IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
321 		t->tm_year += 100;
322 
323 	dev_dbg(dev, "%s secs=%d, mins=%d, "
324 		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
325 		"read", t->tm_sec, t->tm_min,
326 		t->tm_hour, t->tm_mday,
327 		t->tm_mon, t->tm_year, t->tm_wday);
328 
329 	return 0;
330 }
331 
ds1307_set_time(struct device * dev,struct rtc_time * t)332 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
333 {
334 	struct ds1307	*ds1307 = dev_get_drvdata(dev);
335 	const struct chip_desc *chip = &chips[ds1307->type];
336 	int		result;
337 	int		tmp;
338 	u8		regs[7];
339 
340 	dev_dbg(dev, "%s secs=%d, mins=%d, "
341 		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
342 		"write", t->tm_sec, t->tm_min,
343 		t->tm_hour, t->tm_mday,
344 		t->tm_mon, t->tm_year, t->tm_wday);
345 
346 	if (t->tm_year < 100)
347 		return -EINVAL;
348 
349 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
350 	if (t->tm_year > (chip->century_bit ? 299 : 199))
351 		return -EINVAL;
352 #else
353 	if (t->tm_year > 199)
354 		return -EINVAL;
355 #endif
356 
357 	regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
358 	regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
359 	regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
360 	/* rx8130 is bit position, not BCD */
361 	if (ds1307->type == rx_8130)
362 		regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
363 	else
364 		regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
365 	regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
366 	regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
367 
368 	/* assume 20YY not 19YY */
369 	tmp = t->tm_year % 100;
370 	regs[DS1307_REG_YEAR] = bin2bcd(tmp);
371 
372 	if (chip->century_enable_bit)
373 		regs[chip->century_reg] |= chip->century_enable_bit;
374 	if (t->tm_year > 199 && chip->century_bit)
375 		regs[chip->century_reg] |= chip->century_bit;
376 
377 	switch (ds1307->type) {
378 	case ds_1308:
379 	case ds_1338:
380 		regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
381 				   DS1338_BIT_OSF, 0);
382 		break;
383 	case ds_1340:
384 		regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
385 				   DS1340_BIT_OSF, 0);
386 		break;
387 	case ds_1341:
388 		regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
389 				   DS1337_BIT_OSF, 0);
390 		break;
391 	case ds_1388:
392 		regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
393 				   DS1388_BIT_OSF, 0);
394 		break;
395 	case mcp794xx:
396 		/*
397 		 * these bits were cleared when preparing the date/time
398 		 * values and need to be set again before writing the
399 		 * regsfer out to the device.
400 		 */
401 		regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
402 		regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
403 		break;
404 	default:
405 		break;
406 	}
407 
408 	dev_dbg(dev, "%s: %7ph\n", "write", regs);
409 
410 	result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
411 				   sizeof(regs));
412 	if (result) {
413 		dev_err(dev, "%s error %d\n", "write", result);
414 		return result;
415 	}
416 
417 	if (ds1307->type == rx_8130) {
418 		/* clear Voltage Loss Flag as data is available now */
419 		result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
420 				      ~(u8)RX8130_REG_FLAG_VLF);
421 		if (result) {
422 			dev_err(dev, "%s error %d\n", "write", result);
423 			return result;
424 		}
425 	}
426 
427 	return 0;
428 }
429 
ds1337_read_alarm(struct device * dev,struct rtc_wkalrm * t)430 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
431 {
432 	struct ds1307		*ds1307 = dev_get_drvdata(dev);
433 	int			ret;
434 	u8			regs[9];
435 
436 	/* read all ALARM1, ALARM2, and status registers at once */
437 	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
438 			       regs, sizeof(regs));
439 	if (ret) {
440 		dev_err(dev, "%s error %d\n", "alarm read", ret);
441 		return ret;
442 	}
443 
444 	dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
445 		&regs[0], &regs[4], &regs[7]);
446 
447 	/*
448 	 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
449 	 * and that all four fields are checked matches
450 	 */
451 	t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
452 	t->time.tm_min = bcd2bin(regs[1] & 0x7f);
453 	t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
454 	t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
455 
456 	/* ... and status */
457 	t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
458 	t->pending = !!(regs[8] & DS1337_BIT_A1I);
459 
460 	dev_dbg(dev, "%s secs=%d, mins=%d, "
461 		"hours=%d, mday=%d, enabled=%d, pending=%d\n",
462 		"alarm read", t->time.tm_sec, t->time.tm_min,
463 		t->time.tm_hour, t->time.tm_mday,
464 		t->enabled, t->pending);
465 
466 	return 0;
467 }
468 
ds1337_set_alarm(struct device * dev,struct rtc_wkalrm * t)469 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
470 {
471 	struct ds1307		*ds1307 = dev_get_drvdata(dev);
472 	unsigned char		regs[9];
473 	u8			control, status;
474 	int			ret;
475 
476 	dev_dbg(dev, "%s secs=%d, mins=%d, "
477 		"hours=%d, mday=%d, enabled=%d, pending=%d\n",
478 		"alarm set", t->time.tm_sec, t->time.tm_min,
479 		t->time.tm_hour, t->time.tm_mday,
480 		t->enabled, t->pending);
481 
482 	/* read current status of both alarms and the chip */
483 	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
484 			       sizeof(regs));
485 	if (ret) {
486 		dev_err(dev, "%s error %d\n", "alarm write", ret);
487 		return ret;
488 	}
489 	control = regs[7];
490 	status = regs[8];
491 
492 	dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
493 		&regs[0], &regs[4], control, status);
494 
495 	/* set ALARM1, using 24 hour and day-of-month modes */
496 	regs[0] = bin2bcd(t->time.tm_sec);
497 	regs[1] = bin2bcd(t->time.tm_min);
498 	regs[2] = bin2bcd(t->time.tm_hour);
499 	regs[3] = bin2bcd(t->time.tm_mday);
500 
501 	/* set ALARM2 to non-garbage */
502 	regs[4] = 0;
503 	regs[5] = 0;
504 	regs[6] = 0;
505 
506 	/* disable alarms */
507 	regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
508 	regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
509 
510 	ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
511 				sizeof(regs));
512 	if (ret) {
513 		dev_err(dev, "can't set alarm time\n");
514 		return ret;
515 	}
516 
517 	/* optionally enable ALARM1 */
518 	if (t->enabled) {
519 		dev_dbg(dev, "alarm IRQ armed\n");
520 		regs[7] |= DS1337_BIT_A1IE;	/* only ALARM1 is used */
521 		regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
522 	}
523 
524 	return 0;
525 }
526 
ds1307_alarm_irq_enable(struct device * dev,unsigned int enabled)527 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
528 {
529 	struct ds1307		*ds1307 = dev_get_drvdata(dev);
530 
531 	return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
532 				  DS1337_BIT_A1IE,
533 				  enabled ? DS1337_BIT_A1IE : 0);
534 }
535 
do_trickle_setup_ds1339(struct ds1307 * ds1307,u32 ohms,bool diode)536 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
537 {
538 	u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
539 		DS1307_TRICKLE_CHARGER_NO_DIODE;
540 
541 	setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
542 
543 	switch (ohms) {
544 	case 250:
545 		setup |= DS1307_TRICKLE_CHARGER_250_OHM;
546 		break;
547 	case 2000:
548 		setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
549 		break;
550 	case 4000:
551 		setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
552 		break;
553 	default:
554 		dev_warn(ds1307->dev,
555 			 "Unsupported ohm value %u in dt\n", ohms);
556 		return 0;
557 	}
558 	return setup;
559 }
560 
do_trickle_setup_rx8130(struct ds1307 * ds1307,u32 ohms,bool diode)561 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
562 {
563 	/* make sure that the backup battery is enabled */
564 	u8 setup = RX8130_REG_CONTROL1_INIEN;
565 	if (diode)
566 		setup |= RX8130_REG_CONTROL1_CHGEN;
567 
568 	return setup;
569 }
570 
rx8130_irq(int irq,void * dev_id)571 static irqreturn_t rx8130_irq(int irq, void *dev_id)
572 {
573 	struct ds1307           *ds1307 = dev_id;
574 	u8 ctl[3];
575 	int ret;
576 
577 	rtc_lock(ds1307->rtc);
578 
579 	/* Read control registers. */
580 	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
581 			       sizeof(ctl));
582 	if (ret < 0)
583 		goto out;
584 	if (!(ctl[1] & RX8130_REG_FLAG_AF))
585 		goto out;
586 	ctl[1] &= ~RX8130_REG_FLAG_AF;
587 	ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
588 
589 	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
590 				sizeof(ctl));
591 	if (ret < 0)
592 		goto out;
593 
594 	rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
595 
596 out:
597 	rtc_unlock(ds1307->rtc);
598 
599 	return IRQ_HANDLED;
600 }
601 
rx8130_read_alarm(struct device * dev,struct rtc_wkalrm * t)602 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
603 {
604 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
605 	u8 ald[3], ctl[3];
606 	int ret;
607 
608 	/* Read alarm registers. */
609 	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
610 			       sizeof(ald));
611 	if (ret < 0)
612 		return ret;
613 
614 	/* Read control registers. */
615 	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
616 			       sizeof(ctl));
617 	if (ret < 0)
618 		return ret;
619 
620 	t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
621 	t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
622 
623 	/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
624 	t->time.tm_sec = -1;
625 	t->time.tm_min = bcd2bin(ald[0] & 0x7f);
626 	t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
627 	t->time.tm_wday = -1;
628 	t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
629 	t->time.tm_mon = -1;
630 	t->time.tm_year = -1;
631 	t->time.tm_yday = -1;
632 	t->time.tm_isdst = -1;
633 
634 	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
635 		__func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
636 		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
637 
638 	return 0;
639 }
640 
rx8130_set_alarm(struct device * dev,struct rtc_wkalrm * t)641 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
642 {
643 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
644 	u8 ald[3], ctl[3];
645 	int ret;
646 
647 	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
648 		"enabled=%d pending=%d\n", __func__,
649 		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
650 		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
651 		t->enabled, t->pending);
652 
653 	/* Read control registers. */
654 	ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
655 			       sizeof(ctl));
656 	if (ret < 0)
657 		return ret;
658 
659 	ctl[0] &= RX8130_REG_EXTENSION_WADA;
660 	ctl[1] &= ~RX8130_REG_FLAG_AF;
661 	ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
662 
663 	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
664 				sizeof(ctl));
665 	if (ret < 0)
666 		return ret;
667 
668 	/* Hardware alarm precision is 1 minute! */
669 	ald[0] = bin2bcd(t->time.tm_min);
670 	ald[1] = bin2bcd(t->time.tm_hour);
671 	ald[2] = bin2bcd(t->time.tm_mday);
672 
673 	ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
674 				sizeof(ald));
675 	if (ret < 0)
676 		return ret;
677 
678 	if (!t->enabled)
679 		return 0;
680 
681 	ctl[2] |= RX8130_REG_CONTROL0_AIE;
682 
683 	return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
684 }
685 
rx8130_alarm_irq_enable(struct device * dev,unsigned int enabled)686 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
687 {
688 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
689 	int ret, reg;
690 
691 	ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
692 	if (ret < 0)
693 		return ret;
694 
695 	if (enabled)
696 		reg |= RX8130_REG_CONTROL0_AIE;
697 	else
698 		reg &= ~RX8130_REG_CONTROL0_AIE;
699 
700 	return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
701 }
702 
mcp794xx_irq(int irq,void * dev_id)703 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
704 {
705 	struct ds1307           *ds1307 = dev_id;
706 	struct mutex            *lock = &ds1307->rtc->ops_lock;
707 	int reg, ret;
708 
709 	mutex_lock(lock);
710 
711 	/* Check and clear alarm 0 interrupt flag. */
712 	ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
713 	if (ret)
714 		goto out;
715 	if (!(reg & MCP794XX_BIT_ALMX_IF))
716 		goto out;
717 	reg &= ~MCP794XX_BIT_ALMX_IF;
718 	ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
719 	if (ret)
720 		goto out;
721 
722 	/* Disable alarm 0. */
723 	ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
724 				 MCP794XX_BIT_ALM0_EN, 0);
725 	if (ret)
726 		goto out;
727 
728 	rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
729 
730 out:
731 	mutex_unlock(lock);
732 
733 	return IRQ_HANDLED;
734 }
735 
mcp794xx_read_alarm(struct device * dev,struct rtc_wkalrm * t)736 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
737 {
738 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
739 	u8 regs[10];
740 	int ret;
741 
742 	/* Read control and alarm 0 registers. */
743 	ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
744 			       sizeof(regs));
745 	if (ret)
746 		return ret;
747 
748 	t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
749 
750 	/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
751 	t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
752 	t->time.tm_min = bcd2bin(regs[4] & 0x7f);
753 	t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
754 	t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
755 	t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
756 	t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
757 	t->time.tm_year = -1;
758 	t->time.tm_yday = -1;
759 	t->time.tm_isdst = -1;
760 
761 	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
762 		"enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
763 		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
764 		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
765 		!!(regs[6] & MCP794XX_BIT_ALMX_POL),
766 		!!(regs[6] & MCP794XX_BIT_ALMX_IF),
767 		(regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
768 
769 	return 0;
770 }
771 
772 /*
773  * We may have a random RTC weekday, therefore calculate alarm weekday based
774  * on current weekday we read from the RTC timekeeping regs
775  */
mcp794xx_alm_weekday(struct device * dev,struct rtc_time * tm_alarm)776 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
777 {
778 	struct rtc_time tm_now;
779 	int days_now, days_alarm, ret;
780 
781 	ret = ds1307_get_time(dev, &tm_now);
782 	if (ret)
783 		return ret;
784 
785 	days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
786 	days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
787 
788 	return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
789 }
790 
mcp794xx_set_alarm(struct device * dev,struct rtc_wkalrm * t)791 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
792 {
793 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
794 	unsigned char regs[10];
795 	int wday, ret;
796 
797 	wday = mcp794xx_alm_weekday(dev, &t->time);
798 	if (wday < 0)
799 		return wday;
800 
801 	dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
802 		"enabled=%d pending=%d\n", __func__,
803 		t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
804 		t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
805 		t->enabled, t->pending);
806 
807 	/* Read control and alarm 0 registers. */
808 	ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
809 			       sizeof(regs));
810 	if (ret)
811 		return ret;
812 
813 	/* Set alarm 0, using 24-hour and day-of-month modes. */
814 	regs[3] = bin2bcd(t->time.tm_sec);
815 	regs[4] = bin2bcd(t->time.tm_min);
816 	regs[5] = bin2bcd(t->time.tm_hour);
817 	regs[6] = wday;
818 	regs[7] = bin2bcd(t->time.tm_mday);
819 	regs[8] = bin2bcd(t->time.tm_mon + 1);
820 
821 	/* Clear the alarm 0 interrupt flag. */
822 	regs[6] &= ~MCP794XX_BIT_ALMX_IF;
823 	/* Set alarm match: second, minute, hour, day, date, month. */
824 	regs[6] |= MCP794XX_MSK_ALMX_MATCH;
825 	/* Disable interrupt. We will not enable until completely programmed */
826 	regs[0] &= ~MCP794XX_BIT_ALM0_EN;
827 
828 	ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
829 				sizeof(regs));
830 	if (ret)
831 		return ret;
832 
833 	if (!t->enabled)
834 		return 0;
835 	regs[0] |= MCP794XX_BIT_ALM0_EN;
836 	return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
837 }
838 
mcp794xx_alarm_irq_enable(struct device * dev,unsigned int enabled)839 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
840 {
841 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
842 
843 	return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
844 				  MCP794XX_BIT_ALM0_EN,
845 				  enabled ? MCP794XX_BIT_ALM0_EN : 0);
846 }
847 
m41txx_rtc_read_offset(struct device * dev,long * offset)848 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
849 {
850 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
851 	unsigned int ctrl_reg;
852 	u8 val;
853 
854 	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
855 
856 	val = ctrl_reg & M41TXX_M_CALIBRATION;
857 
858 	/* check if positive */
859 	if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
860 		*offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
861 	else
862 		*offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
863 
864 	return 0;
865 }
866 
m41txx_rtc_set_offset(struct device * dev,long offset)867 static int m41txx_rtc_set_offset(struct device *dev, long offset)
868 {
869 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
870 	unsigned int ctrl_reg;
871 
872 	if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
873 		return -ERANGE;
874 
875 	if (offset >= 0) {
876 		ctrl_reg = DIV_ROUND_CLOSEST(offset,
877 					     M41TXX_POS_OFFSET_STEP_PPB);
878 		ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
879 	} else {
880 		ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
881 					     M41TXX_NEG_OFFSET_STEP_PPB);
882 	}
883 
884 	return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
885 				  M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
886 				  ctrl_reg);
887 }
888 
889 #ifdef CONFIG_WATCHDOG_CORE
ds1388_wdt_start(struct watchdog_device * wdt_dev)890 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
891 {
892 	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
893 	u8 regs[2];
894 	int ret;
895 
896 	ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
897 				 DS1388_BIT_WF, 0);
898 	if (ret)
899 		return ret;
900 
901 	ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
902 				 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
903 	if (ret)
904 		return ret;
905 
906 	/*
907 	 * watchdog timeouts are measured in seconds. So ignore hundredths of
908 	 * seconds field.
909 	 */
910 	regs[0] = 0;
911 	regs[1] = bin2bcd(wdt_dev->timeout);
912 
913 	ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
914 				sizeof(regs));
915 	if (ret)
916 		return ret;
917 
918 	return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
919 				  DS1388_BIT_WDE | DS1388_BIT_RST,
920 				  DS1388_BIT_WDE | DS1388_BIT_RST);
921 }
922 
ds1388_wdt_stop(struct watchdog_device * wdt_dev)923 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
924 {
925 	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
926 
927 	return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
928 				  DS1388_BIT_WDE | DS1388_BIT_RST, 0);
929 }
930 
ds1388_wdt_ping(struct watchdog_device * wdt_dev)931 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
932 {
933 	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
934 	u8 regs[2];
935 
936 	return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
937 				sizeof(regs));
938 }
939 
ds1388_wdt_set_timeout(struct watchdog_device * wdt_dev,unsigned int val)940 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
941 				  unsigned int val)
942 {
943 	struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
944 	u8 regs[2];
945 
946 	wdt_dev->timeout = val;
947 	regs[0] = 0;
948 	regs[1] = bin2bcd(wdt_dev->timeout);
949 
950 	return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
951 				 sizeof(regs));
952 }
953 #endif
954 
955 static const struct rtc_class_ops rx8130_rtc_ops = {
956 	.read_time      = ds1307_get_time,
957 	.set_time       = ds1307_set_time,
958 	.read_alarm     = rx8130_read_alarm,
959 	.set_alarm      = rx8130_set_alarm,
960 	.alarm_irq_enable = rx8130_alarm_irq_enable,
961 };
962 
963 static const struct rtc_class_ops mcp794xx_rtc_ops = {
964 	.read_time      = ds1307_get_time,
965 	.set_time       = ds1307_set_time,
966 	.read_alarm     = mcp794xx_read_alarm,
967 	.set_alarm      = mcp794xx_set_alarm,
968 	.alarm_irq_enable = mcp794xx_alarm_irq_enable,
969 };
970 
971 static const struct rtc_class_ops m41txx_rtc_ops = {
972 	.read_time      = ds1307_get_time,
973 	.set_time       = ds1307_set_time,
974 	.read_alarm	= ds1337_read_alarm,
975 	.set_alarm	= ds1337_set_alarm,
976 	.alarm_irq_enable = ds1307_alarm_irq_enable,
977 	.read_offset	= m41txx_rtc_read_offset,
978 	.set_offset	= m41txx_rtc_set_offset,
979 };
980 
981 static const struct chip_desc chips[last_ds_type] = {
982 	[ds_1307] = {
983 		.nvram_offset	= 8,
984 		.nvram_size	= 56,
985 	},
986 	[ds_1308] = {
987 		.nvram_offset	= 8,
988 		.nvram_size	= 56,
989 	},
990 	[ds_1337] = {
991 		.alarm		= 1,
992 		.century_reg	= DS1307_REG_MONTH,
993 		.century_bit	= DS1337_BIT_CENTURY,
994 	},
995 	[ds_1338] = {
996 		.nvram_offset	= 8,
997 		.nvram_size	= 56,
998 	},
999 	[ds_1339] = {
1000 		.alarm		= 1,
1001 		.century_reg	= DS1307_REG_MONTH,
1002 		.century_bit	= DS1337_BIT_CENTURY,
1003 		.bbsqi_bit	= DS1339_BIT_BBSQI,
1004 		.trickle_charger_reg = 0x10,
1005 		.do_trickle_setup = &do_trickle_setup_ds1339,
1006 		.requires_trickle_resistor = true,
1007 		.charge_default = true,
1008 	},
1009 	[ds_1340] = {
1010 		.century_reg	= DS1307_REG_HOUR,
1011 		.century_enable_bit = DS1340_BIT_CENTURY_EN,
1012 		.century_bit	= DS1340_BIT_CENTURY,
1013 		.do_trickle_setup = &do_trickle_setup_ds1339,
1014 		.trickle_charger_reg = 0x08,
1015 		.requires_trickle_resistor = true,
1016 		.charge_default = true,
1017 	},
1018 	[ds_1341] = {
1019 		.century_reg	= DS1307_REG_MONTH,
1020 		.century_bit	= DS1337_BIT_CENTURY,
1021 	},
1022 	[ds_1388] = {
1023 		.offset		= 1,
1024 		.trickle_charger_reg = 0x0a,
1025 	},
1026 	[ds_3231] = {
1027 		.alarm		= 1,
1028 		.century_reg	= DS1307_REG_MONTH,
1029 		.century_bit	= DS1337_BIT_CENTURY,
1030 		.bbsqi_bit	= DS3231_BIT_BBSQW,
1031 	},
1032 	[rx_8130] = {
1033 		.alarm		= 1,
1034 		/* this is battery backed SRAM */
1035 		.nvram_offset	= 0x20,
1036 		.nvram_size	= 4,	/* 32bit (4 word x 8 bit) */
1037 		.offset		= 0x10,
1038 		.irq_handler = rx8130_irq,
1039 		.rtc_ops = &rx8130_rtc_ops,
1040 		.trickle_charger_reg = RX8130_REG_CONTROL1,
1041 		.do_trickle_setup = &do_trickle_setup_rx8130,
1042 	},
1043 	[m41t0] = {
1044 		.rtc_ops	= &m41txx_rtc_ops,
1045 	},
1046 	[m41t00] = {
1047 		.rtc_ops	= &m41txx_rtc_ops,
1048 	},
1049 	[m41t11] = {
1050 		/* this is battery backed SRAM */
1051 		.nvram_offset	= 8,
1052 		.nvram_size	= 56,
1053 		.rtc_ops	= &m41txx_rtc_ops,
1054 	},
1055 	[mcp794xx] = {
1056 		.alarm		= 1,
1057 		/* this is battery backed SRAM */
1058 		.nvram_offset	= 0x20,
1059 		.nvram_size	= 0x40,
1060 		.irq_handler = mcp794xx_irq,
1061 		.rtc_ops = &mcp794xx_rtc_ops,
1062 	},
1063 };
1064 
1065 static const struct i2c_device_id ds1307_id[] = {
1066 	{ "ds1307", ds_1307 },
1067 	{ "ds1308", ds_1308 },
1068 	{ "ds1337", ds_1337 },
1069 	{ "ds1338", ds_1338 },
1070 	{ "ds1339", ds_1339 },
1071 	{ "ds1388", ds_1388 },
1072 	{ "ds1340", ds_1340 },
1073 	{ "ds1341", ds_1341 },
1074 	{ "ds3231", ds_3231 },
1075 	{ "m41t0", m41t0 },
1076 	{ "m41t00", m41t00 },
1077 	{ "m41t11", m41t11 },
1078 	{ "mcp7940x", mcp794xx },
1079 	{ "mcp7941x", mcp794xx },
1080 	{ "pt7c4338", ds_1307 },
1081 	{ "rx8025", rx_8025 },
1082 	{ "isl12057", ds_1337 },
1083 	{ "rx8130", rx_8130 },
1084 	{ }
1085 };
1086 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1087 
1088 static const struct of_device_id ds1307_of_match[] = {
1089 	{
1090 		.compatible = "dallas,ds1307",
1091 		.data = (void *)ds_1307
1092 	},
1093 	{
1094 		.compatible = "dallas,ds1308",
1095 		.data = (void *)ds_1308
1096 	},
1097 	{
1098 		.compatible = "dallas,ds1337",
1099 		.data = (void *)ds_1337
1100 	},
1101 	{
1102 		.compatible = "dallas,ds1338",
1103 		.data = (void *)ds_1338
1104 	},
1105 	{
1106 		.compatible = "dallas,ds1339",
1107 		.data = (void *)ds_1339
1108 	},
1109 	{
1110 		.compatible = "dallas,ds1388",
1111 		.data = (void *)ds_1388
1112 	},
1113 	{
1114 		.compatible = "dallas,ds1340",
1115 		.data = (void *)ds_1340
1116 	},
1117 	{
1118 		.compatible = "dallas,ds1341",
1119 		.data = (void *)ds_1341
1120 	},
1121 	{
1122 		.compatible = "maxim,ds3231",
1123 		.data = (void *)ds_3231
1124 	},
1125 	{
1126 		.compatible = "st,m41t0",
1127 		.data = (void *)m41t0
1128 	},
1129 	{
1130 		.compatible = "st,m41t00",
1131 		.data = (void *)m41t00
1132 	},
1133 	{
1134 		.compatible = "st,m41t11",
1135 		.data = (void *)m41t11
1136 	},
1137 	{
1138 		.compatible = "microchip,mcp7940x",
1139 		.data = (void *)mcp794xx
1140 	},
1141 	{
1142 		.compatible = "microchip,mcp7941x",
1143 		.data = (void *)mcp794xx
1144 	},
1145 	{
1146 		.compatible = "pericom,pt7c4338",
1147 		.data = (void *)ds_1307
1148 	},
1149 	{
1150 		.compatible = "epson,rx8025",
1151 		.data = (void *)rx_8025
1152 	},
1153 	{
1154 		.compatible = "isil,isl12057",
1155 		.data = (void *)ds_1337
1156 	},
1157 	{
1158 		.compatible = "epson,rx8130",
1159 		.data = (void *)rx_8130
1160 	},
1161 	{ }
1162 };
1163 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1164 
1165 /*
1166  * The ds1337 and ds1339 both have two alarms, but we only use the first
1167  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
1168  * signal; ds1339 chips have only one alarm signal.
1169  */
ds1307_irq(int irq,void * dev_id)1170 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1171 {
1172 	struct ds1307		*ds1307 = dev_id;
1173 	struct mutex		*lock = &ds1307->rtc->ops_lock;
1174 	int			stat, ret;
1175 
1176 	mutex_lock(lock);
1177 	ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1178 	if (ret)
1179 		goto out;
1180 
1181 	if (stat & DS1337_BIT_A1I) {
1182 		stat &= ~DS1337_BIT_A1I;
1183 		regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1184 
1185 		ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1186 					 DS1337_BIT_A1IE, 0);
1187 		if (ret)
1188 			goto out;
1189 
1190 		rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1191 	}
1192 
1193 out:
1194 	mutex_unlock(lock);
1195 
1196 	return IRQ_HANDLED;
1197 }
1198 
1199 /*----------------------------------------------------------------------*/
1200 
1201 static const struct rtc_class_ops ds13xx_rtc_ops = {
1202 	.read_time	= ds1307_get_time,
1203 	.set_time	= ds1307_set_time,
1204 	.read_alarm	= ds1337_read_alarm,
1205 	.set_alarm	= ds1337_set_alarm,
1206 	.alarm_irq_enable = ds1307_alarm_irq_enable,
1207 };
1208 
frequency_test_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1209 static ssize_t frequency_test_store(struct device *dev,
1210 				    struct device_attribute *attr,
1211 				    const char *buf, size_t count)
1212 {
1213 	struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1214 	bool freq_test_en;
1215 	int ret;
1216 
1217 	ret = kstrtobool(buf, &freq_test_en);
1218 	if (ret) {
1219 		dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1220 		return ret;
1221 	}
1222 
1223 	regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1224 			   freq_test_en ? M41TXX_BIT_FT : 0);
1225 
1226 	return count;
1227 }
1228 
frequency_test_show(struct device * dev,struct device_attribute * attr,char * buf)1229 static ssize_t frequency_test_show(struct device *dev,
1230 				   struct device_attribute *attr,
1231 				   char *buf)
1232 {
1233 	struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1234 	unsigned int ctrl_reg;
1235 
1236 	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1237 
1238 	return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n");
1239 }
1240 
1241 static DEVICE_ATTR_RW(frequency_test);
1242 
1243 static struct attribute *rtc_freq_test_attrs[] = {
1244 	&dev_attr_frequency_test.attr,
1245 	NULL,
1246 };
1247 
1248 static const struct attribute_group rtc_freq_test_attr_group = {
1249 	.attrs		= rtc_freq_test_attrs,
1250 };
1251 
ds1307_add_frequency_test(struct ds1307 * ds1307)1252 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1253 {
1254 	int err;
1255 
1256 	switch (ds1307->type) {
1257 	case m41t0:
1258 	case m41t00:
1259 	case m41t11:
1260 		err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1261 		if (err)
1262 			return err;
1263 		break;
1264 	default:
1265 		break;
1266 	}
1267 
1268 	return 0;
1269 }
1270 
1271 /*----------------------------------------------------------------------*/
1272 
ds1307_nvram_read(void * priv,unsigned int offset,void * val,size_t bytes)1273 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1274 			     size_t bytes)
1275 {
1276 	struct ds1307 *ds1307 = priv;
1277 	const struct chip_desc *chip = &chips[ds1307->type];
1278 
1279 	return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1280 				val, bytes);
1281 }
1282 
ds1307_nvram_write(void * priv,unsigned int offset,void * val,size_t bytes)1283 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1284 			      size_t bytes)
1285 {
1286 	struct ds1307 *ds1307 = priv;
1287 	const struct chip_desc *chip = &chips[ds1307->type];
1288 
1289 	return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1290 				 val, bytes);
1291 }
1292 
1293 /*----------------------------------------------------------------------*/
1294 
ds1307_trickle_init(struct ds1307 * ds1307,const struct chip_desc * chip)1295 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1296 			      const struct chip_desc *chip)
1297 {
1298 	u32 ohms, chargeable;
1299 	bool diode = chip->charge_default;
1300 
1301 	if (!chip->do_trickle_setup)
1302 		return 0;
1303 
1304 	if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1305 				     &ohms) && chip->requires_trickle_resistor)
1306 		return 0;
1307 
1308 	/* aux-voltage-chargeable takes precedence over the deprecated
1309 	 * trickle-diode-disable
1310 	 */
1311 	if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1312 				     &chargeable)) {
1313 		switch (chargeable) {
1314 		case 0:
1315 			diode = false;
1316 			break;
1317 		case 1:
1318 			diode = true;
1319 			break;
1320 		default:
1321 			dev_warn(ds1307->dev,
1322 				 "unsupported aux-voltage-chargeable value\n");
1323 			break;
1324 		}
1325 	} else if (device_property_read_bool(ds1307->dev,
1326 					     "trickle-diode-disable")) {
1327 		diode = false;
1328 	}
1329 
1330 	return chip->do_trickle_setup(ds1307, ohms, diode);
1331 }
1332 
1333 /*----------------------------------------------------------------------*/
1334 
1335 #if IS_REACHABLE(CONFIG_HWMON)
1336 
1337 /*
1338  * Temperature sensor support for ds3231 devices.
1339  */
1340 
1341 #define DS3231_REG_TEMPERATURE	0x11
1342 
1343 /*
1344  * A user-initiated temperature conversion is not started by this function,
1345  * so the temperature is updated once every 64 seconds.
1346  */
ds3231_hwmon_read_temp(struct device * dev,s32 * mC)1347 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1348 {
1349 	struct ds1307 *ds1307 = dev_get_drvdata(dev);
1350 	u8 temp_buf[2];
1351 	s16 temp;
1352 	int ret;
1353 
1354 	ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1355 			       temp_buf, sizeof(temp_buf));
1356 	if (ret)
1357 		return ret;
1358 	/*
1359 	 * Temperature is represented as a 10-bit code with a resolution of
1360 	 * 0.25 degree celsius and encoded in two's complement format.
1361 	 */
1362 	temp = (temp_buf[0] << 8) | temp_buf[1];
1363 	temp >>= 6;
1364 	*mC = temp * 250;
1365 
1366 	return 0;
1367 }
1368 
ds3231_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)1369 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1370 				      struct device_attribute *attr, char *buf)
1371 {
1372 	int ret;
1373 	s32 temp;
1374 
1375 	ret = ds3231_hwmon_read_temp(dev, &temp);
1376 	if (ret)
1377 		return ret;
1378 
1379 	return sprintf(buf, "%d\n", temp);
1380 }
1381 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1382 			  NULL, 0);
1383 
1384 static struct attribute *ds3231_hwmon_attrs[] = {
1385 	&sensor_dev_attr_temp1_input.dev_attr.attr,
1386 	NULL,
1387 };
1388 ATTRIBUTE_GROUPS(ds3231_hwmon);
1389 
ds1307_hwmon_register(struct ds1307 * ds1307)1390 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1391 {
1392 	struct device *dev;
1393 
1394 	if (ds1307->type != ds_3231)
1395 		return;
1396 
1397 	dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1398 						     ds1307,
1399 						     ds3231_hwmon_groups);
1400 	if (IS_ERR(dev)) {
1401 		dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1402 			 PTR_ERR(dev));
1403 	}
1404 }
1405 
1406 #else
1407 
ds1307_hwmon_register(struct ds1307 * ds1307)1408 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1409 {
1410 }
1411 
1412 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1413 
1414 /*----------------------------------------------------------------------*/
1415 
1416 /*
1417  * Square-wave output support for DS3231
1418  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1419  */
1420 #ifdef CONFIG_COMMON_CLK
1421 
1422 enum {
1423 	DS3231_CLK_SQW = 0,
1424 	DS3231_CLK_32KHZ,
1425 };
1426 
1427 #define clk_sqw_to_ds1307(clk)	\
1428 	container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1429 #define clk_32khz_to_ds1307(clk)	\
1430 	container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1431 
1432 static int ds3231_clk_sqw_rates[] = {
1433 	1,
1434 	1024,
1435 	4096,
1436 	8192,
1437 };
1438 
ds1337_write_control(struct ds1307 * ds1307,u8 mask,u8 value)1439 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1440 {
1441 	struct mutex *lock = &ds1307->rtc->ops_lock;
1442 	int ret;
1443 
1444 	mutex_lock(lock);
1445 	ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1446 				 mask, value);
1447 	mutex_unlock(lock);
1448 
1449 	return ret;
1450 }
1451 
ds3231_clk_sqw_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1452 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1453 						unsigned long parent_rate)
1454 {
1455 	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1456 	int control, ret;
1457 	int rate_sel = 0;
1458 
1459 	ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1460 	if (ret)
1461 		return ret;
1462 	if (control & DS1337_BIT_RS1)
1463 		rate_sel += 1;
1464 	if (control & DS1337_BIT_RS2)
1465 		rate_sel += 2;
1466 
1467 	return ds3231_clk_sqw_rates[rate_sel];
1468 }
1469 
ds3231_clk_sqw_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)1470 static int ds3231_clk_sqw_determine_rate(struct clk_hw *hw,
1471 					 struct clk_rate_request *req)
1472 {
1473 	int i;
1474 
1475 	for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1476 		if (ds3231_clk_sqw_rates[i] <= req->rate) {
1477 			req->rate = ds3231_clk_sqw_rates[i];
1478 
1479 			return 0;
1480 		}
1481 	}
1482 
1483 	req->rate = ds3231_clk_sqw_rates[ARRAY_SIZE(ds3231_clk_sqw_rates) - 1];
1484 
1485 	return 0;
1486 }
1487 
ds3231_clk_sqw_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1488 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1489 				   unsigned long parent_rate)
1490 {
1491 	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1492 	int control = 0;
1493 	int rate_sel;
1494 
1495 	for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1496 			rate_sel++) {
1497 		if (ds3231_clk_sqw_rates[rate_sel] == rate)
1498 			break;
1499 	}
1500 
1501 	if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1502 		return -EINVAL;
1503 
1504 	if (rate_sel & 1)
1505 		control |= DS1337_BIT_RS1;
1506 	if (rate_sel & 2)
1507 		control |= DS1337_BIT_RS2;
1508 
1509 	return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1510 				control);
1511 }
1512 
ds3231_clk_sqw_prepare(struct clk_hw * hw)1513 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1514 {
1515 	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1516 
1517 	return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1518 }
1519 
ds3231_clk_sqw_unprepare(struct clk_hw * hw)1520 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1521 {
1522 	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1523 
1524 	ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1525 }
1526 
ds3231_clk_sqw_is_prepared(struct clk_hw * hw)1527 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1528 {
1529 	struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1530 	int control, ret;
1531 
1532 	ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1533 	if (ret)
1534 		return ret;
1535 
1536 	return !(control & DS1337_BIT_INTCN);
1537 }
1538 
1539 static const struct clk_ops ds3231_clk_sqw_ops = {
1540 	.prepare = ds3231_clk_sqw_prepare,
1541 	.unprepare = ds3231_clk_sqw_unprepare,
1542 	.is_prepared = ds3231_clk_sqw_is_prepared,
1543 	.recalc_rate = ds3231_clk_sqw_recalc_rate,
1544 	.determine_rate = ds3231_clk_sqw_determine_rate,
1545 	.set_rate = ds3231_clk_sqw_set_rate,
1546 };
1547 
ds3231_clk_32khz_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1548 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1549 						  unsigned long parent_rate)
1550 {
1551 	return 32768;
1552 }
1553 
ds3231_clk_32khz_control(struct ds1307 * ds1307,bool enable)1554 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1555 {
1556 	struct mutex *lock = &ds1307->rtc->ops_lock;
1557 	int ret;
1558 
1559 	mutex_lock(lock);
1560 	ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1561 				 DS3231_BIT_EN32KHZ,
1562 				 enable ? DS3231_BIT_EN32KHZ : 0);
1563 	mutex_unlock(lock);
1564 
1565 	return ret;
1566 }
1567 
ds3231_clk_32khz_prepare(struct clk_hw * hw)1568 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1569 {
1570 	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1571 
1572 	return ds3231_clk_32khz_control(ds1307, true);
1573 }
1574 
ds3231_clk_32khz_unprepare(struct clk_hw * hw)1575 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1576 {
1577 	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1578 
1579 	ds3231_clk_32khz_control(ds1307, false);
1580 }
1581 
ds3231_clk_32khz_is_prepared(struct clk_hw * hw)1582 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1583 {
1584 	struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1585 	int status, ret;
1586 
1587 	ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1588 	if (ret)
1589 		return ret;
1590 
1591 	return !!(status & DS3231_BIT_EN32KHZ);
1592 }
1593 
1594 static const struct clk_ops ds3231_clk_32khz_ops = {
1595 	.prepare = ds3231_clk_32khz_prepare,
1596 	.unprepare = ds3231_clk_32khz_unprepare,
1597 	.is_prepared = ds3231_clk_32khz_is_prepared,
1598 	.recalc_rate = ds3231_clk_32khz_recalc_rate,
1599 };
1600 
1601 static const char *ds3231_clks_names[] = {
1602 	[DS3231_CLK_SQW] = "ds3231_clk_sqw",
1603 	[DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1604 };
1605 
1606 static struct clk_init_data ds3231_clks_init[] = {
1607 	[DS3231_CLK_SQW] = {
1608 		.ops = &ds3231_clk_sqw_ops,
1609 	},
1610 	[DS3231_CLK_32KHZ] = {
1611 		.ops = &ds3231_clk_32khz_ops,
1612 	},
1613 };
1614 
ds3231_clks_register(struct ds1307 * ds1307)1615 static int ds3231_clks_register(struct ds1307 *ds1307)
1616 {
1617 	struct device_node *node = ds1307->dev->of_node;
1618 	struct clk_onecell_data	*onecell;
1619 	int i;
1620 
1621 	onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1622 	if (!onecell)
1623 		return -ENOMEM;
1624 
1625 	onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1626 	onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1627 				     sizeof(onecell->clks[0]), GFP_KERNEL);
1628 	if (!onecell->clks)
1629 		return -ENOMEM;
1630 
1631 	/* optional override of the clockname */
1632 	device_property_read_string_array(ds1307->dev, "clock-output-names",
1633 					  ds3231_clks_names,
1634 					  ARRAY_SIZE(ds3231_clks_names));
1635 
1636 	for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1637 		struct clk_init_data init = ds3231_clks_init[i];
1638 
1639 		/*
1640 		 * Interrupt signal due to alarm conditions and square-wave
1641 		 * output share same pin, so don't initialize both.
1642 		 */
1643 		if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
1644 			continue;
1645 
1646 		init.name = ds3231_clks_names[i];
1647 		ds1307->clks[i].init = &init;
1648 
1649 		onecell->clks[i] = devm_clk_register(ds1307->dev,
1650 						     &ds1307->clks[i]);
1651 		if (IS_ERR(onecell->clks[i]))
1652 			return PTR_ERR(onecell->clks[i]);
1653 	}
1654 
1655 	if (node)
1656 		of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1657 
1658 	return 0;
1659 }
1660 
ds1307_clks_register(struct ds1307 * ds1307)1661 static void ds1307_clks_register(struct ds1307 *ds1307)
1662 {
1663 	int ret;
1664 
1665 	if (ds1307->type != ds_3231)
1666 		return;
1667 
1668 	ret = ds3231_clks_register(ds1307);
1669 	if (ret) {
1670 		dev_warn(ds1307->dev, "unable to register clock device %d\n",
1671 			 ret);
1672 	}
1673 }
1674 
1675 #else
1676 
ds1307_clks_register(struct ds1307 * ds1307)1677 static void ds1307_clks_register(struct ds1307 *ds1307)
1678 {
1679 }
1680 
1681 #endif /* CONFIG_COMMON_CLK */
1682 
1683 #ifdef CONFIG_WATCHDOG_CORE
1684 static const struct watchdog_info ds1388_wdt_info = {
1685 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1686 	.identity = "DS1388 watchdog",
1687 };
1688 
1689 static const struct watchdog_ops ds1388_wdt_ops = {
1690 	.owner = THIS_MODULE,
1691 	.start = ds1388_wdt_start,
1692 	.stop = ds1388_wdt_stop,
1693 	.ping = ds1388_wdt_ping,
1694 	.set_timeout = ds1388_wdt_set_timeout,
1695 
1696 };
1697 
ds1307_wdt_register(struct ds1307 * ds1307)1698 static void ds1307_wdt_register(struct ds1307 *ds1307)
1699 {
1700 	struct watchdog_device	*wdt;
1701 	int err;
1702 	int val;
1703 
1704 	if (ds1307->type != ds_1388)
1705 		return;
1706 
1707 	wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1708 	if (!wdt)
1709 		return;
1710 
1711 	err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1712 	if (!err && val & DS1388_BIT_WF)
1713 		wdt->bootstatus = WDIOF_CARDRESET;
1714 
1715 	wdt->info = &ds1388_wdt_info;
1716 	wdt->ops = &ds1388_wdt_ops;
1717 	wdt->timeout = 99;
1718 	wdt->max_timeout = 99;
1719 	wdt->min_timeout = 1;
1720 
1721 	watchdog_init_timeout(wdt, 0, ds1307->dev);
1722 	watchdog_set_drvdata(wdt, ds1307);
1723 	devm_watchdog_register_device(ds1307->dev, wdt);
1724 }
1725 #else
ds1307_wdt_register(struct ds1307 * ds1307)1726 static void ds1307_wdt_register(struct ds1307 *ds1307)
1727 {
1728 }
1729 #endif /* CONFIG_WATCHDOG_CORE */
1730 
1731 static const struct regmap_config regmap_config = {
1732 	.reg_bits = 8,
1733 	.val_bits = 8,
1734 };
1735 
ds1307_probe(struct i2c_client * client)1736 static int ds1307_probe(struct i2c_client *client)
1737 {
1738 	const struct i2c_device_id *id = i2c_client_get_device_id(client);
1739 	struct ds1307		*ds1307;
1740 	const void		*match;
1741 	int			err = -ENODEV;
1742 	int			tmp;
1743 	const struct chip_desc	*chip;
1744 	bool			want_irq;
1745 	bool			ds1307_can_wakeup_device = false;
1746 	unsigned char		regs[8];
1747 	struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1748 	u8			trickle_charger_setup = 0;
1749 
1750 	ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1751 	if (!ds1307)
1752 		return -ENOMEM;
1753 
1754 	dev_set_drvdata(&client->dev, ds1307);
1755 	ds1307->dev = &client->dev;
1756 	ds1307->name = client->name;
1757 
1758 	ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1759 	if (IS_ERR(ds1307->regmap)) {
1760 		dev_err(ds1307->dev, "regmap allocation failed\n");
1761 		return PTR_ERR(ds1307->regmap);
1762 	}
1763 
1764 	i2c_set_clientdata(client, ds1307);
1765 
1766 	match = device_get_match_data(&client->dev);
1767 	if (match) {
1768 		ds1307->type = (uintptr_t)match;
1769 		chip = &chips[ds1307->type];
1770 	} else if (id) {
1771 		chip = &chips[id->driver_data];
1772 		ds1307->type = id->driver_data;
1773 	} else {
1774 		return -ENODEV;
1775 	}
1776 
1777 	want_irq = client->irq > 0 && chip->alarm;
1778 
1779 	if (!pdata)
1780 		trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1781 	else if (pdata->trickle_charger_setup)
1782 		trickle_charger_setup = pdata->trickle_charger_setup;
1783 
1784 	if (trickle_charger_setup && chip->trickle_charger_reg) {
1785 		dev_dbg(ds1307->dev,
1786 			"writing trickle charger info 0x%x to 0x%x\n",
1787 			trickle_charger_setup, chip->trickle_charger_reg);
1788 		regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1789 			     trickle_charger_setup);
1790 	}
1791 
1792 /*
1793  * For devices with no IRQ directly connected to the SoC, the RTC chip
1794  * can be forced as a wakeup source by stating that explicitly in
1795  * the device's .dts file using the "wakeup-source" boolean property.
1796  * If the "wakeup-source" property is set, don't request an IRQ.
1797  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1798  * if supported by the RTC.
1799  */
1800 	if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1801 		ds1307_can_wakeup_device = true;
1802 
1803 	switch (ds1307->type) {
1804 	case ds_1337:
1805 	case ds_1339:
1806 	case ds_1341:
1807 	case ds_3231:
1808 		/* get registers that the "rtc" read below won't read... */
1809 		err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1810 				       regs, 2);
1811 		if (err) {
1812 			dev_dbg(ds1307->dev, "read error %d\n", err);
1813 			goto exit;
1814 		}
1815 
1816 		/* oscillator off?  turn it on, so clock can tick. */
1817 		if (regs[0] & DS1337_BIT_nEOSC)
1818 			regs[0] &= ~DS1337_BIT_nEOSC;
1819 
1820 		/*
1821 		 * Using IRQ or defined as wakeup-source?
1822 		 * Disable the square wave and both alarms.
1823 		 * For some variants, be sure alarms can trigger when we're
1824 		 * running on Vbackup (BBSQI/BBSQW)
1825 		 */
1826 		if (want_irq || ds1307_can_wakeup_device)
1827 			regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1828 
1829 		regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1830 			     regs[0]);
1831 
1832 		/* oscillator fault? warn */
1833 		if (regs[1] & DS1337_BIT_OSF) {
1834 			dev_warn(ds1307->dev, "SET TIME!\n");
1835 		}
1836 		break;
1837 
1838 	case rx_8025:
1839 		err = regmap_bulk_read(ds1307->regmap,
1840 				       RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1841 		if (err) {
1842 			dev_dbg(ds1307->dev, "read error %d\n", err);
1843 			goto exit;
1844 		}
1845 
1846 		/* oscillator off?  turn it on, so clock can tick. */
1847 		if (!(regs[1] & RX8025_BIT_XST)) {
1848 			regs[1] |= RX8025_BIT_XST;
1849 			regmap_write(ds1307->regmap,
1850 				     RX8025_REG_CTRL2 << 4 | 0x08,
1851 				     regs[1]);
1852 			dev_warn(ds1307->dev,
1853 				 "oscillator stop detected - SET TIME!\n");
1854 		}
1855 
1856 		if (regs[1] & RX8025_BIT_PON) {
1857 			regs[1] &= ~RX8025_BIT_PON;
1858 			regmap_write(ds1307->regmap,
1859 				     RX8025_REG_CTRL2 << 4 | 0x08,
1860 				     regs[1]);
1861 			dev_warn(ds1307->dev, "power-on detected\n");
1862 		}
1863 
1864 		if (regs[1] & RX8025_BIT_VDET) {
1865 			regs[1] &= ~RX8025_BIT_VDET;
1866 			regmap_write(ds1307->regmap,
1867 				     RX8025_REG_CTRL2 << 4 | 0x08,
1868 				     regs[1]);
1869 			dev_warn(ds1307->dev, "voltage drop detected\n");
1870 		}
1871 
1872 		/* make sure we are running in 24hour mode */
1873 		if (!(regs[0] & RX8025_BIT_2412)) {
1874 			u8 hour;
1875 
1876 			/* switch to 24 hour mode */
1877 			regmap_write(ds1307->regmap,
1878 				     RX8025_REG_CTRL1 << 4 | 0x08,
1879 				     regs[0] | RX8025_BIT_2412);
1880 
1881 			err = regmap_bulk_read(ds1307->regmap,
1882 					       RX8025_REG_CTRL1 << 4 | 0x08,
1883 					       regs, 2);
1884 			if (err) {
1885 				dev_dbg(ds1307->dev, "read error %d\n", err);
1886 				goto exit;
1887 			}
1888 
1889 			/* correct hour */
1890 			hour = bcd2bin(regs[DS1307_REG_HOUR]);
1891 			if (hour == 12)
1892 				hour = 0;
1893 			if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1894 				hour += 12;
1895 
1896 			regmap_write(ds1307->regmap,
1897 				     DS1307_REG_HOUR << 4 | 0x08, hour);
1898 		}
1899 		break;
1900 	case ds_1388:
1901 		err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1902 		if (err) {
1903 			dev_dbg(ds1307->dev, "read error %d\n", err);
1904 			goto exit;
1905 		}
1906 
1907 		/* oscillator off?  turn it on, so clock can tick. */
1908 		if (tmp & DS1388_BIT_nEOSC) {
1909 			tmp &= ~DS1388_BIT_nEOSC;
1910 			regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1911 		}
1912 		break;
1913 	default:
1914 		break;
1915 	}
1916 
1917 	/* read RTC registers */
1918 	err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1919 			       sizeof(regs));
1920 	if (err) {
1921 		dev_dbg(ds1307->dev, "read error %d\n", err);
1922 		goto exit;
1923 	}
1924 
1925 	if (ds1307->type == mcp794xx &&
1926 	    !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1927 		regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1928 			     regs[DS1307_REG_WDAY] |
1929 			     MCP794XX_BIT_VBATEN);
1930 	}
1931 
1932 	tmp = regs[DS1307_REG_HOUR];
1933 	switch (ds1307->type) {
1934 	case ds_1340:
1935 	case m41t0:
1936 	case m41t00:
1937 	case m41t11:
1938 		/*
1939 		 * NOTE: ignores century bits; fix before deploying
1940 		 * systems that will run through year 2100.
1941 		 */
1942 		break;
1943 	case rx_8025:
1944 		break;
1945 	default:
1946 		if (!(tmp & DS1307_BIT_12HR))
1947 			break;
1948 
1949 		/*
1950 		 * Be sure we're in 24 hour mode.  Multi-master systems
1951 		 * take note...
1952 		 */
1953 		tmp = bcd2bin(tmp & 0x1f);
1954 		if (tmp == 12)
1955 			tmp = 0;
1956 		if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1957 			tmp += 12;
1958 		regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1959 			     bin2bcd(tmp));
1960 	}
1961 
1962 	ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1963 	if (IS_ERR(ds1307->rtc))
1964 		return PTR_ERR(ds1307->rtc);
1965 
1966 	if (want_irq || ds1307_can_wakeup_device)
1967 		device_set_wakeup_capable(ds1307->dev, true);
1968 	else
1969 		clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1970 
1971 	if (ds1307_can_wakeup_device && !want_irq) {
1972 		dev_info(ds1307->dev,
1973 			 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1974 		/* We cannot support UIE mode if we do not have an IRQ line */
1975 		clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features);
1976 	}
1977 
1978 	if (want_irq) {
1979 		err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1980 						chip->irq_handler ?: ds1307_irq,
1981 						IRQF_SHARED | IRQF_ONESHOT,
1982 						ds1307->name, ds1307);
1983 		if (err) {
1984 			client->irq = 0;
1985 			device_set_wakeup_capable(ds1307->dev, false);
1986 			clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1987 			dev_err(ds1307->dev, "unable to request IRQ!\n");
1988 		} else {
1989 			dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1990 		}
1991 	}
1992 
1993 	ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1994 	err = ds1307_add_frequency_test(ds1307);
1995 	if (err)
1996 		return err;
1997 
1998 	err = devm_rtc_register_device(ds1307->rtc);
1999 	if (err)
2000 		return err;
2001 
2002 	if (chip->nvram_size) {
2003 		struct nvmem_config nvmem_cfg = {
2004 			.name = "ds1307_nvram",
2005 			.word_size = 1,
2006 			.stride = 1,
2007 			.size = chip->nvram_size,
2008 			.reg_read = ds1307_nvram_read,
2009 			.reg_write = ds1307_nvram_write,
2010 			.priv = ds1307,
2011 		};
2012 
2013 		devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2014 	}
2015 
2016 	ds1307_hwmon_register(ds1307);
2017 	ds1307_clks_register(ds1307);
2018 	ds1307_wdt_register(ds1307);
2019 
2020 	return 0;
2021 
2022 exit:
2023 	return err;
2024 }
2025 
2026 static struct i2c_driver ds1307_driver = {
2027 	.driver = {
2028 		.name	= "rtc-ds1307",
2029 		.of_match_table = ds1307_of_match,
2030 	},
2031 	.probe		= ds1307_probe,
2032 	.id_table	= ds1307_id,
2033 };
2034 
2035 module_i2c_driver(ds1307_driver);
2036 
2037 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2038 MODULE_LICENSE("GPL");
2039