1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
4 *
5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/property.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spi/spi.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/trigger.h>
25
26 #include <linux/unaligned.h>
27
28 #define MCP3911_REG_CHANNEL0 0x00
29 #define MCP3911_REG_CHANNEL1 0x03
30 #define MCP3911_REG_MOD 0x06
31 #define MCP3911_REG_PHASE 0x07
32 #define MCP3911_REG_GAIN 0x09
33 #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch))
34 #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch))
35
36 #define MCP3911_REG_STATUSCOM 0x0a
37 #define MCP3911_STATUSCOM_DRHIZ BIT(12)
38 #define MCP3911_STATUSCOM_READ GENMASK(7, 6)
39 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
40 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
41 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
42 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
43
44 #define MCP3911_REG_CONFIG 0x0c
45 #define MCP3911_CONFIG_CLKEXT BIT(1)
46 #define MCP3911_CONFIG_VREFEXT BIT(2)
47 #define MCP3911_CONFIG_OSR GENMASK(13, 11)
48
49 #define MCP3911_REG_OFFCAL_CH0 0x0e
50 #define MCP3911_REG_GAINCAL_CH0 0x11
51 #define MCP3911_REG_OFFCAL_CH1 0x14
52 #define MCP3911_REG_GAINCAL_CH1 0x17
53 #define MCP3911_REG_VREFCAL 0x1a
54
55 #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3)
56 #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6)
57
58 /* Internal voltage reference in mV */
59 #define MCP3911_INT_VREF_MV 1200
60
61 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
62 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
63 #define MCP3911_REG_MASK GENMASK(4, 1)
64
65 #define MCP3911_NUM_SCALES 6
66
67 /* Registers compatible with MCP3910 */
68 #define MCP3910_REG_STATUSCOM 0x0c
69 #define MCP3910_STATUSCOM_READ GENMASK(23, 22)
70 #define MCP3910_STATUSCOM_DRHIZ BIT(20)
71
72 #define MCP3910_REG_GAIN 0x0b
73
74 #define MCP3910_REG_CONFIG0 0x0d
75 #define MCP3910_CONFIG0_EN_OFFCAL BIT(23)
76 #define MCP3910_CONFIG0_OSR GENMASK(15, 13)
77
78 #define MCP3910_REG_CONFIG1 0x0e
79 #define MCP3910_CONFIG1_CLKEXT BIT(6)
80 #define MCP3910_CONFIG1_VREFEXT BIT(7)
81
82 #define MCP3910_REG_OFFCAL_CH0 0x0f
83 #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6)
84
85 /* Maximal number of channels used by the MCP39XX family */
86 #define MCP39XX_MAX_NUM_CHANNELS 8
87
88 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
89 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2];
90
91 enum mcp3911_id {
92 MCP3910,
93 MCP3911,
94 MCP3912,
95 MCP3913,
96 MCP3914,
97 MCP3918,
98 MCP3919,
99 };
100
101 struct mcp3911;
102 struct mcp3911_chip_info {
103 const struct iio_chan_spec *channels;
104 unsigned int num_channels;
105
106 int (*config)(struct mcp3911 *adc, bool external_vref);
107 int (*get_osr)(struct mcp3911 *adc, u32 *val);
108 int (*set_osr)(struct mcp3911 *adc, u32 val);
109 int (*enable_offset)(struct mcp3911 *adc, bool enable);
110 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
111 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
112 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
113 };
114
115 struct mcp3911 {
116 struct spi_device *spi;
117 struct mutex lock;
118 struct clk *clki;
119 u32 dev_addr;
120 struct iio_trigger *trig;
121 u32 gain[MCP39XX_MAX_NUM_CHANNELS];
122 const struct mcp3911_chip_info *chip;
123 struct {
124 u32 channels[MCP39XX_MAX_NUM_CHANNELS];
125 s64 ts __aligned(8);
126 } scan;
127
128 u8 tx_buf __aligned(IIO_DMA_MINALIGN);
129 u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3];
130 };
131
mcp3911_read(struct mcp3911 * adc,u8 reg,u32 * val,u8 len)132 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
133 {
134 int ret;
135
136 reg = MCP3911_REG_READ(reg, adc->dev_addr);
137 ret = spi_write_then_read(adc->spi, ®, 1, val, len);
138 if (ret < 0)
139 return ret;
140
141 be32_to_cpus(val);
142 *val >>= ((4 - len) * 8);
143 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
144 FIELD_GET(MCP3911_REG_MASK, reg));
145 return ret;
146 }
147
mcp3911_write(struct mcp3911 * adc,u8 reg,u32 val,u8 len)148 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
149 {
150 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
151
152 val <<= (3 - len) * 8;
153 cpu_to_be32s(&val);
154 val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
155
156 return spi_write(adc->spi, &val, len + 1);
157 }
158
mcp3911_update(struct mcp3911 * adc,u8 reg,u32 mask,u32 val,u8 len)159 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len)
160 {
161 u32 tmp;
162 int ret;
163
164 ret = mcp3911_read(adc, reg, &tmp, len);
165 if (ret)
166 return ret;
167
168 val &= mask;
169 val |= tmp & ~mask;
170 return mcp3911_write(adc, reg, val, len);
171 }
172
mcp3910_enable_offset(struct mcp3911 * adc,bool enable)173 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable)
174 {
175 unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL;
176 unsigned int value = enable ? mask : 0;
177
178 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3);
179 }
180
mcp3910_get_offset(struct mcp3911 * adc,int channel,int * val)181 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val)
182 {
183 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3);
184 }
185
mcp3910_set_offset(struct mcp3911 * adc,int channel,int val)186 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val)
187 {
188 int ret;
189
190 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3);
191 if (ret)
192 return ret;
193
194 return adc->chip->enable_offset(adc, 1);
195 }
196
mcp3911_enable_offset(struct mcp3911 * adc,bool enable)197 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable)
198 {
199 unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL;
200 unsigned int value = enable ? mask : 0;
201
202 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2);
203 }
204
mcp3911_get_offset(struct mcp3911 * adc,int channel,int * val)205 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val)
206 {
207 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3);
208 }
209
mcp3911_set_offset(struct mcp3911 * adc,int channel,int val)210 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val)
211 {
212 int ret;
213
214 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3);
215 if (ret)
216 return ret;
217
218 return adc->chip->enable_offset(adc, 1);
219 }
220
mcp3910_get_osr(struct mcp3911 * adc,u32 * val)221 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val)
222 {
223 int ret;
224 unsigned int osr;
225
226 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3);
227 if (ret)
228 return ret;
229
230 osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val);
231 *val = 32 << osr;
232 return 0;
233 }
234
mcp3910_set_osr(struct mcp3911 * adc,u32 val)235 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val)
236 {
237 unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val);
238 unsigned int mask = MCP3910_CONFIG0_OSR;
239
240 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3);
241 }
242
mcp3911_set_osr(struct mcp3911 * adc,u32 val)243 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val)
244 {
245 unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val);
246 unsigned int mask = MCP3911_CONFIG_OSR;
247
248 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2);
249 }
250
mcp3911_get_osr(struct mcp3911 * adc,u32 * val)251 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val)
252 {
253 int ret;
254 unsigned int osr;
255
256 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
257 if (ret)
258 return ret;
259
260 osr = FIELD_GET(MCP3911_CONFIG_OSR, *val);
261 *val = 32 << osr;
262 return ret;
263 }
264
mcp3910_set_scale(struct mcp3911 * adc,int channel,u32 val)265 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val)
266 {
267 return mcp3911_update(adc, MCP3910_REG_GAIN,
268 MCP3911_GAIN_MASK(channel),
269 MCP3911_GAIN_VAL(channel, val), 3);
270 }
271
mcp3911_set_scale(struct mcp3911 * adc,int channel,u32 val)272 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val)
273 {
274 return mcp3911_update(adc, MCP3911_REG_GAIN,
275 MCP3911_GAIN_MASK(channel),
276 MCP3911_GAIN_VAL(channel, val), 1);
277 }
278
mcp3911_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)279 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
280 struct iio_chan_spec const *chan,
281 long mask)
282 {
283 switch (mask) {
284 case IIO_CHAN_INFO_SCALE:
285 return IIO_VAL_INT_PLUS_NANO;
286 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
287 return IIO_VAL_INT;
288 default:
289 return IIO_VAL_INT_PLUS_NANO;
290 }
291 }
292
mcp3911_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)293 static int mcp3911_read_avail(struct iio_dev *indio_dev,
294 struct iio_chan_spec const *chan,
295 const int **vals, int *type, int *length,
296 long info)
297 {
298 switch (info) {
299 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
300 *type = IIO_VAL_INT;
301 *vals = mcp3911_osr_table;
302 *length = ARRAY_SIZE(mcp3911_osr_table);
303 return IIO_AVAIL_LIST;
304 case IIO_CHAN_INFO_SCALE:
305 *type = IIO_VAL_INT_PLUS_NANO;
306 *vals = (int *)mcp3911_scale_table;
307 *length = ARRAY_SIZE(mcp3911_scale_table) * 2;
308 return IIO_AVAIL_LIST;
309 default:
310 return -EINVAL;
311 }
312 }
313
mcp3911_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * val,int * val2,long mask)314 static int mcp3911_read_raw(struct iio_dev *indio_dev,
315 struct iio_chan_spec const *channel, int *val,
316 int *val2, long mask)
317 {
318 struct mcp3911 *adc = iio_priv(indio_dev);
319 int ret;
320
321 guard(mutex)(&adc->lock);
322 switch (mask) {
323 case IIO_CHAN_INFO_RAW:
324 ret = mcp3911_read(adc,
325 MCP3911_CHANNEL(channel->channel), val, 3);
326 if (ret)
327 return ret;
328
329 *val = sign_extend32(*val, 23);
330 return IIO_VAL_INT;
331 case IIO_CHAN_INFO_OFFSET:
332 ret = adc->chip->get_offset(adc, channel->channel, val);
333 if (ret)
334 return ret;
335
336 return IIO_VAL_INT;
337 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
338 ret = adc->chip->get_osr(adc, val);
339 if (ret)
340 return ret;
341
342 return IIO_VAL_INT;
343 case IIO_CHAN_INFO_SCALE:
344 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0];
345 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1];
346 return IIO_VAL_INT_PLUS_NANO;
347 default:
348 return -EINVAL;
349 }
350 }
351
mcp3911_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int val,int val2,long mask)352 static int mcp3911_write_raw(struct iio_dev *indio_dev,
353 struct iio_chan_spec const *channel, int val,
354 int val2, long mask)
355 {
356 struct mcp3911 *adc = iio_priv(indio_dev);
357
358 guard(mutex)(&adc->lock);
359 switch (mask) {
360 case IIO_CHAN_INFO_SCALE:
361 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
362 if (val == mcp3911_scale_table[i][0] &&
363 val2 == mcp3911_scale_table[i][1]) {
364
365 adc->gain[channel->channel] = BIT(i);
366 return adc->chip->set_scale(adc, channel->channel, i);
367 }
368 }
369 return -EINVAL;
370 case IIO_CHAN_INFO_OFFSET:
371 if (val2 != 0)
372 return -EINVAL;
373
374 return adc->chip->set_offset(adc, channel->channel, val);
375 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
376 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
377 if (val == mcp3911_osr_table[i]) {
378 return adc->chip->set_osr(adc, i);
379 }
380 }
381 return -EINVAL;
382 default:
383 return -EINVAL;
384 }
385 }
386
mcp3911_calc_scale_table(u32 vref_mv)387 static int mcp3911_calc_scale_table(u32 vref_mv)
388 {
389 u32 div;
390 u64 tmp;
391
392 /*
393 * For 24-bit Conversion
394 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5
395 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5)
396 *
397 * ref = Reference voltage
398 * div = (2^23 * 1.5 * gain) = 12582912 * gain
399 */
400 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
401 div = 12582912 * BIT(i);
402 tmp = div_s64((s64)vref_mv * 1000000000LL, div);
403
404 mcp3911_scale_table[i][0] = 0;
405 mcp3911_scale_table[i][1] = tmp;
406 }
407
408 return 0;
409 }
410
411 #define MCP3911_CHAN(idx) { \
412 .type = IIO_VOLTAGE, \
413 .indexed = 1, \
414 .channel = idx, \
415 .scan_index = idx, \
416 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
417 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
418 BIT(IIO_CHAN_INFO_OFFSET) | \
419 BIT(IIO_CHAN_INFO_SCALE), \
420 .info_mask_shared_by_type_available = \
421 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
422 .info_mask_separate_available = \
423 BIT(IIO_CHAN_INFO_SCALE), \
424 .scan_type = { \
425 .sign = 's', \
426 .realbits = 24, \
427 .storagebits = 32, \
428 .endianness = IIO_BE, \
429 }, \
430 }
431
432 static const struct iio_chan_spec mcp3910_channels[] = {
433 MCP3911_CHAN(0),
434 MCP3911_CHAN(1),
435 IIO_CHAN_SOFT_TIMESTAMP(2),
436 };
437
438 static const struct iio_chan_spec mcp3911_channels[] = {
439 MCP3911_CHAN(0),
440 MCP3911_CHAN(1),
441 IIO_CHAN_SOFT_TIMESTAMP(2),
442 };
443
444 static const struct iio_chan_spec mcp3912_channels[] = {
445 MCP3911_CHAN(0),
446 MCP3911_CHAN(1),
447 MCP3911_CHAN(2),
448 MCP3911_CHAN(3),
449 IIO_CHAN_SOFT_TIMESTAMP(4),
450 };
451
452 static const struct iio_chan_spec mcp3913_channels[] = {
453 MCP3911_CHAN(0),
454 MCP3911_CHAN(1),
455 MCP3911_CHAN(2),
456 MCP3911_CHAN(3),
457 MCP3911_CHAN(4),
458 MCP3911_CHAN(5),
459 IIO_CHAN_SOFT_TIMESTAMP(6),
460 };
461
462 static const struct iio_chan_spec mcp3914_channels[] = {
463 MCP3911_CHAN(0),
464 MCP3911_CHAN(1),
465 MCP3911_CHAN(2),
466 MCP3911_CHAN(3),
467 MCP3911_CHAN(4),
468 MCP3911_CHAN(5),
469 MCP3911_CHAN(6),
470 MCP3911_CHAN(7),
471 IIO_CHAN_SOFT_TIMESTAMP(8),
472 };
473
474 static const struct iio_chan_spec mcp3918_channels[] = {
475 MCP3911_CHAN(0),
476 IIO_CHAN_SOFT_TIMESTAMP(1),
477 };
478
479 static const struct iio_chan_spec mcp3919_channels[] = {
480 MCP3911_CHAN(0),
481 MCP3911_CHAN(1),
482 MCP3911_CHAN(2),
483 IIO_CHAN_SOFT_TIMESTAMP(3),
484 };
485
mcp3911_trigger_handler(int irq,void * p)486 static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
487 {
488 struct iio_poll_func *pf = p;
489 struct iio_dev *indio_dev = pf->indio_dev;
490 struct mcp3911 *adc = iio_priv(indio_dev);
491 struct device *dev = &adc->spi->dev;
492 struct spi_transfer xfer[] = {
493 {
494 .tx_buf = &adc->tx_buf,
495 .len = 1,
496 }, {
497 .rx_buf = adc->rx_buf,
498 .len = (adc->chip->num_channels - 1) * 3,
499 },
500 };
501 int scan_index;
502 int i = 0;
503 int ret;
504
505 guard(mutex)(&adc->lock);
506 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr);
507 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer));
508 if (ret < 0) {
509 dev_warn(dev, "failed to get conversion data\n");
510 goto out;
511 }
512
513 iio_for_each_active_channel(indio_dev, scan_index) {
514 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index];
515
516 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]);
517 i++;
518 }
519 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
520 iio_get_time_ns(indio_dev));
521 out:
522 iio_trigger_notify_done(indio_dev->trig);
523
524 return IRQ_HANDLED;
525 }
526
527 static const struct iio_info mcp3911_info = {
528 .read_raw = mcp3911_read_raw,
529 .write_raw = mcp3911_write_raw,
530 .read_avail = mcp3911_read_avail,
531 .write_raw_get_fmt = mcp3911_write_raw_get_fmt,
532 };
533
mcp3911_config(struct mcp3911 * adc,bool external_vref)534 static int mcp3911_config(struct mcp3911 *adc, bool external_vref)
535 {
536 struct device *dev = &adc->spi->dev;
537 u32 regval;
538 int ret;
539
540 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
541 if (ret)
542 return ret;
543
544 regval &= ~MCP3911_CONFIG_VREFEXT;
545 if (external_vref) {
546 dev_dbg(dev, "use external voltage reference\n");
547 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);
548 } else {
549 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
550 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);
551 }
552
553 regval &= ~MCP3911_CONFIG_CLKEXT;
554 if (adc->clki) {
555 dev_dbg(dev, "use external clock as clocksource\n");
556 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);
557 } else {
558 dev_dbg(dev, "use crystal oscillator as clocksource\n");
559 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);
560 }
561
562 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);
563 if (ret)
564 return ret;
565
566 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2);
567 if (ret)
568 return ret;
569
570 /* Address counter incremented, cycle through register types */
571 regval &= ~MCP3911_STATUSCOM_READ;
572 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
573
574 regval &= ~MCP3911_STATUSCOM_DRHIZ;
575 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
576 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0);
577 else
578 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1);
579
580 /* Disable offset to ignore any old values in offset register */
581 regval &= ~MCP3911_STATUSCOM_EN_OFFCAL;
582
583 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
584 if (ret)
585 return ret;
586
587 /* Set gain to 1 for all channels */
588 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1);
589 if (ret)
590 return ret;
591
592 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
593 adc->gain[i] = 1;
594 regval &= ~MCP3911_GAIN_MASK(i);
595 }
596
597 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1);
598 }
599
mcp3910_config(struct mcp3911 * adc,bool external_vref)600 static int mcp3910_config(struct mcp3911 *adc, bool external_vref)
601 {
602 struct device *dev = &adc->spi->dev;
603 u32 regval;
604 int ret;
605
606 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3);
607 if (ret)
608 return ret;
609
610 regval &= ~MCP3910_CONFIG1_VREFEXT;
611 if (external_vref) {
612 dev_dbg(dev, "use external voltage reference\n");
613 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1);
614 } else {
615 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
616 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0);
617 }
618
619 regval &= ~MCP3910_CONFIG1_CLKEXT;
620 if (adc->clki) {
621 dev_dbg(dev, "use external clock as clocksource\n");
622 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1);
623 } else {
624 dev_dbg(dev, "use crystal oscillator as clocksource\n");
625 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0);
626 }
627
628 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3);
629 if (ret)
630 return ret;
631
632 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3);
633 if (ret)
634 return ret;
635
636 /* Address counter incremented, cycle through register types */
637 regval &= ~MCP3910_STATUSCOM_READ;
638 regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02);
639
640 regval &= ~MCP3910_STATUSCOM_DRHIZ;
641 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
642 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0);
643 else
644 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1);
645
646 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3);
647 if (ret)
648 return ret;
649
650 /* Set gain to 1 for all channels */
651 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3);
652 if (ret)
653 return ret;
654
655 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
656 adc->gain[i] = 1;
657 regval &= ~MCP3911_GAIN_MASK(i);
658 }
659 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3);
660 if (ret)
661 return ret;
662
663 /* Disable offset to ignore any old values in offset register */
664 return adc->chip->enable_offset(adc, 0);
665 }
666
mcp3911_set_trigger_state(struct iio_trigger * trig,bool enable)667 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable)
668 {
669 struct mcp3911 *adc = iio_trigger_get_drvdata(trig);
670
671 if (enable)
672 enable_irq(adc->spi->irq);
673 else
674 disable_irq(adc->spi->irq);
675
676 return 0;
677 }
678
679 static const struct iio_trigger_ops mcp3911_trigger_ops = {
680 .validate_device = iio_trigger_validate_own_device,
681 .set_trigger_state = mcp3911_set_trigger_state,
682 };
683
mcp3911_probe(struct spi_device * spi)684 static int mcp3911_probe(struct spi_device *spi)
685 {
686 struct device *dev = &spi->dev;
687 struct iio_dev *indio_dev;
688 struct mcp3911 *adc;
689 bool external_vref;
690 u32 vref_mv;
691 int ret;
692
693 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
694 if (!indio_dev)
695 return -ENOMEM;
696
697 adc = iio_priv(indio_dev);
698 adc->spi = spi;
699 adc->chip = spi_get_device_match_data(spi);
700
701 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
702 if (ret < 0 && ret != -ENODEV)
703 return dev_err_probe(dev, ret, "failed to get vref voltage\n");
704
705 external_vref = ret != -ENODEV;
706 vref_mv = external_vref ? ret / 1000 : MCP3911_INT_VREF_MV;
707
708 adc->clki = devm_clk_get_enabled(dev, NULL);
709 if (IS_ERR(adc->clki)) {
710 if (PTR_ERR(adc->clki) == -ENOENT) {
711 adc->clki = NULL;
712 } else {
713 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n");
714 }
715 }
716
717 /*
718 * Fallback to "device-addr" due to historical mismatch between
719 * dt-bindings and implementation.
720 */
721 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
722 if (ret)
723 device_property_read_u32(dev, "device-addr", &adc->dev_addr);
724 if (adc->dev_addr > 3) {
725 return dev_err_probe(dev, -EINVAL,
726 "invalid device address (%i). Must be in range 0-3.\n",
727 adc->dev_addr);
728 }
729 dev_dbg(dev, "use device address %i\n", adc->dev_addr);
730
731 ret = adc->chip->config(adc, external_vref);
732 if (ret)
733 return ret;
734
735 ret = mcp3911_calc_scale_table(vref_mv);
736 if (ret)
737 return ret;
738
739 /* Set gain to 1 for all channels */
740 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
741 adc->gain[i] = 1;
742 ret = mcp3911_update(adc, MCP3911_REG_GAIN,
743 MCP3911_GAIN_MASK(i),
744 MCP3911_GAIN_VAL(i, 0), 1);
745 if (ret)
746 return ret;
747 }
748
749 indio_dev->name = spi_get_device_id(spi)->name;
750 indio_dev->modes = INDIO_DIRECT_MODE;
751 indio_dev->info = &mcp3911_info;
752 spi_set_drvdata(spi, indio_dev);
753
754 indio_dev->channels = adc->chip->channels;
755 indio_dev->num_channels = adc->chip->num_channels;
756
757 mutex_init(&adc->lock);
758
759 if (spi->irq > 0) {
760 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
761 iio_device_id(indio_dev));
762 if (!adc->trig)
763 return -ENOMEM;
764
765 adc->trig->ops = &mcp3911_trigger_ops;
766 iio_trigger_set_drvdata(adc->trig, adc);
767 ret = devm_iio_trigger_register(dev, adc->trig);
768 if (ret)
769 return ret;
770
771 /*
772 * The device generates interrupts as long as it is powered up.
773 * Some platforms might not allow the option to power it down so
774 * don't enable the interrupt to avoid extra load on the system.
775 */
776 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll,
777 IRQF_NO_AUTOEN | IRQF_ONESHOT,
778 indio_dev->name, adc->trig);
779 if (ret)
780 return ret;
781 }
782
783 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
784 mcp3911_trigger_handler, NULL);
785 if (ret)
786 return ret;
787
788 return devm_iio_device_register(dev, indio_dev);
789 }
790
791 static const struct mcp3911_chip_info mcp3911_chip_info[] = {
792 [MCP3910] = {
793 .channels = mcp3910_channels,
794 .num_channels = ARRAY_SIZE(mcp3910_channels),
795 .config = mcp3910_config,
796 .get_osr = mcp3910_get_osr,
797 .set_osr = mcp3910_set_osr,
798 .enable_offset = mcp3910_enable_offset,
799 .get_offset = mcp3910_get_offset,
800 .set_offset = mcp3910_set_offset,
801 .set_scale = mcp3910_set_scale,
802 },
803 [MCP3911] = {
804 .channels = mcp3911_channels,
805 .num_channels = ARRAY_SIZE(mcp3911_channels),
806 .config = mcp3911_config,
807 .get_osr = mcp3911_get_osr,
808 .set_osr = mcp3911_set_osr,
809 .enable_offset = mcp3911_enable_offset,
810 .get_offset = mcp3911_get_offset,
811 .set_offset = mcp3911_set_offset,
812 .set_scale = mcp3911_set_scale,
813 },
814 [MCP3912] = {
815 .channels = mcp3912_channels,
816 .num_channels = ARRAY_SIZE(mcp3912_channels),
817 .config = mcp3910_config,
818 .get_osr = mcp3910_get_osr,
819 .set_osr = mcp3910_set_osr,
820 .enable_offset = mcp3910_enable_offset,
821 .get_offset = mcp3910_get_offset,
822 .set_offset = mcp3910_set_offset,
823 .set_scale = mcp3910_set_scale,
824 },
825 [MCP3913] = {
826 .channels = mcp3913_channels,
827 .num_channels = ARRAY_SIZE(mcp3913_channels),
828 .config = mcp3910_config,
829 .get_osr = mcp3910_get_osr,
830 .set_osr = mcp3910_set_osr,
831 .enable_offset = mcp3910_enable_offset,
832 .get_offset = mcp3910_get_offset,
833 .set_offset = mcp3910_set_offset,
834 .set_scale = mcp3910_set_scale,
835 },
836 [MCP3914] = {
837 .channels = mcp3914_channels,
838 .num_channels = ARRAY_SIZE(mcp3914_channels),
839 .config = mcp3910_config,
840 .get_osr = mcp3910_get_osr,
841 .set_osr = mcp3910_set_osr,
842 .enable_offset = mcp3910_enable_offset,
843 .get_offset = mcp3910_get_offset,
844 .set_offset = mcp3910_set_offset,
845 .set_scale = mcp3910_set_scale,
846 },
847 [MCP3918] = {
848 .channels = mcp3918_channels,
849 .num_channels = ARRAY_SIZE(mcp3918_channels),
850 .config = mcp3910_config,
851 .get_osr = mcp3910_get_osr,
852 .set_osr = mcp3910_set_osr,
853 .enable_offset = mcp3910_enable_offset,
854 .get_offset = mcp3910_get_offset,
855 .set_offset = mcp3910_set_offset,
856 .set_scale = mcp3910_set_scale,
857 },
858 [MCP3919] = {
859 .channels = mcp3919_channels,
860 .num_channels = ARRAY_SIZE(mcp3919_channels),
861 .config = mcp3910_config,
862 .get_osr = mcp3910_get_osr,
863 .set_osr = mcp3910_set_osr,
864 .enable_offset = mcp3910_enable_offset,
865 .get_offset = mcp3910_get_offset,
866 .set_offset = mcp3910_set_offset,
867 .set_scale = mcp3910_set_scale,
868 },
869 };
870 static const struct of_device_id mcp3911_dt_ids[] = {
871 { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] },
872 { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] },
873 { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] },
874 { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] },
875 { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] },
876 { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] },
877 { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] },
878 { }
879 };
880 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
881
882 static const struct spi_device_id mcp3911_id[] = {
883 { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] },
884 { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] },
885 { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] },
886 { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] },
887 { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] },
888 { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] },
889 { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] },
890 { }
891 };
892 MODULE_DEVICE_TABLE(spi, mcp3911_id);
893
894 static struct spi_driver mcp3911_driver = {
895 .driver = {
896 .name = "mcp3911",
897 .of_match_table = mcp3911_dt_ids,
898 },
899 .probe = mcp3911_probe,
900 .id_table = mcp3911_id,
901 };
902 module_spi_driver(mcp3911_driver);
903
904 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
905 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
906 MODULE_DESCRIPTION("Microchip Technology MCP3911");
907 MODULE_LICENSE("GPL v2");
908