1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * McBSP Sidetone support 4 * 5 * Copyright (C) 2004 Nokia Corporation 6 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> 7 * 8 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 9 * Peter Ujfalusi <peter.ujfalusi@ti.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include "omap-mcbsp.h" 24 #include "omap-mcbsp-priv.h" 25 26 /* OMAP3 sidetone control registers */ 27 #define OMAP_ST_REG_REV 0x00 28 #define OMAP_ST_REG_SYSCONFIG 0x10 29 #define OMAP_ST_REG_IRQSTATUS 0x18 30 #define OMAP_ST_REG_IRQENABLE 0x1C 31 #define OMAP_ST_REG_SGAINCR 0x24 32 #define OMAP_ST_REG_SFIRCR 0x28 33 #define OMAP_ST_REG_SSELCR 0x2C 34 35 /********************** McBSP SSELCR bit definitions ***********************/ 36 #define SIDETONEEN BIT(10) 37 38 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ 39 #define ST_AUTOIDLE BIT(0) 40 41 /********************** McBSP Sidetone SGAINCR bit definitions *************/ 42 #define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */ 43 #define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */ 44 45 /********************** McBSP Sidetone SFIRCR bit definitions **************/ 46 #define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */ 47 48 /********************** McBSP Sidetone SSELCR bit definitions **************/ 49 #define ST_SIDETONEEN BIT(0) 50 #define ST_COEFFWREN BIT(1) 51 #define ST_COEFFWRDONE BIT(2) 52 53 struct omap_mcbsp_st_data { 54 void __iomem *io_base_st; 55 struct clk *mcbsp_iclk; 56 bool running; 57 bool enabled; 58 s16 taps[128]; /* Sidetone filter coefficients */ 59 int nr_taps; /* Number of filter coefficients in use */ 60 s16 ch0gain; 61 s16 ch1gain; 62 }; 63 64 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 65 { 66 writel_relaxed(val, mcbsp->st_data->io_base_st + reg); 67 } 68 69 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) 70 { 71 return readl_relaxed(mcbsp->st_data->io_base_st + reg); 72 } 73 74 #define MCBSP_ST_READ(mcbsp, reg) omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) 75 #define MCBSP_ST_WRITE(mcbsp, reg, val) \ 76 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) 77 78 static void omap_mcbsp_st_on(struct omap_mcbsp *mcbsp) 79 { 80 unsigned int w; 81 82 if (mcbsp->pdata->force_ick_on) 83 mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, true); 84 85 /* Disable Sidetone clock auto-gating for normal operation */ 86 w = MCBSP_ST_READ(mcbsp, SYSCONFIG); 87 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); 88 89 /* Enable McBSP Sidetone */ 90 w = MCBSP_READ(mcbsp, SSELCR); 91 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); 92 93 /* Enable Sidetone from Sidetone Core */ 94 w = MCBSP_ST_READ(mcbsp, SSELCR); 95 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); 96 } 97 98 static void omap_mcbsp_st_off(struct omap_mcbsp *mcbsp) 99 { 100 unsigned int w; 101 102 w = MCBSP_ST_READ(mcbsp, SSELCR); 103 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); 104 105 w = MCBSP_READ(mcbsp, SSELCR); 106 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); 107 108 /* Enable Sidetone clock auto-gating to reduce power consumption */ 109 w = MCBSP_ST_READ(mcbsp, SYSCONFIG); 110 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE); 111 112 if (mcbsp->pdata->force_ick_on) 113 mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, false); 114 } 115 116 static void omap_mcbsp_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) 117 { 118 u16 val, i; 119 120 val = MCBSP_ST_READ(mcbsp, SSELCR); 121 122 if (val & ST_COEFFWREN) 123 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); 124 125 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN); 126 127 for (i = 0; i < 128; i++) 128 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]); 129 130 i = 0; 131 132 val = MCBSP_ST_READ(mcbsp, SSELCR); 133 while (!(val & ST_COEFFWRDONE) && (++i < 1000)) 134 val = MCBSP_ST_READ(mcbsp, SSELCR); 135 136 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); 137 138 if (i == 1000) 139 dev_err(mcbsp->dev, "McBSP FIR load error!\n"); 140 } 141 142 static void omap_mcbsp_st_chgain(struct omap_mcbsp *mcbsp) 143 { 144 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 145 146 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | 147 ST_CH1GAIN(st_data->ch1gain)); 148 } 149 150 static int omap_mcbsp_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, 151 s16 chgain) 152 { 153 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 154 int ret = 0; 155 156 if (!st_data) 157 return -ENOENT; 158 159 guard(spinlock_irq)(&mcbsp->lock); 160 if (channel == 0) 161 st_data->ch0gain = chgain; 162 else if (channel == 1) 163 st_data->ch1gain = chgain; 164 else 165 ret = -EINVAL; 166 167 if (st_data->enabled) 168 omap_mcbsp_st_chgain(mcbsp); 169 170 return ret; 171 } 172 173 static int omap_mcbsp_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, 174 s16 *chgain) 175 { 176 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 177 int ret = 0; 178 179 if (!st_data) 180 return -ENOENT; 181 182 guard(spinlock_irq)(&mcbsp->lock); 183 if (channel == 0) 184 *chgain = st_data->ch0gain; 185 else if (channel == 1) 186 *chgain = st_data->ch1gain; 187 else 188 ret = -EINVAL; 189 190 return ret; 191 } 192 193 static int omap_mcbsp_st_enable(struct omap_mcbsp *mcbsp) 194 { 195 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 196 197 if (!st_data) 198 return -ENODEV; 199 200 guard(spinlock_irq)(&mcbsp->lock); 201 st_data->enabled = 1; 202 omap_mcbsp_st_start(mcbsp); 203 204 return 0; 205 } 206 207 static int omap_mcbsp_st_disable(struct omap_mcbsp *mcbsp) 208 { 209 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 210 int ret = 0; 211 212 if (!st_data) 213 return -ENODEV; 214 215 guard(spinlock_irq)(&mcbsp->lock); 216 omap_mcbsp_st_stop(mcbsp); 217 st_data->enabled = 0; 218 219 return ret; 220 } 221 222 static int omap_mcbsp_st_is_enabled(struct omap_mcbsp *mcbsp) 223 { 224 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 225 226 if (!st_data) 227 return -ENODEV; 228 229 return st_data->enabled; 230 } 231 232 static ssize_t st_taps_show(struct device *dev, 233 struct device_attribute *attr, char *buf) 234 { 235 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 236 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 237 ssize_t status = 0; 238 int i; 239 240 guard(spinlock_irq)(&mcbsp->lock); 241 for (i = 0; i < st_data->nr_taps; i++) 242 status += sysfs_emit_at(buf, status, (i ? ", %d" : "%d"), 243 st_data->taps[i]); 244 if (i) 245 status += sysfs_emit_at(buf, status, "\n"); 246 247 return status; 248 } 249 250 static ssize_t st_taps_store(struct device *dev, 251 struct device_attribute *attr, 252 const char *buf, size_t size) 253 { 254 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 255 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 256 int val, tmp, status, i = 0; 257 258 guard(spinlock_irq)(&mcbsp->lock); 259 memset(st_data->taps, 0, sizeof(st_data->taps)); 260 st_data->nr_taps = 0; 261 262 do { 263 status = sscanf(buf, "%d%n", &val, &tmp); 264 if (status < 0 || status == 0) { 265 return -EINVAL; 266 } 267 if (val < -32768 || val > 32767) { 268 return -EINVAL; 269 } 270 st_data->taps[i++] = val; 271 buf += tmp; 272 if (*buf != ',') 273 break; 274 buf++; 275 } while (1); 276 277 st_data->nr_taps = i; 278 279 return size; 280 } 281 282 static DEVICE_ATTR_RW(st_taps); 283 284 static const struct attribute *sidetone_attrs[] = { 285 &dev_attr_st_taps.attr, 286 NULL, 287 }; 288 289 static const struct attribute_group sidetone_attr_group = { 290 .attrs = (struct attribute **)sidetone_attrs, 291 }; 292 293 int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp) 294 { 295 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 296 297 if (st_data->enabled && !st_data->running) { 298 omap_mcbsp_st_fir_write(mcbsp, st_data->taps); 299 omap_mcbsp_st_chgain(mcbsp); 300 301 if (!mcbsp->free) { 302 omap_mcbsp_st_on(mcbsp); 303 st_data->running = 1; 304 } 305 } 306 307 return 0; 308 } 309 310 int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp) 311 { 312 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 313 314 if (st_data->running) { 315 if (!mcbsp->free) { 316 omap_mcbsp_st_off(mcbsp); 317 st_data->running = 0; 318 } 319 } 320 321 return 0; 322 } 323 324 int omap_mcbsp_st_init(struct platform_device *pdev) 325 { 326 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 327 struct omap_mcbsp_st_data *st_data; 328 struct resource *res; 329 int ret; 330 331 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); 332 if (!res) 333 return 0; 334 335 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL); 336 if (!st_data) 337 return -ENOMEM; 338 339 st_data->mcbsp_iclk = devm_clk_get(mcbsp->dev, "ick"); 340 if (IS_ERR(st_data->mcbsp_iclk)) { 341 dev_warn(mcbsp->dev, 342 "Failed to get ick, sidetone might be broken\n"); 343 st_data->mcbsp_iclk = NULL; 344 } 345 346 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start, 347 resource_size(res)); 348 if (!st_data->io_base_st) 349 return -ENOMEM; 350 351 ret = devm_device_add_group(mcbsp->dev, &sidetone_attr_group); 352 if (ret) 353 return ret; 354 355 mcbsp->st_data = st_data; 356 357 return 0; 358 } 359 360 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, 361 struct snd_ctl_elem_info *uinfo) 362 { 363 struct soc_mixer_control *mc = 364 (struct soc_mixer_control *)kcontrol->private_value; 365 int max = mc->max; 366 int min = mc->min; 367 368 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 369 uinfo->count = 1; 370 uinfo->value.integer.min = min; 371 uinfo->value.integer.max = max; 372 return 0; 373 } 374 375 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \ 376 static int \ 377 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ 378 struct snd_ctl_elem_value *uc) \ 379 { \ 380 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ 381 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ 382 struct soc_mixer_control *mc = \ 383 (struct soc_mixer_control *)kc->private_value; \ 384 int max = mc->max; \ 385 int min = mc->min; \ 386 int val = uc->value.integer.value[0]; \ 387 \ 388 if (val < min || val > max) \ 389 return -EINVAL; \ 390 \ 391 /* OMAP McBSP implementation uses index values 0..4 */ \ 392 return omap_mcbsp_st_set_chgain(mcbsp, channel, val); \ 393 } \ 394 \ 395 static int \ 396 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ 397 struct snd_ctl_elem_value *uc) \ 398 { \ 399 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ 400 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ 401 s16 chgain; \ 402 \ 403 if (omap_mcbsp_st_get_chgain(mcbsp, channel, &chgain)) \ 404 return -EAGAIN; \ 405 \ 406 uc->value.integer.value[0] = chgain; \ 407 return 0; \ 408 } 409 410 OMAP_MCBSP_ST_CHANNEL_VOLUME(0) 411 OMAP_MCBSP_ST_CHANNEL_VOLUME(1) 412 413 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, 414 struct snd_ctl_elem_value *ucontrol) 415 { 416 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 417 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 418 u8 value = ucontrol->value.integer.value[0]; 419 420 if (value == omap_mcbsp_st_is_enabled(mcbsp)) 421 return 0; 422 423 if (value) 424 omap_mcbsp_st_enable(mcbsp); 425 else 426 omap_mcbsp_st_disable(mcbsp); 427 428 return 1; 429 } 430 431 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, 432 struct snd_ctl_elem_value *ucontrol) 433 { 434 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 435 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 436 437 ucontrol->value.integer.value[0] = omap_mcbsp_st_is_enabled(mcbsp); 438 return 0; 439 } 440 441 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ 442 xhandler_get, xhandler_put) \ 443 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 444 .info = omap_mcbsp_st_info_volsw, \ 445 .get = xhandler_get, .put = xhandler_put, \ 446 .private_value = (unsigned long)&(struct soc_mixer_control) \ 447 {.min = xmin, .max = xmax} } 448 449 #define OMAP_MCBSP_ST_CONTROLS(port) \ 450 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \ 451 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \ 452 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \ 453 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \ 454 -32768, 32767, \ 455 omap_mcbsp_get_st_ch0_volume, \ 456 omap_mcbsp_set_st_ch0_volume), \ 457 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \ 458 -32768, 32767, \ 459 omap_mcbsp_get_st_ch1_volume, \ 460 omap_mcbsp_set_st_ch1_volume), \ 461 } 462 463 OMAP_MCBSP_ST_CONTROLS(2); 464 OMAP_MCBSP_ST_CONTROLS(3); 465 466 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd, int port_id) 467 { 468 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 469 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 470 471 if (!mcbsp->st_data) { 472 dev_warn(mcbsp->dev, "No sidetone data for port\n"); 473 return 0; 474 } 475 476 switch (port_id) { 477 case 2: /* McBSP 2 */ 478 return snd_soc_add_dai_controls(cpu_dai, 479 omap_mcbsp2_st_controls, 480 ARRAY_SIZE(omap_mcbsp2_st_controls)); 481 case 3: /* McBSP 3 */ 482 return snd_soc_add_dai_controls(cpu_dai, 483 omap_mcbsp3_st_controls, 484 ARRAY_SIZE(omap_mcbsp3_st_controls)); 485 default: 486 dev_err(mcbsp->dev, "Port %d not supported\n", port_id); 487 break; 488 } 489 490 return -EINVAL; 491 } 492 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); 493