1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #include <linux/devcoredump.h> 8 #include <linux/devm-helpers.h> 9 #include <linux/firmware.h> 10 #include <linux/platform_device.h> 11 #include <linux/of_net.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_reserved_mem.h> 14 #include <linux/regmap.h> 15 16 #include "airoha_eth.h" 17 18 #define NPU_EN7581_FIRMWARE_DATA "airoha/en7581_npu_data.bin" 19 #define NPU_EN7581_FIRMWARE_RV32 "airoha/en7581_npu_rv32.bin" 20 #define NPU_EN7581_7996_FIRMWARE_DATA "airoha/en7581_MT7996_npu_data.bin" 21 #define NPU_EN7581_7996_FIRMWARE_RV32 "airoha/en7581_MT7996_npu_rv32.bin" 22 #define NPU_AN7583_FIRMWARE_DATA "airoha/an7583_npu_data.bin" 23 #define NPU_AN7583_FIRMWARE_RV32 "airoha/an7583_npu_rv32.bin" 24 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000 25 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x10000 26 #define NPU_DUMP_SIZE 512 27 28 #define REG_NPU_LOCAL_SRAM 0x0 29 30 #define NPU_PC_BASE_ADDR 0x305000 31 #define REG_PC_DBG(_n) (0x305000 + ((_n) * 0x100)) 32 33 #define NPU_CLUSTER_BASE_ADDR 0x306000 34 35 #define REG_CR_BOOT_TRIGGER (NPU_CLUSTER_BASE_ADDR + 0x000) 36 #define REG_CR_BOOT_CONFIG (NPU_CLUSTER_BASE_ADDR + 0x004) 37 #define REG_CR_BOOT_BASE(_n) (NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2)) 38 39 #define NPU_MBOX_BASE_ADDR 0x30c000 40 41 #define REG_CR_MBOX_INT_STATUS (NPU_MBOX_BASE_ADDR + 0x000) 42 #define MBOX_INT_STATUS_MASK BIT(8) 43 44 #define REG_CR_MBOX_INT_MASK(_n) (NPU_MBOX_BASE_ADDR + 0x004 + ((_n) << 2)) 45 #define REG_CR_MBQ0_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x030 + ((_n) << 2)) 46 #define REG_CR_MBQ8_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x0b0 + ((_n) << 2)) 47 #define REG_CR_NPU_MIB(_n) (NPU_MBOX_BASE_ADDR + 0x140 + ((_n) << 2)) 48 49 #define NPU_WLAN_BASE_ADDR 0x30d000 50 51 #define REG_IRQ_STATUS (NPU_WLAN_BASE_ADDR + 0x030) 52 #define REG_IRQ_RXDONE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 2) + 0x034) 53 #define NPU_IRQ_RX_MASK(_n) ((_n) == 1 ? BIT(17) : BIT(16)) 54 55 #define REG_TX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x080) 56 #define REG_TX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x084) 57 #define REG_TX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x088) 58 #define REG_TX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x08c) 59 60 #define REG_RX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x180) 61 #define REG_RX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x184) 62 #define REG_RX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x188) 63 #define REG_RX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x18c) 64 65 #define NPU_TIMER_BASE_ADDR 0x310100 66 #define REG_WDT_TIMER_CTRL(_n) (NPU_TIMER_BASE_ADDR + ((_n) * 0x100)) 67 #define WDT_EN_MASK BIT(25) 68 #define WDT_INTR_MASK BIT(21) 69 70 enum { 71 NPU_OP_SET = 1, 72 NPU_OP_SET_NO_WAIT, 73 NPU_OP_GET, 74 NPU_OP_GET_NO_WAIT, 75 }; 76 77 enum { 78 NPU_FUNC_WIFI, 79 NPU_FUNC_TUNNEL, 80 NPU_FUNC_NOTIFY, 81 NPU_FUNC_DBA, 82 NPU_FUNC_TR471, 83 NPU_FUNC_PPE, 84 }; 85 86 enum { 87 NPU_MBOX_ERROR, 88 NPU_MBOX_SUCCESS, 89 }; 90 91 enum { 92 PPE_FUNC_SET_WAIT, 93 PPE_FUNC_SET_WAIT_HWNAT_INIT, 94 PPE_FUNC_SET_WAIT_HWNAT_DEINIT, 95 PPE_FUNC_SET_WAIT_API, 96 PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP, 97 }; 98 99 enum { 100 PPE2_SRAM_SET_ENTRY, 101 PPE_SRAM_SET_ENTRY, 102 PPE_SRAM_SET_VAL, 103 PPE_SRAM_RESET_VAL, 104 }; 105 106 enum { 107 QDMA_WAN_ETHER = 1, 108 QDMA_WAN_PON_XDSL, 109 }; 110 111 struct airoha_npu_fw { 112 const char *name; 113 int max_size; 114 }; 115 116 struct airoha_npu_soc_data { 117 struct airoha_npu_fw fw_rv32; 118 struct airoha_npu_fw fw_data; 119 }; 120 121 #define MBOX_MSG_FUNC_ID GENMASK(14, 11) 122 #define MBOX_MSG_STATIC_BUF BIT(5) 123 #define MBOX_MSG_STATUS GENMASK(4, 2) 124 #define MBOX_MSG_DONE BIT(1) 125 #define MBOX_MSG_WAIT_RSP BIT(0) 126 127 #define PPE_TYPE_L2B_IPV4 2 128 #define PPE_TYPE_L2B_IPV4_IPV6 3 129 130 struct ppe_mbox_data { 131 u32 func_type; 132 u32 func_id; 133 union { 134 struct { 135 u8 cds; 136 u8 xpon_hal_api; 137 u8 wan_xsi; 138 u8 ct_joyme4; 139 u8 max_packet; 140 u8 rsv[3]; 141 u32 ppe_type; 142 u32 wan_mode; 143 u32 wan_sel; 144 } init_info; 145 struct { 146 u32 func_id; 147 u32 size; 148 u32 data; 149 } set_info; 150 struct { 151 u32 npu_stats_addr; 152 u32 foe_stats_addr; 153 } stats_info; 154 }; 155 }; 156 157 struct wlan_mbox_data { 158 u32 ifindex:4; 159 u32 func_type:4; 160 u32 func_id; 161 DECLARE_FLEX_ARRAY(u8, d); 162 }; 163 164 static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id, 165 void *p, int size) 166 { 167 u16 core = 0; /* FIXME */ 168 u32 val, offset = core << 4; 169 dma_addr_t dma_addr; 170 int ret; 171 172 dma_addr = dma_map_single(npu->dev, p, size, DMA_BIDIRECTIONAL); 173 ret = dma_mapping_error(npu->dev, dma_addr); 174 if (ret) 175 return ret; 176 177 spin_lock_bh(&npu->cores[core].lock); 178 179 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); 180 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size); 181 regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); 182 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1); 183 val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP; 184 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val); 185 186 ret = regmap_read_poll_timeout_atomic(npu->regmap, 187 REG_CR_MBQ0_CTRL(3) + offset, 188 val, (val & MBOX_MSG_DONE), 189 100, 100 * MSEC_PER_SEC); 190 if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS) 191 ret = -EINVAL; 192 193 spin_unlock_bh(&npu->cores[core].lock); 194 195 dma_unmap_single(npu->dev, dma_addr, size, DMA_BIDIRECTIONAL); 196 197 return ret; 198 } 199 200 static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr, 201 const char *fw_name, int fw_max_size) 202 { 203 const struct firmware *fw; 204 int ret; 205 206 ret = request_firmware_direct(&fw, fw_name, dev); 207 if (ret) 208 return dev_err_probe(dev, ret == -ENOENT ? -EPROBE_DEFER : ret, 209 "failed to load %s\n", fw_name); 210 211 if (fw->size > fw_max_size) { 212 dev_err(dev, "%s: fw size too overlimit (%zu)\n", 213 fw_name, fw->size); 214 ret = -E2BIG; 215 goto out; 216 } 217 218 memcpy_toio(addr, fw->data, fw->size); 219 out: 220 release_firmware(fw); 221 222 return ret; 223 } 224 225 static int 226 airoha_npu_load_firmware_from_dts(struct device *dev, void __iomem *addr, 227 void __iomem *base) 228 { 229 const char *fw_names[2]; 230 int ret; 231 232 ret = of_property_read_string_array(dev->of_node, "firmware-name", 233 fw_names, ARRAY_SIZE(fw_names)); 234 if (ret != ARRAY_SIZE(fw_names)) 235 return dev_err_probe(dev, -EINVAL, 236 "invalid firmware-name property\n"); 237 238 ret = airoha_npu_load_firmware(dev, addr, fw_names[0], 239 NPU_EN7581_FIRMWARE_RV32_MAX_SIZE); 240 if (ret) 241 return ret; 242 243 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM, 244 fw_names[1], 245 NPU_EN7581_FIRMWARE_DATA_MAX_SIZE); 246 } 247 248 static int airoha_npu_run_firmware(struct device *dev, void __iomem *base, 249 struct resource *res) 250 { 251 const struct airoha_npu_soc_data *soc; 252 void __iomem *addr; 253 int ret; 254 255 soc = of_device_get_match_data(dev); 256 if (!soc) 257 return -EINVAL; 258 259 addr = devm_ioremap_resource(dev, res); 260 if (IS_ERR(addr)) 261 return PTR_ERR(addr); 262 263 /* Try to load firmware images using the firmware names provided via 264 * dts if available. 265 */ 266 if (of_find_property(dev->of_node, "firmware-name", NULL)) 267 return airoha_npu_load_firmware_from_dts(dev, addr, base); 268 269 /* Load rv32 npu firmware */ 270 ret = airoha_npu_load_firmware(dev, addr, soc->fw_rv32.name, 271 soc->fw_rv32.max_size); 272 if (ret) 273 return ret; 274 275 /* Load data npu firmware */ 276 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM, 277 soc->fw_data.name, 278 soc->fw_data.max_size); 279 } 280 281 static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance) 282 { 283 struct airoha_npu *npu = npu_instance; 284 285 /* clear mbox interrupt status */ 286 regmap_write(npu->regmap, REG_CR_MBOX_INT_STATUS, 287 MBOX_INT_STATUS_MASK); 288 289 /* acknowledge npu */ 290 regmap_update_bits(npu->regmap, REG_CR_MBQ8_CTRL(3), 291 MBOX_MSG_STATUS | MBOX_MSG_DONE, MBOX_MSG_DONE); 292 293 return IRQ_HANDLED; 294 } 295 296 static void airoha_npu_wdt_work(struct work_struct *work) 297 { 298 struct airoha_npu_core *core; 299 struct airoha_npu *npu; 300 void *dump; 301 u32 val[3]; 302 int c; 303 304 core = container_of(work, struct airoha_npu_core, wdt_work); 305 npu = core->npu; 306 307 dump = vzalloc(NPU_DUMP_SIZE); 308 if (!dump) 309 return; 310 311 c = core - &npu->cores[0]; 312 regmap_bulk_read(npu->regmap, REG_PC_DBG(c), val, ARRAY_SIZE(val)); 313 snprintf(dump, NPU_DUMP_SIZE, "PC: %08x SP: %08x LR: %08x\n", 314 val[0], val[1], val[2]); 315 316 dev_coredumpv(npu->dev, dump, NPU_DUMP_SIZE, GFP_KERNEL); 317 } 318 319 static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance) 320 { 321 struct airoha_npu_core *core = core_instance; 322 struct airoha_npu *npu = core->npu; 323 int c = core - &npu->cores[0]; 324 u32 val; 325 326 regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK); 327 if (!regmap_read(npu->regmap, REG_WDT_TIMER_CTRL(c), &val) && 328 FIELD_GET(WDT_EN_MASK, val)) 329 schedule_work(&core->wdt_work); 330 331 return IRQ_HANDLED; 332 } 333 334 static int airoha_npu_ppe_init(struct airoha_npu *npu) 335 { 336 struct ppe_mbox_data *ppe_data; 337 int err; 338 339 ppe_data = kzalloc_obj(*ppe_data); 340 if (!ppe_data) 341 return -ENOMEM; 342 343 ppe_data->func_type = NPU_OP_SET; 344 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT; 345 ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6; 346 ppe_data->init_info.wan_mode = QDMA_WAN_ETHER; 347 348 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 349 sizeof(*ppe_data)); 350 kfree(ppe_data); 351 352 return err; 353 } 354 355 static int airoha_npu_ppe_deinit(struct airoha_npu *npu) 356 { 357 struct ppe_mbox_data *ppe_data; 358 int err; 359 360 ppe_data = kzalloc_obj(*ppe_data); 361 if (!ppe_data) 362 return -ENOMEM; 363 364 ppe_data->func_type = NPU_OP_SET; 365 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT; 366 367 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 368 sizeof(*ppe_data)); 369 kfree(ppe_data); 370 371 return err; 372 } 373 374 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu, 375 dma_addr_t foe_addr, 376 int sram_num_entries) 377 { 378 struct ppe_mbox_data *ppe_data; 379 int err; 380 381 ppe_data = kzalloc_obj(*ppe_data); 382 if (!ppe_data) 383 return -ENOMEM; 384 385 ppe_data->func_type = NPU_OP_SET; 386 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 387 ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL; 388 ppe_data->set_info.data = foe_addr; 389 ppe_data->set_info.size = sram_num_entries; 390 391 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 392 sizeof(*ppe_data)); 393 kfree(ppe_data); 394 395 return err; 396 } 397 398 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu, 399 dma_addr_t foe_addr, 400 u32 entry_size, u32 hash, bool ppe2) 401 { 402 struct ppe_mbox_data *ppe_data; 403 int err; 404 405 ppe_data = kzalloc_obj(*ppe_data, GFP_ATOMIC); 406 if (!ppe_data) 407 return -ENOMEM; 408 409 ppe_data->func_type = NPU_OP_SET; 410 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 411 ppe_data->set_info.data = foe_addr; 412 ppe_data->set_info.size = entry_size; 413 ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY 414 : PPE_SRAM_SET_ENTRY; 415 416 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 417 sizeof(*ppe_data)); 418 if (err) 419 goto out; 420 421 ppe_data->set_info.func_id = PPE_SRAM_SET_VAL; 422 ppe_data->set_info.data = hash; 423 ppe_data->set_info.size = sizeof(u32); 424 425 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 426 sizeof(*ppe_data)); 427 out: 428 kfree(ppe_data); 429 430 return err; 431 } 432 433 static int airoha_npu_ppe_stats_setup(struct airoha_npu *npu, 434 dma_addr_t foe_stats_addr, 435 u32 num_stats_entries) 436 { 437 int err, size = num_stats_entries * sizeof(*npu->stats); 438 struct ppe_mbox_data *ppe_data; 439 440 ppe_data = kzalloc_obj(*ppe_data, GFP_ATOMIC); 441 if (!ppe_data) 442 return -ENOMEM; 443 444 ppe_data->func_type = NPU_OP_SET; 445 ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP; 446 ppe_data->stats_info.foe_stats_addr = foe_stats_addr; 447 448 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 449 sizeof(*ppe_data)); 450 if (err) 451 goto out; 452 453 npu->stats = devm_ioremap(npu->dev, 454 ppe_data->stats_info.npu_stats_addr, 455 size); 456 if (!npu->stats) 457 err = -ENOMEM; 458 out: 459 kfree(ppe_data); 460 461 return err; 462 } 463 464 static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex, 465 enum airoha_npu_wlan_set_cmd func_id, 466 void *data, int data_len, gfp_t gfp) 467 { 468 struct wlan_mbox_data *wlan_data; 469 int err, len; 470 471 len = sizeof(*wlan_data) + data_len; 472 wlan_data = kzalloc(len, gfp); 473 if (!wlan_data) 474 return -ENOMEM; 475 476 wlan_data->ifindex = ifindex; 477 wlan_data->func_type = NPU_OP_SET; 478 wlan_data->func_id = func_id; 479 memcpy(wlan_data->d, data, data_len); 480 481 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 482 kfree(wlan_data); 483 484 return err; 485 } 486 487 static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex, 488 enum airoha_npu_wlan_get_cmd func_id, 489 void *data, int data_len, gfp_t gfp) 490 { 491 struct wlan_mbox_data *wlan_data; 492 int err, len; 493 494 len = sizeof(*wlan_data) + data_len; 495 wlan_data = kzalloc(len, gfp); 496 if (!wlan_data) 497 return -ENOMEM; 498 499 wlan_data->ifindex = ifindex; 500 wlan_data->func_type = NPU_OP_GET; 501 wlan_data->func_id = func_id; 502 503 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 504 if (!err) 505 memcpy(data, wlan_data->d, data_len); 506 kfree(wlan_data); 507 508 return err; 509 } 510 511 static int 512 airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu, 513 int ifindex, const char *name, 514 enum airoha_npu_wlan_set_cmd func_id) 515 { 516 struct device *dev = npu->dev; 517 struct resource res; 518 int err; 519 u32 val; 520 521 err = of_reserved_mem_region_to_resource_byname(dev->of_node, name, 522 &res); 523 if (err) 524 return err; 525 526 val = res.start; 527 return airoha_npu_wlan_msg_send(npu, ifindex, func_id, &val, 528 sizeof(val), GFP_KERNEL); 529 } 530 531 static int airoha_npu_wlan_init_memory(struct airoha_npu *npu) 532 { 533 enum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU; 534 u32 val = 0; 535 int err; 536 537 err = airoha_npu_wlan_msg_send(npu, 1, cmd, &val, sizeof(val), 538 GFP_KERNEL); 539 if (err) 540 return err; 541 542 cmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR; 543 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-bufid", cmd); 544 if (err) 545 return err; 546 547 cmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR; 548 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "pkt", cmd); 549 if (err) 550 return err; 551 552 cmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR; 553 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-pkt", cmd); 554 if (err) 555 return err; 556 557 if (of_property_match_string(npu->dev->of_node, "memory-region-names", 558 "ba") >= 0) { 559 cmd = WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR; 560 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "ba", cmd); 561 if (err) 562 return err; 563 } 564 565 cmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU; 566 return airoha_npu_wlan_msg_send(npu, 0, cmd, &val, sizeof(val), 567 GFP_KERNEL); 568 } 569 570 static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid, 571 bool xmit) 572 { 573 if (xmit) 574 return REG_TX_BASE(qid + 2); 575 576 return REG_RX_BASE(qid); 577 } 578 579 static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val) 580 { 581 regmap_write(npu->regmap, REG_IRQ_STATUS, val); 582 } 583 584 static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q) 585 { 586 u32 val; 587 588 regmap_read(npu->regmap, REG_IRQ_STATUS, &val); 589 return val; 590 } 591 592 static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q) 593 { 594 regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 595 } 596 597 static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q) 598 { 599 regmap_clear_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 600 } 601 602 struct airoha_npu *airoha_npu_get(struct device *dev) 603 { 604 struct platform_device *pdev; 605 struct device_node *np; 606 struct airoha_npu *npu; 607 608 np = of_parse_phandle(dev->of_node, "airoha,npu", 0); 609 if (!np) 610 return ERR_PTR(-ENODEV); 611 612 pdev = of_find_device_by_node(np); 613 614 if (!pdev) { 615 dev_err(dev, "cannot find device node %s\n", np->name); 616 of_node_put(np); 617 return ERR_PTR(-ENODEV); 618 } 619 of_node_put(np); 620 621 if (!try_module_get(THIS_MODULE)) { 622 dev_err(dev, "failed to get the device driver module\n"); 623 npu = ERR_PTR(-ENODEV); 624 goto error_pdev_put; 625 } 626 627 npu = platform_get_drvdata(pdev); 628 if (!npu) { 629 npu = ERR_PTR(-ENODEV); 630 goto error_module_put; 631 } 632 633 if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER)) { 634 dev_err(&pdev->dev, 635 "failed to create device link to consumer %s\n", 636 dev_name(dev)); 637 npu = ERR_PTR(-EINVAL); 638 goto error_module_put; 639 } 640 641 return npu; 642 643 error_module_put: 644 module_put(THIS_MODULE); 645 error_pdev_put: 646 platform_device_put(pdev); 647 648 return npu; 649 } 650 EXPORT_SYMBOL_GPL(airoha_npu_get); 651 652 void airoha_npu_put(struct airoha_npu *npu) 653 { 654 module_put(THIS_MODULE); 655 put_device(npu->dev); 656 } 657 EXPORT_SYMBOL_GPL(airoha_npu_put); 658 659 static const struct airoha_npu_soc_data en7581_npu_soc_data = { 660 .fw_rv32 = { 661 .name = NPU_EN7581_FIRMWARE_RV32, 662 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE, 663 }, 664 .fw_data = { 665 .name = NPU_EN7581_FIRMWARE_DATA, 666 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE, 667 }, 668 }; 669 670 static const struct airoha_npu_soc_data an7583_npu_soc_data = { 671 .fw_rv32 = { 672 .name = NPU_AN7583_FIRMWARE_RV32, 673 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE, 674 }, 675 .fw_data = { 676 .name = NPU_AN7583_FIRMWARE_DATA, 677 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE, 678 }, 679 }; 680 681 static const struct of_device_id of_airoha_npu_match[] = { 682 { .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data }, 683 { .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data }, 684 { /* sentinel */ } 685 }; 686 MODULE_DEVICE_TABLE(of, of_airoha_npu_match); 687 688 static const struct regmap_config regmap_config = { 689 .name = "npu", 690 .reg_bits = 32, 691 .val_bits = 32, 692 .reg_stride = 4, 693 .disable_locking = true, 694 }; 695 696 static int airoha_npu_probe(struct platform_device *pdev) 697 { 698 struct device *dev = &pdev->dev; 699 struct airoha_npu *npu; 700 struct resource res; 701 void __iomem *base; 702 int i, irq, err; 703 u32 val; 704 705 base = devm_platform_ioremap_resource(pdev, 0); 706 if (IS_ERR(base)) 707 return PTR_ERR(base); 708 709 npu = devm_kzalloc(dev, sizeof(*npu), GFP_KERNEL); 710 if (!npu) 711 return -ENOMEM; 712 713 npu->dev = dev; 714 npu->ops.ppe_init = airoha_npu_ppe_init; 715 npu->ops.ppe_deinit = airoha_npu_ppe_deinit; 716 npu->ops.ppe_init_stats = airoha_npu_ppe_stats_setup; 717 npu->ops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries; 718 npu->ops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry; 719 npu->ops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory; 720 npu->ops.wlan_send_msg = airoha_npu_wlan_msg_send; 721 npu->ops.wlan_get_msg = airoha_npu_wlan_msg_get; 722 npu->ops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get; 723 npu->ops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set; 724 npu->ops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get; 725 npu->ops.wlan_enable_irq = airoha_npu_wlan_irq_enable; 726 npu->ops.wlan_disable_irq = airoha_npu_wlan_irq_disable; 727 728 npu->regmap = devm_regmap_init_mmio(dev, base, ®map_config); 729 if (IS_ERR(npu->regmap)) 730 return PTR_ERR(npu->regmap); 731 732 err = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 733 if (err) 734 return err; 735 736 irq = platform_get_irq(pdev, 0); 737 if (irq < 0) 738 return irq; 739 740 err = devm_request_irq(dev, irq, airoha_npu_mbox_handler, 741 IRQF_SHARED, "airoha-npu-mbox", npu); 742 if (err) 743 return err; 744 745 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) { 746 struct airoha_npu_core *core = &npu->cores[i]; 747 748 spin_lock_init(&core->lock); 749 core->npu = npu; 750 751 irq = platform_get_irq(pdev, i + 1); 752 if (irq < 0) 753 return irq; 754 755 err = devm_work_autocancel(dev, &core->wdt_work, 756 airoha_npu_wdt_work); 757 if (err) 758 return err; 759 760 err = devm_request_irq(dev, irq, airoha_npu_wdt_handler, 761 IRQF_SHARED, "airoha-npu-wdt", core); 762 if (err) 763 return err; 764 } 765 766 /* wlan IRQ lines */ 767 for (i = 0; i < ARRAY_SIZE(npu->irqs); i++) { 768 irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1); 769 if (irq < 0) 770 return irq; 771 772 npu->irqs[i] = irq; 773 } 774 775 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 776 if (err) 777 return err; 778 779 err = airoha_npu_run_firmware(dev, base, &res); 780 if (err) 781 return err; 782 783 regmap_write(npu->regmap, REG_CR_NPU_MIB(10), 784 res.start + NPU_EN7581_FIRMWARE_RV32_MAX_SIZE); 785 regmap_write(npu->regmap, REG_CR_NPU_MIB(11), 0x40000); /* SRAM 256K */ 786 regmap_write(npu->regmap, REG_CR_NPU_MIB(12), 0); 787 regmap_write(npu->regmap, REG_CR_NPU_MIB(21), 1); 788 msleep(100); 789 790 /* setting booting address */ 791 for (i = 0; i < NPU_NUM_CORES; i++) 792 regmap_write(npu->regmap, REG_CR_BOOT_BASE(i), res.start); 793 usleep_range(1000, 2000); 794 795 /* enable NPU cores */ 796 regmap_write(npu->regmap, REG_CR_BOOT_CONFIG, 0xff); 797 regmap_write(npu->regmap, REG_CR_BOOT_TRIGGER, 0x1); 798 msleep(100); 799 800 if (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION, 801 &val, sizeof(val), GFP_KERNEL)) 802 dev_info(dev, "NPU fw version: %0d.%d\n", 803 (val >> 16) & 0xffff, val & 0xffff); 804 805 platform_set_drvdata(pdev, npu); 806 807 return 0; 808 } 809 810 static struct platform_driver airoha_npu_driver = { 811 .probe = airoha_npu_probe, 812 .driver = { 813 .name = "airoha-npu", 814 .of_match_table = of_airoha_npu_match, 815 }, 816 }; 817 module_platform_driver(airoha_npu_driver); 818 819 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA); 820 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32); 821 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_DATA); 822 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_RV32); 823 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_DATA); 824 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_RV32); 825 MODULE_LICENSE("GPL v2"); 826 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 827 MODULE_DESCRIPTION("Airoha Network Processor Unit driver"); 828