1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
6 * Copyright (C) 2014 Google, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/phy/tegra/xusb.h>
21 #include <linux/platform_device.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/pm.h>
24 #include <linux/pm_domain.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/string_choices.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/phy.h>
32 #include <linux/usb/role.h>
33 #include <soc/tegra/pmc.h>
34
35 #include "xhci.h"
36
37 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
38 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
39
40 /* FPCI CFG registers */
41 #define XUSB_CFG_1 0x004
42 #define XUSB_IO_SPACE_EN BIT(0)
43 #define XUSB_MEM_SPACE_EN BIT(1)
44 #define XUSB_BUS_MASTER_EN BIT(2)
45 #define XUSB_CFG_4 0x010
46 #define XUSB_BASE_ADDR_SHIFT 15
47 #define XUSB_BASE_ADDR_MASK 0x1ffff
48 #define XUSB_CFG_7 0x01c
49 #define XUSB_BASE2_ADDR_SHIFT 16
50 #define XUSB_BASE2_ADDR_MASK 0xffff
51 #define XUSB_CFG_16 0x040
52 #define XUSB_CFG_24 0x060
53 #define XUSB_CFG_AXI_CFG 0x0f8
54 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
55 #define XUSB_CFG_ARU_CONTEXT 0x43c
56 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478
57 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c
58 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480
59 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484
60 #define XUSB_CFG_CSB_BASE_ADDR 0x800
61
62 /* FPCI mailbox registers */
63 /* XUSB_CFG_ARU_MBOX_CMD */
64 #define MBOX_DEST_FALC BIT(27)
65 #define MBOX_DEST_PME BIT(28)
66 #define MBOX_DEST_SMI BIT(29)
67 #define MBOX_DEST_XHCI BIT(30)
68 #define MBOX_INT_EN BIT(31)
69 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
70 #define CMD_DATA_SHIFT 0
71 #define CMD_DATA_MASK 0xffffff
72 #define CMD_TYPE_SHIFT 24
73 #define CMD_TYPE_MASK 0xff
74 /* XUSB_CFG_ARU_MBOX_OWNER */
75 #define MBOX_OWNER_NONE 0
76 #define MBOX_OWNER_FW 1
77 #define MBOX_OWNER_SW 2
78 #define XUSB_CFG_ARU_SMI_INTR 0x428
79 #define MBOX_SMI_INTR_FW_HANG BIT(1)
80 #define MBOX_SMI_INTR_EN BIT(3)
81
82 /* BAR2 registers */
83 #define XUSB_BAR2_ARU_MBOX_CMD 0x004
84 #define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008
85 #define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c
86 #define XUSB_BAR2_ARU_MBOX_OWNER 0x010
87 #define XUSB_BAR2_ARU_SMI_INTR 0x014
88 #define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c
89 #define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0
90 #define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4
91 #define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8
92 #define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c
93 #define XUSB_BAR2_ARU_FW_SCRATCH 0x1000
94 #define XUSB_BAR2_CSB_BASE_ADDR 0x2000
95
96 /* IPFS registers */
97 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0
98 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4
99 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8
100 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100
101 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140
102 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
103 #define IPFS_EN_FPCI BIT(0)
104 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184
105 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
106 #define IPFS_IP_INT_MASK BIT(16)
107 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198
108 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c
109 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
110 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc
111
112 #define CSB_PAGE_SELECT_MASK 0x7fffff
113 #define CSB_PAGE_SELECT_SHIFT 9
114 #define CSB_PAGE_OFFSET_MASK 0x1ff
115 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
116 CSB_PAGE_SELECT_MASK)
117 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
118
119 /* Falcon CSB registers */
120 #define XUSB_FALC_CPUCTL 0x100
121 #define CPUCTL_STARTCPU BIT(1)
122 #define CPUCTL_STATE_HALTED BIT(4)
123 #define CPUCTL_STATE_STOPPED BIT(5)
124 #define XUSB_FALC_BOOTVEC 0x104
125 #define XUSB_FALC_DMACTL 0x10c
126 #define XUSB_FALC_IMFILLRNG1 0x154
127 #define IMFILLRNG1_TAG_MASK 0xffff
128 #define IMFILLRNG1_TAG_LO_SHIFT 0
129 #define IMFILLRNG1_TAG_HI_SHIFT 16
130 #define XUSB_FALC_IMFILLCTL 0x158
131
132 /* CSB ARU registers */
133 #define XUSB_CSB_ARU_SCRATCH0 0x100100
134
135 /* MP CSB registers */
136 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
137 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
138 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
139 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
140 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
141 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
142 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
143 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
144 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
145 #define L2IMEMOP_ACTION_SHIFT 24
146 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
147 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
148 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18
149 #define L2IMEMOP_RESULT_VLD BIT(31)
150 #define XUSB_CSB_MP_APMAP 0x10181c
151 #define APMAP_BOOTPATH BIT(31)
152
153 #define IMEM_BLOCK_SIZE 256
154
155 #define FW_IOCTL_TYPE_SHIFT 24
156 #define FW_IOCTL_CFGTBL_READ 17
157
158 #define WAKE_IRQ_START_INDEX 2
159
160 struct tegra_xusb_fw_header {
161 __le32 boot_loadaddr_in_imem;
162 __le32 boot_codedfi_offset;
163 __le32 boot_codetag;
164 __le32 boot_codesize;
165 __le32 phys_memaddr;
166 __le16 reqphys_memsize;
167 __le16 alloc_phys_memsize;
168 __le32 rodata_img_offset;
169 __le32 rodata_section_start;
170 __le32 rodata_section_end;
171 __le32 main_fnaddr;
172 __le32 fwimg_cksum;
173 __le32 fwimg_created_time;
174 __le32 imem_resident_start;
175 __le32 imem_resident_end;
176 __le32 idirect_start;
177 __le32 idirect_end;
178 __le32 l2_imem_start;
179 __le32 l2_imem_end;
180 __le32 version_id;
181 u8 init_ddirect;
182 u8 reserved[3];
183 __le32 phys_addr_log_buffer;
184 __le32 total_log_entries;
185 __le32 dequeue_ptr;
186 __le32 dummy_var[2];
187 __le32 fwimg_len;
188 u8 magic[8];
189 __le32 ss_low_power_entry_timeout;
190 u8 num_hsic_port;
191 u8 padding[139]; /* Pad to 256 bytes */
192 };
193
194 struct tegra_xusb_phy_type {
195 const char *name;
196 unsigned int num;
197 };
198
199 struct tegra_xusb_mbox_regs {
200 u16 cmd;
201 u16 data_in;
202 u16 data_out;
203 u16 owner;
204 u16 smi_intr;
205 };
206
207 struct tegra_xusb_context_soc {
208 struct {
209 const unsigned int *offsets;
210 unsigned int num_offsets;
211 } ipfs;
212
213 struct {
214 const unsigned int *offsets;
215 unsigned int num_offsets;
216 } fpci;
217 };
218
219 struct tegra_xusb;
220 struct tegra_xusb_soc_ops {
221 u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
222 void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
223 u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
224 void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
225 };
226
227 struct tegra_xusb_soc {
228 const char *firmware;
229 const char * const *supply_names;
230 unsigned int num_supplies;
231 const struct tegra_xusb_phy_type *phy_types;
232 unsigned int num_types;
233 unsigned int max_num_wakes;
234 const struct tegra_xusb_context_soc *context;
235
236 struct {
237 struct {
238 unsigned int offset;
239 unsigned int count;
240 } usb2, ulpi, hsic, usb3;
241 } ports;
242
243 struct tegra_xusb_mbox_regs mbox;
244 const struct tegra_xusb_soc_ops *ops;
245
246 bool scale_ss_clock;
247 bool has_ipfs;
248 bool lpm_support;
249 bool otg_reset_sspi;
250
251 bool has_bar2;
252 };
253
254 struct tegra_xusb_context {
255 u32 *ipfs;
256 u32 *fpci;
257 };
258
259 struct tegra_xusb {
260 struct device *dev;
261 void __iomem *regs;
262 struct usb_hcd *hcd;
263
264 struct mutex lock;
265
266 int xhci_irq;
267 int mbox_irq;
268 int padctl_irq;
269 int *wake_irqs;
270
271 void __iomem *ipfs_base;
272 void __iomem *fpci_base;
273 void __iomem *bar2_base;
274 struct resource *bar2;
275
276 const struct tegra_xusb_soc *soc;
277
278 struct regulator_bulk_data *supplies;
279
280 struct tegra_xusb_padctl *padctl;
281
282 struct clk *host_clk;
283 struct clk *falcon_clk;
284 struct clk *ss_clk;
285 struct clk *ss_src_clk;
286 struct clk *hs_src_clk;
287 struct clk *fs_src_clk;
288 struct clk *pll_u_480m;
289 struct clk *clk_m;
290 struct clk *pll_e;
291
292 struct reset_control *host_rst;
293 struct reset_control *ss_rst;
294
295 struct device *genpd_dev_host;
296 struct device *genpd_dev_ss;
297 bool use_genpd;
298
299 struct phy **phys;
300 unsigned int num_phys;
301
302 struct usb_phy **usbphy;
303 unsigned int num_usb_phys;
304 int otg_usb2_port;
305 int otg_usb3_port;
306 bool host_mode;
307 struct notifier_block id_nb;
308 struct work_struct id_work;
309
310 /* Firmware loading related */
311 struct {
312 size_t size;
313 void *virt;
314 dma_addr_t phys;
315 } fw;
316
317 bool suspended;
318 struct tegra_xusb_context context;
319 u8 lp0_utmi_pad_mask;
320 int num_wakes;
321 };
322
323 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
324
fpci_readl(struct tegra_xusb * tegra,unsigned int offset)325 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
326 {
327 return readl(tegra->fpci_base + offset);
328 }
329
fpci_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)330 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
331 unsigned int offset)
332 {
333 writel(value, tegra->fpci_base + offset);
334 }
335
ipfs_readl(struct tegra_xusb * tegra,unsigned int offset)336 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
337 {
338 return readl(tegra->ipfs_base + offset);
339 }
340
ipfs_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)341 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
342 unsigned int offset)
343 {
344 writel(value, tegra->ipfs_base + offset);
345 }
346
bar2_readl(struct tegra_xusb * tegra,unsigned int offset)347 static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset)
348 {
349 return readl(tegra->bar2_base + offset);
350 }
351
bar2_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)352 static inline void bar2_writel(struct tegra_xusb *tegra, u32 value,
353 unsigned int offset)
354 {
355 writel(value, tegra->bar2_base + offset);
356 }
357
csb_readl(struct tegra_xusb * tegra,unsigned int offset)358 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
359 {
360 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
361
362 return ops->csb_reg_readl(tegra, offset);
363 }
364
csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)365 static void csb_writel(struct tegra_xusb *tegra, u32 value,
366 unsigned int offset)
367 {
368 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
369
370 ops->csb_reg_writel(tegra, value, offset);
371 }
372
fpci_csb_readl(struct tegra_xusb * tegra,unsigned int offset)373 static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
374 {
375 u32 page = CSB_PAGE_SELECT(offset);
376 u32 ofs = CSB_PAGE_OFFSET(offset);
377
378 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
379
380 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
381 }
382
fpci_csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)383 static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value,
384 unsigned int offset)
385 {
386 u32 page = CSB_PAGE_SELECT(offset);
387 u32 ofs = CSB_PAGE_OFFSET(offset);
388
389 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
390 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
391 }
392
bar2_csb_readl(struct tegra_xusb * tegra,unsigned int offset)393 static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
394 {
395 u32 page = CSB_PAGE_SELECT(offset);
396 u32 ofs = CSB_PAGE_OFFSET(offset);
397
398 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
399
400 return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs);
401 }
402
bar2_csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)403 static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value,
404 unsigned int offset)
405 {
406 u32 page = CSB_PAGE_SELECT(offset);
407 u32 ofs = CSB_PAGE_OFFSET(offset);
408
409 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
410 bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs);
411 }
412
tegra_xusb_set_ss_clk(struct tegra_xusb * tegra,unsigned long rate)413 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
414 unsigned long rate)
415 {
416 unsigned long new_parent_rate, old_parent_rate;
417 struct clk *clk = tegra->ss_src_clk;
418 unsigned int div;
419 int err;
420
421 if (clk_get_rate(clk) == rate)
422 return 0;
423
424 switch (rate) {
425 case TEGRA_XHCI_SS_HIGH_SPEED:
426 /*
427 * Reparent to PLLU_480M. Set divider first to avoid
428 * overclocking.
429 */
430 old_parent_rate = clk_get_rate(clk_get_parent(clk));
431 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
432 div = new_parent_rate / rate;
433
434 err = clk_set_rate(clk, old_parent_rate / div);
435 if (err)
436 return err;
437
438 err = clk_set_parent(clk, tegra->pll_u_480m);
439 if (err)
440 return err;
441
442 /*
443 * The rate should already be correct, but set it again just
444 * to be sure.
445 */
446 err = clk_set_rate(clk, rate);
447 if (err)
448 return err;
449
450 break;
451
452 case TEGRA_XHCI_SS_LOW_SPEED:
453 /* Reparent to CLK_M */
454 err = clk_set_parent(clk, tegra->clk_m);
455 if (err)
456 return err;
457
458 err = clk_set_rate(clk, rate);
459 if (err)
460 return err;
461
462 break;
463
464 default:
465 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
466 return -EINVAL;
467 }
468
469 if (clk_get_rate(clk) != rate) {
470 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
471 return -EINVAL;
472 }
473
474 return 0;
475 }
476
extract_field(u32 value,unsigned int start,unsigned int count)477 static unsigned long extract_field(u32 value, unsigned int start,
478 unsigned int count)
479 {
480 return (value >> start) & ((1 << count) - 1);
481 }
482
483 /* Command requests from the firmware */
484 enum tegra_xusb_mbox_cmd {
485 MBOX_CMD_MSG_ENABLED = 1,
486 MBOX_CMD_INC_FALC_CLOCK,
487 MBOX_CMD_DEC_FALC_CLOCK,
488 MBOX_CMD_INC_SSPI_CLOCK,
489 MBOX_CMD_DEC_SSPI_CLOCK,
490 MBOX_CMD_SET_BW, /* no ACK/NAK required */
491 MBOX_CMD_SET_SS_PWR_GATING,
492 MBOX_CMD_SET_SS_PWR_UNGATING,
493 MBOX_CMD_SAVE_DFE_CTLE_CTX,
494 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
495 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
496 MBOX_CMD_START_HSIC_IDLE,
497 MBOX_CMD_STOP_HSIC_IDLE,
498 MBOX_CMD_DBC_WAKE_STACK, /* unused */
499 MBOX_CMD_HSIC_PRETEND_CONNECT,
500 MBOX_CMD_RESET_SSPI,
501 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
502 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
503
504 MBOX_CMD_MAX,
505
506 /* Response message to above commands */
507 MBOX_CMD_ACK = 128,
508 MBOX_CMD_NAK
509 };
510
511 struct tegra_xusb_mbox_msg {
512 u32 cmd;
513 u32 data;
514 };
515
tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg * msg)516 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
517 {
518 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
519 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
520 }
tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg * msg,u32 value)521 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
522 u32 value)
523 {
524 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
525 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
526 }
527
tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)528 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
529 {
530 switch (cmd) {
531 case MBOX_CMD_SET_BW:
532 case MBOX_CMD_ACK:
533 case MBOX_CMD_NAK:
534 return false;
535
536 default:
537 return true;
538 }
539 }
540
tegra_xusb_mbox_send(struct tegra_xusb * tegra,const struct tegra_xusb_mbox_msg * msg)541 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
542 const struct tegra_xusb_mbox_msg *msg)
543 {
544 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
545 bool wait_for_idle = false;
546 u32 value;
547
548 /*
549 * Acquire the mailbox. The firmware still owns the mailbox for
550 * ACK/NAK messages.
551 */
552 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
553 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
554 if (value != MBOX_OWNER_NONE) {
555 dev_err(tegra->dev, "mailbox is busy\n");
556 return -EBUSY;
557 }
558
559 ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
560
561 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
562 if (value != MBOX_OWNER_SW) {
563 dev_err(tegra->dev, "failed to acquire mailbox\n");
564 return -EBUSY;
565 }
566
567 wait_for_idle = true;
568 }
569
570 value = tegra_xusb_mbox_pack(msg);
571 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in);
572
573 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
574 value |= MBOX_INT_EN | MBOX_DEST_FALC;
575 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
576
577 if (wait_for_idle) {
578 unsigned long timeout = jiffies + msecs_to_jiffies(250);
579
580 while (time_before(jiffies, timeout)) {
581 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
582 if (value == MBOX_OWNER_NONE)
583 break;
584
585 usleep_range(10, 20);
586 }
587
588 if (time_after(jiffies, timeout))
589 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
590
591 if (value != MBOX_OWNER_NONE)
592 return -ETIMEDOUT;
593 }
594
595 return 0;
596 }
597
tegra_xusb_mbox_irq(int irq,void * data)598 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
599 {
600 struct tegra_xusb *tegra = data;
601 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
602 u32 value;
603
604 /* clear mailbox interrupts */
605 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr);
606 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr);
607
608 if (value & MBOX_SMI_INTR_FW_HANG)
609 dev_err(tegra->dev, "controller firmware hang\n");
610
611 return IRQ_WAKE_THREAD;
612 }
613
tegra_xusb_mbox_handle(struct tegra_xusb * tegra,const struct tegra_xusb_mbox_msg * msg)614 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
615 const struct tegra_xusb_mbox_msg *msg)
616 {
617 struct tegra_xusb_padctl *padctl = tegra->padctl;
618 const struct tegra_xusb_soc *soc = tegra->soc;
619 struct device *dev = tegra->dev;
620 struct tegra_xusb_mbox_msg rsp;
621 unsigned long mask;
622 unsigned int port;
623 bool idle, enable;
624 int err = 0;
625
626 memset(&rsp, 0, sizeof(rsp));
627
628 switch (msg->cmd) {
629 case MBOX_CMD_INC_FALC_CLOCK:
630 case MBOX_CMD_DEC_FALC_CLOCK:
631 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
632 if (rsp.data != msg->data)
633 rsp.cmd = MBOX_CMD_NAK;
634 else
635 rsp.cmd = MBOX_CMD_ACK;
636
637 break;
638
639 case MBOX_CMD_INC_SSPI_CLOCK:
640 case MBOX_CMD_DEC_SSPI_CLOCK:
641 if (tegra->soc->scale_ss_clock) {
642 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
643 if (err < 0)
644 rsp.cmd = MBOX_CMD_NAK;
645 else
646 rsp.cmd = MBOX_CMD_ACK;
647
648 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
649 } else {
650 rsp.cmd = MBOX_CMD_ACK;
651 rsp.data = msg->data;
652 }
653
654 break;
655
656 case MBOX_CMD_SET_BW:
657 /*
658 * TODO: Request bandwidth once EMC scaling is supported.
659 * Ignore for now since ACK/NAK is not required for SET_BW
660 * messages.
661 */
662 break;
663
664 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
665 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
666 if (err < 0) {
667 dev_err(dev, "failed to save context for USB3#%u: %d\n",
668 msg->data, err);
669 rsp.cmd = MBOX_CMD_NAK;
670 } else {
671 rsp.cmd = MBOX_CMD_ACK;
672 }
673
674 rsp.data = msg->data;
675 break;
676
677 case MBOX_CMD_START_HSIC_IDLE:
678 case MBOX_CMD_STOP_HSIC_IDLE:
679 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
680 idle = false;
681 else
682 idle = true;
683
684 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
685 soc->ports.hsic.count);
686
687 for_each_set_bit(port, &mask, 32) {
688 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
689 idle);
690 if (err < 0)
691 break;
692 }
693
694 if (err < 0) {
695 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
696 idle ? "idle" : "busy", err);
697 rsp.cmd = MBOX_CMD_NAK;
698 } else {
699 rsp.cmd = MBOX_CMD_ACK;
700 }
701
702 rsp.data = msg->data;
703 break;
704
705 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
706 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
707 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
708 enable = false;
709 else
710 enable = true;
711
712 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
713 soc->ports.usb3.count);
714
715 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
716 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
717 port,
718 enable);
719 if (err < 0)
720 break;
721
722 /*
723 * wait 500us for LFPS detector to be disabled before
724 * sending ACK
725 */
726 if (!enable)
727 usleep_range(500, 1000);
728 }
729
730 if (err < 0) {
731 dev_err(dev,
732 "failed to %s LFPS detection on USB3#%u: %d\n",
733 str_enable_disable(enable), port, err);
734 rsp.cmd = MBOX_CMD_NAK;
735 } else {
736 rsp.cmd = MBOX_CMD_ACK;
737 }
738
739 rsp.data = msg->data;
740 break;
741
742 default:
743 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
744 break;
745 }
746
747 if (rsp.cmd) {
748 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
749
750 err = tegra_xusb_mbox_send(tegra, &rsp);
751 if (err < 0)
752 dev_err(dev, "failed to send %s: %d\n", cmd, err);
753 }
754 }
755
tegra_xusb_mbox_thread(int irq,void * data)756 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
757 {
758 struct tegra_xusb *tegra = data;
759 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
760 struct tegra_xusb_mbox_msg msg;
761 u32 value;
762
763 mutex_lock(&tegra->lock);
764
765 if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
766 goto out;
767
768 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out);
769 tegra_xusb_mbox_unpack(&msg, value);
770
771 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
772 value &= ~MBOX_DEST_SMI;
773 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
774
775 /* clear mailbox owner if no ACK/NAK is required */
776 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
777 ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
778
779 tegra_xusb_mbox_handle(tegra, &msg);
780
781 out:
782 mutex_unlock(&tegra->lock);
783 return IRQ_HANDLED;
784 }
785
tegra_xusb_config(struct tegra_xusb * tegra)786 static void tegra_xusb_config(struct tegra_xusb *tegra)
787 {
788 u32 regs = tegra->hcd->rsrc_start;
789 u32 value;
790
791 if (tegra->soc->has_ipfs) {
792 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
793 value |= IPFS_EN_FPCI;
794 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
795
796 usleep_range(10, 20);
797 }
798
799 /* Program BAR0 space */
800 value = fpci_readl(tegra, XUSB_CFG_4);
801 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
802 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
803 fpci_writel(tegra, value, XUSB_CFG_4);
804
805 /* Program BAR2 space */
806 if (tegra->bar2) {
807 value = fpci_readl(tegra, XUSB_CFG_7);
808 value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
809 value |= tegra->bar2->start &
810 (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
811 fpci_writel(tegra, value, XUSB_CFG_7);
812 }
813
814 usleep_range(100, 200);
815
816 /* Enable bus master */
817 value = fpci_readl(tegra, XUSB_CFG_1);
818 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
819 fpci_writel(tegra, value, XUSB_CFG_1);
820
821 if (tegra->soc->has_ipfs) {
822 /* Enable interrupt assertion */
823 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
824 value |= IPFS_IP_INT_MASK;
825 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
826
827 /* Set hysteresis */
828 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
829 }
830 }
831
tegra_xusb_clk_enable(struct tegra_xusb * tegra)832 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
833 {
834 int err;
835
836 err = clk_prepare_enable(tegra->pll_e);
837 if (err < 0)
838 return err;
839
840 err = clk_prepare_enable(tegra->host_clk);
841 if (err < 0)
842 goto disable_plle;
843
844 err = clk_prepare_enable(tegra->ss_clk);
845 if (err < 0)
846 goto disable_host;
847
848 err = clk_prepare_enable(tegra->falcon_clk);
849 if (err < 0)
850 goto disable_ss;
851
852 err = clk_prepare_enable(tegra->fs_src_clk);
853 if (err < 0)
854 goto disable_falc;
855
856 err = clk_prepare_enable(tegra->hs_src_clk);
857 if (err < 0)
858 goto disable_fs_src;
859
860 if (tegra->soc->scale_ss_clock) {
861 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
862 if (err < 0)
863 goto disable_hs_src;
864 }
865
866 return 0;
867
868 disable_hs_src:
869 clk_disable_unprepare(tegra->hs_src_clk);
870 disable_fs_src:
871 clk_disable_unprepare(tegra->fs_src_clk);
872 disable_falc:
873 clk_disable_unprepare(tegra->falcon_clk);
874 disable_ss:
875 clk_disable_unprepare(tegra->ss_clk);
876 disable_host:
877 clk_disable_unprepare(tegra->host_clk);
878 disable_plle:
879 clk_disable_unprepare(tegra->pll_e);
880 return err;
881 }
882
tegra_xusb_clk_disable(struct tegra_xusb * tegra)883 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
884 {
885 clk_disable_unprepare(tegra->pll_e);
886 clk_disable_unprepare(tegra->host_clk);
887 clk_disable_unprepare(tegra->ss_clk);
888 clk_disable_unprepare(tegra->falcon_clk);
889 clk_disable_unprepare(tegra->fs_src_clk);
890 clk_disable_unprepare(tegra->hs_src_clk);
891 }
892
tegra_xusb_phy_enable(struct tegra_xusb * tegra)893 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
894 {
895 unsigned int i;
896 int err;
897
898 for (i = 0; i < tegra->num_phys; i++) {
899 err = phy_init(tegra->phys[i]);
900 if (err)
901 goto disable_phy;
902
903 err = phy_power_on(tegra->phys[i]);
904 if (err) {
905 phy_exit(tegra->phys[i]);
906 goto disable_phy;
907 }
908 }
909
910 return 0;
911
912 disable_phy:
913 while (i--) {
914 phy_power_off(tegra->phys[i]);
915 phy_exit(tegra->phys[i]);
916 }
917
918 return err;
919 }
920
tegra_xusb_phy_disable(struct tegra_xusb * tegra)921 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
922 {
923 unsigned int i;
924
925 for (i = 0; i < tegra->num_phys; i++) {
926 phy_power_off(tegra->phys[i]);
927 phy_exit(tegra->phys[i]);
928 }
929 }
930
931 #ifdef CONFIG_PM_SLEEP
tegra_xusb_init_context(struct tegra_xusb * tegra)932 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
933 {
934 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
935
936 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
937 sizeof(u32), GFP_KERNEL);
938 if (!tegra->context.ipfs)
939 return -ENOMEM;
940
941 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
942 sizeof(u32), GFP_KERNEL);
943 if (!tegra->context.fpci)
944 return -ENOMEM;
945
946 return 0;
947 }
948 #else
tegra_xusb_init_context(struct tegra_xusb * tegra)949 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
950 {
951 return 0;
952 }
953 #endif
954
tegra_xusb_request_firmware(struct tegra_xusb * tegra)955 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
956 {
957 struct tegra_xusb_fw_header *header;
958 const struct firmware *fw;
959 int err;
960
961 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
962 if (err < 0) {
963 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
964 return err;
965 }
966
967 /* Load Falcon controller with its firmware. */
968 header = (struct tegra_xusb_fw_header *)fw->data;
969 tegra->fw.size = le32_to_cpu(header->fwimg_len);
970
971 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
972 &tegra->fw.phys, GFP_KERNEL);
973 if (!tegra->fw.virt) {
974 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
975 release_firmware(fw);
976 return -ENOMEM;
977 }
978
979 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
980 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
981 release_firmware(fw);
982
983 return 0;
984 }
985
tegra_xusb_wait_for_falcon(struct tegra_xusb * tegra)986 static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra)
987 {
988 struct xhci_cap_regs __iomem *cap_regs;
989 struct xhci_op_regs __iomem *op_regs;
990 int ret;
991 u32 value;
992
993 cap_regs = tegra->regs;
994 op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase));
995
996 ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000);
997
998 if (ret)
999 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n",
1000 csb_readl(tegra, XUSB_FALC_CPUCTL));
1001
1002 return ret;
1003 }
1004
tegra_xusb_load_firmware_rom(struct tegra_xusb * tegra)1005 static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra)
1006 {
1007 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
1008 struct tegra_xusb_fw_header *header;
1009 struct device *dev = tegra->dev;
1010 time64_t timestamp;
1011 u64 address;
1012 u32 value;
1013 int err;
1014
1015 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
1016
1017 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1018 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
1019 csb_readl(tegra, XUSB_FALC_CPUCTL));
1020 return 0;
1021 }
1022
1023 /* Program the size of DFI into ILOAD_ATTR. */
1024 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
1025
1026 /*
1027 * Boot code of the firmware reads the ILOAD_BASE registers
1028 * to get to the start of the DFI in system memory.
1029 */
1030 address = tegra->fw.phys + sizeof(*header);
1031 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
1032 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
1033
1034 /* Set BOOTPATH to 1 in APMAP. */
1035 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
1036
1037 /* Invalidate L2IMEM. */
1038 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
1039
1040 /*
1041 * Initiate fetch of bootcode from system memory into L2IMEM.
1042 * Program bootcode location and size in system memory.
1043 */
1044 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
1045 IMEM_BLOCK_SIZE);
1046 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
1047 IMEM_BLOCK_SIZE);
1048 code_blocks = code_tag_blocks + code_size_blocks;
1049
1050 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
1051 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
1052 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
1053 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
1054 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
1055
1056 /* Trigger L2IMEM load operation. */
1057 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
1058 XUSB_CSB_MP_L2IMEMOP_TRIG);
1059
1060 /* Setup Falcon auto-fill. */
1061 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
1062
1063 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
1064 IMFILLRNG1_TAG_LO_SHIFT) |
1065 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
1066 IMFILLRNG1_TAG_HI_SHIFT);
1067 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
1068
1069 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
1070
1071 /* wait for RESULT_VLD to get set */
1072 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
1073 err = readx_poll_timeout(tegra_csb_readl,
1074 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
1075 value & L2IMEMOP_RESULT_VLD, 100, 10000);
1076 if (err < 0) {
1077 dev_err(dev, "DMA controller not ready %#010x\n", value);
1078 return err;
1079 }
1080 #undef tegra_csb_readl
1081
1082 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
1083 XUSB_FALC_BOOTVEC);
1084
1085 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
1086 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
1087
1088 if (tegra_xusb_wait_for_falcon(tegra))
1089 return -EIO;
1090
1091 timestamp = le32_to_cpu(header->fwimg_created_time);
1092
1093 dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp);
1094
1095 return 0;
1096 }
1097
tegra_xusb_read_firmware_header(struct tegra_xusb * tegra,u32 offset)1098 static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset)
1099 {
1100 /*
1101 * We only accept reading the firmware config table
1102 * The offset should not exceed the fw header structure
1103 */
1104 if (offset >= sizeof(struct tegra_xusb_fw_header))
1105 return 0;
1106
1107 bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset,
1108 XUSB_BAR2_ARU_FW_SCRATCH);
1109 return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0);
1110 }
1111
tegra_xusb_init_ifr_firmware(struct tegra_xusb * tegra)1112 static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra)
1113 {
1114 time64_t timestamp;
1115
1116 if (tegra_xusb_wait_for_falcon(tegra))
1117 return -EIO;
1118
1119 #define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32)))
1120 timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header,
1121 fwimg_created_time) << 2);
1122
1123 dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp);
1124
1125 return 0;
1126 }
1127
tegra_xusb_load_firmware(struct tegra_xusb * tegra)1128 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
1129 {
1130 if (!tegra->soc->firmware)
1131 return tegra_xusb_init_ifr_firmware(tegra);
1132 else
1133 return tegra_xusb_load_firmware_rom(tegra);
1134 }
1135
tegra_xusb_powerdomain_remove(struct device * dev,struct tegra_xusb * tegra)1136 static void tegra_xusb_powerdomain_remove(struct device *dev,
1137 struct tegra_xusb *tegra)
1138 {
1139 if (!tegra->use_genpd)
1140 return;
1141
1142 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1143 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1144 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1145 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1146 }
1147
tegra_xusb_powerdomain_init(struct device * dev,struct tegra_xusb * tegra)1148 static int tegra_xusb_powerdomain_init(struct device *dev,
1149 struct tegra_xusb *tegra)
1150 {
1151 int err;
1152
1153 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1154 if (IS_ERR(tegra->genpd_dev_host)) {
1155 err = PTR_ERR(tegra->genpd_dev_host);
1156 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1157 return err;
1158 }
1159
1160 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1161 if (IS_ERR(tegra->genpd_dev_ss)) {
1162 err = PTR_ERR(tegra->genpd_dev_ss);
1163 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1164 return err;
1165 }
1166
1167 tegra->use_genpd = true;
1168
1169 return 0;
1170 }
1171
tegra_xusb_unpowergate_partitions(struct tegra_xusb * tegra)1172 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1173 {
1174 struct device *dev = tegra->dev;
1175 int rc;
1176
1177 if (tegra->use_genpd) {
1178 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss);
1179 if (rc < 0) {
1180 dev_err(dev, "failed to enable XUSB SS partition\n");
1181 return rc;
1182 }
1183
1184 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host);
1185 if (rc < 0) {
1186 dev_err(dev, "failed to enable XUSB Host partition\n");
1187 pm_runtime_put_sync(tegra->genpd_dev_ss);
1188 return rc;
1189 }
1190 } else {
1191 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1192 tegra->ss_clk,
1193 tegra->ss_rst);
1194 if (rc < 0) {
1195 dev_err(dev, "failed to enable XUSB SS partition\n");
1196 return rc;
1197 }
1198
1199 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1200 tegra->host_clk,
1201 tegra->host_rst);
1202 if (rc < 0) {
1203 dev_err(dev, "failed to enable XUSB Host partition\n");
1204 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1205 return rc;
1206 }
1207 }
1208
1209 return 0;
1210 }
1211
tegra_xusb_powergate_partitions(struct tegra_xusb * tegra)1212 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1213 {
1214 struct device *dev = tegra->dev;
1215 int rc;
1216
1217 if (tegra->use_genpd) {
1218 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1219 if (rc < 0) {
1220 dev_err(dev, "failed to disable XUSB Host partition\n");
1221 return rc;
1222 }
1223
1224 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1225 if (rc < 0) {
1226 dev_err(dev, "failed to disable XUSB SS partition\n");
1227 pm_runtime_get_sync(tegra->genpd_dev_host);
1228 return rc;
1229 }
1230 } else {
1231 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1232 if (rc < 0) {
1233 dev_err(dev, "failed to disable XUSB Host partition\n");
1234 return rc;
1235 }
1236
1237 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1238 if (rc < 0) {
1239 dev_err(dev, "failed to disable XUSB SS partition\n");
1240 tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1241 tegra->host_clk,
1242 tegra->host_rst);
1243 return rc;
1244 }
1245 }
1246
1247 return 0;
1248 }
1249
__tegra_xusb_enable_firmware_messages(struct tegra_xusb * tegra)1250 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1251 {
1252 struct tegra_xusb_mbox_msg msg;
1253 int err;
1254
1255 /* Enable firmware messages from controller. */
1256 msg.cmd = MBOX_CMD_MSG_ENABLED;
1257 msg.data = 0;
1258
1259 err = tegra_xusb_mbox_send(tegra, &msg);
1260 if (err < 0)
1261 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1262
1263 return err;
1264 }
1265
tegra_xusb_padctl_irq(int irq,void * data)1266 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1267 {
1268 struct tegra_xusb *tegra = data;
1269
1270 mutex_lock(&tegra->lock);
1271
1272 if (tegra->suspended) {
1273 mutex_unlock(&tegra->lock);
1274 return IRQ_HANDLED;
1275 }
1276
1277 mutex_unlock(&tegra->lock);
1278
1279 pm_runtime_resume(tegra->dev);
1280
1281 return IRQ_HANDLED;
1282 }
1283
tegra_xusb_enable_firmware_messages(struct tegra_xusb * tegra)1284 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1285 {
1286 int err;
1287
1288 mutex_lock(&tegra->lock);
1289 err = __tegra_xusb_enable_firmware_messages(tegra);
1290 mutex_unlock(&tegra->lock);
1291
1292 return err;
1293 }
1294
tegra_xhci_set_port_power(struct tegra_xusb * tegra,bool main,bool set)1295 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1296 bool set)
1297 {
1298 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1299 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd;
1300 unsigned int wait = (!main && !set) ? 1000 : 10;
1301 u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1302 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1303 u32 status;
1304 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1305 u32 status_val = set ? stat_power : 0;
1306
1307 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1308 set ? "set" : "clear", main ? "HS" : "SS");
1309
1310 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1311 NULL, 0);
1312
1313 do {
1314 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1315 (char *) &status, sizeof(status));
1316 if (status_val == (status & stat_power))
1317 break;
1318
1319 if (!main && !set)
1320 usleep_range(600, 700);
1321 else
1322 usleep_range(10, 20);
1323 } while (--wait > 0);
1324
1325 if (status_val != (status & stat_power))
1326 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1327 set ? "set" : "clear",
1328 main ? "HS" : "SS", status);
1329 }
1330
tegra_xusb_get_phy(struct tegra_xusb * tegra,char * name,int port)1331 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1332 int port)
1333 {
1334 unsigned int i, phy_count = 0;
1335
1336 for (i = 0; i < tegra->soc->num_types; i++) {
1337 if (!strncmp(tegra->soc->phy_types[i].name, name,
1338 strlen(name)))
1339 return tegra->phys[phy_count+port];
1340
1341 phy_count += tegra->soc->phy_types[i].num;
1342 }
1343
1344 return NULL;
1345 }
1346
tegra_xhci_id_work(struct work_struct * work)1347 static void tegra_xhci_id_work(struct work_struct *work)
1348 {
1349 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1350 id_work);
1351 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1352 struct tegra_xusb_mbox_msg msg;
1353 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1354 tegra->otg_usb2_port);
1355 u32 status;
1356 int ret;
1357
1358 dev_dbg(tegra->dev, "host mode %s\n", str_on_off(tegra->host_mode));
1359
1360 mutex_lock(&tegra->lock);
1361
1362 if (tegra->host_mode)
1363 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1364 else
1365 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1366
1367 mutex_unlock(&tegra->lock);
1368
1369 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(tegra->padctl,
1370 tegra->otg_usb2_port);
1371
1372 pm_runtime_get_sync(tegra->dev);
1373 if (tegra->host_mode) {
1374 /* switch to host mode */
1375 if (tegra->otg_usb3_port >= 0) {
1376 if (tegra->soc->otg_reset_sspi) {
1377 /* set PP=0 */
1378 tegra_xhci_hc_driver.hub_control(
1379 xhci->shared_hcd, GetPortStatus,
1380 0, tegra->otg_usb3_port+1,
1381 (char *) &status, sizeof(status));
1382 if (status & USB_SS_PORT_STAT_POWER)
1383 tegra_xhci_set_port_power(tegra, false,
1384 false);
1385
1386 /* reset OTG port SSPI */
1387 msg.cmd = MBOX_CMD_RESET_SSPI;
1388 msg.data = tegra->otg_usb3_port+1;
1389
1390 ret = tegra_xusb_mbox_send(tegra, &msg);
1391 if (ret < 0) {
1392 dev_info(tegra->dev,
1393 "failed to RESET_SSPI %d\n",
1394 ret);
1395 }
1396 }
1397
1398 tegra_xhci_set_port_power(tegra, false, true);
1399 }
1400
1401 tegra_xhci_set_port_power(tegra, true, true);
1402
1403 } else {
1404 if (tegra->otg_usb3_port >= 0)
1405 tegra_xhci_set_port_power(tegra, false, false);
1406
1407 tegra_xhci_set_port_power(tegra, true, false);
1408 }
1409 pm_runtime_put_autosuspend(tegra->dev);
1410 }
1411
1412 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
is_usb2_otg_phy(struct tegra_xusb * tegra,unsigned int index)1413 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1414 {
1415 return (tegra->usbphy[index] != NULL);
1416 }
1417
is_usb3_otg_phy(struct tegra_xusb * tegra,unsigned int index)1418 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1419 {
1420 struct tegra_xusb_padctl *padctl = tegra->padctl;
1421 unsigned int i;
1422 int port;
1423
1424 for (i = 0; i < tegra->num_usb_phys; i++) {
1425 if (is_usb2_otg_phy(tegra, i)) {
1426 port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1427 if ((port >= 0) && (index == (unsigned int)port))
1428 return true;
1429 }
1430 }
1431
1432 return false;
1433 }
1434
is_host_mode_phy(struct tegra_xusb * tegra,unsigned int phy_type,unsigned int index)1435 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1436 {
1437 if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1438 return true;
1439
1440 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1441 if (is_usb2_otg_phy(tegra, index))
1442 return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1443 else
1444 return true;
1445 }
1446
1447 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1448 if (is_usb3_otg_phy(tegra, index))
1449 return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1450 else
1451 return true;
1452 }
1453
1454 return false;
1455 }
1456 #endif
1457
tegra_xusb_get_usb2_port(struct tegra_xusb * tegra,struct usb_phy * usbphy)1458 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1459 struct usb_phy *usbphy)
1460 {
1461 unsigned int i;
1462
1463 for (i = 0; i < tegra->num_usb_phys; i++) {
1464 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1465 return i;
1466 }
1467
1468 return -1;
1469 }
1470
tegra_xhci_id_notify(struct notifier_block * nb,unsigned long action,void * data)1471 static int tegra_xhci_id_notify(struct notifier_block *nb,
1472 unsigned long action, void *data)
1473 {
1474 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1475 id_nb);
1476 struct usb_phy *usbphy = (struct usb_phy *)data;
1477
1478 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1479
1480 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1481 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1482 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1483 tegra->host_mode);
1484 return NOTIFY_OK;
1485 }
1486
1487 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1488
1489 tegra->host_mode = usbphy->last_event == USB_EVENT_ID;
1490
1491 schedule_work(&tegra->id_work);
1492
1493 return NOTIFY_OK;
1494 }
1495
tegra_xusb_init_usb_phy(struct tegra_xusb * tegra)1496 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1497 {
1498 unsigned int i;
1499
1500 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1501 sizeof(*tegra->usbphy), GFP_KERNEL);
1502 if (!tegra->usbphy)
1503 return -ENOMEM;
1504
1505 INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1506 tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1507 tegra->otg_usb2_port = -EINVAL;
1508 tegra->otg_usb3_port = -EINVAL;
1509
1510 for (i = 0; i < tegra->num_usb_phys; i++) {
1511 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1512
1513 if (!phy)
1514 continue;
1515
1516 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1517 phy->dev.of_node,
1518 &tegra->id_nb);
1519 if (!IS_ERR(tegra->usbphy[i])) {
1520 dev_dbg(tegra->dev, "usbphy-%d registered", i);
1521 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1522 } else {
1523 /*
1524 * usb-phy is optional, continue if its not available.
1525 */
1526 tegra->usbphy[i] = NULL;
1527 }
1528 }
1529
1530 return 0;
1531 }
1532
tegra_xusb_deinit_usb_phy(struct tegra_xusb * tegra)1533 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1534 {
1535 unsigned int i;
1536
1537 cancel_work_sync(&tegra->id_work);
1538
1539 for (i = 0; i < tegra->num_usb_phys; i++)
1540 if (tegra->usbphy[i])
1541 otg_set_host(tegra->usbphy[i]->otg, NULL);
1542 }
1543
tegra_xusb_setup_wakeup(struct platform_device * pdev,struct tegra_xusb * tegra)1544 static int tegra_xusb_setup_wakeup(struct platform_device *pdev, struct tegra_xusb *tegra)
1545 {
1546 unsigned int i;
1547
1548 if (tegra->soc->max_num_wakes == 0)
1549 return 0;
1550
1551 tegra->wake_irqs = devm_kcalloc(tegra->dev,
1552 tegra->soc->max_num_wakes,
1553 sizeof(*tegra->wake_irqs), GFP_KERNEL);
1554 if (!tegra->wake_irqs)
1555 return -ENOMEM;
1556
1557 /*
1558 * USB wake events are independent of each other, so it is not necessary for a platform
1559 * to utilize all wake-up events supported for a given device. The USB host can operate
1560 * even if wake-up events are not defined or fail to be configured. Therefore, we only
1561 * return critical errors, such as -ENOMEM.
1562 */
1563 for (i = 0; i < tegra->soc->max_num_wakes; i++) {
1564 struct irq_data *data;
1565
1566 tegra->wake_irqs[i] = platform_get_irq(pdev, i + WAKE_IRQ_START_INDEX);
1567 if (tegra->wake_irqs[i] < 0)
1568 break;
1569
1570 data = irq_get_irq_data(tegra->wake_irqs[i]);
1571 if (!data) {
1572 dev_warn(tegra->dev, "get wake event %d irq data fail\n", i);
1573 irq_dispose_mapping(tegra->wake_irqs[i]);
1574 break;
1575 }
1576
1577 irq_set_irq_type(tegra->wake_irqs[i], irqd_get_trigger_type(data));
1578 }
1579
1580 tegra->num_wakes = i;
1581 dev_dbg(tegra->dev, "setup %d wake events\n", tegra->num_wakes);
1582
1583 return 0;
1584 }
1585
tegra_xusb_dispose_wake(struct tegra_xusb * tegra)1586 static void tegra_xusb_dispose_wake(struct tegra_xusb *tegra)
1587 {
1588 unsigned int i;
1589
1590 for (i = 0; i < tegra->num_wakes; i++)
1591 irq_dispose_mapping(tegra->wake_irqs[i]);
1592
1593 tegra->num_wakes = 0;
1594 }
1595
tegra_xusb_probe(struct platform_device * pdev)1596 static int tegra_xusb_probe(struct platform_device *pdev)
1597 {
1598 struct tegra_xusb *tegra;
1599 struct device_node *np;
1600 struct resource *regs;
1601 struct xhci_hcd *xhci;
1602 unsigned int i, j, k;
1603 struct phy *phy;
1604 int err;
1605
1606 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1607
1608 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1609 if (!tegra)
1610 return -ENOMEM;
1611
1612 tegra->soc = of_device_get_match_data(&pdev->dev);
1613 mutex_init(&tegra->lock);
1614 tegra->dev = &pdev->dev;
1615
1616 err = tegra_xusb_init_context(tegra);
1617 if (err < 0)
1618 return err;
1619
1620 tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1621 if (IS_ERR(tegra->regs))
1622 return PTR_ERR(tegra->regs);
1623
1624 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1625 if (IS_ERR(tegra->fpci_base))
1626 return PTR_ERR(tegra->fpci_base);
1627
1628 if (tegra->soc->has_ipfs) {
1629 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1630 if (IS_ERR(tegra->ipfs_base))
1631 return PTR_ERR(tegra->ipfs_base);
1632 } else if (tegra->soc->has_bar2) {
1633 tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2);
1634 if (IS_ERR(tegra->bar2_base))
1635 return PTR_ERR(tegra->bar2_base);
1636 }
1637
1638 tegra->xhci_irq = platform_get_irq(pdev, 0);
1639 if (tegra->xhci_irq < 0)
1640 return tegra->xhci_irq;
1641
1642 tegra->mbox_irq = platform_get_irq(pdev, 1);
1643 if (tegra->mbox_irq < 0)
1644 return tegra->mbox_irq;
1645
1646 err = tegra_xusb_setup_wakeup(pdev, tegra);
1647 if (err)
1648 return err;
1649
1650 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1651 if (IS_ERR(tegra->padctl)) {
1652 err = PTR_ERR(tegra->padctl);
1653 goto dispose_wake;
1654 }
1655
1656 np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1657 if (!np) {
1658 err = -ENODEV;
1659 goto put_padctl;
1660 }
1661
1662 tegra->padctl_irq = of_irq_get(np, 0);
1663 if (tegra->padctl_irq == -EPROBE_DEFER) {
1664 err = tegra->padctl_irq;
1665 goto put_padctl;
1666 } else if (tegra->padctl_irq <= 0) {
1667 /* Older device-trees don't have padctrl interrupt */
1668 tegra->padctl_irq = 0;
1669 dev_dbg(&pdev->dev,
1670 "%pOF is missing an interrupt, disabling PM support\n", np);
1671 }
1672
1673 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1674 if (IS_ERR(tegra->host_clk)) {
1675 err = PTR_ERR(tegra->host_clk);
1676 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1677 goto put_padctl;
1678 }
1679
1680 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1681 if (IS_ERR(tegra->falcon_clk)) {
1682 err = PTR_ERR(tegra->falcon_clk);
1683 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1684 goto put_padctl;
1685 }
1686
1687 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1688 if (IS_ERR(tegra->ss_clk)) {
1689 err = PTR_ERR(tegra->ss_clk);
1690 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1691 goto put_padctl;
1692 }
1693
1694 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1695 if (IS_ERR(tegra->ss_src_clk)) {
1696 err = PTR_ERR(tegra->ss_src_clk);
1697 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1698 goto put_padctl;
1699 }
1700
1701 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1702 if (IS_ERR(tegra->hs_src_clk)) {
1703 err = PTR_ERR(tegra->hs_src_clk);
1704 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1705 goto put_padctl;
1706 }
1707
1708 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1709 if (IS_ERR(tegra->fs_src_clk)) {
1710 err = PTR_ERR(tegra->fs_src_clk);
1711 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1712 goto put_padctl;
1713 }
1714
1715 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1716 if (IS_ERR(tegra->pll_u_480m)) {
1717 err = PTR_ERR(tegra->pll_u_480m);
1718 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1719 goto put_padctl;
1720 }
1721
1722 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1723 if (IS_ERR(tegra->clk_m)) {
1724 err = PTR_ERR(tegra->clk_m);
1725 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1726 goto put_padctl;
1727 }
1728
1729 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1730 if (IS_ERR(tegra->pll_e)) {
1731 err = PTR_ERR(tegra->pll_e);
1732 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1733 goto put_padctl;
1734 }
1735
1736 if (!of_property_present(pdev->dev.of_node, "power-domains")) {
1737 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1738 "xusb_host");
1739 if (IS_ERR(tegra->host_rst)) {
1740 err = PTR_ERR(tegra->host_rst);
1741 dev_err(&pdev->dev,
1742 "failed to get xusb_host reset: %d\n", err);
1743 goto put_padctl;
1744 }
1745
1746 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1747 if (IS_ERR(tegra->ss_rst)) {
1748 err = PTR_ERR(tegra->ss_rst);
1749 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1750 err);
1751 goto put_padctl;
1752 }
1753 } else {
1754 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1755 if (err)
1756 goto put_powerdomains;
1757 }
1758
1759 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1760 sizeof(*tegra->supplies), GFP_KERNEL);
1761 if (!tegra->supplies) {
1762 err = -ENOMEM;
1763 goto put_powerdomains;
1764 }
1765
1766 regulator_bulk_set_supply_names(tegra->supplies,
1767 tegra->soc->supply_names,
1768 tegra->soc->num_supplies);
1769
1770 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1771 tegra->supplies);
1772 if (err) {
1773 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1774 goto put_powerdomains;
1775 }
1776
1777 for (i = 0; i < tegra->soc->num_types; i++) {
1778 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1779 tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1780 tegra->num_phys += tegra->soc->phy_types[i].num;
1781 }
1782
1783 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1784 sizeof(*tegra->phys), GFP_KERNEL);
1785 if (!tegra->phys) {
1786 err = -ENOMEM;
1787 goto put_powerdomains;
1788 }
1789
1790 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1791 char prop[8];
1792
1793 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1794 snprintf(prop, sizeof(prop), "%s-%d",
1795 tegra->soc->phy_types[i].name, j);
1796
1797 phy = devm_phy_optional_get(&pdev->dev, prop);
1798 if (IS_ERR(phy)) {
1799 dev_err(&pdev->dev,
1800 "failed to get PHY %s: %ld\n", prop,
1801 PTR_ERR(phy));
1802 err = PTR_ERR(phy);
1803 goto put_powerdomains;
1804 }
1805
1806 tegra->phys[k++] = phy;
1807 }
1808 }
1809
1810 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1811 dev_name(&pdev->dev));
1812 if (!tegra->hcd) {
1813 err = -ENOMEM;
1814 goto put_powerdomains;
1815 }
1816
1817 tegra->hcd->skip_phy_initialization = 1;
1818 tegra->hcd->regs = tegra->regs;
1819 tegra->hcd->rsrc_start = regs->start;
1820 tegra->hcd->rsrc_len = resource_size(regs);
1821
1822 /*
1823 * This must happen after usb_create_hcd(), because usb_create_hcd()
1824 * will overwrite the drvdata of the device with the hcd it creates.
1825 */
1826 platform_set_drvdata(pdev, tegra);
1827
1828 err = tegra_xusb_clk_enable(tegra);
1829 if (err) {
1830 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1831 goto put_hcd;
1832 }
1833
1834 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1835 if (err) {
1836 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1837 goto disable_clk;
1838 }
1839
1840 err = tegra_xusb_phy_enable(tegra);
1841 if (err < 0) {
1842 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1843 goto disable_regulator;
1844 }
1845
1846 /*
1847 * The XUSB Falcon microcontroller can only address 40 bits, so set
1848 * the DMA mask accordingly.
1849 */
1850 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1851 if (err < 0) {
1852 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1853 goto disable_phy;
1854 }
1855
1856 if (tegra->soc->firmware) {
1857 err = tegra_xusb_request_firmware(tegra);
1858 if (err < 0) {
1859 dev_err(&pdev->dev,
1860 "failed to request firmware: %d\n", err);
1861 goto disable_phy;
1862 }
1863 }
1864
1865 err = tegra_xusb_unpowergate_partitions(tegra);
1866 if (err)
1867 goto free_firmware;
1868
1869 tegra_xusb_config(tegra);
1870
1871 err = tegra_xusb_load_firmware(tegra);
1872 if (err < 0) {
1873 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1874 goto powergate;
1875 }
1876
1877 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1878 if (err < 0) {
1879 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1880 goto powergate;
1881 }
1882
1883 device_wakeup_enable(tegra->hcd->self.controller);
1884
1885 xhci = hcd_to_xhci(tegra->hcd);
1886
1887 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1888 &pdev->dev,
1889 dev_name(&pdev->dev),
1890 tegra->hcd);
1891 if (!xhci->shared_hcd) {
1892 dev_err(&pdev->dev, "failed to create shared HCD\n");
1893 err = -ENOMEM;
1894 goto remove_usb2;
1895 }
1896
1897 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
1898 xhci->shared_hcd->can_do_streams = 1;
1899
1900 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1901 if (err < 0) {
1902 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1903 goto put_usb3;
1904 }
1905
1906 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1907 tegra_xusb_mbox_irq,
1908 tegra_xusb_mbox_thread, 0,
1909 dev_name(&pdev->dev), tegra);
1910 if (err < 0) {
1911 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1912 goto remove_usb3;
1913 }
1914
1915 if (tegra->padctl_irq) {
1916 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq,
1917 NULL, tegra_xusb_padctl_irq,
1918 IRQF_ONESHOT, dev_name(&pdev->dev),
1919 tegra);
1920 if (err < 0) {
1921 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1922 goto remove_usb3;
1923 }
1924 }
1925
1926 err = tegra_xusb_enable_firmware_messages(tegra);
1927 if (err < 0) {
1928 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1929 goto remove_usb3;
1930 }
1931
1932 err = tegra_xusb_init_usb_phy(tegra);
1933 if (err < 0) {
1934 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1935 goto remove_usb3;
1936 }
1937
1938 /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1939 device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1940 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1941
1942 pm_runtime_use_autosuspend(tegra->dev);
1943 pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1944 pm_runtime_mark_last_busy(tegra->dev);
1945 pm_runtime_set_active(tegra->dev);
1946
1947 if (tegra->padctl_irq) {
1948 device_init_wakeup(tegra->dev, true);
1949 pm_runtime_enable(tegra->dev);
1950 }
1951
1952 return 0;
1953
1954 remove_usb3:
1955 usb_remove_hcd(xhci->shared_hcd);
1956 put_usb3:
1957 usb_put_hcd(xhci->shared_hcd);
1958 remove_usb2:
1959 usb_remove_hcd(tegra->hcd);
1960 powergate:
1961 tegra_xusb_powergate_partitions(tegra);
1962 free_firmware:
1963 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1964 tegra->fw.phys);
1965 disable_phy:
1966 tegra_xusb_phy_disable(tegra);
1967 disable_regulator:
1968 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1969 disable_clk:
1970 tegra_xusb_clk_disable(tegra);
1971 put_hcd:
1972 usb_put_hcd(tegra->hcd);
1973 put_powerdomains:
1974 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1975 put_padctl:
1976 of_node_put(np);
1977 tegra_xusb_padctl_put(tegra->padctl);
1978 dispose_wake:
1979 tegra_xusb_dispose_wake(tegra);
1980 return err;
1981 }
1982
tegra_xusb_disable(struct tegra_xusb * tegra)1983 static void tegra_xusb_disable(struct tegra_xusb *tegra)
1984 {
1985 tegra_xusb_powergate_partitions(tegra);
1986 tegra_xusb_powerdomain_remove(tegra->dev, tegra);
1987 tegra_xusb_phy_disable(tegra);
1988 tegra_xusb_clk_disable(tegra);
1989 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1990 }
1991
tegra_xusb_remove(struct platform_device * pdev)1992 static void tegra_xusb_remove(struct platform_device *pdev)
1993 {
1994 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1995 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1996
1997 tegra_xusb_deinit_usb_phy(tegra);
1998
1999 pm_runtime_get_sync(&pdev->dev);
2000 usb_remove_hcd(xhci->shared_hcd);
2001 usb_put_hcd(xhci->shared_hcd);
2002 xhci->shared_hcd = NULL;
2003 usb_remove_hcd(tegra->hcd);
2004 usb_put_hcd(tegra->hcd);
2005
2006 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
2007 tegra->fw.phys);
2008
2009 if (tegra->padctl_irq)
2010 pm_runtime_disable(&pdev->dev);
2011
2012 tegra_xusb_dispose_wake(tegra);
2013
2014 pm_runtime_put(&pdev->dev);
2015
2016 tegra_xusb_disable(tegra);
2017 tegra_xusb_padctl_put(tegra->padctl);
2018 }
2019
tegra_xusb_shutdown(struct platform_device * pdev)2020 static void tegra_xusb_shutdown(struct platform_device *pdev)
2021 {
2022 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
2023
2024 pm_runtime_get_sync(&pdev->dev);
2025 disable_irq(tegra->xhci_irq);
2026 xhci_shutdown(tegra->hcd);
2027 tegra_xusb_disable(tegra);
2028 }
2029
xhci_hub_ports_suspended(struct xhci_hub * hub)2030 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
2031 {
2032 struct device *dev = hub->hcd->self.controller;
2033 bool status = true;
2034 unsigned int i;
2035 u32 value;
2036
2037 for (i = 0; i < hub->num_ports; i++) {
2038 value = xhci_portsc_readl(hub->ports[i]);
2039 if ((value & PORT_PE) == 0)
2040 continue;
2041
2042 if ((value & PORT_PLS_MASK) != XDEV_U3) {
2043 dev_info(dev, "%u-%u isn't suspended: %#010x\n",
2044 hub->hcd->self.busnum, i + 1, value);
2045 status = false;
2046 }
2047 }
2048
2049 return status;
2050 }
2051
tegra_xusb_check_ports(struct tegra_xusb * tegra)2052 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
2053 {
2054 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2055 struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
2056 unsigned long flags;
2057 int err = 0;
2058
2059 if (bus_state->bus_suspended) {
2060 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
2061 * to U3 state, it takes 3ms to enter U3.
2062 */
2063 usleep_range(3000, 4000);
2064 }
2065
2066 spin_lock_irqsave(&xhci->lock, flags);
2067
2068 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
2069 !xhci_hub_ports_suspended(&xhci->usb3_rhub))
2070 err = -EBUSY;
2071
2072 spin_unlock_irqrestore(&xhci->lock, flags);
2073
2074 return err;
2075 }
2076
tegra_xusb_save_context(struct tegra_xusb * tegra)2077 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
2078 {
2079 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
2080 struct tegra_xusb_context *ctx = &tegra->context;
2081 unsigned int i;
2082
2083 if (soc->ipfs.num_offsets > 0) {
2084 for (i = 0; i < soc->ipfs.num_offsets; i++)
2085 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
2086 }
2087
2088 if (soc->fpci.num_offsets > 0) {
2089 for (i = 0; i < soc->fpci.num_offsets; i++)
2090 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
2091 }
2092 }
2093
tegra_xusb_restore_context(struct tegra_xusb * tegra)2094 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
2095 {
2096 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
2097 struct tegra_xusb_context *ctx = &tegra->context;
2098 unsigned int i;
2099
2100 if (soc->fpci.num_offsets > 0) {
2101 for (i = 0; i < soc->fpci.num_offsets; i++)
2102 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
2103 }
2104
2105 if (soc->ipfs.num_offsets > 0) {
2106 for (i = 0; i < soc->ipfs.num_offsets; i++)
2107 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
2108 }
2109 }
2110
tegra_xhci_portsc_to_speed(struct tegra_xusb * tegra,u32 portsc)2111 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
2112 {
2113 if (DEV_LOWSPEED(portsc))
2114 return USB_SPEED_LOW;
2115
2116 if (DEV_HIGHSPEED(portsc))
2117 return USB_SPEED_HIGH;
2118
2119 if (DEV_FULLSPEED(portsc))
2120 return USB_SPEED_FULL;
2121
2122 if (DEV_SUPERSPEED_ANY(portsc))
2123 return USB_SPEED_SUPER;
2124
2125 return USB_SPEED_UNKNOWN;
2126 }
2127
tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb * tegra)2128 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
2129 {
2130 struct tegra_xusb_padctl *padctl = tegra->padctl;
2131 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2132 enum usb_device_speed speed;
2133 struct phy *phy;
2134 unsigned int index, offset;
2135 unsigned int i, j, k;
2136 struct xhci_hub *rhub;
2137 u32 portsc;
2138
2139 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
2140 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
2141 rhub = &xhci->usb3_rhub;
2142 else
2143 rhub = &xhci->usb2_rhub;
2144
2145 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
2146 offset = tegra->soc->ports.usb2.count;
2147 else
2148 offset = 0;
2149
2150 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
2151 phy = tegra->phys[k++];
2152
2153 if (!phy)
2154 continue;
2155
2156 index = j + offset;
2157
2158 if (index >= rhub->num_ports)
2159 continue;
2160
2161 if (!is_host_mode_phy(tegra, i, j))
2162 continue;
2163
2164 portsc = xhci_portsc_readl(rhub->ports[index]);
2165 speed = tegra_xhci_portsc_to_speed(tegra, portsc);
2166 tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
2167 tegra_xusb_padctl_enable_phy_wake(padctl, phy);
2168 }
2169 }
2170 }
2171
tegra_xhci_disable_phy_wake(struct tegra_xusb * tegra)2172 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
2173 {
2174 struct tegra_xusb_padctl *padctl = tegra->padctl;
2175 unsigned int i;
2176
2177 for (i = 0; i < tegra->num_usb_phys; i++) {
2178 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
2179
2180 if (!phy)
2181 continue;
2182
2183 if (tegra_xusb_padctl_remote_wake_detected(padctl, phy))
2184 tegra_phy_xusb_utmi_pad_power_on(phy);
2185 }
2186
2187 for (i = 0; i < tegra->num_phys; i++) {
2188 if (!tegra->phys[i])
2189 continue;
2190
2191 if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i]))
2192 dev_dbg(tegra->dev, "%pOF remote wake detected\n",
2193 tegra->phys[i]->dev.of_node);
2194
2195 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
2196 }
2197 }
2198
tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb * tegra)2199 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
2200 {
2201 struct tegra_xusb_padctl *padctl = tegra->padctl;
2202 unsigned int i;
2203
2204 for (i = 0; i < tegra->num_phys; i++) {
2205 if (!tegra->phys[i])
2206 continue;
2207
2208 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
2209 }
2210 }
2211
tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb * tegra)2212 static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra)
2213 {
2214 unsigned int i, index_to_usb2;
2215 struct phy *phy;
2216
2217 for (i = 0; i < tegra->soc->num_types; i++) {
2218 if (strcmp(tegra->soc->phy_types[i].name, "usb2") == 0)
2219 index_to_usb2 = i;
2220 }
2221
2222 for (i = 0; i < tegra->num_usb_phys; i++) {
2223 if (!is_host_mode_phy(tegra, index_to_usb2, i))
2224 continue;
2225
2226 phy = tegra_xusb_get_phy(tegra, "usb2", i);
2227 if (tegra->lp0_utmi_pad_mask & BIT(i))
2228 tegra_phy_xusb_utmi_pad_power_on(phy);
2229 else
2230 tegra_phy_xusb_utmi_pad_power_down(phy);
2231 }
2232 }
2233
tegra_xusb_enter_elpg(struct tegra_xusb * tegra,bool is_auto_resume)2234 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool is_auto_resume)
2235 {
2236 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2237 struct device *dev = tegra->dev;
2238 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev);
2239 unsigned int i;
2240 int err;
2241 u32 usbcmd;
2242 u32 portsc;
2243
2244 dev_dbg(dev, "entering ELPG\n");
2245
2246 usbcmd = readl(&xhci->op_regs->command);
2247 usbcmd &= ~CMD_EIE;
2248 writel(usbcmd, &xhci->op_regs->command);
2249
2250 err = tegra_xusb_check_ports(tegra);
2251 if (err < 0) {
2252 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
2253 goto out;
2254 }
2255
2256 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) {
2257 if (!xhci->usb2_rhub.ports[i])
2258 continue;
2259 portsc = xhci_portsc_readl(xhci->usb2_rhub.ports[i]);
2260 tegra->lp0_utmi_pad_mask &= ~BIT(i);
2261 if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS))
2262 tegra->lp0_utmi_pad_mask |= BIT(i);
2263 }
2264
2265 err = xhci_suspend(xhci, wakeup);
2266 if (err < 0) {
2267 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
2268 goto out;
2269 }
2270
2271 tegra_xusb_save_context(tegra);
2272
2273 if (wakeup)
2274 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
2275
2276 tegra_xusb_powergate_partitions(tegra);
2277
2278 for (i = 0; i < tegra->num_phys; i++) {
2279 if (!tegra->phys[i])
2280 continue;
2281
2282 phy_power_off(tegra->phys[i]);
2283 if (!wakeup)
2284 phy_exit(tegra->phys[i]);
2285 }
2286
2287 tegra_xusb_clk_disable(tegra);
2288
2289 out:
2290 if (!err)
2291 dev_dbg(tegra->dev, "entering ELPG done\n");
2292 else {
2293 usbcmd = readl(&xhci->op_regs->command);
2294 usbcmd |= CMD_EIE;
2295 writel(usbcmd, &xhci->op_regs->command);
2296
2297 dev_dbg(tegra->dev, "entering ELPG failed\n");
2298 pm_runtime_mark_last_busy(tegra->dev);
2299 }
2300
2301 return err;
2302 }
2303
tegra_xusb_exit_elpg(struct tegra_xusb * tegra,bool is_auto_resume)2304 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool is_auto_resume)
2305 {
2306 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2307 struct device *dev = tegra->dev;
2308 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev);
2309 unsigned int i;
2310 u32 usbcmd;
2311 int err;
2312
2313 dev_dbg(dev, "exiting ELPG\n");
2314 pm_runtime_mark_last_busy(tegra->dev);
2315
2316 err = tegra_xusb_clk_enable(tegra);
2317 if (err < 0) {
2318 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2319 goto out;
2320 }
2321
2322 err = tegra_xusb_unpowergate_partitions(tegra);
2323 if (err)
2324 goto disable_clks;
2325
2326 if (wakeup)
2327 tegra_xhci_disable_phy_wake(tegra);
2328
2329 for (i = 0; i < tegra->num_phys; i++) {
2330 if (!tegra->phys[i])
2331 continue;
2332
2333 if (!wakeup)
2334 phy_init(tegra->phys[i]);
2335
2336 phy_power_on(tegra->phys[i]);
2337 }
2338 if (tegra->suspended)
2339 tegra_xhci_program_utmi_power_lp0_exit(tegra);
2340
2341 tegra_xusb_config(tegra);
2342 tegra_xusb_restore_context(tegra);
2343
2344 err = tegra_xusb_load_firmware(tegra);
2345 if (err < 0) {
2346 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2347 goto disable_phy;
2348 }
2349
2350 err = __tegra_xusb_enable_firmware_messages(tegra);
2351 if (err < 0) {
2352 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2353 goto disable_phy;
2354 }
2355
2356 if (wakeup)
2357 tegra_xhci_disable_phy_sleepwalk(tegra);
2358
2359 err = xhci_resume(xhci, false, is_auto_resume);
2360 if (err < 0) {
2361 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2362 goto disable_phy;
2363 }
2364
2365 usbcmd = readl(&xhci->op_regs->command);
2366 usbcmd |= CMD_EIE;
2367 writel(usbcmd, &xhci->op_regs->command);
2368
2369 goto out;
2370
2371 disable_phy:
2372 for (i = 0; i < tegra->num_phys; i++) {
2373 if (!tegra->phys[i])
2374 continue;
2375
2376 phy_power_off(tegra->phys[i]);
2377 if (!wakeup)
2378 phy_exit(tegra->phys[i]);
2379 }
2380 tegra_xusb_powergate_partitions(tegra);
2381 disable_clks:
2382 tegra_xusb_clk_disable(tegra);
2383 out:
2384 if (!err)
2385 dev_dbg(dev, "exiting ELPG done\n");
2386 else
2387 dev_dbg(dev, "exiting ELPG failed\n");
2388
2389 return err;
2390 }
2391
tegra_xusb_suspend(struct device * dev)2392 static __maybe_unused int tegra_xusb_suspend(struct device *dev)
2393 {
2394 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2395 int err;
2396
2397 synchronize_irq(tegra->mbox_irq);
2398
2399 mutex_lock(&tegra->lock);
2400
2401 if (pm_runtime_suspended(dev)) {
2402 err = tegra_xusb_exit_elpg(tegra, true);
2403 if (err < 0)
2404 goto out;
2405 }
2406
2407 err = tegra_xusb_enter_elpg(tegra, false);
2408 if (err < 0) {
2409 if (pm_runtime_suspended(dev)) {
2410 pm_runtime_disable(dev);
2411 pm_runtime_set_active(dev);
2412 pm_runtime_enable(dev);
2413 }
2414
2415 goto out;
2416 }
2417
2418 out:
2419 if (!err) {
2420 tegra->suspended = true;
2421 pm_runtime_disable(dev);
2422
2423 if (device_may_wakeup(dev)) {
2424 unsigned int i;
2425
2426 if (enable_irq_wake(tegra->padctl_irq))
2427 dev_err(dev, "failed to enable padctl wakes\n");
2428
2429 for (i = 0; i < tegra->num_wakes; i++)
2430 enable_irq_wake(tegra->wake_irqs[i]);
2431 }
2432 }
2433
2434 mutex_unlock(&tegra->lock);
2435
2436 return err;
2437 }
2438
tegra_xusb_resume(struct device * dev)2439 static __maybe_unused int tegra_xusb_resume(struct device *dev)
2440 {
2441 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2442 int err;
2443
2444 mutex_lock(&tegra->lock);
2445
2446 if (!tegra->suspended) {
2447 mutex_unlock(&tegra->lock);
2448 return 0;
2449 }
2450
2451 err = tegra_xusb_exit_elpg(tegra, false);
2452 if (err < 0) {
2453 mutex_unlock(&tegra->lock);
2454 return err;
2455 }
2456
2457 if (device_may_wakeup(dev)) {
2458 unsigned int i;
2459
2460 if (disable_irq_wake(tegra->padctl_irq))
2461 dev_err(dev, "failed to disable padctl wakes\n");
2462
2463 for (i = 0; i < tegra->num_wakes; i++)
2464 disable_irq_wake(tegra->wake_irqs[i]);
2465 }
2466 tegra->suspended = false;
2467 mutex_unlock(&tegra->lock);
2468
2469 pm_runtime_set_active(dev);
2470 pm_runtime_enable(dev);
2471
2472 return 0;
2473 }
2474
tegra_xusb_runtime_suspend(struct device * dev)2475 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev)
2476 {
2477 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2478 int ret;
2479
2480 synchronize_irq(tegra->mbox_irq);
2481 mutex_lock(&tegra->lock);
2482 ret = tegra_xusb_enter_elpg(tegra, true);
2483 mutex_unlock(&tegra->lock);
2484
2485 return ret;
2486 }
2487
tegra_xusb_runtime_resume(struct device * dev)2488 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev)
2489 {
2490 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2491 int err;
2492
2493 mutex_lock(&tegra->lock);
2494 err = tegra_xusb_exit_elpg(tegra, true);
2495 mutex_unlock(&tegra->lock);
2496
2497 return err;
2498 }
2499
2500 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2501 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2502 tegra_xusb_runtime_resume, NULL)
2503 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2504 };
2505
2506 static const char * const tegra124_supply_names[] = {
2507 "avddio-pex",
2508 "dvddio-pex",
2509 "avdd-usb",
2510 "hvdd-usb-ss",
2511 };
2512
2513 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2514 { .name = "usb3", .num = 2, },
2515 { .name = "usb2", .num = 3, },
2516 { .name = "hsic", .num = 2, },
2517 };
2518
2519 static const unsigned int tegra124_xusb_context_ipfs[] = {
2520 IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2521 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2522 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2523 IPFS_XUSB_HOST_MSI_VEC0_0,
2524 IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2525 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2526 IPFS_XUSB_HOST_INTR_MASK_0,
2527 IPFS_XUSB_HOST_INTR_ENABLE_0,
2528 IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2529 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2530 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2531 };
2532
2533 static const unsigned int tegra124_xusb_context_fpci[] = {
2534 XUSB_CFG_ARU_CONTEXT_HS_PLS,
2535 XUSB_CFG_ARU_CONTEXT_FS_PLS,
2536 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2537 XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2538 XUSB_CFG_ARU_CONTEXT,
2539 XUSB_CFG_AXI_CFG,
2540 XUSB_CFG_24,
2541 XUSB_CFG_16,
2542 };
2543
2544 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2545 .ipfs = {
2546 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2547 .offsets = tegra124_xusb_context_ipfs,
2548 },
2549 .fpci = {
2550 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2551 .offsets = tegra124_xusb_context_fpci,
2552 },
2553 };
2554
2555 static const struct tegra_xusb_soc_ops tegra124_ops = {
2556 .mbox_reg_readl = &fpci_readl,
2557 .mbox_reg_writel = &fpci_writel,
2558 .csb_reg_readl = &fpci_csb_readl,
2559 .csb_reg_writel = &fpci_csb_writel,
2560 };
2561
2562 static const struct tegra_xusb_soc tegra124_soc = {
2563 .firmware = "nvidia/tegra124/xusb.bin",
2564 .supply_names = tegra124_supply_names,
2565 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2566 .phy_types = tegra124_phy_types,
2567 .num_types = ARRAY_SIZE(tegra124_phy_types),
2568 .context = &tegra124_xusb_context,
2569 .ports = {
2570 .usb2 = { .offset = 4, .count = 4, },
2571 .hsic = { .offset = 6, .count = 2, },
2572 .usb3 = { .offset = 0, .count = 2, },
2573 },
2574 .scale_ss_clock = true,
2575 .has_ipfs = true,
2576 .otg_reset_sspi = false,
2577 .ops = &tegra124_ops,
2578 .mbox = {
2579 .cmd = 0xe4,
2580 .data_in = 0xe8,
2581 .data_out = 0xec,
2582 .owner = 0xf0,
2583 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2584 },
2585 };
2586 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2587
2588 static const char * const tegra210_supply_names[] = {
2589 "dvddio-pex",
2590 "hvddio-pex",
2591 "avdd-usb",
2592 };
2593
2594 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2595 { .name = "usb3", .num = 4, },
2596 { .name = "usb2", .num = 4, },
2597 { .name = "hsic", .num = 1, },
2598 };
2599
2600 static const struct tegra_xusb_soc tegra210_soc = {
2601 .firmware = "nvidia/tegra210/xusb.bin",
2602 .supply_names = tegra210_supply_names,
2603 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2604 .phy_types = tegra210_phy_types,
2605 .num_types = ARRAY_SIZE(tegra210_phy_types),
2606 .context = &tegra124_xusb_context,
2607 .ports = {
2608 .usb2 = { .offset = 4, .count = 4, },
2609 .hsic = { .offset = 8, .count = 1, },
2610 .usb3 = { .offset = 0, .count = 4, },
2611 },
2612 .scale_ss_clock = false,
2613 .has_ipfs = true,
2614 .otg_reset_sspi = true,
2615 .ops = &tegra124_ops,
2616 .mbox = {
2617 .cmd = 0xe4,
2618 .data_in = 0xe8,
2619 .data_out = 0xec,
2620 .owner = 0xf0,
2621 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2622 },
2623 };
2624 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2625
2626 static const char * const tegra186_supply_names[] = {
2627 };
2628 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2629
2630 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2631 { .name = "usb3", .num = 3, },
2632 { .name = "usb2", .num = 3, },
2633 { .name = "hsic", .num = 1, },
2634 };
2635
2636 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2637 .fpci = {
2638 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2639 .offsets = tegra124_xusb_context_fpci,
2640 },
2641 };
2642
2643 static const struct tegra_xusb_soc tegra186_soc = {
2644 .firmware = "nvidia/tegra186/xusb.bin",
2645 .supply_names = tegra186_supply_names,
2646 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2647 .phy_types = tegra186_phy_types,
2648 .num_types = ARRAY_SIZE(tegra186_phy_types),
2649 .context = &tegra186_xusb_context,
2650 .ports = {
2651 .usb3 = { .offset = 0, .count = 3, },
2652 .usb2 = { .offset = 3, .count = 3, },
2653 .hsic = { .offset = 6, .count = 1, },
2654 },
2655 .scale_ss_clock = false,
2656 .has_ipfs = false,
2657 .otg_reset_sspi = false,
2658 .ops = &tegra124_ops,
2659 .mbox = {
2660 .cmd = 0xe4,
2661 .data_in = 0xe8,
2662 .data_out = 0xec,
2663 .owner = 0xf0,
2664 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2665 },
2666 .lpm_support = true,
2667 };
2668
2669 static const char * const tegra194_supply_names[] = {
2670 };
2671
2672 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2673 { .name = "usb3", .num = 4, },
2674 { .name = "usb2", .num = 4, },
2675 };
2676
2677 static const struct tegra_xusb_soc tegra194_soc = {
2678 .firmware = "nvidia/tegra194/xusb.bin",
2679 .supply_names = tegra194_supply_names,
2680 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2681 .phy_types = tegra194_phy_types,
2682 .num_types = ARRAY_SIZE(tegra194_phy_types),
2683 .context = &tegra186_xusb_context,
2684 .ports = {
2685 .usb3 = { .offset = 0, .count = 4, },
2686 .usb2 = { .offset = 4, .count = 4, },
2687 },
2688 .scale_ss_clock = false,
2689 .has_ipfs = false,
2690 .otg_reset_sspi = false,
2691 .ops = &tegra124_ops,
2692 .mbox = {
2693 .cmd = 0x68,
2694 .data_in = 0x6c,
2695 .data_out = 0x70,
2696 .owner = 0x74,
2697 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2698 },
2699 .lpm_support = true,
2700 };
2701 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2702
2703 static const struct tegra_xusb_soc_ops tegra234_ops = {
2704 .mbox_reg_readl = &bar2_readl,
2705 .mbox_reg_writel = &bar2_writel,
2706 .csb_reg_readl = &bar2_csb_readl,
2707 .csb_reg_writel = &bar2_csb_writel,
2708 };
2709
2710 static const struct tegra_xusb_soc tegra234_soc = {
2711 .supply_names = tegra194_supply_names,
2712 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2713 .phy_types = tegra194_phy_types,
2714 .num_types = ARRAY_SIZE(tegra194_phy_types),
2715 .max_num_wakes = 7,
2716 .context = &tegra186_xusb_context,
2717 .ports = {
2718 .usb3 = { .offset = 0, .count = 4, },
2719 .usb2 = { .offset = 4, .count = 4, },
2720 },
2721 .scale_ss_clock = false,
2722 .has_ipfs = false,
2723 .otg_reset_sspi = false,
2724 .ops = &tegra234_ops,
2725 .mbox = {
2726 .cmd = XUSB_BAR2_ARU_MBOX_CMD,
2727 .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN,
2728 .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT,
2729 .owner = XUSB_BAR2_ARU_MBOX_OWNER,
2730 .smi_intr = XUSB_BAR2_ARU_SMI_INTR,
2731 },
2732 .lpm_support = true,
2733 .has_bar2 = true,
2734 };
2735
2736 static const struct of_device_id tegra_xusb_of_match[] = {
2737 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2738 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2739 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2740 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2741 { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc },
2742 { },
2743 };
2744 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2745
2746 static struct platform_driver tegra_xusb_driver = {
2747 .probe = tegra_xusb_probe,
2748 .remove = tegra_xusb_remove,
2749 .shutdown = tegra_xusb_shutdown,
2750 .driver = {
2751 .name = "tegra-xusb",
2752 .pm = &tegra_xusb_pm_ops,
2753 .of_match_table = tegra_xusb_of_match,
2754 },
2755 };
2756
tegra_xhci_quirks(struct device * dev,struct xhci_hcd * xhci)2757 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2758 {
2759 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2760
2761 if (tegra && tegra->soc->lpm_support)
2762 xhci->quirks |= XHCI_LPM_SUPPORT;
2763 }
2764
tegra_xhci_setup(struct usb_hcd * hcd)2765 static int tegra_xhci_setup(struct usb_hcd *hcd)
2766 {
2767 return xhci_gen_setup(hcd, tegra_xhci_quirks);
2768 }
2769
tegra_xhci_hub_control(struct usb_hcd * hcd,u16 type_req,u16 value,u16 index,char * buf,u16 length)2770 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index,
2771 char *buf, u16 length)
2772 {
2773 struct tegra_xusb *tegra = dev_get_drvdata(hcd->self.controller);
2774 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2775 struct xhci_hub *rhub;
2776 struct xhci_bus_state *bus_state;
2777 int port = (index & 0xff) - 1;
2778 unsigned int i;
2779 struct xhci_port **ports;
2780 u32 portsc;
2781 int ret;
2782 struct phy *phy;
2783
2784 rhub = &xhci->usb2_rhub;
2785 bus_state = &rhub->bus_state;
2786 if (bus_state->resuming_ports && hcd->speed == HCD_USB2) {
2787 ports = rhub->ports;
2788 i = rhub->num_ports;
2789 while (i--) {
2790 if (!test_bit(i, &bus_state->resuming_ports))
2791 continue;
2792 portsc = xhci_portsc_readl(ports[i]);
2793 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2794 tegra_phy_xusb_utmi_pad_power_on(
2795 tegra_xusb_get_phy(tegra, "usb2", (int) i));
2796 }
2797 }
2798
2799 if (hcd->speed == HCD_USB2) {
2800 phy = tegra_xusb_get_phy(tegra, "usb2", port);
2801 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) {
2802 if (!index || index > rhub->num_ports)
2803 return -EPIPE;
2804 tegra_phy_xusb_utmi_pad_power_on(phy);
2805 }
2806 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) {
2807 if (!index || index > rhub->num_ports)
2808 return -EPIPE;
2809 ports = rhub->ports;
2810 portsc = xhci_portsc_readl(ports[port]);
2811 if (portsc & PORT_CONNECT)
2812 tegra_phy_xusb_utmi_pad_power_on(phy);
2813 }
2814 }
2815
2816 ret = xhci_hub_control(hcd, type_req, value, index, buf, length);
2817 if (ret < 0)
2818 return ret;
2819
2820 if (hcd->speed == HCD_USB2) {
2821 /* Use phy where we set previously */
2822 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND))
2823 /* We don't suspend the PAD while HNP role swap happens on the OTG port */
2824 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2825 tegra_phy_xusb_utmi_pad_power_down(phy);
2826
2827 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) {
2828 ports = rhub->ports;
2829 portsc = xhci_portsc_readl(ports[port]);
2830 if (!(portsc & PORT_CONNECT)) {
2831 /* We don't suspend the PAD while HNP role swap happens on the OTG
2832 * port
2833 */
2834 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2835 tegra_phy_xusb_utmi_pad_power_down(phy);
2836 }
2837 }
2838 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST))
2839 tegra_phy_xusb_utmi_pad_power_on(phy);
2840 }
2841
2842 return ret;
2843 }
2844
2845 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2846 .reset = tegra_xhci_setup,
2847 .hub_control = tegra_xhci_hub_control,
2848 };
2849
tegra_xusb_init(void)2850 static int __init tegra_xusb_init(void)
2851 {
2852 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2853
2854 return platform_driver_register(&tegra_xusb_driver);
2855 }
2856 module_init(tegra_xusb_init);
2857
tegra_xusb_exit(void)2858 static void __exit tegra_xusb_exit(void)
2859 {
2860 platform_driver_unregister(&tegra_xusb_driver);
2861 }
2862 module_exit(tegra_xusb_exit);
2863
2864 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2865 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2866 MODULE_LICENSE("GPL v2");
2867