1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_panel_replay.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 #include "link/protocols/link_hdmi_frl.h" 52 53 #include "dm_helpers.h" 54 #include "link_enc_cfg.h" 55 #include "resource.h" 56 #include "dsc.h" 57 #include "dccg.h" 58 #include "clk_mgr.h" 59 #include "atomfirmware.h" 60 #include "vpg.h" 61 62 #define DC_LOGGER \ 63 dc_logger 64 #define DC_LOGGER_INIT(logger) \ 65 struct dal_logger *dc_logger = logger 66 67 #define LINK_INFO(...) \ 68 DC_LOG_HW_HOTPLUG( \ 69 __VA_ARGS__) 70 71 #define RETIMER_REDRIVER_INFO(...) \ 72 DC_LOG_RETIMER_REDRIVER( \ 73 __VA_ARGS__) 74 75 #define FRL_INFO(...) \ 76 DC_LOG_HDMI_FRL_LTP( \ 77 __VA_ARGS__) 78 79 #define MAX_MTP_SLOT_COUNT 64 80 #define LINK_TRAINING_ATTEMPTS 4 81 #define PEAK_FACTOR_X1000 1006 82 83 void link_blank_all_dp_displays(struct dc *dc) 84 { 85 unsigned int i; 86 uint8_t dpcd_power_state = '\0'; 87 enum dc_status status = DC_ERROR_UNEXPECTED; 88 89 for (i = 0; i < dc->link_count; i++) { 90 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 91 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 92 continue; 93 94 /* DP 2.0 spec requires that we read LTTPR caps first */ 95 dp_retrieve_lttpr_cap(dc->links[i]); 96 /* if any of the displays are lit up turn them off */ 97 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 98 &dpcd_power_state, sizeof(dpcd_power_state)); 99 100 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 101 link_blank_dp_stream(dc->links[i], true); 102 } 103 104 } 105 106 void link_blank_all_edp_displays(struct dc *dc) 107 { 108 unsigned int i; 109 uint8_t dpcd_power_state = '\0'; 110 enum dc_status status = DC_ERROR_UNEXPECTED; 111 112 for (i = 0; i < dc->link_count; i++) { 113 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 114 (!dc->links[i]->edp_sink_present)) 115 continue; 116 117 /* if any of the displays are lit up turn them off */ 118 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 119 &dpcd_power_state, sizeof(dpcd_power_state)); 120 121 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 122 link_blank_dp_stream(dc->links[i], true); 123 } 124 } 125 126 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 127 { 128 unsigned int j; 129 struct dc *dc = link->ctx->dc; 130 enum signal_type signal = link->connector_signal; 131 132 if ((signal == SIGNAL_TYPE_EDP) || 133 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 134 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 135 link->link_enc->funcs->get_dig_frontend && 136 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 137 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 138 139 if (fe != ENGINE_ID_UNKNOWN) 140 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 141 if (fe == dc->res_pool->stream_enc[j]->id) { 142 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 143 dc->res_pool->stream_enc[j]); 144 break; 145 } 146 } 147 } 148 149 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 150 (link->type != dc_connection_none)) 151 dpcd_write_rx_power_ctrl(link, false); 152 } 153 } 154 155 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 156 { 157 struct pipe_ctx *pipes[MAX_PIPES]; 158 struct dc_stream_state *streams[MAX_PIPES]; 159 struct dc_state *state = link->dc->current_state; 160 uint8_t count; 161 int i; 162 struct dc_stream_update stream_update; 163 bool dpms_off = true; 164 struct link_resource link_res = {0}; 165 166 memset(&stream_update, 0, sizeof(stream_update)); 167 stream_update.dpms_off = &dpms_off; 168 169 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 170 171 /* The subsequent call to dc_commit_updates_for_stream for a full update 172 * will release the current state and swap to a new state. Releasing the 173 * current state results in the stream pointers in the pipe_ctx structs 174 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 175 */ 176 for (i = 0; i < count; i++) 177 streams[i] = pipes[i]->stream; 178 179 for (i = 0; i < count; i++) { 180 stream_update.stream = streams[i]; 181 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 182 streams[i], &stream_update, 183 state); 184 } 185 186 /* link can be also enabled by vbios. In this case it is not recorded 187 * in pipe_ctx. Disable link phy here to make sure it is completely off 188 */ 189 if (dc_is_dp_signal(link->connector_signal)) 190 dp_disable_link_phy(link, &link_res, link->connector_signal); 191 } 192 193 void link_resume(struct dc_link *link) 194 { 195 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 196 program_hpd_filter(link); 197 } 198 199 /* This function returns true if the pipe is used to feed video signal directly 200 * to the link. 201 */ 202 static bool is_master_pipe_for_link(const struct dc_link *link, 203 const struct pipe_ctx *pipe) 204 { 205 return resource_is_pipe_type(pipe, OTG_MASTER) && 206 pipe->stream->link == link; 207 } 208 209 /* 210 * This function finds all master pipes feeding to a given link with dpms set to 211 * on in given dc state. 212 */ 213 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 214 struct dc_state *state, 215 uint8_t *count, 216 struct pipe_ctx *pipes[MAX_PIPES]) 217 { 218 int i; 219 struct pipe_ctx *pipe = NULL; 220 221 *count = 0; 222 for (i = 0; i < MAX_PIPES; i++) { 223 pipe = &state->res_ctx.pipe_ctx[i]; 224 225 if (is_master_pipe_for_link(link, pipe) && 226 pipe->stream->dpms_off == false) { 227 pipes[(*count)++] = pipe; 228 } 229 } 230 } 231 232 static struct ext_hdmi_settings create_ext_hdmi_settings( 233 uint8_t address, 234 uint8_t reg_num, 235 uint8_t reg_num_6g, 236 const struct i2c_reg_info *reg_settings, 237 const struct i2c_reg_info *reg_settings_6g 238 ) 239 { 240 struct ext_hdmi_settings result = { 241 .slv_addr = address, 242 .reg_num = reg_num, 243 .reg_num_6g = reg_num_6g, 244 }; 245 246 memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings)); 247 memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g)); 248 return result; 249 } 250 251 static bool get_ext_hdmi_settings( 252 const struct integrated_info *info, 253 enum engine_id eng_id, 254 struct ext_hdmi_settings *settings 255 ) 256 { 257 if (!settings || !info) 258 return false; 259 260 /* 261 * Get retimer settings from sbios for passing SI eye test for DCE11 262 * The setting values are varied based on board revision and port id 263 * Therefore the setting values of each ports is passed by sbios. 264 */ 265 266 // Check if current bios contains ext Hdmi settings 267 if (!(info->gpu_cap_info & 0x20)) 268 return false; 269 270 switch (eng_id) { 271 case ENGINE_ID_DIGA: 272 *settings = create_ext_hdmi_settings( 273 info->dp0_ext_hdmi_slv_addr, 274 info->dp0_ext_hdmi_reg_num, 275 info->dp0_ext_hdmi_6g_reg_num, 276 info->dp0_ext_hdmi_reg_settings, 277 info->dp0_ext_hdmi_6g_reg_settings 278 ); 279 break; 280 case ENGINE_ID_DIGB: 281 *settings = create_ext_hdmi_settings( 282 info->dp1_ext_hdmi_slv_addr, 283 info->dp1_ext_hdmi_reg_num, 284 info->dp1_ext_hdmi_6g_reg_num, 285 info->dp1_ext_hdmi_reg_settings, 286 info->dp1_ext_hdmi_6g_reg_settings 287 ); 288 break; 289 case ENGINE_ID_DIGC: 290 *settings = create_ext_hdmi_settings( 291 info->dp2_ext_hdmi_slv_addr, 292 info->dp2_ext_hdmi_reg_num, 293 info->dp2_ext_hdmi_6g_reg_num, 294 info->dp2_ext_hdmi_reg_settings, 295 info->dp2_ext_hdmi_6g_reg_settings 296 ); 297 break; 298 case ENGINE_ID_DIGD: 299 *settings = create_ext_hdmi_settings( 300 info->dp3_ext_hdmi_slv_addr, 301 info->dp3_ext_hdmi_reg_num, 302 info->dp3_ext_hdmi_6g_reg_num, 303 info->dp3_ext_hdmi_reg_settings, 304 info->dp3_ext_hdmi_6g_reg_settings 305 ); 306 break; 307 default: 308 return false; 309 } 310 311 // Validate settings from bios integrated info table 312 if ( 313 !settings->slv_addr 314 || settings->reg_num > ARRAY_SIZE(settings->reg_settings) 315 || settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g) 316 ) { 317 return false; 318 } 319 320 for (size_t i = 0; i < settings->reg_num; i++) { 321 if (settings->reg_settings[i].i2c_reg_index > 0x20) 322 return false; 323 } 324 325 for (size_t i = 0; i < settings->reg_num_6g; i++) { 326 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 327 return false; 328 } 329 return true; 330 } 331 332 static bool write_i2c( 333 const struct dc_link *link, 334 uint8_t address, 335 uint8_t *buffer, 336 uint32_t length 337 ) 338 { 339 struct i2c_payload payload = { 340 .write = true, 341 .address = address, 342 .length = length, 343 .data = buffer, 344 }; 345 struct i2c_command cmd = { 346 .payloads = &payload, 347 .number_of_payloads = 1, 348 .engine = I2C_COMMAND_ENGINE_DEFAULT, 349 .speed = link->ctx->dc->caps.i2c_speed_in_khz, 350 }; 351 352 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 353 } 354 355 static bool write_i2c_retimer_offset_value( 356 const struct dc_link *link, 357 uint8_t address, 358 uint8_t offset, 359 uint8_t value 360 ) 361 { 362 DC_LOGGER_INIT(link->ctx->logger); 363 uint8_t buffer[] = { offset, value }; 364 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 365 366 RETIMER_REDRIVER_INFO( 367 "Retimer write, address: 0x%x, offset: 0x%x, value: 0x%x, success: %d\n", 368 address, offset, value, success 369 ); 370 return success; 371 } 372 373 static bool write_i2c_retimer_vga( 374 const struct dc_link *link, 375 uint8_t address 376 ) 377 { 378 DC_LOGGER_INIT(link->ctx->logger); 379 const uint8_t vga_data[][2] = { 380 { 0xFF, 0x01 }, 381 { 0x00, 0x23 }, 382 { 0xFF, 0x00 }, 383 }; 384 385 for (size_t i = 0; i < ARRAY_SIZE(vga_data); i++) { 386 if (!write_i2c_retimer_offset_value(link, address, vga_data[i][0], vga_data[i][1])) { 387 DC_LOG_ERROR("Set retimer failed, vga index: %zu\n", i); 388 return false; 389 } 390 } 391 return true; 392 } 393 394 static bool write_i2c_retimer_byte( 395 const struct dc_link *link, 396 uint8_t address, 397 uint8_t index, 398 uint8_t value 399 ) 400 { 401 DC_LOGGER_INIT(link->ctx->logger); 402 const uint8_t apply_rx_tx_change = 0x4; 403 404 if (index > 0x20) 405 return true; 406 407 if (!write_i2c_retimer_offset_value(link, address, index, value)) { 408 DC_LOG_ERROR("Set retimer failed, 3g index: 0x%x, value: 0x%x\n", index, value); 409 return false; 410 } 411 412 // Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 413 // needs to be set to 1 on every 0x0A-0x0C write. 414 if (0x0A <= index && index <= 0x0C) { 415 uint8_t offset = 0x0A; 416 417 // Query current value from offset 0x0A 418 if (index == 0x0A) { 419 // Just written correct value, so no need to read it back 420 } else { 421 if (!link_query_ddc_data( 422 link->ddc, address, &offset, 1, &value, 1 423 )) { 424 DC_LOG_ERROR("Set retimer failed, link_query_ddc_data\n"); 425 return false; 426 } 427 } 428 429 value |= apply_rx_tx_change; 430 if (!write_i2c_retimer_offset_value(link, address, offset, value)) { 431 DC_LOG_ERROR("Set retimer failed, 3g offset: 0x%x, value: 0x%x\n", offset, value); 432 return false; 433 } 434 } 435 return true; 436 } 437 438 static bool write_i2c_retimer_setting( 439 const struct dc_link *link, 440 bool is_vga_mode, 441 bool is_over_340mhz, 442 struct ext_hdmi_settings *settings) 443 { 444 DC_LOGGER_INIT(link->ctx->logger); 445 const uint8_t address = settings->slv_addr >> 1; 446 447 for (size_t i = 0; i < settings->reg_num; i++) { 448 const uint8_t index = settings->reg_settings[i].i2c_reg_index; 449 uint8_t value = settings->reg_settings[i].i2c_reg_val; 450 451 if (!write_i2c_retimer_byte(link, address, index, value)) { 452 DC_LOG_ERROR("Set retimer failed, index: %zu\n", i); 453 return false; 454 } 455 } 456 457 if (is_over_340mhz) { 458 for (size_t i = 0; i < settings->reg_num_6g; i++) { 459 const uint8_t index = settings->reg_settings_6g[i].i2c_reg_index; 460 uint8_t value = settings->reg_settings_6g[i].i2c_reg_val; 461 462 if (!write_i2c_retimer_byte(link, address, index, value)) { 463 DC_LOG_ERROR("Set retimer failed, 6g index: %zu\n", i); 464 return false; 465 } 466 } 467 } 468 469 if (is_vga_mode) { 470 return write_i2c_retimer_vga(link, address); 471 } 472 return true; 473 } 474 475 static bool write_i2c_default_retimer_setting( 476 const struct dc_link *link, 477 bool is_vga_mode, 478 bool is_over_340mhz) 479 { 480 const uint8_t address = 0xBA >> 1; 481 482 DC_LOGGER_INIT(link->ctx->logger); 483 484 const uint8_t data[][2] = { 485 { 0x0A, 0x13 }, 486 { 0x0A, 0x17 }, 487 { 0x0B, is_over_340mhz ? 0xDA : 0xD8 }, 488 { 0x0A, 0x17 }, 489 { 0x0C, is_over_340mhz ? 0x1D : 0x91 }, 490 { 0x0A, 0x17 }, 491 }; 492 493 for (size_t i = 0; i < ARRAY_SIZE(data); i++) { 494 if (!write_i2c_retimer_offset_value(link, address, data[i][0], data[i][1])) { 495 DC_LOG_ERROR("Set default retimer failed, index: %zu\n", i); 496 return false; 497 } 498 } 499 500 if (is_vga_mode) { 501 return write_i2c_retimer_vga(link, address); 502 } 503 return true; 504 } 505 506 static bool write_i2c_redriver_setting( 507 const struct dc_link *link, 508 bool is_over_340mhz) 509 { 510 DC_LOGGER_INIT(link->ctx->logger); 511 const uint8_t address = 0xF0 >> 1; 512 uint8_t buffer[16] = { 513 [3] = 0x4E, 514 [4] = 0x4E, 515 [5] = 0x4E, 516 [6] = is_over_340mhz ? 0x4E : 0x4A, 517 }; 518 519 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 520 521 RETIMER_REDRIVER_INFO( 522 "Redriver write, address: 0x%x, buffer: { [3]: 0x%x, 0x%x, 0x%x, 0x%x }, success: %d\n", 523 address, buffer[3], buffer[4], buffer[5], buffer[6], success 524 ); 525 526 if (!success) 527 DC_LOG_ERROR("Set redriver failed"); 528 return success; 529 } 530 531 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 532 { 533 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 534 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 535 struct cp_psp_stream_config config = {0}; 536 enum dp_panel_mode panel_mode = 537 dp_get_panel_mode(pipe_ctx->stream->link); 538 539 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 540 return; 541 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 542 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 543 ASSERT(link_enc); 544 if (link_enc == NULL) 545 return; 546 547 /* otg instance */ 548 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 549 550 /* dig front end */ 551 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 552 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 553 config.dig_fe = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst; 554 555 /* stream encoder index */ 556 config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA); 557 if (dp_is_128b_132b_signal(pipe_ctx)) 558 config.stream_enc_idx = 559 (uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0); 560 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 561 config.stream_enc_idx = 562 (uint8_t)(pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0); 563 564 /* dig back end */ 565 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 566 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 567 config.dig_be = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst; 568 569 /* link encoder index */ 570 config.link_enc_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); 571 if (dp_is_128b_132b_signal(pipe_ctx)) 572 config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst; 573 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 574 config.link_enc_idx = (uint8_t)pipe_ctx->stream->link->hpo_frl_link_enc->inst; 575 576 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 577 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 578 config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1); 579 else 580 config.dio_output_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); 581 582 583 /* phy index */ 584 config.phy_idx = resource_transmitter_to_phy_idx( 585 pipe_ctx->stream->link->dc, link_enc->transmitter); 586 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 587 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 588 config.phy_idx = 0; 589 590 /* stream properties */ 591 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 592 config.mst_enabled = (pipe_ctx->stream->signal == 593 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 594 config.frl_enabled = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ? 1 : 0; 595 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 596 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 597 1 : 0; 598 config.dpms_off = dpms_off; 599 600 /* dm stream context */ 601 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 602 603 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 604 } 605 606 void link_wait_for_unlocked(struct dc_link *link) 607 { 608 unsigned long long enter_timestamp; 609 unsigned long long finish_timestamp; 610 unsigned long long time_taken_in_ns; 611 bool waited = false; 612 613 DC_LOGGER_INIT(link->ctx->logger); 614 615 enter_timestamp = dm_get_timestamp(link->ctx); 616 617 while (link->is_link_locked) { // busy wait 618 if (!waited) { 619 DC_LOG_DC("%s: 0x%p ...", __func__, link); 620 621 waited = true; 622 } 623 624 udelay(1); 625 } 626 627 if (!waited) 628 return; 629 630 finish_timestamp = dm_get_timestamp(link->ctx); 631 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, 632 finish_timestamp, enter_timestamp); 633 634 DC_LOG_DC("%s: 0x%p took %llu ms.", __func__, 635 link, div_u64(time_taken_in_ns, 1000000)); 636 } 637 638 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 639 { 640 struct dc *dc = pipe_ctx->stream->ctx->dc; 641 642 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 643 return; 644 645 if (pipe_ctx->stream->timing.flags.DSC) 646 return; 647 648 dc->hwss.set_avmute(pipe_ctx, enable); 649 } 650 651 static void enable_mst_on_sink(struct dc_link *link, bool enable) 652 { 653 unsigned char mstmCntl = 0; 654 655 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 656 if (enable) 657 mstmCntl |= DP_MST_EN; 658 else 659 mstmCntl &= (~DP_MST_EN); 660 661 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 662 } 663 664 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 665 struct dsc_optc_config *config) 666 { 667 uint32_t precision = 1 << 28; 668 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 669 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 670 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 671 DC_LOGGER_INIT(dsc->ctx->logger); 672 673 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 674 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 675 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 676 */ 677 ll_bytes_per_pix_fraq *= 10000000; 678 ll_bytes_per_pix_fraq /= precision; 679 680 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 681 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 682 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 683 DC_LOG_DSC("\tslice_width %d", config->slice_width); 684 } 685 686 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 687 { 688 struct dc *dc = pipe_ctx->stream->ctx->dc; 689 struct dc_stream_state *stream = pipe_ctx->stream; 690 bool result = false; 691 692 if (dc_is_virtual_signal(stream->signal)) 693 result = true; 694 else 695 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 696 return result; 697 } 698 699 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 700 { 701 struct dc *dc = pipe_ctx->stream->ctx->dc; 702 struct dc_stream_state *stream = pipe_ctx->stream; 703 bool result = false; 704 705 if (dc_is_virtual_signal(stream->signal)) 706 result = true; 707 else 708 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 709 return result; 710 } 711 712 713 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 714 * i.e. after dp_enable_dsc_on_rx() had been called 715 */ 716 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 717 { 718 /* TODO: Move this to HWSS as this is hardware programming sequence not a 719 * link layer sequence 720 */ 721 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 722 struct dc *dc = pipe_ctx->stream->ctx->dc; 723 struct dc_stream_state *stream = pipe_ctx->stream; 724 struct pipe_ctx *odm_pipe; 725 int opp_cnt = 1; 726 struct dccg *dccg = dc->res_pool->dccg; 727 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 728 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 729 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 730 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 731 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 732 * this problem. We are implementing a workaround here to keep using dscclk 733 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 734 * 48Mhz) pixel clock to avoid hitting this problem. 735 */ 736 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 737 stream->timing.pix_clk_100hz > 480000; 738 DC_LOGGER_INIT(dsc->ctx->logger); 739 740 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 741 opp_cnt++; 742 743 if (enable) { 744 struct dsc_config dsc_cfg; 745 struct dsc_optc_config dsc_optc_cfg = {0}; 746 enum optc_dsc_mode optc_dsc_mode; 747 748 /* Enable DSC hw block */ 749 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 750 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 751 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 752 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 753 dsc_cfg.color_depth = stream->timing.display_color_depth; 754 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 755 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 756 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 757 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 758 dsc_cfg.dsc_padding = 0; 759 760 if (should_use_dto_dscclk) 761 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 762 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 763 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 764 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 765 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 766 767 if (should_use_dto_dscclk) 768 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 769 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 770 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 771 } 772 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 773 dsc_cfg.pic_width *= opp_cnt; 774 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 775 776 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 777 778 /* Enable DSC in encoder */ 779 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 780 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 781 dsc_optc_config_log(dsc, &dsc_optc_cfg); 782 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 783 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 784 optc_dsc_mode, 785 dsc_optc_cfg.bytes_per_pixel, 786 dsc_optc_cfg.slice_width); 787 788 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 789 } 790 else if (dc_is_hdmi_frl_signal(stream->signal)) { 791 uint8_t dsc_packed_pps[128]; 792 struct dc_crtc_timing patched_crtc_timing = stream->timing; 793 794 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id); 795 dsc_optc_config_log(dsc, &dsc_optc_cfg); 796 797 /* if we are borrowing from hblank, h_addressable and pic_width need to be adjusted */ 798 if (dc->debug.enable_hblank_borrow) { 799 dsc_cfg.pic_width = stream->timing.h_addressable; 800 } 801 802 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 803 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 804 pipe_ctx->stream_res.hpo_frl_stream_enc, &patched_crtc_timing, &dsc_packed_pps[0]); 805 } 806 807 /* Enable DSC in OPTC */ 808 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 809 dsc_optc_config_log(dsc, &dsc_optc_cfg); 810 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 811 optc_dsc_mode, 812 dsc_optc_cfg.bytes_per_pixel, 813 dsc_optc_cfg.slice_width); 814 } else { 815 /* disable DSC in OPTC */ 816 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 817 pipe_ctx->stream_res.tg, 818 OPTC_DSC_DISABLED, 0, 0); 819 820 /* disable DSC in stream encoder */ 821 if (dc_is_dp_signal(stream->signal)) { 822 if (dp_is_128b_132b_signal(pipe_ctx)) 823 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 824 pipe_ctx->stream_res.hpo_dp_stream_enc, 825 false, 826 NULL, 827 true); 828 else { 829 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 830 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 831 pipe_ctx->stream_res.stream_enc, 832 OPTC_DSC_DISABLED, 0, 0); 833 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 834 pipe_ctx->stream_res.stream_enc, false, NULL, true); 835 } 836 } 837 else if (dc_is_hdmi_frl_signal(stream->signal)) 838 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 839 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL); 840 841 /* disable DSC block */ 842 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 843 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 844 /* 845 * TODO - dsc_disconnect is a double buffered register. 846 * by the time we call dsc_disable, dsc may still remain 847 * connected to OPP. In this case OPTC will no longer 848 * get correct pixel data because DSCC is off. However 849 * we also can't wait for the disconnect pending 850 * complete, because this function can be called 851 * with/without OTG master lock acquired. When the lock 852 * is acquired we will never get pending complete until 853 * we release the lock later. So there is no easy way to 854 * solve this problem especially when the lock is 855 * acquired. DSC is a front end hw block it should be 856 * programmed as part of front end sequence, where the 857 * commit sequence without lock and update sequence 858 * with lock are completely separated. However because 859 * we are programming dsc as part of back end link 860 * programming sequence, we don't know if front end OPTC 861 * master lock is acquired. The back end should be 862 * agnostic to front end lock. DSC programming shouldn't 863 * belong to this sequence. 864 */ 865 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 866 if (dccg->funcs->set_ref_dscclk) 867 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 868 } 869 } 870 } 871 872 /* 873 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 874 * hence PPS info packet update need to use frame update instead of immediate update. 875 * Added parameter immediate_update for this purpose. 876 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 877 * which is the only place where a "false" would be passed in for param immediate_update. 878 * 879 * immediate_update is only applicable when DSC is enabled. 880 */ 881 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 882 { 883 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 884 struct dc_stream_state *stream = pipe_ctx->stream; 885 886 if (!pipe_ctx->stream->timing.flags.DSC) 887 return false; 888 889 if (!dsc) 890 return false; 891 892 DC_LOGGER_INIT(dsc->ctx->logger); 893 894 if (enable) { 895 struct dsc_config dsc_cfg; 896 uint8_t dsc_packed_pps[128]; 897 898 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 899 memset(dsc_packed_pps, 0, 128); 900 901 /* Enable DSC hw block */ 902 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 903 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 904 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 905 dsc_cfg.color_depth = stream->timing.display_color_depth; 906 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 907 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 908 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 909 910 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 911 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 912 if (dc_is_dp_signal(stream->signal)) { 913 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 914 if (dp_is_128b_132b_signal(pipe_ctx)) 915 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 916 pipe_ctx->stream_res.hpo_dp_stream_enc, 917 true, 918 &dsc_packed_pps[0], 919 immediate_update); 920 else 921 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 922 pipe_ctx->stream_res.stream_enc, 923 true, 924 &dsc_packed_pps[0], 925 immediate_update); 926 } 927 else if (dc_is_hdmi_frl_signal(stream->signal)) { 928 //TODO: bring HDMI FRL in line with DP 929 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id); 930 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 931 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, &dsc_packed_pps[0]); 932 } 933 } else { 934 /* disable DSC PPS in stream encoder */ 935 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 936 if (dc_is_dp_signal(stream->signal)) { 937 if (dp_is_128b_132b_signal(pipe_ctx)) 938 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 939 pipe_ctx->stream_res.hpo_dp_stream_enc, 940 false, 941 NULL, 942 true); 943 else 944 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 945 pipe_ctx->stream_res.stream_enc, false, NULL, true); 946 } 947 else if (dc_is_hdmi_frl_signal(stream->signal)) 948 //TODO: bring HDMI FRL in line with DP 949 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 950 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL); 951 } 952 953 return true; 954 } 955 956 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 957 { 958 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 959 bool result = false; 960 961 if (!pipe_ctx->stream->timing.flags.DSC) 962 goto out; 963 if (!dsc) 964 goto out; 965 966 if (enable) { 967 { 968 link_set_dsc_on_stream(pipe_ctx, true); 969 result = true; 970 } 971 } else { 972 dp_set_dsc_on_rx(pipe_ctx, false); 973 link_set_dsc_on_stream(pipe_ctx, false); 974 result = true; 975 } 976 out: 977 return result; 978 } 979 980 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 981 { 982 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 983 984 if (!pipe_ctx->stream->timing.flags.DSC) 985 return false; 986 if (!dsc) 987 return false; 988 989 link_set_dsc_on_stream(pipe_ctx, true); 990 link_set_dsc_pps_packet(pipe_ctx, true, false); 991 return true; 992 } 993 994 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 995 { 996 struct dc_stream_state *stream = pipe_ctx->stream; 997 998 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 999 struct dc_link *link = stream->link; 1000 union down_spread_ctrl old_downspread; 1001 union down_spread_ctrl new_downspread; 1002 1003 memset(&old_downspread, 0, sizeof(old_downspread)); 1004 1005 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1006 &old_downspread.raw, sizeof(old_downspread)); 1007 1008 new_downspread.raw = old_downspread.raw; 1009 1010 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1011 (stream->ignore_msa_timing_param) ? 1 : 0; 1012 1013 if (new_downspread.raw != old_downspread.raw) { 1014 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1015 &new_downspread.raw, sizeof(new_downspread)); 1016 } 1017 1018 } else { 1019 dm_helpers_mst_enable_stream_features(stream); 1020 } 1021 } 1022 1023 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1024 { 1025 const uint32_t VCP_Y_PRECISION = 1000; 1026 uint64_t vcp_x, vcp_y; 1027 DC_LOGGER_INIT(link->ctx->logger); 1028 1029 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1030 avg_time_slots_per_mtp = dc_fixpt_add( 1031 avg_time_slots_per_mtp, 1032 dc_fixpt_from_fraction( 1033 1, 1034 2*VCP_Y_PRECISION)); 1035 1036 vcp_x = dc_fixpt_floor( 1037 avg_time_slots_per_mtp); 1038 vcp_y = dc_fixpt_floor( 1039 dc_fixpt_mul_int( 1040 dc_fixpt_sub_int( 1041 avg_time_slots_per_mtp, 1042 dc_fixpt_floor( 1043 avg_time_slots_per_mtp)), 1044 VCP_Y_PRECISION)); 1045 1046 1047 if (link->type == dc_connection_mst_branch) 1048 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1049 "X: %llu " 1050 "Y: %llu/%d", 1051 vcp_x, 1052 vcp_y, 1053 VCP_Y_PRECISION); 1054 else 1055 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1056 "X: %llu " 1057 "Y: %llu/%d", 1058 vcp_x, 1059 vcp_y, 1060 VCP_Y_PRECISION); 1061 } 1062 1063 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1064 { 1065 struct fixed31_32 mbytes_per_sec; 1066 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1067 &stream->link->cur_link_settings); 1068 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1069 1070 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1071 1072 return dc_fixpt_div_int(mbytes_per_sec, 54); 1073 } 1074 1075 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1076 { 1077 struct fixed31_32 peak_kbps; 1078 uint32_t numerator = 0; 1079 uint32_t denominator = 1; 1080 1081 /* 1082 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1083 * required when determining PBN/time slot utilization on the link between 1084 * us and the branch, since that overhead is already accounted for in 1085 * the get_pbn_per_slot function. 1086 * 1087 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1088 * common multiplier to render an integer PBN for all link rate/lane 1089 * counts combinations 1090 * calculate 1091 * peak_kbps *= (64/54) 1092 * peak_kbps /= (8 * 1000) convert to bytes 1093 */ 1094 1095 numerator = 64; 1096 denominator = 54 * 8 * 1000; 1097 kbps *= numerator; 1098 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1099 1100 return peak_kbps; 1101 } 1102 1103 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1104 { 1105 uint64_t kbps; 1106 enum dc_link_encoding_format link_encoding; 1107 1108 if (dp_is_128b_132b_signal(pipe_ctx)) 1109 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1110 else 1111 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1112 1113 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1114 return get_pbn_from_bw_in_kbps(kbps); 1115 } 1116 1117 1118 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1119 static void get_lane_status( 1120 struct dc_link *link, 1121 uint32_t lane_count, 1122 union lane_status *status, 1123 union lane_align_status_updated *status_updated) 1124 { 1125 unsigned int lane; 1126 uint8_t dpcd_buf[3] = {0}; 1127 1128 if (status == NULL || status_updated == NULL) { 1129 return; 1130 } 1131 1132 core_link_read_dpcd( 1133 link, 1134 DP_LANE0_1_STATUS, 1135 dpcd_buf, 1136 sizeof(dpcd_buf)); 1137 1138 for (lane = 0; lane < lane_count; lane++) { 1139 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1140 } 1141 1142 status_updated->raw = dpcd_buf[2]; 1143 } 1144 1145 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1146 { 1147 /* 1148 * wait for ACT handled 1149 */ 1150 int i; 1151 const int act_retries = 30; 1152 enum act_return_status result = ACT_FAILED; 1153 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1154 union payload_table_update_status update_status = {0}; 1155 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1156 union lane_align_status_updated lane_status_updated; 1157 DC_LOGGER_INIT(link->ctx->logger); 1158 1159 if (!display_connected || link->aux_access_disabled) 1160 return true; 1161 for (i = 0; i < act_retries; i++) { 1162 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1163 1164 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1165 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1166 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1167 !dp_is_interlane_aligned(lane_status_updated)) { 1168 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1169 "polling for ACT handled."); 1170 result = ACT_LINK_LOST; 1171 break; 1172 } 1173 core_link_read_dpcd( 1174 link, 1175 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1176 &update_status.raw, 1177 1); 1178 1179 if (update_status.bits.ACT_HANDLED == 1) { 1180 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1181 result = ACT_SUCCESS; 1182 break; 1183 } 1184 1185 fsleep(5000); 1186 } 1187 1188 if (result == ACT_FAILED) { 1189 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1190 "continue on. Something is wrong with the branch."); 1191 } 1192 1193 return (result == ACT_SUCCESS); 1194 } 1195 1196 static void update_mst_stream_alloc_table( 1197 struct dc_link *link, 1198 struct stream_encoder *stream_enc, 1199 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1200 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1201 { 1202 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1203 struct link_mst_stream_allocation *dc_alloc; 1204 1205 int i; 1206 int j; 1207 1208 /* if DRM proposed_table has more than one new payload */ 1209 ASSERT(proposed_table->stream_count - 1210 link->mst_stream_alloc_table.stream_count < 2); 1211 1212 /* copy proposed_table to link, add stream encoder */ 1213 for (i = 0; i < proposed_table->stream_count; i++) { 1214 1215 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1216 dc_alloc = 1217 &link->mst_stream_alloc_table.stream_allocations[j]; 1218 1219 if (dc_alloc->vcp_id == 1220 proposed_table->stream_allocations[i].vcp_id) { 1221 1222 work_table[i] = *dc_alloc; 1223 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1224 break; /* exit j loop */ 1225 } 1226 } 1227 1228 /* new vcp_id */ 1229 if (j == link->mst_stream_alloc_table.stream_count) { 1230 work_table[i].vcp_id = 1231 proposed_table->stream_allocations[i].vcp_id; 1232 work_table[i].slot_count = 1233 proposed_table->stream_allocations[i].slot_count; 1234 work_table[i].stream_enc = stream_enc; 1235 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1236 } 1237 } 1238 1239 /* update link->mst_stream_alloc_table with work_table */ 1240 link->mst_stream_alloc_table.stream_count = 1241 proposed_table->stream_count; 1242 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1243 link->mst_stream_alloc_table.stream_allocations[i] = 1244 work_table[i]; 1245 } 1246 1247 static void remove_stream_from_alloc_table( 1248 struct dc_link *link, 1249 struct stream_encoder *dio_stream_enc, 1250 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1251 { 1252 int i = 0; 1253 struct link_mst_stream_allocation_table *table = 1254 &link->mst_stream_alloc_table; 1255 1256 if (hpo_dp_stream_enc) { 1257 for (; i < table->stream_count; i++) 1258 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1259 break; 1260 } else { 1261 for (; i < table->stream_count; i++) 1262 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1263 break; 1264 } 1265 1266 if (i < table->stream_count) { 1267 i++; 1268 for (; i < table->stream_count; i++) 1269 table->stream_allocations[i-1] = table->stream_allocations[i]; 1270 memset(&table->stream_allocations[table->stream_count-1], 0, 1271 sizeof(struct link_mst_stream_allocation)); 1272 table->stream_count--; 1273 } 1274 } 1275 1276 static void print_mst_streams(struct dc_link *link) 1277 { 1278 int i; 1279 1280 DC_LOGGER_INIT(link->ctx->logger); 1281 1282 DC_LOG_MST("%s stream_count: %d:\n", 1283 __func__, 1284 link->mst_stream_alloc_table.stream_count); 1285 1286 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1287 DC_LOG_MST("stream_enc[%d]: %p\n", i, 1288 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc); 1289 DC_LOG_MST("stream[%d].hpo_dp_stream_enc: %p\n", i, 1290 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc); 1291 DC_LOG_MST("stream[%d].vcp_id: %d\n", i, 1292 link->mst_stream_alloc_table.stream_allocations[i].vcp_id); 1293 DC_LOG_MST("stream[%d].slot_count: %d\n", i, 1294 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1295 } 1296 } 1297 1298 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1299 { 1300 struct dc_stream_state *stream = pipe_ctx->stream; 1301 struct dc_link *link = stream->link; 1302 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1303 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1304 bool mst_mode = (link->type == dc_connection_mst_branch); 1305 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1306 const struct dc_link_settings empty_link_settings = {0}; 1307 DC_LOGGER_INIT(link->ctx->logger); 1308 1309 /* deallocate_mst_payload is called before disable link. When mode or 1310 * disable/enable monitor, new stream is created which is not in link 1311 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1312 * should not done. For new mode set, map_resources will get engine 1313 * for new stream, so stream_enc->id should be validated until here. 1314 */ 1315 1316 /* slot X.Y */ 1317 if (link_hwss->ext.set_throttled_vcp_size) 1318 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1319 if (link_hwss->ext.set_hblank_min_symbol_width) 1320 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1321 &empty_link_settings, 1322 avg_time_slots_per_mtp); 1323 1324 if (mst_mode) { 1325 /* when link is in mst mode, reply on mst manager to remove 1326 * payload 1327 */ 1328 if (dm_helpers_dp_mst_write_payload_allocation_table( 1329 stream->ctx, 1330 stream, 1331 &proposed_table, 1332 false)) 1333 update_mst_stream_alloc_table( 1334 link, 1335 pipe_ctx->stream_res.stream_enc, 1336 pipe_ctx->stream_res.hpo_dp_stream_enc, 1337 &proposed_table); 1338 else 1339 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1340 pipe_ctx->pipe_idx); 1341 } else { 1342 /* when link is no longer in mst mode (mst hub unplugged), 1343 * remove payload with default dc logic 1344 */ 1345 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1346 pipe_ctx->stream_res.hpo_dp_stream_enc); 1347 } 1348 1349 print_mst_streams(link); 1350 1351 /* update mst stream allocation table hardware state */ 1352 if (link_hwss->ext.update_stream_allocation_table == NULL || 1353 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1354 DC_LOG_DEBUG("Unknown encoding format\n"); 1355 return DC_ERROR_UNEXPECTED; 1356 } 1357 1358 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1359 &link->mst_stream_alloc_table); 1360 1361 if (mst_mode) 1362 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1363 stream->ctx, 1364 stream); 1365 1366 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1367 stream->ctx, 1368 stream); 1369 1370 return DC_OK; 1371 } 1372 1373 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1374 * because stream_encoder is not exposed to dm 1375 */ 1376 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1377 { 1378 struct dc_stream_state *stream = pipe_ctx->stream; 1379 struct dc_link *link = stream->link; 1380 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1381 struct fixed31_32 avg_time_slots_per_mtp; 1382 struct fixed31_32 pbn; 1383 struct fixed31_32 pbn_per_slot; 1384 enum act_return_status ret; 1385 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1386 DC_LOGGER_INIT(link->ctx->logger); 1387 1388 /* enable_link_dp_mst already check link->enabled_stream_count 1389 * and stream is in link->stream[]. This is called during set mode, 1390 * stream_enc is available. 1391 */ 1392 1393 /* get calculate VC payload for stream: stream_alloc */ 1394 if (dm_helpers_dp_mst_write_payload_allocation_table( 1395 stream->ctx, 1396 stream, 1397 &proposed_table, 1398 true)) 1399 update_mst_stream_alloc_table( 1400 link, 1401 pipe_ctx->stream_res.stream_enc, 1402 pipe_ctx->stream_res.hpo_dp_stream_enc, 1403 &proposed_table); 1404 else 1405 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1406 pipe_ctx->pipe_idx); 1407 1408 print_mst_streams(link); 1409 1410 ASSERT(proposed_table.stream_count > 0); 1411 1412 /* program DP source TX for payload */ 1413 if (link_hwss->ext.update_stream_allocation_table == NULL || 1414 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1415 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1416 return DC_ERROR_UNEXPECTED; 1417 } 1418 1419 link_hwss->ext.update_stream_allocation_table(link, 1420 &pipe_ctx->link_res, 1421 &link->mst_stream_alloc_table); 1422 1423 /* send down message */ 1424 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1425 stream->ctx, 1426 stream); 1427 1428 if (ret != ACT_LINK_LOST) 1429 dm_helpers_dp_mst_send_payload_allocation( 1430 stream->ctx, 1431 stream); 1432 1433 /* slot X.Y for only current stream */ 1434 pbn_per_slot = get_pbn_per_slot(stream); 1435 if (pbn_per_slot.value == 0) { 1436 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1437 return DC_UNSUPPORTED_VALUE; 1438 } 1439 pbn = get_pbn_from_timing(pipe_ctx); 1440 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1441 1442 log_vcp_x_y(link, avg_time_slots_per_mtp); 1443 1444 if (link_hwss->ext.set_throttled_vcp_size) 1445 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1446 if (link_hwss->ext.set_hblank_min_symbol_width) 1447 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1448 &link->cur_link_settings, 1449 avg_time_slots_per_mtp); 1450 1451 return DC_OK; 1452 } 1453 1454 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1455 const struct dc_stream_state *stream, 1456 const struct dc_link *link) 1457 { 1458 struct fixed31_32 link_bw_effective = 1459 dc_fixpt_from_int( 1460 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1461 struct fixed31_32 timeslot_bw_effective = 1462 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1463 struct fixed31_32 timing_bw = 1464 dc_fixpt_from_int( 1465 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1466 dc_link_get_highest_encoding_format(link))); 1467 struct fixed31_32 avg_time_slots_per_mtp = 1468 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1469 1470 return avg_time_slots_per_mtp; 1471 } 1472 1473 1474 static bool write_128b_132b_sst_payload_allocation_table( 1475 const struct dc_stream_state *stream, 1476 struct dc_link *link, 1477 struct link_mst_stream_allocation_table *proposed_table, 1478 bool allocate) 1479 { 1480 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1481 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1482 bool result = false; 1483 uint8_t req_slot_count = 0; 1484 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1485 union payload_table_update_status update_status = { 0 }; 1486 const uint32_t max_retries = 30; 1487 uint32_t retries = 0; 1488 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1489 DC_LOGGER_INIT(link->ctx->logger); 1490 1491 if (allocate) { 1492 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1493 req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp); 1494 /// Validation should filter out modes that exceed link BW 1495 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1496 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1497 return false; 1498 } else { 1499 /// Leave req_slot_count = 0 if allocate is false. 1500 } 1501 1502 proposed_table->stream_count = 1; /// Always 1 stream for SST 1503 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1504 proposed_table->stream_allocations[0].vcp_id = vc_id; 1505 1506 if (!display_connected || link->aux_access_disabled) 1507 return true; 1508 1509 /// Write DPCD 2C0 = 1 to start updating 1510 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1511 core_link_write_dpcd( 1512 link, 1513 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1514 &update_status.raw, 1515 1); 1516 1517 /// Program the changes in DPCD 1C0 - 1C2 1518 ASSERT(vc_id == 1); 1519 core_link_write_dpcd( 1520 link, 1521 DP_PAYLOAD_ALLOCATE_SET, 1522 &vc_id, 1523 1); 1524 1525 ASSERT(start_time_slot == 0); 1526 core_link_write_dpcd( 1527 link, 1528 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1529 &start_time_slot, 1530 1); 1531 1532 core_link_write_dpcd( 1533 link, 1534 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1535 &req_slot_count, 1536 1); 1537 1538 /// Poll till DPCD 2C0 read 1 1539 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1540 1541 while (retries < max_retries) { 1542 if (core_link_read_dpcd( 1543 link, 1544 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1545 &update_status.raw, 1546 1) == DC_OK) { 1547 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1548 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1549 result = true; 1550 break; 1551 } 1552 } else { 1553 union dpcd_rev dpcdRev = {0}; 1554 1555 if (core_link_read_dpcd( 1556 link, 1557 DP_DPCD_REV, 1558 &dpcdRev.raw, 1559 1) != DC_OK) { 1560 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1561 "of sink while polling payload table " 1562 "updated status bit."); 1563 break; 1564 } 1565 } 1566 retries++; 1567 fsleep(5000); 1568 } 1569 1570 if (!result && retries == max_retries) { 1571 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1572 "continue on. Something is wrong with the branch."); 1573 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1574 } 1575 1576 return result; 1577 } 1578 1579 /* 1580 * Payload allocation/deallocation for SST introduced in DP2.0 1581 */ 1582 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1583 bool allocate) 1584 { 1585 struct dc_stream_state *stream = pipe_ctx->stream; 1586 struct dc_link *link = stream->link; 1587 struct link_mst_stream_allocation_table proposed_table = {0}; 1588 struct fixed31_32 avg_time_slots_per_mtp; 1589 const struct dc_link_settings empty_link_settings = {0}; 1590 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1591 DC_LOGGER_INIT(link->ctx->logger); 1592 1593 /* slot X.Y for SST payload deallocate */ 1594 if (!allocate) { 1595 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1596 1597 log_vcp_x_y(link, avg_time_slots_per_mtp); 1598 1599 if (link_hwss->ext.set_throttled_vcp_size) 1600 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1601 avg_time_slots_per_mtp); 1602 if (link_hwss->ext.set_hblank_min_symbol_width) 1603 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1604 &empty_link_settings, 1605 avg_time_slots_per_mtp); 1606 } 1607 1608 /* calculate VC payload and update branch with new payload allocation table*/ 1609 if (!write_128b_132b_sst_payload_allocation_table( 1610 stream, 1611 link, 1612 &proposed_table, 1613 allocate)) { 1614 DC_LOG_ERROR("SST Update Payload: Failed to update " 1615 "allocation table for " 1616 "pipe idx: %d\n", 1617 pipe_ctx->pipe_idx); 1618 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1619 } 1620 1621 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1622 1623 ASSERT(proposed_table.stream_count == 1); 1624 1625 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1626 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1627 "vcp_id: %d " 1628 "slot_count: %d\n", 1629 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1630 proposed_table.stream_allocations[0].vcp_id, 1631 proposed_table.stream_allocations[0].slot_count); 1632 1633 /* program DP source TX for payload */ 1634 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1635 &proposed_table); 1636 1637 /* poll for ACT handled */ 1638 if (!poll_for_allocation_change_trigger(link)) { 1639 // Failures will result in blackscreen and errors logged 1640 BREAK_TO_DEBUGGER(); 1641 } 1642 1643 /* slot X.Y for SST payload allocate */ 1644 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1645 DP_128b_132b_ENCODING) { 1646 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1647 1648 log_vcp_x_y(link, avg_time_slots_per_mtp); 1649 1650 if (link_hwss->ext.set_throttled_vcp_size) 1651 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1652 avg_time_slots_per_mtp); 1653 if (link_hwss->ext.set_hblank_min_symbol_width) 1654 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1655 &link->cur_link_settings, 1656 avg_time_slots_per_mtp); 1657 } 1658 1659 /* Always return DC_OK. 1660 * If part of sequence fails, log failure(s) and show blackscreen 1661 */ 1662 return DC_OK; 1663 } 1664 1665 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1666 { 1667 struct dc_stream_state *stream = pipe_ctx->stream; 1668 struct dc_link *link = stream->link; 1669 struct fixed31_32 avg_time_slots_per_mtp; 1670 struct fixed31_32 pbn; 1671 struct fixed31_32 pbn_per_slot; 1672 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1673 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1674 DC_LOGGER_INIT(link->ctx->logger); 1675 1676 /* decrease throttled vcp size */ 1677 pbn_per_slot = get_pbn_per_slot(stream); 1678 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1679 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1680 1681 if (link_hwss->ext.set_throttled_vcp_size) 1682 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1683 if (link_hwss->ext.set_hblank_min_symbol_width) 1684 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1685 &link->cur_link_settings, 1686 avg_time_slots_per_mtp); 1687 1688 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1689 dm_helpers_dp_mst_send_payload_allocation( 1690 stream->ctx, 1691 stream); 1692 1693 /* notify immediate branch device table update */ 1694 if (dm_helpers_dp_mst_write_payload_allocation_table( 1695 stream->ctx, 1696 stream, 1697 &proposed_table, 1698 true)) { 1699 /* update mst stream allocation table software state */ 1700 update_mst_stream_alloc_table( 1701 link, 1702 pipe_ctx->stream_res.stream_enc, 1703 pipe_ctx->stream_res.hpo_dp_stream_enc, 1704 &proposed_table); 1705 } else { 1706 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1707 pipe_ctx->pipe_idx); 1708 } 1709 1710 print_mst_streams(link); 1711 1712 ASSERT(proposed_table.stream_count > 0); 1713 1714 /* update mst stream allocation table hardware state */ 1715 if (link_hwss->ext.update_stream_allocation_table == NULL || 1716 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1717 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1718 return DC_ERROR_UNEXPECTED; 1719 } 1720 1721 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1722 &link->mst_stream_alloc_table); 1723 1724 /* poll for immediate branch device ACT handled */ 1725 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1726 stream->ctx, 1727 stream); 1728 1729 return DC_OK; 1730 } 1731 1732 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1733 { 1734 struct dc_stream_state *stream = pipe_ctx->stream; 1735 struct dc_link *link = stream->link; 1736 struct fixed31_32 avg_time_slots_per_mtp; 1737 struct fixed31_32 pbn; 1738 struct fixed31_32 pbn_per_slot; 1739 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1740 enum act_return_status ret; 1741 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1742 DC_LOGGER_INIT(link->ctx->logger); 1743 1744 /* notify immediate branch device table update */ 1745 if (dm_helpers_dp_mst_write_payload_allocation_table( 1746 stream->ctx, 1747 stream, 1748 &proposed_table, 1749 true)) { 1750 /* update mst stream allocation table software state */ 1751 update_mst_stream_alloc_table( 1752 link, 1753 pipe_ctx->stream_res.stream_enc, 1754 pipe_ctx->stream_res.hpo_dp_stream_enc, 1755 &proposed_table); 1756 } 1757 1758 print_mst_streams(link); 1759 1760 ASSERT(proposed_table.stream_count > 0); 1761 1762 /* update mst stream allocation table hardware state */ 1763 if (link_hwss->ext.update_stream_allocation_table == NULL || 1764 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1765 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1766 return DC_ERROR_UNEXPECTED; 1767 } 1768 1769 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1770 &link->mst_stream_alloc_table); 1771 1772 /* poll for immediate branch device ACT handled */ 1773 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1774 stream->ctx, 1775 stream); 1776 1777 if (ret != ACT_LINK_LOST) { 1778 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1779 dm_helpers_dp_mst_send_payload_allocation( 1780 stream->ctx, 1781 stream); 1782 } 1783 1784 /* increase throttled vcp size */ 1785 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1786 pbn_per_slot = get_pbn_per_slot(stream); 1787 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1788 1789 if (link_hwss->ext.set_throttled_vcp_size) 1790 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1791 if (link_hwss->ext.set_hblank_min_symbol_width) 1792 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1793 &link->cur_link_settings, 1794 avg_time_slots_per_mtp); 1795 1796 return DC_OK; 1797 } 1798 1799 static void disable_link_dp(struct dc_link *link, 1800 const struct link_resource *link_res, 1801 enum signal_type signal) 1802 { 1803 struct dc_link_settings link_settings = link->cur_link_settings; 1804 1805 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1806 link->mst_stream_alloc_table.stream_count > 0) 1807 /* disable MST link only when last vc payload is deallocated */ 1808 return; 1809 1810 dp_disable_link_phy(link, link_res, signal); 1811 1812 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1813 if (!link->skip_implict_edp_power_control) 1814 link->dc->hwss.edp_power_control(link, false); 1815 } 1816 1817 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) 1818 /* set the sink to SST mode after disabling the link */ 1819 enable_mst_on_sink(link, false); 1820 1821 if (link_dp_get_encoding_format(&link_settings) == 1822 DP_8b_10b_ENCODING) { 1823 dp_set_fec_enable(link, link_res, false); 1824 dp_set_fec_ready(link, link_res, false); 1825 } 1826 } 1827 1828 static void disable_link(struct dc_link *link, 1829 const struct link_resource *link_res, 1830 enum signal_type signal) 1831 { 1832 if (dc_is_dp_signal(signal)) { 1833 disable_link_dp(link, link_res, signal); 1834 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1835 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1836 } else { 1837 link->dc->hwss.disable_link_output(link, link_res, signal); 1838 } 1839 1840 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1841 /* MST disable link only when no stream use the link */ 1842 if (link->mst_stream_alloc_table.stream_count <= 0) 1843 link->link_status.link_active = false; 1844 } else { 1845 link->link_status.link_active = false; 1846 } 1847 } 1848 1849 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1850 { 1851 struct dc_stream_state *stream = pipe_ctx->stream; 1852 struct dc_link *link = stream->link; 1853 enum dc_color_depth display_color_depth; 1854 enum engine_id eng_id; 1855 struct ext_hdmi_settings settings = {0}; 1856 bool is_over_340mhz = false; 1857 bool is_vga_mode = (stream->timing.h_addressable == 640) 1858 && (stream->timing.v_addressable == 480); 1859 struct dc *dc = pipe_ctx->stream->ctx->dc; 1860 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1861 1862 if (stream->phy_pix_clk == 0) 1863 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1864 if (stream->phy_pix_clk > 340000) 1865 is_over_340mhz = true; 1866 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1867 ASSERT(false); 1868 return; 1869 } 1870 1871 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1872 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1873 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1874 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1875 /* DP159, Retimer settings */ 1876 eng_id = pipe_ctx->stream_res.stream_enc->id; 1877 1878 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) { 1879 write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); 1880 } else { 1881 write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); 1882 } 1883 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1884 /* PI3EQX1204, Redriver settings */ 1885 write_i2c_redriver_setting(link, is_over_340mhz); 1886 } 1887 } 1888 1889 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1890 write_scdc_data( 1891 stream->link->ddc, 1892 stream->phy_pix_clk, 1893 (stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0)); 1894 1895 if (dc->debug.enable_hdmi_idcc) { 1896 union hdmi_idcc_source_id source_id; 1897 1898 source_id.raw = 0xff; 1899 write_idcc_data(stream->link->ddc, HDMI_IDCC_SCOPE_WRITE, 1900 &source_id.raw, 0, 1); 1901 } 1902 memset(&stream->link->cur_link_settings, 0, 1903 sizeof(struct dc_link_settings)); 1904 1905 display_color_depth = stream->timing.display_color_depth; 1906 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1907 display_color_depth = COLOR_DEPTH_888; 1908 1909 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1910 * character clock in case that beyond 340MHz. 1911 */ 1912 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 1913 link_hwss->setup_stream_encoder(pipe_ctx); 1914 1915 dc->hwss.enable_tmds_link_output( 1916 link, 1917 &pipe_ctx->link_res, 1918 pipe_ctx->stream->signal, 1919 pipe_ctx->clock_source->id, 1920 display_color_depth, 1921 stream->phy_pix_clk); 1922 1923 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1924 read_scdc_data(link->ddc); 1925 } 1926 1927 static enum dc_status enable_link_hdmi_frl(struct pipe_ctx *pipe_ctx) 1928 { 1929 enum link_result link_stat = LINK_RESULT_UNKNOWN; 1930 enum dc_status status = DC_OK; 1931 struct dc_stream_state *stream = pipe_ctx->stream; 1932 struct dc *core_dc = pipe_ctx->stream->ctx->dc; 1933 enum clock_source_id frl_phy_clock_source_id; 1934 bool frl_poll_start = true; 1935 1936 DC_LOGGER_INIT(stream->ctx->logger); 1937 1938 if ((!stream->link->link_enc) || 1939 (!stream->link->hpo_frl_link_enc) || 1940 (!core_dc->res_pool->dccg->funcs->enable_hdmicharclk) || 1941 (!(pipe_ctx->stream_res.hpo_frl_stream_enc))) 1942 return DC_ERROR_UNEXPECTED; 1943 1944 /* get link settings for video mode timing */ 1945 hdmi_frl_decide_link_settings(stream, &stream->link->frl_link_settings, &pipe_ctx->dsc_padding_params); 1946 1947 switch (stream->link->frl_link_settings.frl_link_rate) { 1948 case HDMI_FRL_LINK_RATE_3GBPS: 1949 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 166667; 1950 break; 1951 case HDMI_FRL_LINK_RATE_6GBPS: 1952 case HDMI_FRL_LINK_RATE_6GBPS_4LANE: 1953 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 333333; 1954 break; 1955 case HDMI_FRL_LINK_RATE_8GBPS: 1956 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 444444; 1957 break; 1958 case HDMI_FRL_LINK_RATE_10GBPS: 1959 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 555555; 1960 break; 1961 case HDMI_FRL_LINK_RATE_12GBPS: 1962 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 666667; 1963 break; 1964 case HDMI_FRL_LINK_RATE_16GBPS: 1965 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 888889; 1966 break; 1967 case HDMI_FRL_LINK_RATE_20GBPS: 1968 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1111111; 1969 break; 1970 case HDMI_FRL_LINK_RATE_24GBPS: 1971 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1333333; 1972 break; 1973 default: 1974 break; 1975 } 1976 1977 stream->phy_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; 1978 1979 memset(&stream->link->cur_link_settings, 0, 1980 sizeof(struct dc_link_settings)); 1981 1982 /* Find proper clock source in HDMI FRL mode for phy used for DCCG */ 1983 frl_phy_clock_source_id = hdmi_frl_find_matching_phypll(stream->link); 1984 1985 FRL_INFO("FRL LINK TRAINING: LTS:P Start\n"); 1986 /* Setup FRL PHY, enable HDMI character clock and HPO link encoder */ 1987 core_dc->hwss.setup_hdmi_frl_link(stream->link, 1988 (pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0), 1989 frl_phy_clock_source_id); 1990 1991 link_stat = hdmi_frl_perform_link_training_with_retries(stream->link); 1992 1993 if (core_dc->res_pool->dccg->funcs->set_valid_pixel_rate) 1994 core_dc->res_pool->dccg->funcs->set_valid_pixel_rate( 1995 core_dc->res_pool->dccg, 1996 core_dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(core_dc->clk_mgr), 1997 pipe_ctx->stream_res.tg->inst, 1998 (stream->timing.pix_clk_100hz / 10)); 1999 2000 /* Enable FRL packet transmission */ 2001 if (link_stat == LINK_RESULT_SUCCESS) { 2002 stream->link->hpo_frl_link_enc->funcs->enable_output( 2003 stream->link->hpo_frl_link_enc); 2004 if (stream->link->frl_flags.apply_vsdb_rcc_wa) 2005 stream->link->hpo_frl_link_enc->funcs->apply_vsdb_rcc_wa(stream->link->hpo_frl_link_enc); 2006 if (frl_poll_start) 2007 hdmi_frl_poll_start(stream->link->ddc); 2008 2009 FRL_INFO("FRL LINK TRAINING: LTS:P Success\n"); 2010 2011 /* Set HDMISTREAMCLK source to DTBCLK0 and bypass DTO */ 2012 if (core_dc->res_pool->dccg->funcs->set_hdmistreamclk) { 2013 core_dc->res_pool->dccg->funcs->set_hdmistreamclk( 2014 core_dc->res_pool->dccg, 2015 DTBCLK0, 2016 pipe_ctx->stream_res.tg->inst); 2017 } 2018 2019 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_enable( 2020 pipe_ctx->stream_res.hpo_frl_stream_enc, 2021 pipe_ctx->stream_res.tg->inst); 2022 } else { 2023 status = DC_FAIL_HDMI_FRL_LINK_TRAINING; 2024 stream->link->frl_link_settings.frl_link_rate = 0; 2025 } 2026 2027 return status; 2028 } 2029 2030 static enum dc_status enable_link_dp(struct dc_state *state, 2031 struct pipe_ctx *pipe_ctx) 2032 { 2033 struct dc_stream_state *stream = pipe_ctx->stream; 2034 enum dc_status status; 2035 bool skip_video_pattern; 2036 struct dc_link *link = stream->link; 2037 const struct dc_link_settings *link_settings = 2038 &pipe_ctx->link_config.dp_link_settings; 2039 bool fec_enable; 2040 int i; 2041 bool apply_seamless_boot_optimization = false; 2042 uint32_t bl_oled_enable_delay = 50; // in ms 2043 uint32_t post_oui_delay = 30; // 30ms 2044 /* Reduce link bandwidth between failed link training attempts. */ 2045 bool do_fallback = false; 2046 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2047 2048 // Increase retry count if attempting DP1.x on FIXED_VS link 2049 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2050 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2051 lt_attempts = 10; 2052 2053 // check for seamless boot 2054 for (i = 0; i < state->stream_count; i++) { 2055 if (state->streams[i]->apply_seamless_boot_optimization) { 2056 apply_seamless_boot_optimization = true; 2057 break; 2058 } 2059 } 2060 2061 /* Train with fallback when enabling DPIA link. Conventional links are 2062 * trained with fallback during sink detection. 2063 */ 2064 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2065 !link->dc->config.enable_dpia_pre_training) 2066 do_fallback = true; 2067 2068 /* 2069 * Temporary w/a to get DP2.0 link rates to work with SST. 2070 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2071 */ 2072 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2073 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2074 link->dc->debug.set_mst_en_for_sst) { 2075 enable_mst_on_sink(link, true); 2076 } else if (link->dpcd_caps.is_mst_capable && 2077 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2078 /* disable mst on sink */ 2079 enable_mst_on_sink(link, false); 2080 } 2081 2082 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2083 /*in case it is not on*/ 2084 if (!link->dc->config.edp_no_power_sequencing) 2085 link->dc->hwss.edp_power_control(link, true); 2086 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2087 } 2088 2089 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2090 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2091 } else { 2092 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2093 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2094 if (state->clk_mgr && !apply_seamless_boot_optimization) 2095 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2096 state, false); 2097 } 2098 2099 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2100 dpcd_set_source_specific_data(link); 2101 if (link->dpcd_sink_ext_caps.raw != 0) { 2102 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2103 msleep(post_oui_delay); 2104 } 2105 2106 // similarly, mode switch can cause loss of cable ID 2107 dpcd_write_cable_id_to_dprx(link); 2108 2109 skip_video_pattern = true; 2110 2111 if (link_settings->link_rate == LINK_RATE_LOW) 2112 skip_video_pattern = false; 2113 2114 if (stream->sink_patches.oled_optimize_display_on) 2115 set_default_brightness_aux(link); 2116 2117 if (perform_link_training_with_retries(link_settings, 2118 skip_video_pattern, 2119 lt_attempts, 2120 pipe_ctx, 2121 pipe_ctx->stream->signal, 2122 do_fallback)) { 2123 status = DC_OK; 2124 } else { 2125 status = DC_FAIL_DP_LINK_TRAINING; 2126 } 2127 2128 if (link->preferred_training_settings.fec_enable) 2129 fec_enable = *link->preferred_training_settings.fec_enable; 2130 else 2131 fec_enable = true; 2132 2133 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2134 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2135 2136 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2137 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2138 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2139 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2140 if (!stream->sink_patches.oled_optimize_display_on) { 2141 set_default_brightness_aux(link); 2142 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2143 msleep(bl_oled_enable_delay); 2144 edp_backlight_enable_aux(link, true); 2145 } else { 2146 edp_backlight_enable_aux(link, true); 2147 } 2148 } 2149 2150 return status; 2151 } 2152 2153 static enum dc_status enable_link_edp( 2154 struct dc_state *state, 2155 struct pipe_ctx *pipe_ctx) 2156 { 2157 return enable_link_dp(state, pipe_ctx); 2158 } 2159 2160 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2161 { 2162 struct dc_stream_state *stream = pipe_ctx->stream; 2163 struct dc_link *link = stream->link; 2164 struct dc *dc = stream->ctx->dc; 2165 2166 if (stream->phy_pix_clk == 0) 2167 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2168 2169 memset(&stream->link->cur_link_settings, 0, 2170 sizeof(struct dc_link_settings)); 2171 dc->hwss.enable_lvds_link_output( 2172 link, 2173 &pipe_ctx->link_res, 2174 pipe_ctx->clock_source->id, 2175 stream->phy_pix_clk); 2176 2177 } 2178 2179 static enum dc_status enable_link_dp_mst( 2180 struct dc_state *state, 2181 struct pipe_ctx *pipe_ctx) 2182 { 2183 struct dc_link *link = pipe_ctx->stream->link; 2184 unsigned char mstm_cntl = 0; 2185 2186 /* sink signal type after MST branch is MST. Multiple MST sinks 2187 * share one link. Link DP PHY is enable or training only once. 2188 */ 2189 if (link->link_status.link_active) 2190 return DC_OK; 2191 2192 /* clear payload table */ 2193 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2194 if (mstm_cntl & DP_MST_EN) 2195 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2196 2197 /* to make sure the pending down rep can be processed 2198 * before enabling the link 2199 */ 2200 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2201 2202 /* set the sink to MST mode before enabling the link */ 2203 enable_mst_on_sink(link, true); 2204 2205 return enable_link_dp(state, pipe_ctx); 2206 } 2207 2208 static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx) 2209 { 2210 struct dc_link *link = pipe_ctx->stream->link; 2211 2212 link->dc->hwss.enable_analog_link_output( 2213 link, pipe_ctx->stream->timing.pix_clk_100hz); 2214 2215 return DC_OK; 2216 } 2217 2218 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2219 { 2220 struct dc_link *link = pipe_ctx->stream->link; 2221 2222 link->dc->hwss.enable_dp_link_output(link, 2223 &pipe_ctx->link_res, 2224 SIGNAL_TYPE_DISPLAY_PORT, 2225 pipe_ctx->clock_source->id, 2226 &pipe_ctx->link_config.dp_link_settings); 2227 return DC_OK; 2228 } 2229 2230 static enum dc_status enable_link( 2231 struct dc_state *state, 2232 struct pipe_ctx *pipe_ctx) 2233 { 2234 enum dc_status status = DC_ERROR_UNEXPECTED; 2235 struct dc_stream_state *stream = pipe_ctx->stream; 2236 struct dc_link *link = NULL; 2237 2238 if (stream == NULL) 2239 return DC_ERROR_UNEXPECTED; 2240 link = stream->link; 2241 2242 /* There's some scenarios where driver is unloaded with display 2243 * still enabled. When driver is reloaded, it may cause a display 2244 * to not light up if there is a mismatch between old and new 2245 * link settings. Need to call disable first before enabling at 2246 * new link settings. 2247 */ 2248 if (link->link_status.link_active) 2249 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2250 2251 switch (pipe_ctx->stream->signal) { 2252 case SIGNAL_TYPE_DISPLAY_PORT: 2253 status = enable_link_dp(state, pipe_ctx); 2254 break; 2255 case SIGNAL_TYPE_EDP: 2256 status = enable_link_edp(state, pipe_ctx); 2257 break; 2258 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2259 status = enable_link_dp_mst(state, pipe_ctx); 2260 msleep(200); 2261 break; 2262 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2263 case SIGNAL_TYPE_DVI_DUAL_LINK: 2264 case SIGNAL_TYPE_HDMI_TYPE_A: 2265 enable_link_hdmi(pipe_ctx); 2266 status = DC_OK; 2267 break; 2268 case SIGNAL_TYPE_HDMI_FRL: 2269 if (link->local_sink && 2270 link->local_sink->edid_caps.panel_patch.delay_hdmi_link_training && 2271 stream->timing.pix_clk_100hz == 6627500) { 2272 msleep(link->local_sink->edid_caps.panel_patch.delay_hdmi_link_training); 2273 } 2274 status = enable_link_hdmi_frl(pipe_ctx); 2275 break; 2276 case SIGNAL_TYPE_LVDS: 2277 enable_link_lvds(pipe_ctx); 2278 status = DC_OK; 2279 break; 2280 case SIGNAL_TYPE_RGB: 2281 status = enable_link_analog(pipe_ctx); 2282 break; 2283 case SIGNAL_TYPE_VIRTUAL: 2284 status = enable_link_virtual(pipe_ctx); 2285 break; 2286 default: 2287 break; 2288 } 2289 2290 if (status == DC_OK) { 2291 pipe_ctx->stream->link->link_status.link_active = true; 2292 } 2293 2294 return status; 2295 } 2296 2297 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int stream_bw) 2298 { 2299 struct dc_link *link = stream->sink->link; 2300 int req_bw = stream_bw; 2301 2302 DC_LOGGER_INIT(link->ctx->logger); 2303 2304 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2305 return false; 2306 2307 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2308 int sink_index = -1; 2309 unsigned int i = 0; 2310 2311 for (i = 0; i < link->sink_count; i++) { 2312 if (link->remote_sinks[i] == NULL) 2313 continue; 2314 2315 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) { 2316 DC_LOG_DEBUG("%s: add remote_sink=%s, request_bw=%d\n", __func__, 2317 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2318 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2319 2320 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2321 } else 2322 sink_index = i; 2323 } 2324 2325 if (sink_index >= 0) 2326 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = stream_bw; 2327 else 2328 DC_LOG_WARNING("%s: stream sink_id=%u not found in remote_sinks[]\n", 2329 __func__, stream->sink->sink_id); 2330 2331 if (req_bw) { 2332 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2333 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2334 } else 2335 link->dpia_bw_alloc_config.dp_overhead = 0; 2336 } 2337 2338 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2339 2340 return true; 2341 } 2342 2343 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2344 { 2345 bool ret; 2346 2347 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2348 dc_link_get_highest_encoding_format(stream->sink->link)); 2349 2350 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2351 2352 return ret; 2353 } 2354 2355 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2356 { 2357 bool ret; 2358 2359 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2360 2361 return ret; 2362 } 2363 2364 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2365 { 2366 struct dc *dc = pipe_ctx->stream->ctx->dc; 2367 struct dc_stream_state *stream = pipe_ctx->stream; 2368 struct dc_link *link = stream->sink->link; 2369 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2370 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2371 2372 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2373 2374 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2375 2376 if (dp_is_128b_132b_signal(pipe_ctx)) 2377 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2378 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2379 vpg = pipe_ctx->stream_res.hpo_frl_stream_enc->vpg; 2380 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2381 return; 2382 2383 if (pipe_ctx->stream->sink) { 2384 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2385 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2386 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2387 pipe_ctx->stream->sink->edid_caps.display_name, 2388 pipe_ctx->stream->signal, link->link_index, link->sink_count); 2389 } 2390 } 2391 2392 link_wait_for_unlocked(link); 2393 2394 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2395 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2396 set_avmute(pipe_ctx, true); 2397 } 2398 2399 dc->hwss.disable_audio_stream(pipe_ctx); 2400 2401 update_psp_stream_config(pipe_ctx, true); 2402 dc->hwss.blank_stream(pipe_ctx); 2403 2404 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2405 deallocate_usb4_bandwidth(pipe_ctx->stream); 2406 2407 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2408 deallocate_mst_payload(pipe_ctx); 2409 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2410 dp_is_128b_132b_signal(pipe_ctx)) 2411 update_sst_payload(pipe_ctx, false); 2412 2413 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2414 struct ext_hdmi_settings settings = {0}; 2415 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2416 2417 unsigned short masked_chip_caps = link->chip_caps & 2418 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2419 //Need to inform that sink is going to use legacy HDMI mode. 2420 write_scdc_data( 2421 link->ddc, 2422 165000,//vbios only handles 165Mhz. 2423 false); 2424 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2425 /* DP159, Retimer settings */ 2426 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) 2427 write_i2c_retimer_setting(link, false, false, &settings); 2428 else 2429 write_i2c_default_retimer_setting(link, false, false); 2430 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2431 /* PI3EQX1204, Redriver settings */ 2432 write_i2c_redriver_setting(link, false); 2433 } 2434 } 2435 2436 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2437 !dp_is_128b_132b_signal(pipe_ctx)) { 2438 2439 /* In DP1.x SST mode, our encoder will go to TPS1 2440 * when link is on but stream is off. 2441 * Disabling link before stream will avoid exposing TPS1 pattern 2442 * during the disable sequence as it will confuse some receivers 2443 * state machine. 2444 * In DP2 or MST mode, our encoder will stay video active 2445 */ 2446 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2447 dc->hwss.disable_stream(pipe_ctx); 2448 } else { 2449 dc->hwss.disable_stream(pipe_ctx); 2450 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2451 } 2452 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2453 2454 if (pipe_ctx->stream->timing.flags.DSC) { 2455 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2456 link_set_dsc_enable(pipe_ctx, false); 2457 else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2458 link_set_dsc_on_stream(pipe_ctx, false); 2459 } 2460 if (dp_is_128b_132b_signal(pipe_ctx)) { 2461 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2462 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2463 } 2464 2465 if (vpg && vpg->funcs->vpg_powerdown) 2466 vpg->funcs->vpg_powerdown(vpg); 2467 2468 /* for psp not exist case */ 2469 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2470 /* reset internal save state to default since eDP is off */ 2471 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2472 /* since current psp not loaded, we need to reset it to default */ 2473 link->panel_mode = panel_mode; 2474 } 2475 } 2476 2477 void link_set_dpms_on( 2478 struct dc_state *state, 2479 struct pipe_ctx *pipe_ctx) 2480 { 2481 struct dc *dc = pipe_ctx->stream->ctx->dc; 2482 struct dc_stream_state *stream = pipe_ctx->stream; 2483 struct dc_link *link = stream->sink->link; 2484 enum dc_status status; 2485 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2486 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2487 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2488 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2489 bool apply_edp_fast_boot_optimization = 2490 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2491 2492 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2493 2494 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2495 2496 if (dp_is_128b_132b_signal(pipe_ctx)) 2497 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2498 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2499 vpg = pipe_ctx->stream_res.hpo_frl_stream_enc->vpg; 2500 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2501 return; 2502 2503 if (pipe_ctx->stream->sink) { 2504 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2505 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2506 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2507 pipe_ctx->stream->sink->edid_caps.display_name, 2508 pipe_ctx->stream->signal, 2509 link->link_index, 2510 link->sink_count); 2511 } 2512 } 2513 2514 link_wait_for_unlocked(stream->link); 2515 if (!dc->config.unify_link_enc_assignment) 2516 link_enc = link_enc_cfg_get_link_enc(link); 2517 ASSERT(link_enc); 2518 2519 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2520 && !dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) 2521 && !dp_is_128b_132b_signal(pipe_ctx)) { 2522 if (link_enc) 2523 link_enc->funcs->setup( 2524 link_enc, 2525 pipe_ctx->stream->signal); 2526 } 2527 2528 pipe_ctx->stream->link->link_state_valid = true; 2529 2530 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2531 hdmi_frl_decide_link_settings(stream, &stream->link->frl_link_settings, &pipe_ctx->dsc_padding_params); 2532 2533 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2534 if (dp_is_128b_132b_signal(pipe_ctx)) 2535 otg_out_dest = OUT_MUX_HPO_DP; 2536 else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2537 otg_out_dest = OUT_MUX_HPO_FRL; 2538 else 2539 otg_out_dest = OUT_MUX_DIO; 2540 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2541 } 2542 2543 link_hwss->setup_stream_attribute(pipe_ctx); 2544 2545 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2546 2547 // Enable VPG before building infoframe 2548 if (vpg && vpg->funcs->vpg_poweron) 2549 vpg->funcs->vpg_poweron(vpg); 2550 2551 resource_build_info_frame(pipe_ctx); 2552 dc->hwss.update_info_frame(pipe_ctx); 2553 2554 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2555 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2556 2557 /* Do not touch link on seamless boot optimization. */ 2558 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2559 pipe_ctx->stream->dpms_off = false; 2560 2561 /* Still enable stream features & audio on seamless boot for DP external displays */ 2562 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2563 enable_stream_features(pipe_ctx); 2564 dc->hwss.enable_audio_stream(pipe_ctx); 2565 } 2566 2567 update_psp_stream_config(pipe_ctx, false); 2568 return; 2569 } 2570 2571 /* eDP lit up by bios already, no need to enable again. */ 2572 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2573 apply_edp_fast_boot_optimization && 2574 !pipe_ctx->stream->timing.flags.DSC && 2575 !pipe_ctx->next_odm_pipe) { 2576 pipe_ctx->stream->dpms_off = false; 2577 update_psp_stream_config(pipe_ctx, false); 2578 2579 if (link->is_dds) { 2580 uint32_t post_oui_delay = 30; // 30ms 2581 2582 dpcd_set_source_specific_data(link); 2583 msleep(post_oui_delay); 2584 } 2585 2586 return; 2587 } 2588 2589 if (pipe_ctx->stream->dpms_off) 2590 return; 2591 2592 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2593 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2594 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2595 */ 2596 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2597 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2598 return; 2599 } 2600 2601 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2602 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2603 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2604 * will be automatically set at a later time when the video is enabled 2605 * (DP_VID_STREAM_EN = 1). 2606 */ 2607 if (pipe_ctx->stream->timing.flags.DSC) { 2608 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2609 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2610 link_set_dsc_enable(pipe_ctx, true); 2611 } 2612 2613 if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) 2614 dp_setup_replay(link, stream); 2615 2616 status = enable_link(state, pipe_ctx); 2617 2618 if (status != DC_OK) { 2619 DC_LOG_WARNING("enabling link %u failed: %d\n", 2620 pipe_ctx->stream->link->link_index, 2621 status); 2622 2623 /* Abort stream enable *unless* the failure was due to 2624 * DP link training - some DP monitors will recover and 2625 * show the stream anyway. But MST displays can't proceed 2626 * without link training. 2627 */ 2628 if ((status != DC_FAIL_DP_LINK_TRAINING && 2629 status != DC_FAIL_HDMI_FRL_LINK_TRAINING) || 2630 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2631 if (false == stream->link->link_status.link_active) 2632 disable_link(stream->link, &pipe_ctx->link_res, 2633 pipe_ctx->stream->signal); 2634 BREAK_TO_DEBUGGER(); 2635 return; 2636 } 2637 } 2638 2639 if (pipe_ctx->stream->timing.flags.DSC && 2640 dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2641 //TODO: bring HDMI FRL in line with DP 2642 link_set_dsc_on_stream(pipe_ctx, true); 2643 2644 /* turn off otg test pattern if enable */ 2645 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2646 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2647 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2648 COLOR_DEPTH_UNDEFINED); 2649 2650 /* This second call is needed to reconfigure the DIG 2651 * as a workaround for the incorrect value being applied 2652 * from transmitter control. 2653 */ 2654 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2655 dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) || 2656 dp_is_128b_132b_signal(pipe_ctx))) { 2657 2658 if (link_enc) 2659 link_enc->funcs->setup( 2660 link_enc, 2661 pipe_ctx->stream->signal); 2662 2663 } 2664 2665 dc->hwss.enable_stream(pipe_ctx); 2666 2667 /* Set DPS PPS SDP (AKA "info frames") */ 2668 if (pipe_ctx->stream->timing.flags.DSC) { 2669 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2670 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2671 dp_set_dsc_on_rx(pipe_ctx, true); 2672 link_set_dsc_pps_packet(pipe_ctx, true, true); 2673 } 2674 } 2675 2676 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2677 dp_set_hblank_reduction_on_rx(pipe_ctx); 2678 2679 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2680 allocate_usb4_bandwidth(pipe_ctx->stream); 2681 2682 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2683 allocate_mst_payload(pipe_ctx); 2684 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2685 dp_is_128b_132b_signal(pipe_ctx)) 2686 update_sst_payload(pipe_ctx, true); 2687 2688 /* Corruption was observed on systems with display mux when stream gets 2689 * enabled after the mux switch. Having a small delay between link 2690 * training and stream unblank resolves the corruption issue. 2691 * This is workaround. 2692 */ 2693 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2694 link->is_display_mux_present) 2695 msleep(20); 2696 2697 dc->hwss.unblank_stream(pipe_ctx, 2698 &pipe_ctx->stream->link->cur_link_settings); 2699 2700 if (stream->sink_patches.delay_ignore_msa > 0) 2701 msleep(stream->sink_patches.delay_ignore_msa); 2702 2703 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2704 enable_stream_features(pipe_ctx); 2705 update_psp_stream_config(pipe_ctx, false); 2706 2707 dc->hwss.enable_audio_stream(pipe_ctx); 2708 2709 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2710 set_avmute(pipe_ctx, false); 2711 } 2712 } 2713