1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
4 *
5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6 * Copyright (c) 2025 Collabora Ltd.
7 */
8
9 #include <linux/module.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/delay.h>
12 #include <linux/of_gpio.h>
13 #include <linux/of_device.h>
14 #include <linux/clk.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/spinlock.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/tlv.h>
22
23 #include "rockchip_sai.h"
24
25 #define DRV_NAME "rockchip-sai"
26
27 #define CLK_SHIFT_RATE_HZ_MAX 5
28 #define FW_RATIO_MAX 8
29 #define FW_RATIO_MIN 1
30 #define MAXBURST_PER_FIFO 8
31
32 #define TIMEOUT_US 1000
33 #define WAIT_TIME_MS_MAX 10000
34
35 #define MAX_LANES 4
36
37 enum fpw_mode {
38 FPW_ONE_BCLK_WIDTH,
39 FPW_ONE_SLOT_WIDTH,
40 FPW_HALF_FRAME_WIDTH,
41 };
42
43 struct rk_sai_dev {
44 struct device *dev;
45 struct clk *hclk;
46 struct clk *mclk;
47 struct regmap *regmap;
48 struct reset_control *rst_h;
49 struct reset_control *rst_m;
50 struct snd_dmaengine_dai_dma_data capture_dma_data;
51 struct snd_dmaengine_dai_dma_data playback_dma_data;
52 struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
53 unsigned int mclk_rate;
54 unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
55 unsigned int tx_lanes;
56 unsigned int rx_lanes;
57 unsigned int sdi[MAX_LANES];
58 unsigned int sdo[MAX_LANES];
59 unsigned int version;
60 enum fpw_mode fpw;
61 int fw_ratio;
62 bool has_capture;
63 bool has_playback;
64 bool is_master_mode;
65 bool is_tdm;
66 bool initialized;
67 /* protects register writes that depend on the state of XFER[1:0] */
68 spinlock_t xfer_lock;
69 };
70
rockchip_sai_stream_valid(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)71 static bool rockchip_sai_stream_valid(struct snd_pcm_substream *substream,
72 struct snd_soc_dai *dai)
73 {
74 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
75
76 if (!substream)
77 return false;
78
79 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
80 sai->has_playback)
81 return true;
82
83 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
84 sai->has_capture)
85 return true;
86
87 return false;
88 }
89
rockchip_sai_fsync_lost_detect(struct rk_sai_dev * sai,bool en)90 static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en)
91 {
92 unsigned int fw, cnt;
93
94 if (sai->is_master_mode || sai->version < SAI_VER_2311)
95 return 0;
96
97 regmap_read(sai->regmap, SAI_FSCR, &fw);
98 cnt = SAI_FSCR_FW_V(fw) << 1; /* two fsync lost */
99
100 regmap_update_bits(sai->regmap, SAI_INTCR,
101 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC);
102 regmap_update_bits(sai->regmap, SAI_INTCR,
103 SAI_INTCR_FSLOST_MASK,
104 SAI_INTCR_FSLOST(en));
105 /*
106 * The `cnt` is the number of SCLK cycles of the CRU's SCLK signal that
107 * should be used as timeout. Consequently, in slave mode, this value
108 * is only correct if the CRU SCLK is equal to the external SCLK.
109 */
110 regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT,
111 SAI_FS_TIMEOUT_VAL_MASK | SAI_FS_TIMEOUT_EN_MASK,
112 SAI_FS_TIMEOUT_VAL(cnt) | SAI_FS_TIMEOUT_EN(en));
113
114 return 0;
115 }
116
rockchip_sai_fsync_err_detect(struct rk_sai_dev * sai,bool en)117 static int rockchip_sai_fsync_err_detect(struct rk_sai_dev *sai,
118 bool en)
119 {
120 if (sai->is_master_mode || sai->version < SAI_VER_2311)
121 return 0;
122
123 regmap_update_bits(sai->regmap, SAI_INTCR,
124 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC);
125 regmap_update_bits(sai->regmap, SAI_INTCR,
126 SAI_INTCR_FSERR_MASK,
127 SAI_INTCR_FSERR(en));
128
129 return 0;
130 }
131
rockchip_sai_poll_clk_idle(struct rk_sai_dev * sai)132 static int rockchip_sai_poll_clk_idle(struct rk_sai_dev *sai)
133 {
134 unsigned int reg, idle, val;
135 int ret;
136
137 if (sai->version >= SAI_VER_2307) {
138 reg = SAI_STATUS;
139 idle = SAI_STATUS_FS_IDLE;
140 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle;
141 } else {
142 reg = SAI_XFER;
143 idle = SAI_XFER_FS_IDLE;
144 }
145
146 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val,
147 (val & idle), 10, TIMEOUT_US);
148 if (ret < 0)
149 dev_warn(sai->dev, "Failed to idle FS\n");
150
151 return ret;
152 }
153
rockchip_sai_poll_stream_idle(struct rk_sai_dev * sai,bool playback,bool capture)154 static int rockchip_sai_poll_stream_idle(struct rk_sai_dev *sai, bool playback, bool capture)
155 {
156 unsigned int reg, val;
157 unsigned int idle = 0;
158 int ret;
159
160 if (sai->version >= SAI_VER_2307) {
161 reg = SAI_STATUS;
162 if (playback)
163 idle |= SAI_STATUS_TX_IDLE;
164 if (capture)
165 idle |= SAI_STATUS_RX_IDLE;
166 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle;
167 } else {
168 reg = SAI_XFER;
169 if (playback)
170 idle |= SAI_XFER_TX_IDLE;
171 if (capture)
172 idle |= SAI_XFER_RX_IDLE;
173 }
174
175 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val,
176 (val & idle), 10, TIMEOUT_US);
177 if (ret < 0)
178 dev_warn(sai->dev, "Failed to idle stream\n");
179
180 return ret;
181 }
182
183 /**
184 * rockchip_sai_xfer_clk_stop_and_wait() - stop the xfer clock and wait for it to be idle
185 * @sai: pointer to the driver instance's rk_sai_dev struct
186 * @to_restore: pointer to store the CLK/FSS register values in as they were
187 * found before they were cleared, or NULL.
188 *
189 * Clear the XFER_CLK and XFER_FSS registers if needed, then busy-waits for the
190 * XFER clocks to be idle. Before clearing the bits, it stores the state of the
191 * registers as it encountered them in to_restore if it isn't NULL.
192 *
193 * Context: Any context. Expects sai->xfer_lock to be held by caller.
194 */
rockchip_sai_xfer_clk_stop_and_wait(struct rk_sai_dev * sai,unsigned int * to_restore)195 static void rockchip_sai_xfer_clk_stop_and_wait(struct rk_sai_dev *sai, unsigned int *to_restore)
196 {
197 unsigned int mask = SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK;
198 unsigned int disable = SAI_XFER_CLK_DIS | SAI_XFER_FSS_DIS;
199 unsigned int val;
200
201 assert_spin_locked(&sai->xfer_lock);
202
203 regmap_read(sai->regmap, SAI_XFER, &val);
204 if ((val & mask) == disable)
205 goto wait_for_idle;
206
207 if (sai->is_master_mode)
208 regmap_update_bits(sai->regmap, SAI_XFER, mask, disable);
209
210 wait_for_idle:
211 rockchip_sai_poll_clk_idle(sai);
212
213 if (to_restore)
214 *to_restore = val;
215 }
216
rockchip_sai_runtime_suspend(struct device * dev)217 static int rockchip_sai_runtime_suspend(struct device *dev)
218 {
219 struct rk_sai_dev *sai = dev_get_drvdata(dev);
220 unsigned long flags;
221
222 rockchip_sai_fsync_lost_detect(sai, 0);
223 rockchip_sai_fsync_err_detect(sai, 0);
224
225 spin_lock_irqsave(&sai->xfer_lock, flags);
226 rockchip_sai_xfer_clk_stop_and_wait(sai, NULL);
227 spin_unlock_irqrestore(&sai->xfer_lock, flags);
228
229 regcache_cache_only(sai->regmap, true);
230 /*
231 * After FS is idle, we should wait at least 2 BCLK cycles to make sure
232 * the CLK gate operation has completed, and only then disable mclk.
233 *
234 * Otherwise, the BCLK is still ungated, and once the mclk is enabled,
235 * there is a risk that a few BCLK cycles leak. This is true especially
236 * at low speeds, such as with a samplerate of 8k.
237 *
238 * Ideally we'd adjust the delay based on the samplerate, but it's such
239 * a tiny value that we can just delay for the maximum clock period
240 * for the sake of simplicity.
241 *
242 * The maximum BCLK period is 31us @ 8K-8Bit (64kHz BCLK). We wait for
243 * 40us to give ourselves a safety margin in case udelay falls short.
244 */
245 udelay(40);
246 clk_disable_unprepare(sai->mclk);
247 clk_disable_unprepare(sai->hclk);
248
249 return 0;
250 }
251
rockchip_sai_runtime_resume(struct device * dev)252 static int rockchip_sai_runtime_resume(struct device *dev)
253 {
254 struct rk_sai_dev *sai = dev_get_drvdata(dev);
255 int ret;
256
257 ret = clk_prepare_enable(sai->hclk);
258 if (ret)
259 goto err_hclk;
260
261 ret = clk_prepare_enable(sai->mclk);
262 if (ret)
263 goto err_mclk;
264
265 regcache_cache_only(sai->regmap, false);
266 regcache_mark_dirty(sai->regmap);
267 ret = regcache_sync(sai->regmap);
268 if (ret)
269 goto err_regmap;
270
271 return 0;
272
273 err_regmap:
274 clk_disable_unprepare(sai->mclk);
275 err_mclk:
276 clk_disable_unprepare(sai->hclk);
277 err_hclk:
278 return ret;
279 }
280
rockchip_sai_fifo_xrun_detect(struct rk_sai_dev * sai,int stream,bool en)281 static void rockchip_sai_fifo_xrun_detect(struct rk_sai_dev *sai,
282 int stream, bool en)
283 {
284 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
285 /* clear irq status which was asserted before TXUIE enabled */
286 regmap_update_bits(sai->regmap, SAI_INTCR,
287 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
288 regmap_update_bits(sai->regmap, SAI_INTCR,
289 SAI_INTCR_TXUIE_MASK,
290 SAI_INTCR_TXUIE(en));
291 } else {
292 /* clear irq status which was asserted before RXOIE enabled */
293 regmap_update_bits(sai->regmap, SAI_INTCR,
294 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
295 regmap_update_bits(sai->regmap, SAI_INTCR,
296 SAI_INTCR_RXOIE_MASK,
297 SAI_INTCR_RXOIE(en));
298 }
299 }
300
rockchip_sai_dma_ctrl(struct rk_sai_dev * sai,int stream,bool en)301 static void rockchip_sai_dma_ctrl(struct rk_sai_dev *sai,
302 int stream, bool en)
303 {
304 if (!en)
305 rockchip_sai_fifo_xrun_detect(sai, stream, 0);
306
307 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
308 regmap_update_bits(sai->regmap, SAI_DMACR,
309 SAI_DMACR_TDE_MASK,
310 SAI_DMACR_TDE(en));
311 } else {
312 regmap_update_bits(sai->regmap, SAI_DMACR,
313 SAI_DMACR_RDE_MASK,
314 SAI_DMACR_RDE(en));
315 }
316
317 if (en)
318 rockchip_sai_fifo_xrun_detect(sai, stream, 1);
319 }
320
rockchip_sai_reset(struct rk_sai_dev * sai)321 static void rockchip_sai_reset(struct rk_sai_dev *sai)
322 {
323 /*
324 * It is advised to reset the hclk domain before resetting the mclk
325 * domain, especially in slave mode without a clock input.
326 *
327 * To deal with the aforementioned case of slave mode without a clock
328 * input, we work around a potential issue by resetting the whole
329 * controller, bringing it back into master mode, and then recovering
330 * the controller configuration in the regmap.
331 */
332 reset_control_assert(sai->rst_h);
333 udelay(10);
334 reset_control_deassert(sai->rst_h);
335 udelay(10);
336 reset_control_assert(sai->rst_m);
337 udelay(10);
338 reset_control_deassert(sai->rst_m);
339 udelay(10);
340
341 /* recover regmap config */
342 regcache_mark_dirty(sai->regmap);
343 regcache_sync(sai->regmap);
344 }
345
rockchip_sai_clear(struct rk_sai_dev * sai,unsigned int clr)346 static int rockchip_sai_clear(struct rk_sai_dev *sai, unsigned int clr)
347 {
348 unsigned int val = 0;
349 int ret = 0;
350
351 regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
352 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
353 !(val & clr), 10, TIMEOUT_US);
354 if (ret < 0) {
355 dev_warn(sai->dev, "Failed to clear %u\n", clr);
356 rockchip_sai_reset(sai);
357 }
358
359 return ret;
360 }
361
rockchip_sai_xfer_start(struct rk_sai_dev * sai,int stream)362 static void rockchip_sai_xfer_start(struct rk_sai_dev *sai, int stream)
363 {
364 unsigned int msk, val;
365
366 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
367 msk = SAI_XFER_TXS_MASK;
368 val = SAI_XFER_TXS_EN;
369
370 } else {
371 msk = SAI_XFER_RXS_MASK;
372 val = SAI_XFER_RXS_EN;
373 }
374
375 regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
376 }
377
rockchip_sai_xfer_stop(struct rk_sai_dev * sai,int stream)378 static void rockchip_sai_xfer_stop(struct rk_sai_dev *sai, int stream)
379 {
380 unsigned int msk = 0, val = 0, clr = 0;
381 bool playback;
382 bool capture;
383
384 if (stream < 0) {
385 playback = true;
386 capture = true;
387 } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
388 playback = true;
389 capture = false;
390 } else {
391 playback = true;
392 capture = false;
393 }
394
395 if (playback) {
396 msk |= SAI_XFER_TXS_MASK;
397 val |= SAI_XFER_TXS_DIS;
398 clr |= SAI_CLR_TXC;
399 }
400 if (capture) {
401 msk |= SAI_XFER_RXS_MASK;
402 val |= SAI_XFER_RXS_DIS;
403 clr |= SAI_CLR_RXC;
404 }
405
406 regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
407 rockchip_sai_poll_stream_idle(sai, playback, capture);
408
409 rockchip_sai_clear(sai, clr);
410 }
411
rockchip_sai_start(struct rk_sai_dev * sai,int stream)412 static void rockchip_sai_start(struct rk_sai_dev *sai, int stream)
413 {
414 rockchip_sai_dma_ctrl(sai, stream, 1);
415 rockchip_sai_xfer_start(sai, stream);
416 }
417
rockchip_sai_stop(struct rk_sai_dev * sai,int stream)418 static void rockchip_sai_stop(struct rk_sai_dev *sai, int stream)
419 {
420 rockchip_sai_dma_ctrl(sai, stream, 0);
421 rockchip_sai_xfer_stop(sai, stream);
422 }
423
rockchip_sai_fmt_create(struct rk_sai_dev * sai,unsigned int fmt)424 static void rockchip_sai_fmt_create(struct rk_sai_dev *sai, unsigned int fmt)
425 {
426 unsigned int xcr_mask = 0, xcr_val = 0, xsft_mask = 0, xsft_val = 0;
427 unsigned int fscr_mask = 0, fscr_val = 0;
428
429 assert_spin_locked(&sai->xfer_lock);
430
431 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
432 case SND_SOC_DAIFMT_RIGHT_J:
433 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
434 xcr_val = SAI_XCR_VDJ_R | SAI_XCR_EDGE_SHIFT_0;
435 xsft_mask = SAI_XSHIFT_RIGHT_MASK;
436 xsft_val = SAI_XSHIFT_RIGHT(0);
437 fscr_mask = SAI_FSCR_EDGE_MASK;
438 fscr_val = SAI_FSCR_EDGE_DUAL;
439 sai->fpw = FPW_HALF_FRAME_WIDTH;
440 break;
441 case SND_SOC_DAIFMT_LEFT_J:
442 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
443 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
444 xsft_mask = SAI_XSHIFT_RIGHT_MASK;
445 xsft_val = SAI_XSHIFT_RIGHT(0);
446 fscr_mask = SAI_FSCR_EDGE_MASK;
447 fscr_val = SAI_FSCR_EDGE_DUAL;
448 sai->fpw = FPW_HALF_FRAME_WIDTH;
449 break;
450 case SND_SOC_DAIFMT_I2S:
451 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
452 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_1;
453 xsft_mask = SAI_XSHIFT_RIGHT_MASK;
454 if (sai->is_tdm)
455 xsft_val = SAI_XSHIFT_RIGHT(1);
456 else
457 xsft_val = SAI_XSHIFT_RIGHT(2);
458 fscr_mask = SAI_FSCR_EDGE_MASK;
459 fscr_val = SAI_FSCR_EDGE_DUAL;
460 sai->fpw = FPW_HALF_FRAME_WIDTH;
461 break;
462 case SND_SOC_DAIFMT_DSP_A:
463 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
464 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
465 xsft_mask = SAI_XSHIFT_RIGHT_MASK;
466 xsft_val = SAI_XSHIFT_RIGHT(2);
467 fscr_mask = SAI_FSCR_EDGE_MASK;
468 fscr_val = SAI_FSCR_EDGE_RISING;
469 sai->fpw = FPW_ONE_BCLK_WIDTH;
470 break;
471 case SND_SOC_DAIFMT_DSP_B:
472 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
473 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
474 xsft_mask = SAI_XSHIFT_RIGHT_MASK;
475 xsft_val = SAI_XSHIFT_RIGHT(0);
476 fscr_mask = SAI_FSCR_EDGE_MASK;
477 fscr_val = SAI_FSCR_EDGE_RISING;
478 sai->fpw = FPW_ONE_BCLK_WIDTH;
479 break;
480 default:
481 dev_err(sai->dev, "Unsupported fmt %u\n", fmt);
482 break;
483 }
484
485 regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val);
486 regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val);
487 regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val);
488 regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val);
489 regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val);
490 }
491
rockchip_sai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)492 static int rockchip_sai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
493 {
494 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
495 unsigned int mask = 0, val = 0;
496 unsigned int clk_gates;
497 unsigned long flags;
498 int ret = 0;
499
500 pm_runtime_get_sync(dai->dev);
501
502 mask = SAI_CKR_MSS_MASK;
503 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
504 case SND_SOC_DAIFMT_BP_FP:
505 val = SAI_CKR_MSS_MASTER;
506 sai->is_master_mode = true;
507 break;
508 case SND_SOC_DAIFMT_BC_FC:
509 val = SAI_CKR_MSS_SLAVE;
510 sai->is_master_mode = false;
511 break;
512 default:
513 ret = -EINVAL;
514 goto err_pm_put;
515 }
516
517 spin_lock_irqsave(&sai->xfer_lock, flags);
518 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates);
519 if (sai->initialized) {
520 if (sai->has_capture && sai->has_playback)
521 rockchip_sai_xfer_stop(sai, -1);
522 else if (sai->has_capture)
523 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE);
524 else
525 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK);
526 } else {
527 rockchip_sai_clear(sai, 0);
528 sai->initialized = true;
529 }
530
531 regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
532
533 mask = SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK;
534 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
535 case SND_SOC_DAIFMT_NB_NF:
536 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL;
537 break;
538 case SND_SOC_DAIFMT_NB_IF:
539 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED;
540 break;
541 case SND_SOC_DAIFMT_IB_NF:
542 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL;
543 break;
544 case SND_SOC_DAIFMT_IB_IF:
545 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED;
546 break;
547 default:
548 ret = -EINVAL;
549 goto err_xfer_unlock;
550 }
551
552 regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
553
554 rockchip_sai_fmt_create(sai, fmt);
555
556 err_xfer_unlock:
557 if (clk_gates)
558 regmap_update_bits(sai->regmap, SAI_XFER,
559 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK,
560 clk_gates);
561 spin_unlock_irqrestore(&sai->xfer_lock, flags);
562 err_pm_put:
563 pm_runtime_put(dai->dev);
564
565 return ret;
566 }
567
rockchip_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)568 static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
569 struct snd_pcm_hw_params *params,
570 struct snd_soc_dai *dai)
571 {
572 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
573 struct snd_dmaengine_dai_dma_data *dma_data;
574 unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
575 unsigned int ch_per_lane, slot_width;
576 unsigned int val, fscr, reg;
577 unsigned int lanes, req_lanes;
578 unsigned long flags;
579 int ret = 0;
580
581 if (!rockchip_sai_stream_valid(substream, dai))
582 return 0;
583
584 dma_data = snd_soc_dai_get_dma_data(dai, substream);
585 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
586
587 pm_runtime_get_sync(sai->dev);
588
589 regmap_read(sai->regmap, SAI_DMACR, &val);
590
591 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
592 reg = SAI_TXCR;
593 lanes = sai->tx_lanes;
594 } else {
595 reg = SAI_RXCR;
596 lanes = sai->rx_lanes;
597 }
598
599 if (!sai->is_tdm) {
600 req_lanes = DIV_ROUND_UP(params_channels(params), 2);
601 if (lanes < req_lanes) {
602 dev_err(sai->dev, "not enough lanes (%d) for requested number of %s channels (%d)\n",
603 lanes, reg == SAI_TXCR ? "playback" : "capture",
604 params_channels(params));
605 ret = -EINVAL;
606 goto err_pm_put;
607 } else {
608 lanes = req_lanes;
609 }
610 }
611
612 dev_dbg(sai->dev, "using %d lanes totalling %d%s channels for %s\n",
613 lanes, params_channels(params), sai->is_tdm ? " (TDM)" : "",
614 reg == SAI_TXCR ? "playback" : "capture");
615
616 switch (params_format(params)) {
617 case SNDRV_PCM_FORMAT_S8:
618 case SNDRV_PCM_FORMAT_U8:
619 val = SAI_XCR_VDW(8);
620 break;
621 case SNDRV_PCM_FORMAT_S16_LE:
622 val = SAI_XCR_VDW(16);
623 break;
624 case SNDRV_PCM_FORMAT_S24_LE:
625 val = SAI_XCR_VDW(24);
626 break;
627 case SNDRV_PCM_FORMAT_S32_LE:
628 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
629 val = SAI_XCR_VDW(32);
630 break;
631 default:
632 ret = -EINVAL;
633 goto err_pm_put;
634 }
635
636 val |= SAI_XCR_CSR(lanes);
637
638 spin_lock_irqsave(&sai->xfer_lock, flags);
639
640 regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val);
641
642 regmap_read(sai->regmap, reg, &val);
643
644 slot_width = SAI_XCR_SBW_V(val);
645 ch_per_lane = params_channels(params) / lanes;
646
647 regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK,
648 SAI_XCR_SNB(ch_per_lane));
649
650 fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane);
651
652 switch (sai->fpw) {
653 case FPW_ONE_BCLK_WIDTH:
654 fscr |= SAI_FSCR_FPW(1);
655 break;
656 case FPW_ONE_SLOT_WIDTH:
657 fscr |= SAI_FSCR_FPW(slot_width);
658 break;
659 case FPW_HALF_FRAME_WIDTH:
660 fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2);
661 break;
662 default:
663 dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw);
664 ret = -EINVAL;
665 goto err_xfer_unlock;
666 }
667
668 regmap_update_bits(sai->regmap, SAI_FSCR,
669 SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr);
670
671 if (sai->is_master_mode) {
672 bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
673 ret = clk_set_rate(sai->mclk, sai->mclk_rate);
674 if (ret) {
675 dev_err(sai->dev, "Failed to set mclk to %u: %pe\n",
676 sai->mclk_rate, ERR_PTR(ret));
677 goto err_xfer_unlock;
678 }
679
680 mclk_rate = clk_get_rate(sai->mclk);
681 if (mclk_rate < bclk_rate) {
682 dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n",
683 mclk_rate, bclk_rate);
684 ret = -EINVAL;
685 goto err_xfer_unlock;
686 }
687
688 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
689 mclk_req_rate = bclk_rate * div_bclk;
690
691 if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
692 mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
693 dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
694 mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
695 ret = -EINVAL;
696 goto err_xfer_unlock;
697 }
698
699 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
700 SAI_CKR_MDIV(div_bclk));
701 }
702
703 err_xfer_unlock:
704 spin_unlock_irqrestore(&sai->xfer_lock, flags);
705 err_pm_put:
706 pm_runtime_put(sai->dev);
707
708 return ret;
709 }
710
rockchip_sai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)711 static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
712 struct snd_soc_dai *dai)
713 {
714 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
715 unsigned long flags;
716
717 if (!rockchip_sai_stream_valid(substream, dai))
718 return 0;
719
720 if (sai->is_master_mode) {
721 /*
722 * We should wait for the first BCLK pulse to have definitely
723 * occurred after any DIV settings have potentially been
724 * changed in order to guarantee a clean clock signal once we
725 * ungate the clock.
726 *
727 * Ideally, this would be done depending on the samplerate, but
728 * for the sake of simplicity, we'll just delay for the maximum
729 * possible clock offset time, which is quite a small value.
730 *
731 * The maximum BCLK offset is 15.6us @ 8K-8Bit (64kHz BCLK). We
732 * wait for 20us in order to give us a safety margin in case
733 * udelay falls short.
734 */
735 udelay(20);
736 spin_lock_irqsave(&sai->xfer_lock, flags);
737 regmap_update_bits(sai->regmap, SAI_XFER,
738 SAI_XFER_CLK_MASK |
739 SAI_XFER_FSS_MASK,
740 SAI_XFER_CLK_EN |
741 SAI_XFER_FSS_EN);
742 spin_unlock_irqrestore(&sai->xfer_lock, flags);
743 }
744
745 rockchip_sai_fsync_lost_detect(sai, 1);
746 rockchip_sai_fsync_err_detect(sai, 1);
747
748 return 0;
749 }
750
rockchip_sai_path_config(struct rk_sai_dev * sai,int num,bool is_rx)751 static void rockchip_sai_path_config(struct rk_sai_dev *sai,
752 int num, bool is_rx)
753 {
754 int i;
755
756 if (is_rx)
757 for (i = 0; i < num; i++)
758 regmap_update_bits(sai->regmap, SAI_PATH_SEL,
759 SAI_RX_PATH_MASK(i),
760 SAI_RX_PATH(i, sai->sdi[i]));
761 else
762 for (i = 0; i < num; i++)
763 regmap_update_bits(sai->regmap, SAI_PATH_SEL,
764 SAI_TX_PATH_MASK(i),
765 SAI_TX_PATH(i, sai->sdo[i]));
766 }
767
rockchip_sai_path_prepare(struct rk_sai_dev * sai,struct device_node * np,bool is_rx)768 static int rockchip_sai_path_prepare(struct rk_sai_dev *sai,
769 struct device_node *np,
770 bool is_rx)
771 {
772 const char *path_prop;
773 unsigned int *data;
774 unsigned int *lanes;
775 int i, num, ret;
776
777 if (is_rx) {
778 path_prop = "rockchip,sai-rx-route";
779 data = sai->sdi;
780 lanes = &sai->rx_lanes;
781 } else {
782 path_prop = "rockchip,sai-tx-route";
783 data = sai->sdo;
784 lanes = &sai->tx_lanes;
785 }
786
787 num = of_count_phandle_with_args(np, path_prop, NULL);
788 if (num == -ENOENT) {
789 return 0;
790 } else if (num > MAX_LANES || num == 0) {
791 dev_err(sai->dev, "found %d entries in %s, outside of range 1 to %d\n",
792 num, path_prop, MAX_LANES);
793 return -EINVAL;
794 } else if (num < 0) {
795 dev_err(sai->dev, "error in %s property: %pe\n", path_prop,
796 ERR_PTR(num));
797 return num;
798 }
799
800 *lanes = num;
801 ret = device_property_read_u32_array(sai->dev, path_prop, data, num);
802 if (ret < 0) {
803 dev_err(sai->dev, "failed to read property '%s': %pe\n",
804 path_prop, ERR_PTR(ret));
805 return ret;
806 }
807
808 for (i = 0; i < num; i++) {
809 if (data[i] >= MAX_LANES) {
810 dev_err(sai->dev, "%s[%d] is %d, should be less than %d\n",
811 path_prop, i, data[i], MAX_LANES);
812 return -EINVAL;
813 }
814 }
815
816 rockchip_sai_path_config(sai, num, is_rx);
817
818 return 0;
819 }
820
rockchip_sai_parse_paths(struct rk_sai_dev * sai,struct device_node * np)821 static int rockchip_sai_parse_paths(struct rk_sai_dev *sai,
822 struct device_node *np)
823 {
824 int ret;
825
826 if (sai->has_playback) {
827 sai->tx_lanes = 1;
828 ret = rockchip_sai_path_prepare(sai, np, false);
829 if (ret < 0) {
830 dev_err(sai->dev, "Failed to prepare TX path: %pe\n",
831 ERR_PTR(ret));
832 return ret;
833 }
834 }
835
836 if (sai->has_capture) {
837 sai->rx_lanes = 1;
838 ret = rockchip_sai_path_prepare(sai, np, true);
839 if (ret < 0) {
840 dev_err(sai->dev, "Failed to prepare RX path: %pe\n",
841 ERR_PTR(ret));
842 return ret;
843 }
844 }
845
846 return 0;
847 }
848
rockchip_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)849 static int rockchip_sai_trigger(struct snd_pcm_substream *substream,
850 int cmd, struct snd_soc_dai *dai)
851 {
852 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
853 int ret = 0;
854
855 if (!rockchip_sai_stream_valid(substream, dai))
856 return 0;
857
858 switch (cmd) {
859 case SNDRV_PCM_TRIGGER_START:
860 case SNDRV_PCM_TRIGGER_RESUME:
861 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
862 rockchip_sai_start(sai, substream->stream);
863 break;
864 case SNDRV_PCM_TRIGGER_SUSPEND:
865 case SNDRV_PCM_TRIGGER_STOP:
866 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
867 rockchip_sai_stop(sai, substream->stream);
868 break;
869 default:
870 ret = -EINVAL;
871 break;
872 }
873
874 return ret;
875 }
876
877
rockchip_sai_dai_probe(struct snd_soc_dai * dai)878 static int rockchip_sai_dai_probe(struct snd_soc_dai *dai)
879 {
880 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
881
882 snd_soc_dai_init_dma_data(dai,
883 sai->has_playback ? &sai->playback_dma_data : NULL,
884 sai->has_capture ? &sai->capture_dma_data : NULL);
885
886 return 0;
887 }
888
rockchip_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)889 static int rockchip_sai_startup(struct snd_pcm_substream *substream,
890 struct snd_soc_dai *dai)
891 {
892 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
893 int stream = substream->stream;
894
895 if (!rockchip_sai_stream_valid(substream, dai))
896 return 0;
897
898 if (sai->substreams[stream])
899 return -EBUSY;
900
901 if (sai->wait_time[stream])
902 substream->wait_time = sai->wait_time[stream];
903
904 sai->substreams[stream] = substream;
905
906 return 0;
907 }
908
rockchip_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)909 static void rockchip_sai_shutdown(struct snd_pcm_substream *substream,
910 struct snd_soc_dai *dai)
911 {
912 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
913
914 if (!rockchip_sai_stream_valid(substream, dai))
915 return;
916
917 sai->substreams[substream->stream] = NULL;
918 }
919
rockchip_sai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)920 static int rockchip_sai_set_tdm_slot(struct snd_soc_dai *dai,
921 unsigned int tx_mask, unsigned int rx_mask,
922 int slots, int slot_width)
923 {
924 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
925 unsigned long flags;
926 unsigned int clk_gates;
927 int sw = slot_width;
928
929 if (!slots) {
930 /* Disabling TDM, set slot width back to 32 bits */
931 sai->is_tdm = false;
932 sw = 32;
933 } else {
934 sai->is_tdm = true;
935 }
936
937 if (sw < 16 || sw > 32)
938 return -EINVAL;
939
940 pm_runtime_get_sync(dai->dev);
941 spin_lock_irqsave(&sai->xfer_lock, flags);
942 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates);
943 regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK,
944 SAI_XCR_SBW(sw));
945 regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK,
946 SAI_XCR_SBW(sw));
947 regmap_update_bits(sai->regmap, SAI_XFER,
948 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK,
949 clk_gates);
950 spin_unlock_irqrestore(&sai->xfer_lock, flags);
951 pm_runtime_put(dai->dev);
952
953 return 0;
954 }
955
rockchip_sai_set_sysclk(struct snd_soc_dai * dai,int stream,unsigned int freq,int dir)956 static int rockchip_sai_set_sysclk(struct snd_soc_dai *dai, int stream,
957 unsigned int freq, int dir)
958 {
959 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
960
961 sai->mclk_rate = freq;
962
963 return 0;
964 }
965
966 static const struct snd_soc_dai_ops rockchip_sai_dai_ops = {
967 .probe = rockchip_sai_dai_probe,
968 .startup = rockchip_sai_startup,
969 .shutdown = rockchip_sai_shutdown,
970 .hw_params = rockchip_sai_hw_params,
971 .set_fmt = rockchip_sai_set_fmt,
972 .set_sysclk = rockchip_sai_set_sysclk,
973 .prepare = rockchip_sai_prepare,
974 .trigger = rockchip_sai_trigger,
975 .set_tdm_slot = rockchip_sai_set_tdm_slot,
976 };
977
978 static const struct snd_soc_dai_driver rockchip_sai_dai = {
979 .ops = &rockchip_sai_dai_ops,
980 .symmetric_rate = 1,
981 };
982
rockchip_sai_wr_reg(struct device * dev,unsigned int reg)983 static bool rockchip_sai_wr_reg(struct device *dev, unsigned int reg)
984 {
985 switch (reg) {
986 case SAI_TXCR:
987 case SAI_FSCR:
988 case SAI_RXCR:
989 case SAI_MONO_CR:
990 case SAI_XFER:
991 case SAI_CLR:
992 case SAI_CKR:
993 case SAI_DMACR:
994 case SAI_INTCR:
995 case SAI_TXDR:
996 case SAI_PATH_SEL:
997 case SAI_TX_SLOT_MASK0:
998 case SAI_TX_SLOT_MASK1:
999 case SAI_TX_SLOT_MASK2:
1000 case SAI_TX_SLOT_MASK3:
1001 case SAI_RX_SLOT_MASK0:
1002 case SAI_RX_SLOT_MASK1:
1003 case SAI_RX_SLOT_MASK2:
1004 case SAI_RX_SLOT_MASK3:
1005 case SAI_TX_SHIFT:
1006 case SAI_RX_SHIFT:
1007 case SAI_FSXN:
1008 case SAI_FS_TIMEOUT:
1009 case SAI_LOOPBACK_LR:
1010 return true;
1011 default:
1012 return false;
1013 }
1014 }
1015
rockchip_sai_rd_reg(struct device * dev,unsigned int reg)1016 static bool rockchip_sai_rd_reg(struct device *dev, unsigned int reg)
1017 {
1018 switch (reg) {
1019 case SAI_TXCR:
1020 case SAI_FSCR:
1021 case SAI_RXCR:
1022 case SAI_MONO_CR:
1023 case SAI_XFER:
1024 case SAI_CLR:
1025 case SAI_CKR:
1026 case SAI_TXFIFOLR:
1027 case SAI_RXFIFOLR:
1028 case SAI_DMACR:
1029 case SAI_INTCR:
1030 case SAI_INTSR:
1031 case SAI_TXDR:
1032 case SAI_RXDR:
1033 case SAI_PATH_SEL:
1034 case SAI_TX_SLOT_MASK0:
1035 case SAI_TX_SLOT_MASK1:
1036 case SAI_TX_SLOT_MASK2:
1037 case SAI_TX_SLOT_MASK3:
1038 case SAI_RX_SLOT_MASK0:
1039 case SAI_RX_SLOT_MASK1:
1040 case SAI_RX_SLOT_MASK2:
1041 case SAI_RX_SLOT_MASK3:
1042 case SAI_TX_DATA_CNT:
1043 case SAI_RX_DATA_CNT:
1044 case SAI_TX_SHIFT:
1045 case SAI_RX_SHIFT:
1046 case SAI_STATUS:
1047 case SAI_VERSION:
1048 case SAI_FSXN:
1049 case SAI_FS_TIMEOUT:
1050 case SAI_LOOPBACK_LR:
1051 return true;
1052 default:
1053 return false;
1054 }
1055 }
1056
rockchip_sai_volatile_reg(struct device * dev,unsigned int reg)1057 static bool rockchip_sai_volatile_reg(struct device *dev, unsigned int reg)
1058 {
1059 switch (reg) {
1060 case SAI_XFER:
1061 case SAI_INTCR:
1062 case SAI_INTSR:
1063 case SAI_CLR:
1064 case SAI_TXFIFOLR:
1065 case SAI_RXFIFOLR:
1066 case SAI_TXDR:
1067 case SAI_RXDR:
1068 case SAI_TX_DATA_CNT:
1069 case SAI_RX_DATA_CNT:
1070 case SAI_STATUS:
1071 case SAI_VERSION:
1072 return true;
1073 default:
1074 return false;
1075 }
1076 }
1077
rockchip_sai_precious_reg(struct device * dev,unsigned int reg)1078 static bool rockchip_sai_precious_reg(struct device *dev, unsigned int reg)
1079 {
1080 switch (reg) {
1081 case SAI_RXDR:
1082 return true;
1083 default:
1084 return false;
1085 }
1086 }
1087
1088 static const struct reg_default rockchip_sai_reg_defaults[] = {
1089 { SAI_TXCR, 0x00000bff },
1090 { SAI_FSCR, 0x0001f03f },
1091 { SAI_RXCR, 0x00000bff },
1092 { SAI_PATH_SEL, 0x0000e4e4 },
1093 };
1094
1095 static const struct regmap_config rockchip_sai_regmap_config = {
1096 .reg_bits = 32,
1097 .reg_stride = 4,
1098 .val_bits = 32,
1099 .max_register = SAI_LOOPBACK_LR,
1100 .reg_defaults = rockchip_sai_reg_defaults,
1101 .num_reg_defaults = ARRAY_SIZE(rockchip_sai_reg_defaults),
1102 .writeable_reg = rockchip_sai_wr_reg,
1103 .readable_reg = rockchip_sai_rd_reg,
1104 .volatile_reg = rockchip_sai_volatile_reg,
1105 .precious_reg = rockchip_sai_precious_reg,
1106 .cache_type = REGCACHE_FLAT,
1107 };
1108
rockchip_sai_init_dai(struct rk_sai_dev * sai,struct resource * res,struct snd_soc_dai_driver ** dp)1109 static int rockchip_sai_init_dai(struct rk_sai_dev *sai, struct resource *res,
1110 struct snd_soc_dai_driver **dp)
1111 {
1112 struct device_node *node = sai->dev->of_node;
1113 struct snd_soc_dai_driver *dai;
1114 struct property *dma_names;
1115 const char *dma_name;
1116
1117 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1118 if (!strcmp(dma_name, "tx"))
1119 sai->has_playback = true;
1120 if (!strcmp(dma_name, "rx"))
1121 sai->has_capture = true;
1122 }
1123
1124 dai = devm_kmemdup(sai->dev, &rockchip_sai_dai,
1125 sizeof(*dai), GFP_KERNEL);
1126 if (!dai)
1127 return -ENOMEM;
1128
1129 if (sai->has_playback) {
1130 dai->playback.stream_name = "Playback";
1131 dai->playback.channels_min = 1;
1132 dai->playback.channels_max = 512;
1133 dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
1134 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
1135 SNDRV_PCM_FMTBIT_S16_LE |
1136 SNDRV_PCM_FMTBIT_S24_LE |
1137 SNDRV_PCM_FMTBIT_S32_LE |
1138 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1139
1140 sai->playback_dma_data.addr = res->start + SAI_TXDR;
1141 sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1142 sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
1143 }
1144
1145 if (sai->has_capture) {
1146 dai->capture.stream_name = "Capture";
1147 dai->capture.channels_min = 1;
1148 dai->capture.channels_max = 512;
1149 dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
1150 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
1151 SNDRV_PCM_FMTBIT_S16_LE |
1152 SNDRV_PCM_FMTBIT_S24_LE |
1153 SNDRV_PCM_FMTBIT_S32_LE |
1154 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1155
1156 sai->capture_dma_data.addr = res->start + SAI_RXDR;
1157 sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1158 sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
1159 }
1160
1161 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK,
1162 SAI_DMACR_TDL(16));
1163 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK,
1164 SAI_DMACR_RDL(16));
1165
1166 if (dp)
1167 *dp = dai;
1168
1169 return 0;
1170 }
1171
1172 static const char * const mono_text[] = { "Disable", "Enable" };
1173
1174 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
1175
1176 static const char * const lplrc_text[] = { "L:MIC R:LP", "L:LP R:MIC" };
1177 static const char * const lplr_text[] = { "Disable", "Enable" };
1178
1179 static const char * const lpx_text[] = {
1180 "From SDO0", "From SDO1", "From SDO2", "From SDO3" };
1181
1182 static const char * const lps_text[] = { "Disable", "Enable" };
1183 static const char * const sync_out_text[] = { "From CRU", "From IO" };
1184 static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
1185
1186 static const char * const rpaths_text[] = {
1187 "From SDI0", "From SDI1", "From SDI2", "From SDI3" };
1188
1189 static const char * const tpaths_text[] = {
1190 "From PATH0", "From PATH1", "From PATH2", "From PATH3" };
1191
1192 /* MONO_CR */
1193 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
1194 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
1195
1196 /* PATH_SEL */
1197 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
1198 static SOC_ENUM_SINGLE_DECL(lp2_enum, SAI_PATH_SEL, 26, lpx_text);
1199 static SOC_ENUM_SINGLE_DECL(lp1_enum, SAI_PATH_SEL, 24, lpx_text);
1200 static SOC_ENUM_SINGLE_DECL(lp0_enum, SAI_PATH_SEL, 22, lpx_text);
1201 static SOC_ENUM_SINGLE_DECL(lp3_switch, SAI_PATH_SEL, 21, lps_text);
1202 static SOC_ENUM_SINGLE_DECL(lp2_switch, SAI_PATH_SEL, 20, lps_text);
1203 static SOC_ENUM_SINGLE_DECL(lp1_switch, SAI_PATH_SEL, 19, lps_text);
1204 static SOC_ENUM_SINGLE_DECL(lp0_switch, SAI_PATH_SEL, 18, lps_text);
1205 static SOC_ENUM_SINGLE_DECL(sync_out_switch, SAI_PATH_SEL, 17, sync_out_text);
1206 static SOC_ENUM_SINGLE_DECL(sync_in_switch, SAI_PATH_SEL, 16, sync_in_text);
1207 static SOC_ENUM_SINGLE_DECL(rpath3_enum, SAI_PATH_SEL, 14, rpaths_text);
1208 static SOC_ENUM_SINGLE_DECL(rpath2_enum, SAI_PATH_SEL, 12, rpaths_text);
1209 static SOC_ENUM_SINGLE_DECL(rpath1_enum, SAI_PATH_SEL, 10, rpaths_text);
1210 static SOC_ENUM_SINGLE_DECL(rpath0_enum, SAI_PATH_SEL, 8, rpaths_text);
1211 static SOC_ENUM_SINGLE_DECL(tpath3_enum, SAI_PATH_SEL, 6, tpaths_text);
1212 static SOC_ENUM_SINGLE_DECL(tpath2_enum, SAI_PATH_SEL, 4, tpaths_text);
1213 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
1214 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
1215
1216 /* LOOPBACK_LR */
1217 static SOC_ENUM_SINGLE_DECL(lp3lrc_enum, SAI_LOOPBACK_LR, 7, lplrc_text);
1218 static SOC_ENUM_SINGLE_DECL(lp2lrc_enum, SAI_LOOPBACK_LR, 6, lplrc_text);
1219 static SOC_ENUM_SINGLE_DECL(lp1lrc_enum, SAI_LOOPBACK_LR, 5, lplrc_text);
1220 static SOC_ENUM_SINGLE_DECL(lp0lrc_enum, SAI_LOOPBACK_LR, 4, lplrc_text);
1221 static SOC_ENUM_SINGLE_DECL(lp3lr_switch, SAI_LOOPBACK_LR, 3, lplr_text);
1222 static SOC_ENUM_SINGLE_DECL(lp2lr_switch, SAI_LOOPBACK_LR, 2, lplr_text);
1223 static SOC_ENUM_SINGLE_DECL(lp1lr_switch, SAI_LOOPBACK_LR, 1, lplr_text);
1224 static SOC_ENUM_SINGLE_DECL(lp0lr_switch, SAI_LOOPBACK_LR, 0, lplr_text);
1225
rockchip_sai_wait_time_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1226 static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
1227 struct snd_ctl_elem_info *uinfo)
1228 {
1229 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1230 uinfo->count = 1;
1231 uinfo->value.integer.min = 0;
1232 uinfo->value.integer.max = WAIT_TIME_MS_MAX;
1233 uinfo->value.integer.step = 1;
1234
1235 return 0;
1236 }
1237
rockchip_sai_rd_wait_time_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1238 static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
1239 struct snd_ctl_elem_value *ucontrol)
1240 {
1241 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1242 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1243
1244 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
1245
1246 return 0;
1247 }
1248
rockchip_sai_rd_wait_time_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1249 static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
1250 struct snd_ctl_elem_value *ucontrol)
1251 {
1252 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1253 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1254
1255 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1256 return -EINVAL;
1257
1258 sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
1259
1260 return 1;
1261 }
1262
rockchip_sai_wr_wait_time_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1263 static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
1264 struct snd_ctl_elem_value *ucontrol)
1265 {
1266 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1267 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1268
1269 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
1270
1271 return 0;
1272 }
1273
rockchip_sai_wr_wait_time_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1274 static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
1275 struct snd_ctl_elem_value *ucontrol)
1276 {
1277 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1278 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1279
1280 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1281 return -EINVAL;
1282
1283 sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
1284
1285 return 1;
1286 }
1287
1288 #define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
1289 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
1290 .info = rockchip_sai_wait_time_info, \
1291 .get = xhandler_get, .put = xhandler_put }
1292
1293 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
1294 SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
1295 2, 128, 0, rmss_tlv),
1296 SOC_ENUM("Receive Mono Switch", rmono_switch),
1297 SOC_ENUM("Transmit Mono Switch", tmono_switch),
1298
1299 SOC_ENUM("SDI3 Loopback I2S LR Channel Sel", lp3lrc_enum),
1300 SOC_ENUM("SDI2 Loopback I2S LR Channel Sel", lp2lrc_enum),
1301 SOC_ENUM("SDI1 Loopback I2S LR Channel Sel", lp1lrc_enum),
1302 SOC_ENUM("SDI0 Loopback I2S LR Channel Sel", lp0lrc_enum),
1303 SOC_ENUM("SDI3 Loopback I2S LR Switch", lp3lr_switch),
1304 SOC_ENUM("SDI2 Loopback I2S LR Switch", lp2lr_switch),
1305 SOC_ENUM("SDI1 Loopback I2S LR Switch", lp1lr_switch),
1306 SOC_ENUM("SDI0 Loopback I2S LR Switch", lp0lr_switch),
1307
1308 SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
1309 SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
1310 SOC_ENUM("SDI1 Loopback Src Select", lp1_enum),
1311 SOC_ENUM("SDI0 Loopback Src Select", lp0_enum),
1312 SOC_ENUM("SDI3 Loopback Switch", lp3_switch),
1313 SOC_ENUM("SDI2 Loopback Switch", lp2_switch),
1314 SOC_ENUM("SDI1 Loopback Switch", lp1_switch),
1315 SOC_ENUM("SDI0 Loopback Switch", lp0_switch),
1316 SOC_ENUM("Sync Out Switch", sync_out_switch),
1317 SOC_ENUM("Sync In Switch", sync_in_switch),
1318 SOC_ENUM("Receive PATH3 Source Select", rpath3_enum),
1319 SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
1320 SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
1321 SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1322 SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
1323 SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
1324 SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
1325 SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
1326
1327 SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
1328 rockchip_sai_rd_wait_time_get,
1329 rockchip_sai_rd_wait_time_put),
1330 SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
1331 rockchip_sai_wr_wait_time_get,
1332 rockchip_sai_wr_wait_time_put),
1333 };
1334
1335 static const struct snd_soc_component_driver rockchip_sai_component = {
1336 .name = DRV_NAME,
1337 .controls = rockchip_sai_controls,
1338 .num_controls = ARRAY_SIZE(rockchip_sai_controls),
1339 .legacy_dai_naming = 1,
1340 };
1341
rockchip_sai_isr(int irq,void * devid)1342 static irqreturn_t rockchip_sai_isr(int irq, void *devid)
1343 {
1344 struct rk_sai_dev *sai = (struct rk_sai_dev *)devid;
1345 struct snd_pcm_substream *substream;
1346 u32 val;
1347
1348 regmap_read(sai->regmap, SAI_INTSR, &val);
1349 if (val & SAI_INTSR_TXUI_ACT) {
1350 dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
1351 regmap_update_bits(sai->regmap, SAI_INTCR,
1352 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1353 regmap_update_bits(sai->regmap, SAI_INTCR,
1354 SAI_INTCR_TXUIE_MASK,
1355 SAI_INTCR_TXUIE(0));
1356 substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
1357 if (substream)
1358 snd_pcm_stop_xrun(substream);
1359 }
1360
1361 if (val & SAI_INTSR_RXOI_ACT) {
1362 dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
1363 regmap_update_bits(sai->regmap, SAI_INTCR,
1364 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1365 regmap_update_bits(sai->regmap, SAI_INTCR,
1366 SAI_INTCR_RXOIE_MASK,
1367 SAI_INTCR_RXOIE(0));
1368 substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
1369 if (substream)
1370 snd_pcm_stop_xrun(substream);
1371 }
1372
1373 if (val & SAI_INTSR_FSERRI_ACT) {
1374 dev_warn_ratelimited(sai->dev, "Frame Sync Error\n");
1375 regmap_update_bits(sai->regmap, SAI_INTCR,
1376 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC);
1377 regmap_update_bits(sai->regmap, SAI_INTCR,
1378 SAI_INTCR_FSERR_MASK,
1379 SAI_INTCR_FSERR(0));
1380 }
1381
1382 if (val & SAI_INTSR_FSLOSTI_ACT) {
1383 dev_warn_ratelimited(sai->dev, "Frame Sync Lost\n");
1384 regmap_update_bits(sai->regmap, SAI_INTCR,
1385 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC);
1386 regmap_update_bits(sai->regmap, SAI_INTCR,
1387 SAI_INTCR_FSLOST_MASK,
1388 SAI_INTCR_FSLOST(0));
1389 }
1390
1391 return IRQ_HANDLED;
1392 }
1393
rockchip_sai_probe(struct platform_device * pdev)1394 static int rockchip_sai_probe(struct platform_device *pdev)
1395 {
1396 struct device_node *node = pdev->dev.of_node;
1397 struct rk_sai_dev *sai;
1398 struct snd_soc_dai_driver *dai;
1399 struct resource *res;
1400 void __iomem *regs;
1401 int ret, irq;
1402
1403 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1404 if (!sai)
1405 return -ENOMEM;
1406
1407 sai->dev = &pdev->dev;
1408 sai->fw_ratio = 1;
1409 /* match to register default */
1410 sai->is_master_mode = true;
1411 dev_set_drvdata(&pdev->dev, sai);
1412
1413 spin_lock_init(&sai->xfer_lock);
1414
1415 sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
1416 if (IS_ERR(sai->rst_h))
1417 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_h),
1418 "Error in 'h' reset control\n");
1419
1420 sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m");
1421 if (IS_ERR(sai->rst_m))
1422 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_m),
1423 "Error in 'm' reset control\n");
1424
1425 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1426 if (IS_ERR(regs))
1427 return dev_err_probe(&pdev->dev, PTR_ERR(regs),
1428 "Failed to get and ioremap resource\n");
1429
1430 sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1431 &rockchip_sai_regmap_config);
1432 if (IS_ERR(sai->regmap))
1433 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1434 "Failed to initialize regmap\n");
1435
1436 irq = platform_get_irq_optional(pdev, 0);
1437 if (irq > 0) {
1438 ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
1439 IRQF_SHARED, node->name, sai);
1440 if (ret) {
1441 return dev_err_probe(&pdev->dev, ret,
1442 "Failed to request irq %d\n", irq);
1443 }
1444 } else {
1445 dev_dbg(&pdev->dev, "Asked for an IRQ but got %d\n", irq);
1446 }
1447
1448 sai->mclk = devm_clk_get(&pdev->dev, "mclk");
1449 if (IS_ERR(sai->mclk)) {
1450 return dev_err_probe(&pdev->dev, PTR_ERR(sai->mclk),
1451 "Failed to get mclk\n");
1452 }
1453
1454 sai->hclk = devm_clk_get(&pdev->dev, "hclk");
1455 if (IS_ERR(sai->hclk)) {
1456 return dev_err_probe(&pdev->dev, PTR_ERR(sai->hclk),
1457 "Failed to get hclk\n");
1458 }
1459
1460 ret = clk_prepare_enable(sai->hclk);
1461 if (ret)
1462 return dev_err_probe(&pdev->dev, ret, "Failed to enable hclk\n");
1463
1464 regmap_read(sai->regmap, SAI_VERSION, &sai->version);
1465
1466 ret = rockchip_sai_init_dai(sai, res, &dai);
1467 if (ret) {
1468 dev_err(&pdev->dev, "Failed to initialize DAI: %d\n", ret);
1469 goto err_disable_hclk;
1470 }
1471
1472 ret = rockchip_sai_parse_paths(sai, node);
1473 if (ret) {
1474 dev_err(&pdev->dev, "Failed to parse paths: %d\n", ret);
1475 goto err_disable_hclk;
1476 }
1477
1478 /*
1479 * From here on, all register accesses need to be wrapped in
1480 * pm_runtime_get_sync/pm_runtime_put calls
1481 *
1482 * NB: we don't rely on _resume_and_get in case of !CONFIG_PM
1483 */
1484 devm_pm_runtime_enable(&pdev->dev);
1485 pm_runtime_get_noresume(&pdev->dev);
1486 ret = rockchip_sai_runtime_resume(&pdev->dev);
1487 if (ret) {
1488 dev_err(&pdev->dev, "Failed to resume device: %pe\n", ERR_PTR(ret));
1489 goto err_disable_hclk;
1490 }
1491
1492 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1493 if (ret) {
1494 dev_err(&pdev->dev, "Failed to register PCM: %d\n", ret);
1495 goto err_runtime_suspend;
1496 }
1497
1498 ret = devm_snd_soc_register_component(&pdev->dev,
1499 &rockchip_sai_component,
1500 dai, 1);
1501 if (ret) {
1502 dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
1503 goto err_runtime_suspend;
1504 }
1505
1506 pm_runtime_use_autosuspend(&pdev->dev);
1507 pm_runtime_put(&pdev->dev);
1508
1509 clk_disable_unprepare(sai->hclk);
1510
1511 return 0;
1512
1513 err_runtime_suspend:
1514 /* If we're !CONFIG_PM, we get -ENOSYS and disable manually */
1515 if (pm_runtime_put(&pdev->dev))
1516 rockchip_sai_runtime_suspend(&pdev->dev);
1517 err_disable_hclk:
1518 clk_disable_unprepare(sai->hclk);
1519
1520 return ret;
1521 }
1522
rockchip_sai_remove(struct platform_device * pdev)1523 static void rockchip_sai_remove(struct platform_device *pdev)
1524 {
1525 #ifndef CONFIG_PM
1526 rockchip_sai_runtime_suspend(&pdev->dev);
1527 #endif
1528 }
1529
1530 static const struct dev_pm_ops rockchip_sai_pm_ops = {
1531 SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1532 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1533 };
1534
1535 static const struct of_device_id rockchip_sai_match[] = {
1536 { .compatible = "rockchip,rk3576-sai", },
1537 {},
1538 };
1539 MODULE_DEVICE_TABLE(of, rockchip_sai_match);
1540
1541 static struct platform_driver rockchip_sai_driver = {
1542 .probe = rockchip_sai_probe,
1543 .remove = rockchip_sai_remove,
1544 .driver = {
1545 .name = DRV_NAME,
1546 .of_match_table = rockchip_sai_match,
1547 .pm = &rockchip_sai_pm_ops,
1548 },
1549 };
1550 module_platform_driver(rockchip_sai_driver);
1551
1552 MODULE_DESCRIPTION("Rockchip SAI ASoC Interface");
1553 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1554 MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
1555 MODULE_LICENSE("GPL");
1556